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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kuXZXSYcn3CjrCkUfQltUf7eFan4nW/1Ly3AEtwlx3vvcdxEg8zsNAmyQm0BJ0Kq8betnYYpIkGeuT7mmoV8NEPhB2hhP5cvEO5Y5sPzMAudxjJ7Fl1u5ggNrdgmGOZqjdkpBktM6urkStJH9az2WfB59yOd8z8yzNf6s5vG8OoCWvuCI20+yZZmJV8j4vkvLK5di0lmCZ2dOCrfPfG8mjIFlXtyMyTPg+k2N9g+iXZT0bq95Jl+QU0BRlDuwM1oHUpAe56f0kBLoS7B3o+34G7lIRFgLRr9MBiD/cGZM7j6bCynGfSDWuGy4OMlP2T+RKXLlGNaUPetAAGpgaMnB0ielkYvrfGI1f3wrVveuUKEsWITYaZGmQ4dtY6phuMqZraageX5DU/EqvNMxMTHGQS02D3/Hdz0GWFbBzMnSH9WHFU2xlISQOBvMSfVyzAEC+q99LsYcAjA4LSoLvfqoYQ0ZfbfHE0rGsOteTSThAq5KJzjK+wZbnq5W+ZErBYAs/Im9MHXkplsQLCPO/xfDPKx6/2H60DeIa4256uoBuV440ze26Cw18j9a9BrlYQTc2oexx1vR4BylyABMgLQDtgr84YHUXmU2jJYx7EXJf2q00ykM6qaynZ7EForHJ9Np8jbUnBD5TMTI2+CGSDOCf+7gjwjdAnB37zQ9txkfoVwQSrAD5muNIlKRbszODxN4uQxp/Te6b0lKhTptSbT4rJ6jW0F0xlAZnS3lZfo3QmHt+De3TRLcdixKOsrY5O9AGX1kil4lRFp0qiSluHsYPIS9JEjs/tdtvJMJ3Zo1Fcm+8rM6xuT/6/9U92PjujFEntxX/y4Daj86I4IT5r7Hx1dhn39KstzCZBFry7vyYQL5ObP27jtFQwxs0Lw5yVdKH8FmbN2KDHgEFx9VJG+RWYuktLB3OgNiwEp18nAjOIZmHbzIV8zP2rfkk0eNrmP24lvQo1+idy92o/6utE+K5LcuwIppcebv3ZP+yLsteo7mMOfyvI2zAH0Lehe1uThcY5jj1qNOlxC3Sm6gG71/BSNVBADRi5kC6QqUoqkgvCwAIDZulmkyjUxa3CbWOxcjE+Bzbe9D+ARvrIxUJkJRzA1u8VVMCM+Gg755bUnvWvJdqdoeiqoKFTzIGB5uXO2W9ZkGd9x1OwWX2uOT211kVhD2Z1/YHlnpJR9qgnVvhd2YeCuqPpk+5QoGUFVj67+fFw1oUK7fBxW5BR+yatCfnZNXZGnmsSLYr2qByLa+nbRO4A44tasWIWvXTdFr1aY2ZUjE474BnyE0MLNaLs5gluhkFst+vZ01ClU+1XFIPU9La3B8afNo2NdpDyWCdn6Y6J4rP+jQkHAU1XgA62zv6t8zUi4euKlx8imdmtFb0MJNziIpndLipOpXGxiVsfUNNJswvL5aJOoNEWVTvcbC9lvn5GQ2Hmxaf2xRWRNJPVATYsB+sFpEHpTAtsXWkyY0kUFUuzCj0OAPTr4gtya/dahaNzJrtxuEKUqNWWTB8lKVcvFwFKSdg5GPU0YIfOQdaDTtWVstMDPUoXpfzyo5GYc+nIhagj3IJUh2Kvre45dbGfR+1EYCf4/09QDdkNm X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a8ce6366-015d-4e77-2e28-08daf8330cff X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 02:32:17.3604 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Ua2wmvzHWuVHMoFzQI3DXWXEMVqf2hhZbJcLjIveIt+XLjKSwQtUZ/1npOlcY5JneMYLkHsJQIRKh8xhcJmaIQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7786 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230116_183228_631595_4E6D0EF9 X-CRM114-Status: GOOD ( 12.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org RealVideo, or also spelled as Real Video, is a suite of proprietary video compression formats developed by RealNetworks - the specific format changes with the version. RealVideo codecs are identified by four-character codes. RV30 and RV40 are RealNetworks' proprietary H.264-based codecs. Reviewed-by: Nicolas Dufresne Signed-off-by: Ming Qian --- .../media/v4l/pixfmt-compressed.rst | 20 +++++++++++++++++++ drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ include/uapi/linux/videodev2.h | 2 ++ 3 files changed, 24 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst index a0230f357680..06b78e5589d2 100644 --- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst +++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst @@ -237,6 +237,26 @@ Compressed Formats Metadata associated with the frame to decode is required to be passed through the ``V4L2_CID_STATELESS_FWHT_PARAMS`` control. See the :ref:`associated Codec Control ID `. + * .. _V4L2-PIX-FMT-RV30: + + - ``V4L2_PIX_FMT_RV30`` + - 'RV30' + - RealVideo, or also spelled as Real Video, is a suite of + proprietary video compression formats developed by + RealNetworks - the specific format changes with the version. + RealVideo codecs are identified by four-character codes. + RV30 corresponds to RealVideo 8, suspected to be based + largely on an early draft of H.264 + * .. _V4L2-PIX-FMT-RV40: + + - ``V4L2_PIX_FMT_RV40`` + - 'RV40' + - RV40 represents RealVideo 9 and RealVideo 10. + RealVideo 9, suspected to be based on H.264. + RealVideo 10, aka RV9 EHQ, This refers to an improved encoder + for the RV9 format that is fully backwards compatible with + RV9 players - the format and decoder did not change, only + the encoder did. As a result, it uses the same FourCC. .. raw:: latex diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c index 9b5b04b8aa69..0546b00d3fc9 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c @@ -1473,6 +1473,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ case V4L2_PIX_FMT_FWHT_STATELESS: descr = "FWHT Stateless"; break; /* used in vicodec */ case V4L2_PIX_FMT_SPK: descr = "Sorenson Spark"; break; + case V4L2_PIX_FMT_RV30: descr = "RealVideo 8"; break; + case V4L2_PIX_FMT_RV40: descr = "RealVideo 9 & 10"; break; case V4L2_PIX_FMT_CPIA1: descr = "GSPCA CPiA YUV"; break; case V4L2_PIX_FMT_WNVA: descr = "WNVA"; break; case V4L2_PIX_FMT_SN9C10X: descr = "GSPCA SN9C10X"; break; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 262ef10cfa02..b121154a6e24 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -740,6 +740,8 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ #define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */ #define V4L2_PIX_FMT_SPK v4l2_fourcc('S', 'P', 'K', '0') /* Sorenson Spark */ +#define V4L2_PIX_FMT_RV30 v4l2_fourcc('R', 'V', '3', '0') /* RealVideo 8 */ +#define V4L2_PIX_FMT_RV40 v4l2_fourcc('R', 'V', '4', '0') /* RealVideo 9 & 10 */ /* Vendor-specific formats */ #define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */ From patchwork Tue Jan 17 02:31:55 2023 Content-Type: text/plain; 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RV30 and RV40 are support by amphion decoder. Signed-off-by: Ming Qian --- drivers/media/platform/amphion/vdec.c | 14 +++++++++++++ drivers/media/platform/amphion/vpu_malone.c | 23 +++++++++++++++++++++ drivers/media/platform/amphion/vpu_malone.h | 1 + 3 files changed, 38 insertions(+) diff --git a/drivers/media/platform/amphion/vdec.c b/drivers/media/platform/amphion/vdec.c index 09304b96f40d..03477998b9eb 100644 --- a/drivers/media/platform/amphion/vdec.c +++ b/drivers/media/platform/amphion/vdec.c @@ -172,6 +172,20 @@ static const struct vpu_format vdec_formats[] = { .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED }, + { + .pixfmt = V4L2_PIX_FMT_RV30, + .mem_planes = 1, + .comp_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED + }, + { + .pixfmt = V4L2_PIX_FMT_RV40, + .mem_planes = 1, + .comp_planes = 1, + .type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + .flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED + }, {0, 0, 0, 0}, }; diff --git a/drivers/media/platform/amphion/vpu_malone.c b/drivers/media/platform/amphion/vpu_malone.c index 67ba637c4c7f..26039741166a 100644 --- a/drivers/media/platform/amphion/vpu_malone.c +++ b/drivers/media/platform/amphion/vpu_malone.c @@ -68,6 +68,8 @@ #define STREAM_CONFIG_NUM_DBE_SET(x, y) CONFIG_SET(x, y, 30, 0x40000000) #define STREAM_CONFIG_FS_CTRL_MODE_SET(x, y) CONFIG_SET(x, y, 31, 0x80000000) +#define MALONE_DEC_FMT_RV_MASK BIT(21) + enum vpu_malone_stream_input_mode { INVALID_MODE = 0, FRAME_LVL, @@ -478,6 +480,9 @@ u32 vpu_malone_get_version(struct vpu_shared_addr *shared) { struct malone_iface *iface = shared->iface; + vpu_malone_enable_format(V4L2_PIX_FMT_RV30, iface->fw_version & MALONE_DEC_FMT_RV_MASK); + vpu_malone_enable_format(V4L2_PIX_FMT_RV40, iface->fw_version & MALONE_DEC_FMT_RV_MASK); + return iface->fw_version; } @@ -563,8 +568,22 @@ static struct malone_fmt_mapping fmt_mappings[] = { {V4L2_PIX_FMT_JPEG, MALONE_FMT_JPG}, {V4L2_PIX_FMT_VP8, MALONE_FMT_VP8}, {V4L2_PIX_FMT_SPK, MALONE_FMT_SPK}, + {V4L2_PIX_FMT_RV30, MALONE_FMT_RV}, + {V4L2_PIX_FMT_RV40, MALONE_FMT_RV}, }; +void vpu_malone_enable_format(u32 pixelformat, int enable) +{ + u32 i; + + for (i = 0; i < ARRAY_SIZE(fmt_mappings); i++) { + if (pixelformat == fmt_mappings[i].pixelformat) { + fmt_mappings[i].is_disabled = enable ? 0 : 1; + return; + } + } +} + static enum vpu_malone_format vpu_malone_format_remap(u32 pixelformat) { u32 i; @@ -989,6 +1008,8 @@ static const struct malone_padding_scode padding_scodes[] = { {SCODE_PADDING_EOS, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, {SCODE_PADDING_EOS, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, {SCODE_PADDING_EOS, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_RV30, {0x34010000, 0x0}}, + {SCODE_PADDING_EOS, V4L2_PIX_FMT_RV40, {0x34010000, 0x0}}, {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0xefff0000, 0x0}}, {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264, {0x0B010000, 0}}, {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H264_MVC, {0x0B010000, 0}}, @@ -1001,6 +1022,8 @@ static const struct malone_padding_scode padding_scodes[] = { {SCODE_PADDING_ABORT, V4L2_PIX_FMT_H263, {0xb1010000, 0x0}}, {SCODE_PADDING_ABORT, V4L2_PIX_FMT_VP8, {0x34010000, 0x0}}, {SCODE_PADDING_ABORT, V4L2_PIX_FMT_SPK, {0x34010000, 0x0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_RV30, {0x34010000, 0x0}}, + {SCODE_PADDING_ABORT, V4L2_PIX_FMT_RV40, {0x34010000, 0x0}}, {SCODE_PADDING_EOS, V4L2_PIX_FMT_JPEG, {0x0, 0x0}}, {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264, {0x15010000, 0x0}}, {SCODE_PADDING_BUFFLUSH, V4L2_PIX_FMT_H264_MVC, {0x15010000, 0x0}}, diff --git a/drivers/media/platform/amphion/vpu_malone.h b/drivers/media/platform/amphion/vpu_malone.h index 02a9d9530970..c95b53629199 100644 --- a/drivers/media/platform/amphion/vpu_malone.h +++ b/drivers/media/platform/amphion/vpu_malone.h @@ -41,5 +41,6 @@ int vpu_malone_post_cmd(struct vpu_shared_addr *shared, u32 instance); int vpu_malone_init_instance(struct vpu_shared_addr *shared, u32 instance); u32 vpu_malone_get_max_instance_count(struct vpu_shared_addr *shared); bool vpu_malone_check_fmt(enum vpu_core_type type, u32 pixelfmt); +void vpu_malone_enable_format(u32 pixelformat, int enable); #endif