From patchwork Tue Jan 17 13:51:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 13104690 X-Patchwork-Delegate: kieran@bingham.xyz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54065C3DA78 for ; Tue, 17 Jan 2023 13:53:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230418AbjAQNx0 (ORCPT ); Tue, 17 Jan 2023 08:53:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230433AbjAQNxG (ORCPT ); Tue, 17 Jan 2023 08:53:06 -0500 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62D933C2A9 for ; Tue, 17 Jan 2023 05:52:15 -0800 (PST) Received: from desky.lan (91-154-32-225.elisa-laajakaista.fi [91.154.32.225]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 1CDDC471; Tue, 17 Jan 2023 14:52:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1673963533; bh=8LQ0qfaUL2/HC55J0kE1QcsDS6Omt/aY1NupNg5Ximw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g0spKC14+T7Q5SyFt1CeVL9QeeXXwqxZZE3y45iOyomugeBQY3Ncv8AC+EoYtQKK5 zgpjgLzUwzt7BlDvfX10oiMP/52rz7a5HG9MaMy9GcXcVZV5lzx8ClXIM3PCJkUIid Kg+CzsUNkVLbXe3oJCeU9kZw+m0Sa37rV+OfwM4Y= From: Tomi Valkeinen To: Laurent Pinchart , Kieran Bingham , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org Cc: Tomi Valkeinen Subject: [PATCH 1/6] drm: rcar-du: dsi: add 'select RESET_CONTROLLER' Date: Tue, 17 Jan 2023 15:51:49 +0200 Message-Id: <20230117135154.387208-2-tomi.valkeinen+renesas@ideasonboard.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> References: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The RCAR DSI driver uses reset controller, so we should select it in the Kconfig. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig index fd2c2eaee26b..a8f862c68b4f 100644 --- a/drivers/gpu/drm/rcar-du/Kconfig +++ b/drivers/gpu/drm/rcar-du/Kconfig @@ -55,6 +55,7 @@ config DRM_RCAR_MIPI_DSI def_tristate DRM_RCAR_DU depends on DRM_RCAR_USE_MIPI_DSI select DRM_MIPI_DSI + select RESET_CONTROLLER config DRM_RCAR_VSP bool "R-Car DU VSP Compositor Support" if ARM From patchwork Tue Jan 17 13:51:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 13104691 X-Patchwork-Delegate: kieran@bingham.xyz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C539C678D4 for ; Tue, 17 Jan 2023 13:53:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229667AbjAQNxs (ORCPT ); Tue, 17 Jan 2023 08:53:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229753AbjAQNxG (ORCPT ); Tue, 17 Jan 2023 08:53:06 -0500 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5408F3CE0D for ; Tue, 17 Jan 2023 05:52:16 -0800 (PST) Received: from desky.lan (91-154-32-225.elisa-laajakaista.fi [91.154.32.225]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id A48B14DA; Tue, 17 Jan 2023 14:52:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1673963534; bh=gqEoZlraEbJMlFqHIIVcwSD4C6uq/6FiErgijUHtE68=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sGst5Ep6px+bRn3jaPjTxWE4iOOW7p8VEFILJT408Jw8JYCL9v1Jy5cbaQZD25P+2 p4ZMFosyGsHY7VgYLqysuOcJmn4/DA9GOq8E4GjAqLe1TlEVQRY99NscTtBK6xkEJv HAlU+uQzSmRmeOP3mgIGncICTPc0x7zeHxZ6QIi4= From: Tomi Valkeinen To: Laurent Pinchart , Kieran Bingham , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org Cc: Koji Matsuoka , LUU HOAI , Tomi Valkeinen Subject: [PATCH 2/6] drm: rcar-du: lvds: Add reset control Date: Tue, 17 Jan 2023 15:51:50 +0200 Message-Id: <20230117135154.387208-3-tomi.valkeinen+renesas@ideasonboard.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> References: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Koji Matsuoka Reset LVDS using the reset control as CPG reset/release is required in H/W manual sequence. Signed-off-by: Koji Matsuoka Signed-off-by: LUU HOAI [tomi.valkeinen: Rewrite the patch description] Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/rcar-du/Kconfig | 1 + drivers/gpu/drm/rcar-du/rcar_lvds.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig index a8f862c68b4f..151e400b996d 100644 --- a/drivers/gpu/drm/rcar-du/Kconfig +++ b/drivers/gpu/drm/rcar-du/Kconfig @@ -43,6 +43,7 @@ config DRM_RCAR_LVDS select DRM_PANEL select OF_FLATTREE select OF_OVERLAY + select RESET_CONTROLLER config DRM_RCAR_USE_MIPI_DSI bool "R-Car DU MIPI DSI Encoder Support" diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 81a060c2fe3f..674b727cdaa2 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -60,6 +61,7 @@ struct rcar_lvds_device_info { struct rcar_lvds { struct device *dev; const struct rcar_lvds_device_info *info; + struct reset_control *rstc; struct drm_bridge bridge; @@ -316,6 +318,8 @@ int rcar_lvds_pclk_enable(struct drm_bridge *bridge, unsigned long freq) dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq); + reset_control_deassert(lvds->rstc); + ret = clk_prepare_enable(lvds->clocks.mod); if (ret < 0) return ret; @@ -338,6 +342,8 @@ void rcar_lvds_pclk_disable(struct drm_bridge *bridge) rcar_lvds_write(lvds, LVDPLLCR, 0); clk_disable_unprepare(lvds->clocks.mod); + + reset_control_assert(lvds->rstc); } EXPORT_SYMBOL_GPL(rcar_lvds_pclk_disable); @@ -396,6 +402,8 @@ static void __rcar_lvds_atomic_enable(struct drm_bridge *bridge, u32 lvdcr0; int ret; + reset_control_deassert(lvds->rstc); + ret = clk_prepare_enable(lvds->clocks.mod); if (ret < 0) return; @@ -552,6 +560,7 @@ static void rcar_lvds_atomic_disable(struct drm_bridge *bridge, old_bridge_state); clk_disable_unprepare(lvds->clocks.mod); + reset_control_assert(lvds->rstc); } static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge, @@ -844,6 +853,12 @@ static int rcar_lvds_probe(struct platform_device *pdev) if (ret < 0) return ret; + lvds->rstc = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(lvds->rstc)) { + dev_err(&pdev->dev, "failed to get cpg reset\n"); + return PTR_ERR(lvds->rstc); + } + drm_bridge_add(&lvds->bridge); return 0; From patchwork Tue Jan 17 13:51:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 13104694 X-Patchwork-Delegate: kieran@bingham.xyz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40E4CC677F1 for ; Tue, 17 Jan 2023 13:53:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230421AbjAQNxw (ORCPT ); Tue, 17 Jan 2023 08:53:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230310AbjAQNxH (ORCPT ); Tue, 17 Jan 2023 08:53:07 -0500 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 505F22B627 for ; Tue, 17 Jan 2023 05:52:17 -0800 (PST) Received: from desky.lan (91-154-32-225.elisa-laajakaista.fi [91.154.32.225]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 464FE7F8; Tue, 17 Jan 2023 14:52:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1673963534; bh=L99YGDzzTbqbieWnC8cqQjbsz6I2by92epxdF6ewtvg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ztc73Q/CiFlMxpPJLagAtwFUiilyMmBfMOaPY85ZDErmrTBNAK+L1pQ0stkP2qhna 890W2NrHxyFaYVj1sSMoP7rpdGIO+FPzKi1OzQEg9Zu+dgZnRSwgBD8IwrNqG2mjYu gzivRXnU1b/PfYKBMwqVFO/ftxn6BHq+EBbmqUoQ= From: Tomi Valkeinen To: Laurent Pinchart , Kieran Bingham , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org Cc: Koji Matsuoka , LUU HOAI , Tomi Valkeinen Subject: [PATCH 3/6] drm: rcar-du: Fix LVDS stop sequence Date: Tue, 17 Jan 2023 15:51:51 +0200 Message-Id: <20230117135154.387208-4-tomi.valkeinen+renesas@ideasonboard.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> References: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Koji Matsuoka According to H/W manual, LVDCR0 register must be cleared bit by bit when disabling LVDS. Signed-off-by: Koji Matsuoka Signed-off-by: LUU HOAI [tomi.valkeinen: simplified the code a bit] Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/rcar-du/rcar_lvds.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c index 674b727cdaa2..01800cef1c33 100644 --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c @@ -87,6 +87,11 @@ static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data) iowrite32(data, lvds->mmio + reg); } +static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg) +{ + return ioread32(lvds->mmio + reg); +} + /* ----------------------------------------------------------------------------- * PLL Setup */ @@ -549,8 +554,28 @@ static void rcar_lvds_atomic_disable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state) { struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); + u32 lvdcr0; + + lvdcr0 = rcar_lvds_read(lvds, LVDCR0); + + lvdcr0 &= ~LVDCR0_LVRES; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + + if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) { + lvdcr0 &= ~LVDCR0_LVEN; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + } + + if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) { + lvdcr0 &= ~LVDCR0_PWD; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + } + + if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) { + lvdcr0 &= ~LVDCR0_PLLON; + rcar_lvds_write(lvds, LVDCR0, lvdcr0); + } - rcar_lvds_write(lvds, LVDCR0, 0); rcar_lvds_write(lvds, LVDCR1, 0); rcar_lvds_write(lvds, LVDPLLCR, 0); From patchwork Tue Jan 17 13:51:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 13104693 X-Patchwork-Delegate: kieran@bingham.xyz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD198C678D4 for ; Tue, 17 Jan 2023 13:53:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230126AbjAQNxv (ORCPT ); Tue, 17 Jan 2023 08:53:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230421AbjAQNxH (ORCPT ); Tue, 17 Jan 2023 08:53:07 -0500 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DC30367C9 for ; Tue, 17 Jan 2023 05:52:18 -0800 (PST) Received: from desky.lan (91-154-32-225.elisa-laajakaista.fi [91.154.32.225]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id D94ED9B4; Tue, 17 Jan 2023 14:52:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1673963535; bh=nwNb+R2m8O+B0Ore4iFPAO4AUuomuoYhlVe81JT742c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CXYTgyRQphLWuchct4JoHz6i3rcKVkh0b8fOARBqptxIa/sYLEWfmT7hm12p/k0l8 jYqqisgjPzquXR1STKGkB/jTNLwWiDqMAg6LUEIOHuYQanf7eZPtjlkpLzfOzqd8kD XoenqrPSPUojfeZh+e2pU9GAj1/wHiWsVIlPl800= From: Tomi Valkeinen To: Laurent Pinchart , Kieran Bingham , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org Cc: Tomi Valkeinen Subject: [PATCH 4/6] drm: rcar-du: Add quirk for H3 ES1 pclk WA Date: Tue, 17 Jan 2023 15:51:52 +0200 Message-Id: <20230117135154.387208-5-tomi.valkeinen+renesas@ideasonboard.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> References: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org rcar_du_crtc.c does a soc_device_match() in rcar_du_crtc_set_display_timing() to find out if the SoC is H3 ES1, and if so, apply a WA. We will need another H3 ES1 check in the following patch, so rather than adding more soc_device_match() calls, let's add a rcar_du_device_info entry for the ES1, and a quirk flag, RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY, for the WA. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 8 +--- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 51 +++++++++++++++++++++++++- drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 + 3 files changed, 52 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 3619e1ddeb62..f2d3266509cc 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include @@ -204,11 +203,6 @@ static void rcar_du_escr_divider(struct clk *clk, unsigned long target, } } -static const struct soc_device_attribute rcar_du_r8a7795_es1[] = { - { .soc_id = "r8a7795", .revision = "ES1.*" }, - { /* sentinel */ } -}; - static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) { const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode; @@ -238,7 +232,7 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) * no post-divider when a display PLL is present (as shown by * the workaround breaking HDMI output on M3-W during testing). */ - if (soc_device_match(rcar_du_r8a7795_es1)) { + if (rcdu->info->quirks & RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY) { target *= 2; div = 1; } diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index c7c5217cfc1a..ba2e069fc0f7 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -386,6 +387,42 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = { .dpll_mask = BIT(2) | BIT(1), }; +static const struct rcar_du_device_info rcar_du_r8a7795_es1_info = { + .gen = 3, + .features = RCAR_DU_FEATURE_CRTC_IRQ + | RCAR_DU_FEATURE_CRTC_CLOCK + | RCAR_DU_FEATURE_VSP1_SOURCE + | RCAR_DU_FEATURE_INTERLACED + | RCAR_DU_FEATURE_TVM_SYNC, + .quirks = RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY, + .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), + .routes = { + /* + * R8A7795 has one RGB output, two HDMI outputs and one + * LVDS output. + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(3), + .port = 0, + }, + [RCAR_DU_OUTPUT_HDMI0] = { + .possible_crtcs = BIT(1), + .port = 1, + }, + [RCAR_DU_OUTPUT_HDMI1] = { + .possible_crtcs = BIT(2), + .port = 2, + }, + [RCAR_DU_OUTPUT_LVDS0] = { + .possible_crtcs = BIT(0), + .port = 3, + }, + }, + .num_lvds = 1, + .num_rpf = 5, + .dpll_mask = BIT(2) | BIT(1), +}; + static const struct rcar_du_device_info rcar_du_r8a7796_info = { .gen = 3, .features = RCAR_DU_FEATURE_CRTC_IRQ @@ -576,6 +613,11 @@ static const struct of_device_id rcar_du_of_table[] = { MODULE_DEVICE_TABLE(of, rcar_du_of_table); +static const struct soc_device_attribute rcar_du_soc_table[] = { + { .soc_id = "r8a7795", .revision = "ES1.*", .data = &rcar_du_r8a7795_es1_info }, + { /* sentinel */ } +}; + const char *rcar_du_output_name(enum rcar_du_output output) { static const char * const names[] = { @@ -670,6 +712,7 @@ static int rcar_du_probe(struct platform_device *pdev) struct rcar_du_device *rcdu; unsigned int mask; int ret; + const struct soc_device_attribute *soc_attr; if (drm_firmware_drivers_only()) return -ENODEV; @@ -681,7 +724,13 @@ static int rcar_du_probe(struct platform_device *pdev) return PTR_ERR(rcdu); rcdu->dev = &pdev->dev; - rcdu->info = of_device_get_match_data(rcdu->dev); + + soc_attr = soc_device_match(rcar_du_soc_table); + if (soc_attr) + rcdu->info = soc_attr->data; + + if (!rcdu->info) + rcdu->info = of_device_get_match_data(rcdu->dev); platform_set_drvdata(pdev, rcdu); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h index 5cfa2bb7ad93..df87ccab146f 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h @@ -34,6 +34,7 @@ struct rcar_du_device; #define RCAR_DU_FEATURE_NO_BLENDING BIT(5) /* PnMR.SPIM does not have ALP nor EOR bits */ #define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */ +#define RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY BIT(1) /* H3 ES1 has pclk stability issue */ enum rcar_du_output { RCAR_DU_OUTPUT_DPAD0, From patchwork Tue Jan 17 13:51:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 13104695 X-Patchwork-Delegate: kieran@bingham.xyz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E40CC63797 for ; Tue, 17 Jan 2023 13:53:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229578AbjAQNxx (ORCPT ); Tue, 17 Jan 2023 08:53:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231200AbjAQNxH (ORCPT ); Tue, 17 Jan 2023 08:53:07 -0500 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 596F9367D0 for ; Tue, 17 Jan 2023 05:52:19 -0800 (PST) Received: from desky.lan (91-154-32-225.elisa-laajakaista.fi [91.154.32.225]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 6323410C; Tue, 17 Jan 2023 14:52:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1673963535; bh=9zJMA+T0kpeqlThAXlVjsVpNsaP+x+3i5UuNerWj0QE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fra4FbYR8Z+i/rXDTefhCcOYvEUfLfOiIWvx8SYJwsOtgVoQTc8hLGGMl3ZE0IMlM l9r9dba8UjK92pMy6WZzt8gwgP6a3StgrSruu1r/hk4OAYdaM3IodPhvrUV7bR9os8 G7n5zq4tW1jbnsKBMoBTPRuGKUtuYqYSpxttmuWg= From: Tomi Valkeinen To: Laurent Pinchart , Kieran Bingham , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org Cc: Tomi Valkeinen Subject: [PATCH 5/6] drm: rcar-du: Fix setting a reserved bit in DPLLCR Date: Tue, 17 Jan 2023 15:51:53 +0200 Message-Id: <20230117135154.387208-6-tomi.valkeinen+renesas@ideasonboard.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> References: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org On H3 ES1 two bits in DPLLCR are used to select the DU input dot clock source. These are bits 20 and 21 for DU2, and bits 22 and 23 for DU1. On non-ES1, only the higher bits are used (bits 21 and 23), and the lower bits are reserved and should be set to 0 (or not set at all). The current code always sets the lower bits, even on non-ES1. For both DU1 and DU2, on all SoC versions, when writing zeroes to those bits the input clock is DCLKIN, and thus there's no difference between ES1 and non-ES1. For DU1, writing 0b10 to the bits (or only writing the higher bit) results in using PLL0 as the input clock, so in this case there's also no difference between ES1 and non-ES1. However, for DU2, writing 0b10 to the bits results in using PLL0 as the input clock on ES1, whereas on non-ES1 it results in using PLL1. On ES1 you need to write 0b11 to select PLL1. The current code always writes 0b11 to PLCS0 field to select PLL1 on all SoC versions, which works but causes an illegal (in the sense of not allowed by the documentation) write to a reserved bit field. To remove the illegal bit write on PLSC0 we need to handle the input dot clock selection differently for ES1 and non-ES1. Add a new quirk, RCAR_DU_QUIRK_H3_ES1_PLL, for this, and a new rcar_du_device_info entry for the ES1 SoC. Using these, we can always set the bit 21 on PLSC0 when choosing the PLL as the source clock, and additionally set the bit 20 when on ES1. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 12 ++++++++++-- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 3 ++- drivers/gpu/drm/rcar-du/rcar_du_drv.h | 1 + drivers/gpu/drm/rcar-du/rcar_du_regs.h | 3 ++- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index f2d3266509cc..8d660a6141bf 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -245,12 +245,20 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) | DPLLCR_STBY; - if (rcrtc->index == 1) + if (rcrtc->index == 1) { dpllcr |= DPLLCR_PLCS1 | DPLLCR_INCS_DOTCLKIN1; - else + } else { dpllcr |= DPLLCR_PLCS0 | DPLLCR_INCS_DOTCLKIN0; + /* + * On H3 ES1.x, in addition to setting bit 21 (PLCS0), + * also bit 20 has to be set to select PLL1 as the + * clock source. + */ + if (rcdu->info->quirks & RCAR_DU_QUIRK_H3_ES1_PLL) + dpllcr |= DPLLCR_PLCS0_H3ES1X_PLL1_SEL; + } rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index ba2e069fc0f7..d689f2510081 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -394,7 +394,8 @@ static const struct rcar_du_device_info rcar_du_r8a7795_es1_info = { | RCAR_DU_FEATURE_VSP1_SOURCE | RCAR_DU_FEATURE_INTERLACED | RCAR_DU_FEATURE_TVM_SYNC, - .quirks = RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY, + .quirks = RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY + | RCAR_DU_QUIRK_H3_ES1_PLL, .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0), .routes = { /* diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h index df87ccab146f..acc3673fefe1 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h @@ -35,6 +35,7 @@ struct rcar_du_device; #define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */ #define RCAR_DU_QUIRK_H3_ES1_PCLK_STABILITY BIT(1) /* H3 ES1 has pclk stability issue */ +#define RCAR_DU_QUIRK_H3_ES1_PLL BIT(2) /* H3 ES1 PLL setup differs from non-ES1 */ enum rcar_du_output { RCAR_DU_OUTPUT_DPAD0, diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h index c1bcb0e8b5b4..94d913f66c8f 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h @@ -288,7 +288,8 @@ * isn't implemented by other SoC in the Gen3 family it can safely be set * unconditionally. */ -#define DPLLCR_PLCS0 (3 << 20) +#define DPLLCR_PLCS0 (1 << 21) +#define DPLLCR_PLCS0_H3ES1X_PLL1_SEL (1 << 20) #define DPLLCR_CLKE (1 << 18) #define DPLLCR_FDPLL(n) ((n) << 12) #define DPLLCR_N(n) ((n) << 5) From patchwork Tue Jan 17 13:51:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 13104692 X-Patchwork-Delegate: kieran@bingham.xyz Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6561BC678D8 for ; Tue, 17 Jan 2023 13:53:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229695AbjAQNxs (ORCPT ); Tue, 17 Jan 2023 08:53:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229648AbjAQNxH (ORCPT ); Tue, 17 Jan 2023 08:53:07 -0500 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FD833CE01 for ; Tue, 17 Jan 2023 05:52:20 -0800 (PST) Received: from desky.lan (91-154-32-225.elisa-laajakaista.fi [91.154.32.225]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id E38D0D82; Tue, 17 Jan 2023 14:52:15 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1673963536; bh=LdgNO4mlS+bDhCW6ZYK8PP12dsBSr+UsUcfX9WmNzf8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bueo1NttkH2NIz6B3rUHM82uW1AuE2dulOctORJFSZp/iatiw1zV/ESmdjw/i14a1 tWim98wkisChMgFK62+SkEteZNXlc/PuVXXgGWv1Jvzo5h3fB77Vg/SgmyXxMrYhSi oUgKweQR0MfUdmftqjKCp6whuqzIe4QEGFtuqgUg= From: Tomi Valkeinen To: Laurent Pinchart , Kieran Bingham , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org Cc: Tomi Valkeinen Subject: [PATCH 6/6] drm: rcar-du: Stop accessing non-existant registers on gen4 Date: Tue, 17 Jan 2023 15:51:54 +0200 Message-Id: <20230117135154.387208-7-tomi.valkeinen+renesas@ideasonboard.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> References: <20230117135154.387208-1-tomi.valkeinen+renesas@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org The following registers do not exist on gen4, so we should not write them: DEF6Rm, DEF8Rm, ESCRn, OTARn. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 8 +++++--- drivers/gpu/drm/rcar-du/rcar_du_group.c | 6 ++++-- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 8d660a6141bf..56b23333993c 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -289,10 +289,12 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) escr = params.escr; } - dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr); + if (rcdu->info->gen < 4) { + dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr); - rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr); - rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0); + rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr); + rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0); + } /* Signal polarities */ dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index 6da01760ede5..c236e2aa8a01 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -148,7 +148,8 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) } rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5); - rcar_du_group_setup_pins(rgrp); + if (rcdu->info->gen < 4) + rcar_du_group_setup_pins(rgrp); /* * TODO: Handle routing of the DU output to CMM dynamically, as we @@ -160,7 +161,8 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) rcar_du_group_write(rgrp, DEFR7, defr7); if (rcdu->info->gen >= 2) { - rcar_du_group_setup_defr8(rgrp); + if (rcdu->info->gen < 4) + rcar_du_group_setup_defr8(rgrp); rcar_du_group_setup_didsr(rgrp); }