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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 01/11] xen/ns16550: Remove unneeded truncation check in the DT init code Date: Tue, 17 Jan 2023 17:43:48 +0000 Message-ID: <20230117174358.15344-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT110:EE_|DM6PR12MB4548:EE_ X-MS-Office365-Filtering-Correlation-Id: ef8f7b73-a161-45c4-ea0d-08daf8b2911b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: F7hWv/vho/RRk/vtgb5mfAOPpDbXN3M+/UnYIJ6AZgnhJx0cT1Bm4gIzHZRmqxPztiDUtbCf48PauaK0I6GpTb4TrJE8pdm8GovL0EPHCKLiwT9KzDRwjawIgmHinAwzSfRMOg5ZVO2ifIq0RVNJ9RQR27cRq8/yBig2Ujugd73b8VTmNmverjAiR4/0pbnflKy7ZnzXXSzQd+TOkrCPERbds5yRaonEj6SZS+wa6IpcMpVdxbzbeef4qibwk3b92rWxsBnAarUC37q/mq+YeRC+++HnWQYYjemJNP+LNDFgYRZkESluCB9fc4csA4WKBftts0sNYytF7TeUQ5uKjP8+EKODhGQl6f5f07SzOKyclBVMm0tpZfktStDE62rftHda68deQ7J8lriinLfP9NRnWU3I3x25ust/ungmUUj3sYjZHC1XsPiQv4HPVNXzkSKV2AteaDPcrVhmv9Yx1MDzzMEPAOWKGg8AORno6nzU13/LzS1fJnPPFh0WQ8lIRyK6zVDGwIYFmlkAxEAYO9lUfOPaC5Aa6bxBnJoXXkT0HE5h3QsP/dwVK5dwWi71letTmLjcLfTFEIm+I5RmC9A1z7SF3uwZ4irmZaHxx36b7lZLoDaFe0XPeWbT2AFPDaq6pfArfXVUemgXzCujql68bjCN5E1u/990dZgrYMt+k5UC2KRL0EabLflkhdNi7E+equbJBoj2D7IFIWWAhh5CeyQUVwZ7hwLbcm2s0f0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(39860400002)(136003)(376002)(346002)(451199015)(46966006)(36840700001)(40470700004)(6666004)(6916009)(70206006)(336012)(478600001)(186003)(83380400001)(26005)(4326008)(8936002)(47076005)(41300700001)(5660300002)(2906002)(36860700001)(426003)(8676002)(36756003)(82740400003)(70586007)(82310400005)(356005)(40480700001)(103116003)(81166007)(316002)(1076003)(86362001)(2616005)(54906003)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 17:45:04.7958 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef8f7b73-a161-45c4-ea0d-08daf8b2911b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT110.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4548 In an earlier commit (7c1de0038895), "ns16550.io_size" was u32 and "io_size" was u64. Thus, the ASSERT() was needed to check if the values are the same. However, in a later commit (c9f8e0aee507), "ns16550.io_size" was changed to u64. Thus, the ASSERT() became redundant. So, now as "io_size" and "uart->io_size" are both u64, there will be no truncation. Thus, one can remove the ASSERT() and extra assignment. Signed-off-by: Ayan Kumar Halder Reviewed-by: Jan Beulich --- Changes from : v1 - 1. Updated commit message/title. 2. Added Rb. xen/drivers/char/ns16550.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 01a05c9aa8..58d0ccd889 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1747,7 +1747,6 @@ static int __init ns16550_uart_dt_init(struct dt_device_node *dev, struct ns16550 *uart; int res; u32 reg_shift, reg_width; - u64 io_size; uart = &ns16550_com[0]; @@ -1758,14 +1757,10 @@ static int __init ns16550_uart_dt_init(struct dt_device_node *dev, uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &uart->io_base, &io_size); + res = dt_device_get_address(dev, 0, &uart->io_base, &uart->io_size); if ( res ) return res; - uart->io_size = io_size; - - ASSERT(uart->io_size == io_size); /* Detect truncation */ - res = dt_property_read_u32(dev, "reg-shift", ®_shift); if ( !res ) uart->reg_shift = 0; From patchwork Tue Jan 17 17:43:49 2023 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 02/11] xen/arm: Use the correct format specifier Date: Tue, 17 Jan 2023 17:43:49 +0000 Message-ID: <20230117174358.15344-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT099:EE_|SJ0PR12MB6711:EE_ X-MS-Office365-Filtering-Correlation-Id: caf5fa31-0dad-4921-9d95-08daf8b29277 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 83tzEEaKGpH2lT3YXC7K1VuXRUPey+l2KjDutukA8VUAT03mS+dOpaZy/7DF7wU7VF5A9/ohujfc1kaXKZC+He0XpqF4uR3OtAUCMcUfG/FIe0nRCWYKmug+kdPZiJ/wRlOocQ71soMlZe9yxWpUKF+Eh1zgkvmPgpfL4oR0CwFYL/ESFNr4z70K2ctAs13baB8F+J6Gh0255glhhzbDKnx+BLNSuQasrQCpqbEVfVmYJwp9QeYbpm0FAWE4z2YDtcuGSsKSoBJm7Obc062ZAm5aUv+ypwGr1pNfn6ICBQXQ5q/9DRR2KR7LoQ++EQ/2nTzO5HyYgxS+n6XahINrCoCrV09dtEZChSBFAKLhSRbAjqCmMtNU0Txrr0hFh32Xqdpv5sl1Rg/0LbE1gmuD/j4wI9+AwkZ8H8uFXbYWiCTqmOXkR/nCYHxUcKGu1nJY4B5EmZZtYWraP6bvNAgR5nHVHlyTkecBrhPSjtzeTQlhseIpTPUz5dR+OgPHAs3aHaqPaDuXaAi7ikkHtRwQ6ce2cTEQQKQvUUTs5efYoAdn1Bm5leExgOxm+JwWl6EtaHMg2L6IQLAxRV4qmc1ALRCBD7jE5hPM2SkxXbWior9AFr9Qglp3P9MaNcxlYQXXNxaeaXwnIQDFXGw/GJkAStxD23iMNaCLi8oAqtf5kyv4Fsn/7GQWIOdBpgoO/4yWqRfxu8RtGxVZqTAULNoku8bTVx4ArYb4xaE9G7fOH+g= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(39860400002)(396003)(346002)(451199015)(40470700004)(36840700001)(46966006)(5660300002)(36756003)(40460700003)(41300700001)(36860700001)(8936002)(103116003)(26005)(186003)(82740400003)(478600001)(336012)(83380400001)(2616005)(1076003)(47076005)(82310400005)(6666004)(54906003)(426003)(316002)(356005)(4326008)(86362001)(8676002)(70206006)(6916009)(81166007)(70586007)(40480700001)(2906002)(36900700001);DIR:OUT;SFP:1101; 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One should use 'PRIpaddr' to display 'paddr_t' variables. 2. One should use 'PRIx64' to display 'u64' in hex format. The current use of 'PRIpaddr' for printing PTE is buggy as this is not a physical address. Signed-off-by: Ayan Kumar Halder Reviewed-by: Stefano Stabellini --- Changes from - v1 - 1. Moved the patch earlier. 2. Moved a part of change from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr" into this patch. xen/arch/arm/domain_build.c | 10 +++++----- xen/arch/arm/gic-v2.c | 6 +++--- xen/arch/arm/mm.c | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 829cea8de8..33a5945a2d 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1315,7 +1315,7 @@ static int __init make_memory_node(const struct domain *d, dt_dprintk("Create memory node\n"); /* ePAPR 3.4 */ - snprintf(buf, sizeof(buf), "memory@%"PRIx64, mem->bank[i].start); + snprintf(buf, sizeof(buf), "memory@%"PRIpaddr, mem->bank[i].start); res = fdt_begin_node(fdt, buf); if ( res ) return res; @@ -1383,7 +1383,7 @@ static int __init make_shm_memory_node(const struct domain *d, __be32 *cells; unsigned int len = (addrcells + sizecells) * sizeof(__be32); - snprintf(buf, sizeof(buf), "xen-shmem@%"PRIx64, mem->bank[i].start); + snprintf(buf, sizeof(buf), "xen-shmem@%"PRIpaddr, mem->bank[i].start); res = fdt_begin_node(fdt, buf); if ( res ) return res; @@ -2719,7 +2719,7 @@ static int __init make_gicv2_domU_node(struct kernel_info *kinfo) /* Placeholder for interrupt-controller@ + a 64-bit number + \0 */ char buf[38]; - snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIx64, + snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIpaddr, vgic_dist_base(&d->arch.vgic)); res = fdt_begin_node(fdt, buf); if ( res ) @@ -2775,7 +2775,7 @@ static int __init make_gicv3_domU_node(struct kernel_info *kinfo) char buf[38]; unsigned int i, len = 0; - snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIx64, + snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIpaddr, vgic_dist_base(&d->arch.vgic)); res = fdt_begin_node(fdt, buf); @@ -2861,7 +2861,7 @@ static int __init make_vpl011_uart_node(struct kernel_info *kinfo) /* Placeholder for sbsa-uart@ + a 64-bit number + \0 */ char buf[27]; - snprintf(buf, sizeof(buf), "sbsa-uart@%"PRIx64, d->arch.vpl011.base_addr); + snprintf(buf, sizeof(buf), "sbsa-uart@%"PRIpaddr, d->arch.vpl011.base_addr); res = fdt_begin_node(fdt, buf); if ( res ) return res; diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 61802839cb..5d4d298b86 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -1049,7 +1049,7 @@ static void __init gicv2_dt_init(void) if ( csize < SZ_8K ) { printk(XENLOG_WARNING "GICv2: WARNING: " - "The GICC size is too small: %#"PRIx64" expected %#x\n", + "The GICC size is too small: %#"PRIpaddr" expected %#x\n", csize, SZ_8K); if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) ) { @@ -1280,11 +1280,11 @@ static int __init gicv2_init(void) gicv2.map_cbase += aliased_offset; printk(XENLOG_WARNING - "GICv2: Adjusting CPU interface base to %#"PRIx64"\n", + "GICv2: Adjusting CPU interface base to %#"PRIpaddr"\n", cbase + aliased_offset); } else if ( csize == SZ_128K ) printk(XENLOG_WARNING - "GICv2: GICC size=%#"PRIx64" but not aliased\n", + "GICv2: GICC size=%#"PRIpaddr" but not aliased\n", csize); gicv2.map_hbase = ioremap_nocache(hbase, PAGE_SIZE); diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index 0fc6f2992d..fab54618ab 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -249,7 +249,7 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr, pte = mapping[offsets[level]]; - printk("%s[0x%03x] = 0x%"PRIpaddr"\n", + printk("%s[0x%03x] = 0x%"PRIx64"\n", level_strs[level], offsets[level], pte.bits); if ( level == 3 || !pte.walk.valid || !pte.walk.table ) From patchwork Tue Jan 17 17:43:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13104941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CAF5C677F1 for ; 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bh=pYKh2ZpT1JIDy592j7PXcRkkm4hFksMRdjO4SCJ7TpY=; b=IPGdLr2g8jW7hUYBMMSzi68G7E1sm1cRH4WIX6n5xirqovHGq4CNGLgIIfpCkOkIBn3my1SWe5gXceoAUhUAR1l/U1VTwYp+GmkecTSCbqWkKjYkCf+0UpxHMUeUuOtxnfJyECr34LTW8ZkYxlveoloaGfccilE4cNQz+wGRzB4= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 03/11] xen/arm: domain_build: Replace use of paddr_t in find_domU_holes() Date: Tue, 17 Jan 2023 17:43:50 +0000 Message-ID: <20230117174358.15344-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT091:EE_|PH7PR12MB6489:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d411da9-0977-475b-90d2-08daf8b29389 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 17:45:08.8698 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4d411da9-0977-475b-90d2-08daf8b29389 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT091.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6489 bankbase, banksize and bankend are used to hold values of type 'unsigned long long'. This can be represented as 'uint64_t' instead of 'paddr_t'. This will ensure consistency with allocate_static_memory() (where we use 'uint64_t' for rambase and ramsize). In future, paddr_t can be used for 'uin32_t' as well to represent 32bit physical addresses. Signed-off-by: Ayan Kumar Halder Acked-by: Stefano Stabellini --- Changes from - v1 - Modified the title/commit message from "[XEN v1 6/9] xen/arm: Use 'u64' to represent 'unsigned long long" and moved it earlier. xen/arch/arm/domain_build.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 33a5945a2d..f904f12408 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1726,9 +1726,9 @@ static int __init find_domU_holes(const struct kernel_info *kinfo, struct meminfo *ext_regions) { unsigned int i; - paddr_t bankend; - const paddr_t bankbase[] = GUEST_RAM_BANK_BASES; - const paddr_t banksize[] = GUEST_RAM_BANK_SIZES; + uint64_t bankend; + const uint64_t bankbase[] = GUEST_RAM_BANK_BASES; + const uint64_t banksize[] = GUEST_RAM_BANK_SIZES; int res = -ENOENT; for ( i = 0; i < GUEST_RAM_BANKS; i++ ) From patchwork Tue Jan 17 17:43:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13104942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 57DEAC54E76 for ; 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bh=vkQVewwIqXR9Op0ttYXasbtHBsayU2os3eE5hDirBvk=; b=N+749NBDsQndCdGQprdG18U2/zH7ULvaxiouy8Hv1GWcU30Y2v53MOMC3mQKY8mTZf2QjWiHN0ugmyV+ERXaa391oezfW2S7ETee80u1eu8Hx7XOAETOStJj4VEhzOZmOkD4sH0nGKwBSL2bbWWmgbu6yvde6HwZBxki16Zh3/c= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 04/11] xen/arm: Typecast the DT values into paddr_t Date: Tue, 17 Jan 2023 17:43:51 +0000 Message-ID: <20230117174358.15344-5-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT040:EE_|DS0PR12MB7748:EE_ X-MS-Office365-Filtering-Correlation-Id: 08810278-fe2d-4d21-a9ab-08daf8b294bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 17:45:10.9227 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 08810278-fe2d-4d21-a9ab-08daf8b294bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7748 In future, we wish to support 32 bit physical address. However, one can only read u64 values from the DT. Thus, we need to typecast the values appropriately from u64 to paddr_t. device_tree_get_reg() should now be able to return paddr_t. This is invoked by various callers to get DT address and size. Similarly, dt_read_number() is invoked as well to get DT address and size. The return value is typecasted to paddr_t. fdt_get_mem_rsv() can only accept u64 values. So, we provide a warpper for this called fdt_get_mem_rsv_paddr() which will do the necessary typecasting before invoking fdt_get_mem_rsv() and while returning. Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. Dropped "[XEN v1 2/9] xen/arm: Define translate_dt_address_size() for the translation between u64 and paddr_t" and "[XEN v1 4/9] xen/arm: Use translate_dt_address_size() to translate between device tree addr/size and paddr_t", instead this approach achieves the same purpose. 2. No need to check for truncation while converting values from u64 to paddr_t. xen/arch/arm/bootfdt.c | 23 +++++++++------ xen/arch/arm/domain_build.c | 2 +- xen/arch/arm/include/asm/device_tree.h | 40 ++++++++++++++++++++++++++ xen/arch/arm/include/asm/setup.h | 2 +- xen/arch/arm/setup.c | 14 ++++----- xen/arch/arm/smpboot.c | 2 +- 6 files changed, 65 insertions(+), 18 deletions(-) create mode 100644 xen/arch/arm/include/asm/device_tree.h diff --git a/xen/arch/arm/bootfdt.c b/xen/arch/arm/bootfdt.c index 0085c28d74..f536a3f3ab 100644 --- a/xen/arch/arm/bootfdt.c +++ b/xen/arch/arm/bootfdt.c @@ -11,9 +11,9 @@ #include #include #include -#include #include #include +#include #include static bool __init device_tree_node_matches(const void *fdt, int node, @@ -53,10 +53,15 @@ static bool __init device_tree_node_compatible(const void *fdt, int node, } void __init device_tree_get_reg(const __be32 **cell, u32 address_cells, - u32 size_cells, u64 *start, u64 *size) + u32 size_cells, paddr_t *start, paddr_t *size) { - *start = dt_next_cell(address_cells, cell); - *size = dt_next_cell(size_cells, cell); + /* + * dt_next_cell will return u64 whereas paddr_t may be u64 or u32. Thus, one + * needs to cast paddr_t to u32. Note that we do not check for truncation as + * it is user's responsibility to provide the correct values in the DT. + */ + *start = (paddr_t) dt_next_cell(address_cells, cell); + *size = (paddr_t) dt_next_cell(size_cells, cell); } static int __init device_tree_get_meminfo(const void *fdt, int node, @@ -326,7 +331,7 @@ static int __init process_chosen_node(const void *fdt, int node, printk("linux,initrd-start property has invalid length %d\n", len); return -EINVAL; } - start = dt_read_number((void *)&prop->data, dt_size_to_cells(len)); + start = (paddr_t) dt_read_number((void *)&prop->data, dt_size_to_cells(len)); prop = fdt_get_property(fdt, node, "linux,initrd-end", &len); if ( !prop ) @@ -339,7 +344,7 @@ static int __init process_chosen_node(const void *fdt, int node, printk("linux,initrd-end property has invalid length %d\n", len); return -EINVAL; } - end = dt_read_number((void *)&prop->data, dt_size_to_cells(len)); + end = (paddr_t) dt_read_number((void *)&prop->data, dt_size_to_cells(len)); if ( start >= end ) { @@ -594,9 +599,11 @@ static void __init early_print_info(void) for ( i = 0; i < nr_rsvd; i++ ) { paddr_t s, e; - if ( fdt_get_mem_rsv(device_tree_flattened, i, &s, &e) < 0 ) + + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, i, &s, &e) < 0 ) continue; - /* fdt_get_mem_rsv returns length */ + + /* fdt_get_mem_rsv_paddr returns length */ e += s; printk(" RESVD[%u]: %"PRIpaddr" - %"PRIpaddr"\n", i, s, e); } diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index f904f12408..72b9afbb4c 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -949,7 +949,7 @@ static int __init process_shm(struct domain *d, struct kernel_info *kinfo, BUG_ON(!prop); cells = (const __be32 *)prop->value; device_tree_get_reg(&cells, addr_cells, addr_cells, &pbase, &gbase); - psize = dt_read_number(cells, size_cells); + psize = (paddr_t) dt_read_number(cells, size_cells); if ( !IS_ALIGNED(pbase, PAGE_SIZE) || !IS_ALIGNED(gbase, PAGE_SIZE) ) { printk("%pd: physical address 0x%"PRIpaddr", or guest address 0x%"PRIpaddr" is not suitably aligned.\n", diff --git a/xen/arch/arm/include/asm/device_tree.h b/xen/arch/arm/include/asm/device_tree.h new file mode 100644 index 0000000000..51e0f0ae20 --- /dev/null +++ b/xen/arch/arm/include/asm/device_tree.h @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * xen/arch/arm/include/asm/device_tree.h + * + * Wrapper functions for device tree. This helps to convert dt values + * between u64 and paddr_t. + * + * Copyright (C) 2023, Advanced Micro Devices, Inc. All Rights Reserved. + */ + +#ifndef __ARCH_ARM_DEVICE_TREE__ +#define __ARCH_ARM_DEVICE_TREE__ + +#include + +inline int fdt_get_mem_rsv_paddr(const void *fdt, int n, + paddr_t *address, + paddr_t *size) +{ + uint64_t dt_addr; + uint64_t dt_size; + int ret = 0; + + ret = fdt_get_mem_rsv(fdt, n, &dt_addr, &dt_size); + + *address = (paddr_t) dt_addr; + *size = (paddr_t) dt_size; + + return ret; +} + +#endif /* __ARCH_ARM_DEVICE_TREE__ */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/setup.h b/xen/arch/arm/include/asm/setup.h index a926f30a2b..6105e5cae3 100644 --- a/xen/arch/arm/include/asm/setup.h +++ b/xen/arch/arm/include/asm/setup.h @@ -158,7 +158,7 @@ extern uint32_t hyp_traps_vector[]; void init_traps(void); void device_tree_get_reg(const __be32 **cell, u32 address_cells, - u32 size_cells, u64 *start, u64 *size); + u32 size_cells, paddr_t *start, paddr_t *size); u32 device_tree_get_u32(const void *fdt, int node, const char *prop_name, u32 dflt); diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 1f26f67b90..da13439e62 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include @@ -39,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -222,11 +222,11 @@ static void __init dt_unreserved_regions(paddr_t s, paddr_t e, { paddr_t r_s, r_e; - if ( fdt_get_mem_rsv(device_tree_flattened, i, &r_s, &r_e ) < 0 ) + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, i, &r_s, &r_e ) < 0 ) /* If we can't read it, pretend it doesn't exist... */ continue; - r_e += r_s; /* fdt_get_mem_rsv returns length */ + r_e += r_s; /* fdt_get_mem_rsv_paddr returns length */ if ( s < r_e && r_s < e ) { @@ -502,13 +502,13 @@ static paddr_t __init consider_modules(paddr_t s, paddr_t e, { paddr_t mod_s, mod_e; - if ( fdt_get_mem_rsv(device_tree_flattened, - i - mi->nr_mods, - &mod_s, &mod_e ) < 0 ) + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, + i - mi->nr_mods, + &mod_s, &mod_e ) < 0 ) /* If we can't read it, pretend it doesn't exist... */ continue; - /* fdt_get_mem_rsv returns length */ + /* fdt_get_mem_rsv_paddr returns length */ mod_e += mod_s; if ( s < mod_e && mod_s < e ) diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index 412ae22869..ee59b1d379 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -159,7 +159,7 @@ static void __init dt_smp_init_cpus(void) continue; } - addr = dt_read_number(prop, dt_n_addr_cells(cpu)); + addr = (paddr_t) dt_read_number(prop, dt_n_addr_cells(cpu)); hwid = addr; if ( hwid != addr ) From patchwork Tue Jan 17 17:43:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13104943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4CDDC3DA78 for ; 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bh=D93ZyLBoRJyeXnXktUxKPuF+KODu71JUMQB/vCvmEr0=; b=xk/3wIcN6Bk2fhiazUkYrqkYd+jALndxbPIrEJyRFsXi0Ue/NP7nc+loUmuD/XMocIRVkD7gvtqUqXMLy4Ms+BMh8yUkkoFQ7BC7c1fLdLoBEPoDfDMzvtxvzADO80auBBZ9MpbrPry88ooBv0H9aawojCt4F3OxSN6cHH9vGqg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 05/11] xen/arm: Use paddr_t instead of u64 for address/size Date: Tue, 17 Jan 2023 17:43:52 +0000 Message-ID: <20230117174358.15344-6-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT056:EE_|PH0PR12MB8007:EE_ X-MS-Office365-Filtering-Correlation-Id: f020d4bf-5c91-4f3f-1acc-08daf8b295d0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 17:45:12.7188 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f020d4bf-5c91-4f3f-1acc-08daf8b295d0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8007 One should now be able to use 'paddr_t' to represent address and size. Consequently, one should use 'PRIpaddr' as a format specifier for paddr_t. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. Rebased the patch. xen/arch/arm/domain_build.c | 9 +++++---- xen/arch/arm/gic-v3.c | 2 +- xen/arch/arm/platforms/exynos5.c | 26 +++++++++++++------------- xen/drivers/char/exynos4210-uart.c | 2 +- xen/drivers/char/ns16550.c | 8 ++++---- xen/drivers/char/omap-uart.c | 2 +- xen/drivers/char/pl011.c | 4 ++-- xen/drivers/char/scif-uart.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 6 +++--- 9 files changed, 31 insertions(+), 30 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 72b9afbb4c..cf8ae37a14 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1666,7 +1666,7 @@ static int __init find_memory_holes(const struct kernel_info *kinfo, dt_for_each_device_node( dt_host, np ) { unsigned int naddr; - u64 addr, size; + paddr_t addr, size; naddr = dt_number_of_address(np); @@ -2445,7 +2445,7 @@ static int __init handle_device(struct domain *d, struct dt_device_node *dev, unsigned int naddr; unsigned int i; int res; - u64 addr, size; + paddr_t addr, size; bool own_device = !dt_device_for_passthrough(dev); /* * We want to avoid mapping the MMIO in dom0 for the following cases: @@ -2941,9 +2941,10 @@ static int __init handle_passthrough_prop(struct kernel_info *kinfo, if ( res ) { printk(XENLOG_ERR "Unable to permit to dom%d access to" - " 0x%"PRIx64" - 0x%"PRIx64"\n", + " 0x%"PRIpaddr" - 0x%"PRIpaddr"\n", kinfo->d->domain_id, - mstart & PAGE_MASK, PAGE_ALIGN(mstart + size) - 1); + (paddr_t) (mstart & PAGE_MASK), + (paddr_t) (PAGE_ALIGN(mstart + size) - 1)); return res; } diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index bb59ea94cd..391dfa53d7 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1393,7 +1393,7 @@ static void __init gicv3_dt_init(void) for ( i = 0; i < gicv3.rdist_count; i++ ) { - uint64_t rdist_base, rdist_size; + paddr_t rdist_base, rdist_size; res = dt_device_get_address(node, 1 + i, &rdist_base, &rdist_size); if ( res ) diff --git a/xen/arch/arm/platforms/exynos5.c b/xen/arch/arm/platforms/exynos5.c index 6560507092..f79fad9957 100644 --- a/xen/arch/arm/platforms/exynos5.c +++ b/xen/arch/arm/platforms/exynos5.c @@ -42,8 +42,8 @@ static int exynos5_init_time(void) void __iomem *mct; int rc; struct dt_device_node *node; - u64 mct_base_addr; - u64 size; + paddr_t mct_base_addr; + paddr_t size; node = dt_find_compatible_node(NULL, NULL, "samsung,exynos4210-mct"); if ( !node ) @@ -59,7 +59,7 @@ static int exynos5_init_time(void) return -ENXIO; } - dprintk(XENLOG_INFO, "mct_base_addr: %016llx size: %016llx\n", + dprintk(XENLOG_INFO, "mct_base_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"\n", mct_base_addr, size); mct = ioremap_nocache(mct_base_addr, size); @@ -97,9 +97,9 @@ static int __init exynos5_smp_init(void) struct dt_device_node *node; void __iomem *sysram; char *compatible; - u64 sysram_addr; - u64 size; - u64 sysram_offset; + paddr_t sysram_addr; + paddr_t size; + paddr_t sysram_offset; int rc; node = dt_find_compatible_node(NULL, NULL, "samsung,secure-firmware"); @@ -131,7 +131,7 @@ static int __init exynos5_smp_init(void) dprintk(XENLOG_ERR, "Error in %s\n", compatible); return -ENXIO; } - dprintk(XENLOG_INFO, "sysram_addr: %016llx size: %016llx offset: %016llx\n", + dprintk(XENLOG_INFO,"sysram_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"offset: 0x%"PRIpaddr"\n", sysram_addr, size, sysram_offset); sysram = ioremap_nocache(sysram_addr, size); @@ -189,7 +189,7 @@ static int exynos5_cpu_power_up(void __iomem *power, int cpu) return 0; } -static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) +static int exynos5_get_pmu_baseandsize(paddr_t *power_base_addr, paddr_t *size) { struct dt_device_node *node; int rc; @@ -215,7 +215,7 @@ static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) return -ENXIO; } - dprintk(XENLOG_DEBUG, "power_base_addr: %016llx size: %016llx\n", + dprintk(XENLOG_DEBUG, "power_base_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"\n", *power_base_addr, *size); return 0; @@ -223,8 +223,8 @@ static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) static int exynos5_cpu_up(int cpu) { - u64 power_base_addr; - u64 size; + paddr_t power_base_addr; + paddr_t size; void __iomem *power; int rc; @@ -256,8 +256,8 @@ static int exynos5_cpu_up(int cpu) static void exynos5_reset(void) { - u64 power_base_addr; - u64 size; + paddr_t power_base_addr; + paddr_t size; void __iomem *pmu; int rc; diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos4210-uart.c index 43aaf02e18..32cc8c78b5 100644 --- a/xen/drivers/char/exynos4210-uart.c +++ b/xen/drivers/char/exynos4210-uart.c @@ -303,7 +303,7 @@ static int __init exynos4210_uart_init(struct dt_device_node *dev, const char *config = data; struct exynos4210_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 58d0ccd889..8ef895a2bb 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -42,8 +42,8 @@ static struct ns16550 { int baud, clock_hz, data_bits, parity, stop_bits, fifo_size, irq; - u64 io_base; /* I/O port or memory-mapped I/O address. */ - u64 io_size; + paddr_t io_base; /* I/O port or memory-mapped I/O address. */ + paddr_t io_size; int reg_shift; /* Bits to shift register offset by */ int reg_width; /* Size of access to use, the registers * themselves are still bytes */ @@ -1166,7 +1166,7 @@ static const struct ns16550_config __initconst uart_config[] = static int __init pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) { - u64 orig_base = uart->io_base; + paddr_t orig_base = uart->io_base; unsigned int b, d, f, nextf, i; /* NB. Start at bus 1 to avoid AMT: a plug-in card cannot be on bus 0. */ @@ -1259,7 +1259,7 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) else size = len & PCI_BASE_ADDRESS_MEM_MASK; - uart->io_base = ((u64)bar_64 << 32) | + uart->io_base = (paddr_t) ((u64)bar_64 << 32) | (bar & PCI_BASE_ADDRESS_MEM_MASK); } /* IO based */ diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c index d6a5d59aa2..3b53e1909a 100644 --- a/xen/drivers/char/omap-uart.c +++ b/xen/drivers/char/omap-uart.c @@ -324,7 +324,7 @@ static int __init omap_uart_init(struct dt_device_node *dev, struct omap_uart *uart; u32 clkspec; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index be67242bc0..256ec11e3f 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -222,7 +222,7 @@ static struct uart_driver __read_mostly pl011_driver = { .vuart_info = pl011_vuart, }; -static int __init pl011_uart_init(int irq, u64 addr, u64 size, bool sbsa) +static int __init pl011_uart_init(int irq, paddr_t addr, paddr_t size, bool sbsa) { struct pl011 *uart; @@ -258,7 +258,7 @@ static int __init pl011_dt_uart_init(struct dt_device_node *dev, { const char *config = data; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) { diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 2fccafe340..b425881d06 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -311,7 +311,7 @@ static int __init scif_uart_init(struct dt_device_node *dev, const char *config = data; struct scif_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 0a514821b3..490d253d44 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -73,8 +73,8 @@ /* Xen: Helpers to get device MMIO and IRQs */ struct resource { - u64 addr; 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bh=hBI9VqrGtClHg+8xIqkrnP/L1ZKhG2r8i7jBnpGNVWI=; b=3U+5t0MTlHq86NY2G1CMdGAubzCrZzk4zEoa6FRjFwnxXrB+LcLU7bZAXnhTBqVkd+rdJ+TjiXMIxy4F/H/iwqAqKN8f8wQIsmdrOLLq7Fc9/W0qtU18h63nFwEsyrcYCEdd/yll2Vyr29bj7qgy7wYZf90lIZTiLuhqT41iKks= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 06/11] xen/arm: Introduce a wrapper for dt_device_get_address() to handle paddr_t Date: Tue, 17 Jan 2023 17:43:53 +0000 Message-ID: <20230117174358.15344-7-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108EA:EE_|SN7PR12MB7107:EE_ X-MS-Office365-Filtering-Correlation-Id: 62c086d7-5878-4187-a977-08daf8b2975e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 17:45:15.3308 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62c086d7-5878-4187-a977-08daf8b2975e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7107 dt_device_get_address() can accept u64 only for address and size. The various callers will use 'paddr_t' datatype for address and size. 'paddr_t' is currently defined as u64, but we may support u32 as well. Thus, we need an appropriate wrapper which can handle this type conversion. The callers will now invoke dt_device_get_paddr(). This inturn invokes dt_device_get_address() with u64 address/size. And then it typecasts the u64 address/size to paddr_t address/size. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. New patch introduced. xen/arch/arm/domain_build.c | 5 +++-- xen/arch/arm/gic-v2.c | 11 ++++++----- xen/arch/arm/gic-v3.c | 9 +++++---- xen/arch/arm/include/asm/device_tree.h | 19 +++++++++++++++++++ xen/arch/arm/platforms/exynos5.c | 7 ++++--- xen/arch/arm/platforms/sunxi.c | 3 ++- xen/drivers/char/exynos4210-uart.c | 3 ++- xen/drivers/char/ns16550.c | 3 ++- xen/drivers/char/omap-uart.c | 3 ++- xen/drivers/char/pl011.c | 3 ++- xen/drivers/char/scif-uart.c | 3 ++- xen/drivers/passthrough/arm/smmu.c | 3 ++- 12 files changed, 51 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index cf8ae37a14..21199b624b 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1672,7 +1673,7 @@ static int __init find_memory_holes(const struct kernel_info *kinfo, for ( i = 0; i < naddr; i++ ) { - res = dt_device_get_address(np, i, &addr, &size); + res = dt_device_get_paddr(np, i, &addr, &size); if ( res ) { printk(XENLOG_ERR "Unable to retrieve address %u for %s\n", @@ -2500,7 +2501,7 @@ static int __init handle_device(struct domain *d, struct dt_device_node *dev, /* Give permission and map MMIOs */ for ( i = 0; i < naddr; i++ ) { - res = dt_device_get_address(dev, i, &addr, &size); + res = dt_device_get_paddr(dev, i, &addr, &size); if ( res ) { printk(XENLOG_ERR "Unable to retrieve address %u for %s\n", diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 5d4d298b86..5230c4ebaf 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -993,7 +994,7 @@ static void gicv2_extension_dt_init(const struct dt_device_node *node) continue; /* Get register frame resource from DT. */ - if ( dt_device_get_address(v2m, 0, &addr, &size) ) + if ( dt_device_get_paddr(v2m, 0, &addr, &size) ) panic("GICv2: Cannot find a valid v2m frame address\n"); /* @@ -1018,19 +1019,19 @@ static void __init gicv2_dt_init(void) paddr_t vsize; const struct dt_device_node *node = gicv2_info.node; - res = dt_device_get_address(node, 0, &dbase, NULL); + res = dt_device_get_paddr(node, 0, &dbase, NULL); if ( res ) panic("GICv2: Cannot find a valid address for the distributor\n"); - res = dt_device_get_address(node, 1, &cbase, &csize); + res = dt_device_get_paddr(node, 1, &cbase, &csize); if ( res ) panic("GICv2: Cannot find a valid address for the CPU\n"); - res = dt_device_get_address(node, 2, &hbase, NULL); + res = dt_device_get_paddr(node, 2, &hbase, NULL); if ( res ) panic("GICv2: Cannot find a valid address for the hypervisor\n"); - res = dt_device_get_address(node, 3, &vbase, &vsize); + res = dt_device_get_paddr(node, 3, &vbase, &vsize); if ( res ) panic("GICv2: Cannot find a valid address for the virtual CPU\n"); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 391dfa53d7..58d2eb0690 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -1377,7 +1378,7 @@ static void __init gicv3_dt_init(void) int res, i; const struct dt_device_node *node = gicv3_info.node; - res = dt_device_get_address(node, 0, &dbase, NULL); + res = dt_device_get_paddr(node, 0, &dbase, NULL); if ( res ) panic("GICv3: Cannot find a valid distributor address\n"); @@ -1395,7 +1396,7 @@ static void __init gicv3_dt_init(void) { paddr_t rdist_base, rdist_size; - res = dt_device_get_address(node, 1 + i, &rdist_base, &rdist_size); + res = dt_device_get_paddr(node, 1 + i, &rdist_base, &rdist_size); if ( res ) panic("GICv3: No rdist base found for region %d\n", i); @@ -1417,10 +1418,10 @@ static void __init gicv3_dt_init(void) * For GICv3 supporting GICv2, GICC and GICV base address will be * provided. */ - res = dt_device_get_address(node, 1 + gicv3.rdist_count, + res = dt_device_get_paddr(node, 1 + gicv3.rdist_count, &cbase, &csize); if ( !res ) - dt_device_get_address(node, 1 + gicv3.rdist_count + 2, + dt_device_get_paddr(node, 1 + gicv3.rdist_count + 2, &vbase, &vsize); } diff --git a/xen/arch/arm/include/asm/device_tree.h b/xen/arch/arm/include/asm/device_tree.h index 51e0f0ae20..7f58f1f278 100644 --- a/xen/arch/arm/include/asm/device_tree.h +++ b/xen/arch/arm/include/asm/device_tree.h @@ -11,6 +11,7 @@ #ifndef __ARCH_ARM_DEVICE_TREE__ #define __ARCH_ARM_DEVICE_TREE__ +#include #include inline int fdt_get_mem_rsv_paddr(const void *fdt, int n, @@ -29,6 +30,24 @@ inline int fdt_get_mem_rsv_paddr(const void *fdt, int n, return ret; } +inline int dt_device_get_paddr(const struct dt_device_node *dev, + unsigned int index, paddr_t *addr, + paddr_t *size) +{ + u64 dt_addr, dt_size; + int ret; + + ret = dt_device_get_address(dev, index, &dt_addr, &dt_size); + + if ( addr ) + *addr = dt_addr; + + if ( size ) + *size = dt_size; + + return ret; +} + #endif /* __ARCH_ARM_DEVICE_TREE__ */ /* * Local variables: diff --git a/xen/arch/arm/platforms/exynos5.c b/xen/arch/arm/platforms/exynos5.c index f79fad9957..55b6ac1e7e 100644 --- a/xen/arch/arm/platforms/exynos5.c +++ b/xen/arch/arm/platforms/exynos5.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -52,7 +53,7 @@ static int exynos5_init_time(void) return -ENXIO; } - rc = dt_device_get_address(node, 0, &mct_base_addr, &size); + rc = dt_device_get_paddr(node, 0, &mct_base_addr, &size); if ( rc ) { dprintk(XENLOG_ERR, "Error in \"samsung,exynos4210-mct\"\n"); @@ -125,7 +126,7 @@ static int __init exynos5_smp_init(void) return -ENXIO; } - rc = dt_device_get_address(node, 0, &sysram_addr, &size); + rc = dt_device_get_paddr(node, 0, &sysram_addr, &size); if ( rc ) { dprintk(XENLOG_ERR, "Error in %s\n", compatible); @@ -208,7 +209,7 @@ static int exynos5_get_pmu_baseandsize(paddr_t *power_base_addr, paddr_t *size) return -ENXIO; } - rc = dt_device_get_address(node, 0, power_base_addr, size); + rc = dt_device_get_paddr(node, 0, power_base_addr, size); if ( rc ) { dprintk(XENLOG_ERR, "Error in \"samsung,exynos5XXX-pmu\"\n"); diff --git a/xen/arch/arm/platforms/sunxi.c b/xen/arch/arm/platforms/sunxi.c index e8e4d88bef..ce47f97507 100644 --- a/xen/arch/arm/platforms/sunxi.c +++ b/xen/arch/arm/platforms/sunxi.c @@ -18,6 +18,7 @@ #include #include +#include #include #include @@ -50,7 +51,7 @@ static void __iomem *sunxi_map_watchdog(bool *new_wdt) return NULL; } - ret = dt_device_get_address(node, 0, &wdt_start, &wdt_len); + ret = dt_device_get_paddr(node, 0, &wdt_start, &wdt_len); if ( ret ) { dprintk(XENLOG_ERR, "Cannot read watchdog register address\n"); diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos4210-uart.c index 32cc8c78b5..6d2008c44f 100644 --- a/xen/drivers/char/exynos4210-uart.c +++ b/xen/drivers/char/exynos4210-uart.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -316,7 +317,7 @@ static int __init exynos4210_uart_init(struct dt_device_node *dev, uart->parity = PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("exynos4210: Unable to retrieve the base" diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 8ef895a2bb..7226f3c2f7 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -35,6 +35,7 @@ #include #ifdef CONFIG_HAS_DEVICE_TREE #include +#include #endif #ifdef CONFIG_X86 #include @@ -1757,7 +1758,7 @@ static int __init ns16550_uart_dt_init(struct dt_device_node *dev, uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &uart->io_base, &uart->io_size); + res = dt_device_get_paddr(dev, 0, &uart->io_base, &uart->io_size); if ( res ) return res; diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c index 3b53e1909a..06200bc9f1 100644 --- a/xen/drivers/char/omap-uart.c +++ b/xen/drivers/char/omap-uart.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -344,7 +345,7 @@ static int __init omap_uart_init(struct dt_device_node *dev, uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("omap-uart: Unable to retrieve the base" diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index 256ec11e3f..b4c1d9d592 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -265,7 +266,7 @@ static int __init pl011_dt_uart_init(struct dt_device_node *dev, printk("WARNING: UART configuration is not supported\n"); } - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("pl011: Unable to retrieve the base" diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index b425881d06..af14388f70 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -318,7 +319,7 @@ static int __init scif_uart_init(struct dt_device_node *dev, uart = &scif_com; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("scif-uart: Unable to retrieve the base" diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 490d253d44..0c89cb644e 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include @@ -101,7 +102,7 @@ static struct resource *platform_get_resource(struct platform_device *pdev, switch (type) { case IORESOURCE_MEM: - ret = dt_device_get_address(pdev, num, &res.addr, &res.size); + ret = dt_device_get_paddr(pdev, num, &res.addr, &res.size); return ((ret) ? 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pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 07/11] xen/arm: smmu: Use writeq_relaxed_non_atomic() for writing to SMMU_CBn_TTBR0 Date: Tue, 17 Jan 2023 17:43:54 +0000 Message-ID: <20230117174358.15344-8-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT041:EE_|CH3PR12MB8235:EE_ X-MS-Office365-Filtering-Correlation-Id: 628ddd1f-16b1-4dac-a72c-08daf8b297b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HGChrRYxvKrxib8KCUVvR8Ynjli+YfbldbI/mAGeq0DnVrcMloryHfOHV74Vealsg6UfypAuLJhz++xhcPunSGIZ7fFb5qspIaBg7DA0CqjAIpywXUoEuPB8LReZUp60eIjByYIvvKCDcWvsFCdzGy5WnZNX3xP5nO7wIt9P1/nQ5/TG2x7KyTWIsQR1J0k0ONVKUAorn/2QW2+HtnRCRn/WOfs/8rXq2g+GiiJRwb9cT2LeLTtWpxJjDtecWei20g3fNjymiZgHfYJJSU1VSjKGCfVdDEg41A4FKpcdq3kCXSkb5NFRfaFgumLQPK26II29kp28kHTCLP3CZjCSySKoQEr1w2aWltUqwjGcLrJHAJi9fpxHfhODfEbmyVe7bFCorQHToTsYptL0KE6uEcxFOARx+zYHF4ixQRzX6dqKtouR+Zn5b7Q95e2/fwQb0zK8oRzjXc8Xu3a9hPYOrJROrOlVlFnb+K6MFlypbwZ0jdmXn7YTz8ZMSUQYN42qfGzTqeCdJGgBb483bqNX+uaofqrD2y6e5FhaSjoD3ezp7CrbRfWWeiuXxGV6ndj4dXoJNDEpZnat0DPtXYCHtl111GTYVl9Qrv/dx8atosLiJaMxBaXDjfNRYaCM8XfaJ+FO7Yyn8Dg2PoLoz2YRI/rlpZ0lCFH2ecNZWsoGbeE35Mm6Xthp/DWBiOh/LL31TkHsG7FU0sEzcNmpxTy1O3uc+HZd8Rn07x41LIu547M= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(376002)(39860400002)(346002)(451199015)(40470700004)(46966006)(36840700001)(86362001)(8676002)(82310400005)(103116003)(36756003)(4326008)(26005)(6916009)(70586007)(47076005)(426003)(2616005)(41300700001)(70206006)(186003)(1076003)(6666004)(54906003)(478600001)(81166007)(40460700003)(356005)(2906002)(82740400003)(5660300002)(83380400001)(336012)(36860700001)(316002)(8936002)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 17:45:15.9074 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 628ddd1f-16b1-4dac-a72c-08daf8b297b6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8235 Refer ARM IHI 0062D.c ID070116 (SMMU 2.0 spec), 17-360, 17.3.9, SMMU_CBn_TTBR0 is a 64 bit register. Thus, one can use writeq_relaxed_non_atomic() to write to it instead of invoking writel_relaxed() twice for lower half and upper half of the register. This also helps us as p2maddr is 'paddr_t' (which may be u32 in future). Thus, one can assign p2maddr to a 64 bit register and do the bit manipulations on it, to generate the value for SMMU_CBn_TTBR0. Signed-off-by: Ayan Kumar Halder Reviewed-by: Stefano Stabellini --- Changes from - v1 - 1. Extracted the patch from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". Use writeq_relaxed_non_atomic() to write u64 register in a non-atomic fashion. xen/drivers/passthrough/arm/smmu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 0c89cb644e..84b6803b4e 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -500,8 +500,7 @@ enum arm_smmu_s2cr_privcfg { #define ARM_SMMU_CB_SCTLR 0x0 #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_CB_TTBCR2 0x10 -#define ARM_SMMU_CB_TTBR0_LO 0x20 -#define ARM_SMMU_CB_TTBR0_HI 0x24 +#define ARM_SMMU_CB_TTBR0 0x20 #define ARM_SMMU_CB_TTBCR 0x30 #define ARM_SMMU_CB_S1_MAIR0 0x38 #define ARM_SMMU_CB_FSR 0x58 @@ -1084,6 +1083,7 @@ static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) { u32 reg; + u64 reg64; bool stage1; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; struct arm_smmu_device *smmu = smmu_domain->smmu; @@ -1178,12 +1178,13 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) dev_notice(smmu->dev, "d%u: p2maddr 0x%"PRIpaddr"\n", smmu_domain->cfg.domain->domain_id, p2maddr); - reg = (p2maddr & ((1ULL << 32) - 1)); - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); - reg = (p2maddr >> 32); + reg64 = p2maddr; + if (stage1) - reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); + reg64 |= (((uint64_t) (ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT)) + << 32); + + writeq_relaxed_non_atomic(reg64, cb_base + ARM_SMMU_CB_TTBR0); /* * TTBCR From patchwork Tue Jan 17 17:43:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13104945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3AA8CC3DA78 for ; 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bh=mTuCjvySdNRIh7I98ybx4BVBMGxho8OVLY6od2Qthjw=; b=Wu2tFbFbTZJhJ+MWeMPPAlKPVK/uY+pEecQY8t3xN90+o6eK07clUBZ1XPFNgqziNrSrSrjZjiU77iA5xbH8ZV0cfTbTt1kTxGq4DlO2M2wecU5HUuW5R4wyzlMYCyZ6eizSzdFlqAs9NycAVdAcXgycHVeNfll8zlDKVzSNSd8= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 08/11] xen/arm: guest_walk: LPAE specific bits should be enclosed within "ifndef CONFIG_ARM_PA_32" Date: Tue, 17 Jan 2023 17:43:55 +0000 Message-ID: <20230117174358.15344-9-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E9:EE_|BN9PR12MB5226:EE_ X-MS-Office365-Filtering-Correlation-Id: 954f94af-97fa-4e29-e7d2-08daf8b29971 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 17:45:18.2498 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 954f94af-97fa-4e29-e7d2-08daf8b29971 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5226 In the subsequent patch, we introduce "CONFIG_ARM_PA_32" to support 32 bit physical addresses. Thus, the code specific to "Large Page Address Extension" (ie LPAE) should be enclosed within "ifndef CONFIG_ARM_PA_32". Refer xen/arch/arm/include/asm/short-desc.h, "short_desc_l1_supersec_t" unsigned int extbase1:4; /* Extended base address, PA[35:32] */ unsigned int extbase2:4; /* Extended base address, PA[39:36] */ Thus, extbase1 and extbase2 are not valid when 32 bit physical addresses are supported. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. Extracted from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". xen/arch/arm/guest_walk.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index 43d3215304..0feb7b76ec 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -154,8 +154,10 @@ static bool guest_walk_sd(const struct vcpu *v, mask = (1ULL << L1DESC_SUPERSECTION_SHIFT) - 1; *ipa = gva & mask; *ipa |= (paddr_t)(pte.supersec.base) << L1DESC_SUPERSECTION_SHIFT; +#ifndef CONFIG_ARM_PA_32 *ipa |= (paddr_t)(pte.supersec.extbase1) << L1DESC_SUPERSECTION_EXT_BASE1_SHIFT; *ipa |= (paddr_t)(pte.supersec.extbase2) << L1DESC_SUPERSECTION_EXT_BASE2_SHIFT; +#endif /* CONFIG_ARM_PA_32 */ } /* Set permissions so that the caller can check the flags by herself. */ From patchwork Tue Jan 17 17:43:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13104947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE831C3DA78 for ; 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bh=ALYkcOUMY24lQgvkESpS4YUl/I55d3ApiAMvpoBf2ic=; b=x9Nf9HJ3X6O8CwHCK6nMnjMJEVJ+WY86syFIbkpFC5NqXJFya1VE9xPO27DOOrmdr1OEDQff7BN7wCXLONZL1yIO6Za2I/NS5+7fFU2n0+y5bEqK1fOVLdvjnCMnSbcgSgfiODtI85LFvvDhMg6yMZ+fI3IknB5gAjfoEB92qWc= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 09/11] xen/arm: Introduce ARM_PA_32 to support 32 bit physical address Date: Tue, 17 Jan 2023 17:43:56 +0000 Message-ID: <20230117174358.15344-10-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E9:EE_|IA0PR12MB8374:EE_ X-MS-Office365-Filtering-Correlation-Id: 90c57a63-798f-47d6-f560-08daf8b29a00 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 17:45:19.7498 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 90c57a63-798f-47d6-f560-08daf8b29a00 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8374 We have introduced a new config option to support 32 bit physical address. By default, it is disabled. ARM_PA_32 cannot be enabled on ARM_64 as the memory management unit works on 48bit physical addresses. On ARM_32, it can be used on systems where large page address extension is not supported. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. No changes. xen/arch/arm/Kconfig | 9 +++++++++ xen/arch/arm/include/asm/page-bits.h | 2 ++ xen/arch/arm/include/asm/types.h | 7 +++++++ 3 files changed, 18 insertions(+) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 239d3aed3c..aeb0f7252e 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -39,6 +39,15 @@ config ACPI config ARM_EFI bool +config ARM_PA_32 + bool "32 bit Physical Address" + depends on ARM_32 + default n + ---help--- + + Support 32 bit physical addresses. + If unsure, say N + config GICV3 bool "GICv3 driver" depends on !NEW_VGIC diff --git a/xen/arch/arm/include/asm/page-bits.h b/xen/arch/arm/include/asm/page-bits.h index 5d6477e599..8f4dcebcfd 100644 --- a/xen/arch/arm/include/asm/page-bits.h +++ b/xen/arch/arm/include/asm/page-bits.h @@ -5,6 +5,8 @@ #ifdef CONFIG_ARM_64 #define PADDR_BITS 48 +#elif CONFIG_ARM_PA_32 +#define PADDR_BITS 32 #else #define PADDR_BITS 40 #endif diff --git a/xen/arch/arm/include/asm/types.h b/xen/arch/arm/include/asm/types.h index 083acbd151..f9595b9098 100644 --- a/xen/arch/arm/include/asm/types.h +++ b/xen/arch/arm/include/asm/types.h @@ -37,9 +37,16 @@ typedef signed long long s64; typedef unsigned long long u64; typedef u32 vaddr_t; #define PRIvaddr PRIx32 +#if defined(CONFIG_ARM_PA_32) +typedef u32 paddr_t; +#define INVALID_PADDR (~0UL) +#define PADDR_SHIFT BITS_PER_LONG +#define PRIpaddr PRIx32 +#else typedef u64 paddr_t; #define INVALID_PADDR (~0ULL) #define PRIpaddr "016llx" +#endif typedef u32 register_t; #define PRIregister "08x" #elif defined (CONFIG_ARM_64) From patchwork Tue Jan 17 17:43:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13104956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE2AEC3DA78 for ; Tue, 17 Jan 2023 17:57:50 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.479711.743754 (Exim 4.92) (envelope-from ) id 1pHqD6-0007dp-4I; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 10/11] xen/arm: Restrict zeroeth_table_offset for ARM_64 Date: Tue, 17 Jan 2023 17:43:57 +0000 Message-ID: <20230117174358.15344-11-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108EA:EE_|BL1PR12MB5192:EE_ X-MS-Office365-Filtering-Correlation-Id: 912192a8-fd13-4b16-0a2b-08daf8b29b29 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NrnV0HM/yiIGDqCOfLcrWsMZDJpcA5DkX+OvzhersBZx/ZKarMkHPr6M/EdxLRrqDsYvv+npmG5+08I9sCdEtEcZ7Wgsaoj1ftNXdW5sM6D2ykUOQosnI3hVj4ZcaSIQIPFjiKCnfW7Ao6Eo3MW1ND+KeJjNTEw3HEmGRxK33oGzkBxcx8aLzcOQjnsmj5YZHLp2f2VrtYqSEdhO2jDvS/32c0xhuIOBzCGniTp+ucUMuf3/dAfEsslunSuK9W3BZFXzYvYz+eJv8JDIyXyzTDqi2vS7WJVSNteOxHg92Cv9Vx5Gn9Ra2gy+ZwK6BkEpLzZS+snc/RH3ciL82gIYOOCM0dpbGmXQiWVcsuii9HvS9ZdSzSEJrJ+tU5Td3u/BNWGIlHAG8Dtha8bbfbvR8RDRS8oXmNjsfg19yC8mMlauL4wpCqKlRIejORplrYsUOvRBzd2kyKvxiYDQv1h99u4p2c2C6yFSAND/IrxFG+YGLOKusbn0DCCRlXMz2qKMezPC/2Ae/kXxlotjuVu/X7jT+dc64v2p3Ymq2F/T3bvkEFuSnb8I3qjck0SSIRE/+1woxZRbaZY4hP6fDO6+0E4ab7nAjsbDyBRMuMM+NSEl9rDoJ3AIYzN/GciOsMll8Lpdia5cCIjVmY1WuKoHd5UvPIbLmguwqclk6lk7WDRuxFcco5yfEIixeV/c+eNpV3TvRqJ7NoUb+bfBCykPJ2QwZdl8FHgv4r+/X4f/3HE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(346002)(136003)(376002)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(36756003)(86362001)(356005)(8936002)(6916009)(8676002)(70206006)(70586007)(5660300002)(2906002)(4326008)(36860700001)(82740400003)(81166007)(83380400001)(103116003)(478600001)(40460700003)(6666004)(54906003)(316002)(40480700001)(82310400005)(41300700001)(47076005)(336012)(426003)(1076003)(2616005)(26005)(186003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 17:45:21.1746 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 912192a8-fd13-4b16-0a2b-08daf8b29b29 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5192 zeroeth_table_offset is not accessed by ARM_32. Also, when 32 bit physical addresses are used (ie ARM_PA_32=y), this causes an overflow. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - Removed the duplicate declaration for DECLARE_OFFSETS. xen/arch/arm/include/asm/lpae.h | 4 ++++ xen/arch/arm/mm.c | 7 +------ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/include/asm/lpae.h b/xen/arch/arm/include/asm/lpae.h index 3fdd5d0de2..2744e0eebf 100644 --- a/xen/arch/arm/include/asm/lpae.h +++ b/xen/arch/arm/include/asm/lpae.h @@ -259,7 +259,11 @@ lpae_t mfn_to_xen_entry(mfn_t mfn, unsigned int attr); #define first_table_offset(va) TABLE_OFFSET(first_linear_offset(va)) #define second_table_offset(va) TABLE_OFFSET(second_linear_offset(va)) #define third_table_offset(va) TABLE_OFFSET(third_linear_offset(va)) +#ifdef CONFIG_ARM_64 #define zeroeth_table_offset(va) TABLE_OFFSET(zeroeth_linear_offset(va)) +#else +#define zeroeth_table_offset(va) 0 +#endif /* * Macros to define page-tables: diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index fab54618ab..95784e0c59 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -207,12 +207,7 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr, { static const char *level_strs[4] = { "0TH", "1ST", "2ND", "3RD" }; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , Ayan Kumar Halder Subject: [XEN v2 11/11] xen/arm: p2m: Enable support for 32bit IPA Date: Tue, 17 Jan 2023 17:43:58 +0000 Message-ID: <20230117174358.15344-12-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230117174358.15344-1-ayan.kumar.halder@amd.com> References: <20230117174358.15344-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E9:EE_|MN0PR12MB6003:EE_ X-MS-Office365-Filtering-Correlation-Id: decc4f7b-83ff-4bc6-1c26-08daf8b29c2a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: z8gaDb+q0YxsODVGSp4Qzyz0rZZ0aV8Er2c4KtZ1LLzKshoDeE5Cmrcjdk+jMis9w726fSVcuMPlJ5u8PGraQnqlChyv4wjRAzLUU/i1LawdYRQGxoZG905gHGbsWo3eEWpYspewdrvSe8GoztTQkJOVxuvrOKUp22PvQDJAsOaaGStxfhldGNut2kozWWffK5VZ6lseQUPBmKNFU8hzawo9O64tMH42wKBMcB1w3ZsIA9OnMTnCZDhgwcBEXRL++QRcutO/JauR5Asao6Yq0Kf+bW5x64H1alZC3tSp1SgGYLcGbJSmV6qfy+ThuI7i7w8ZL/dOLkRclpQMwGrYGoSQsoKFraqjIn9FoE/A4jmY0Q17CVAVXjkmW143z1e8rrLH3N93VzIxt4Ds4Hf9MVt5cqF6LpmLnvivtDqxW6cVyGY2WveRRzczBn54lo99VwBqucvOzkWvwPpeOmjmWCveBtpDZXQ0jQpYwMG6FgZv60mY1TCtlqGEe2Nm5mY3yEUENjKkTiuEX6Vb1MZYhZGibBwiGDx/N+y+d+aVqH3e1aIeXR6pToDYQKXg8P0x/JC4FM6IFdXjgr4wFqvQg9dajFVXptOKihVx3hIRCQ6V3OHgbW6iax+hEW2OGatJzwz2+1puRDdXLlFz2L3gOcBhoIeOvaAp9CvphoKWB6mvQMVzi75vdW4L9sIzVA6DWIXjaErOL4WiS+8XT8n2YkXPqehjpJxLRsREfxyBgt4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(396003)(346002)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(41300700001)(8936002)(36756003)(83380400001)(2616005)(70206006)(70586007)(6916009)(4326008)(47076005)(426003)(8676002)(336012)(54906003)(316002)(5660300002)(81166007)(356005)(82740400003)(82310400005)(86362001)(1076003)(2906002)(40460700003)(103116003)(36860700001)(40480700001)(478600001)(186003)(26005)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2023 17:45:23.3593 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: decc4f7b-83ff-4bc6-1c26-08daf8b29c2a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6003 VTCR.T0SZ should be set as 0x20 to support 32bit IPA. Refer ARM DDI 0487I.a ID081822, G8-9824, G8.2.171, VTCR, "Virtualization Translation Control Register" for the bit descriptions. Signed-off-by: Ayan Kumar Halder Acked-by: Stefano Stabellini --- Changes from - v1 - New patch. xen/arch/arm/p2m.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 948f199d84..cfdea55e71 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2266,13 +2266,17 @@ void __init setup_virt_paging(void) register_t val = VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WBWA; #ifdef CONFIG_ARM_32 - if ( p2m_ipa_bits < 40 ) + if ( p2m_ipa_bits < PADDR_BITS ) panic("P2M: Not able to support %u-bit IPA at the moment\n", p2m_ipa_bits); - printk("P2M: 40-bit IPA\n"); - p2m_ipa_bits = 40; + printk("P2M: %u-bit IPA\n",PADDR_BITS); + p2m_ipa_bits = PADDR_BITS; +#ifdef CONFIG_ARM_PA_32 + val |= VTCR_T0SZ(0x20); /* 32 bit IPA */ +#else val |= VTCR_T0SZ(0x18); /* 40 bit IPA */ +#endif val |= VTCR_SL0(0x1); /* P2M starts at first level */ #else /* CONFIG_ARM_64 */ static const struct {