From patchwork Thu Jan 19 09:22:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 13107666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2712DC00A5A for ; Thu, 19 Jan 2023 10:11:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIR8d-0004G3-K1; Thu, 19 Jan 2023 04:23:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8c-0004Fh-4q for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:14 -0500 Received: from mail.ispras.ru ([83.149.199.84]) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8a-0006D0-Ke for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:13 -0500 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id BA341406BB55; Thu, 19 Jan 2023 09:22:48 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru BA341406BB55 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1674120168; bh=TWAOjLkooBwZEu2UaJXs+LLyZ13Mqhg7vRWmDDIM4UM=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=Kp1FbAxTlM9qfa7ftLwiM8QwQikG9HmCoxzASq/wzjAKT04xGAgAqz2Dcb/Gxc1v9 BAxCMIuZ35owL9hp7euwbhM6wFQ9cHvct2behsIjI0L/s7xiB2oOHRKB07JlXmUOnp LgdHXf+Jv85DW7WTWl7yYh3UDE+T+O5CcHDV+O1U= Subject: [PATCH v2 1/5] target/avr: fix long address calculation From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, mrolnik@gmail.com, philmd@linaro.org, richard.henderson@linaro.org Date: Thu, 19 Jan 2023 12:22:48 +0300 Message-ID: <167412016849.3110454.2779669980014238134.stgit@pasha-ThinkPad-X280> In-Reply-To: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> References: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org AVR ELPMX instruction (and some others) use three registers to form long 24-bit address from RAMPZ and two 8-bit registers. RAMPZ stores shifted 8 bits like ff0000 to simplify address calculation. This patch fixes full address calculation in function gen_get_addr by changing the mess in offsets of deposit tcg instructions. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Richard Henderson Reviewed-by: Michael Rolnik --- target/avr/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/avr/translate.c b/target/avr/translate.c index 2bed56f135..552f739b3d 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1572,8 +1572,8 @@ static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L) { TCGv addr = tcg_temp_new_i32(); - tcg_gen_deposit_tl(addr, M, H, 8, 8); - tcg_gen_deposit_tl(addr, L, addr, 8, 16); + tcg_gen_deposit_tl(addr, H, M, 8, 8); + tcg_gen_deposit_tl(addr, addr, L, 0, 8); return addr; } From patchwork Thu Jan 19 09:22:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 13107632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EDEEC00A5A for ; Thu, 19 Jan 2023 09:43:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIR8i-0004Gy-O7; Thu, 19 Jan 2023 04:23:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8g-0004Gn-Rf for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:18 -0500 Received: from mail.ispras.ru ([83.149.199.84]) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8e-0006De-T3 for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:18 -0500 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id 2AF4940737A8; Thu, 19 Jan 2023 09:22:54 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru 2AF4940737A8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1674120174; bh=++Rr7MMTBehGJdeIJds0h7Va3KLRSL+wROe3FXxfus8=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=qiRQOoewgrWpdO4m5rHAMRaL1jjm4skfWwR2fkJmWW1IYL5oiIZxnlstEDYTwk/vq I7W02XdEObTncI5lSyKRx5rZXecpJWnCjbVTwouNmEwRjapZj6YJ2Lyoepo2lO9TES hdrE8o3bXk2aWodv3c5KRgrAnZ5UUm3WKrd+47VM= Subject: [PATCH v2 2/5] target/avr: implement small RAM/large RAM feature From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, mrolnik@gmail.com, philmd@linaro.org, richard.henderson@linaro.org Date: Thu, 19 Jan 2023 12:22:54 +0300 Message-ID: <167412017399.3110454.14047770996929512612.stgit@pasha-ThinkPad-X280> In-Reply-To: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> References: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org translate.c functions use RAMPZ for RAM access. This register is also used for ROM reads. However, in MCUs with 64k RAM support RAMPZ is used for ROM only. Therefore when RAMPZ is set, addressing the RAM becomes incorrect in the emulator. This patch adds LARGE RAM feature which can be used in xmega controllers, that could be added later. For the currently supported MCUs this feature is disabled and RAMPZ is not used for RAM access. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Richard Henderson --- target/avr/cpu.h | 2 ++ target/avr/translate.c | 63 ++++++++++++++++++++++++++++++------------------ 2 files changed, 41 insertions(+), 24 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index f19dd72926..7c3895b65e 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -106,6 +106,8 @@ typedef enum AVRFeature { AVR_FEATURE_RAMPX, AVR_FEATURE_RAMPY, AVR_FEATURE_RAMPZ, + + AVR_FEATURE_LARGE_RAM, } AVRFeature; typedef struct CPUArchState { diff --git a/target/avr/translate.c b/target/avr/translate.c index 552f739b3d..40b15d116e 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1542,13 +1542,17 @@ static bool trans_BRBS(DisasContext *ctx, arg_BRBS *a) * M assumed to be in 0x000000ff format * L assumed to be in 0x000000ff format */ -static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L) +static void gen_set_addr_short(TCGv addr, TCGv M, TCGv L) { - tcg_gen_andi_tl(L, addr, 0x000000ff); tcg_gen_andi_tl(M, addr, 0x0000ff00); tcg_gen_shri_tl(M, M, 8); +} + +static void gen_set_addr(TCGv addr, TCGv H, TCGv M, TCGv L) +{ + gen_set_addr_short(addr, M, L); tcg_gen_andi_tl(H, addr, 0x00ff0000); } @@ -1563,9 +1567,13 @@ static void gen_set_yaddr(TCGv addr) gen_set_addr(addr, cpu_rampY, cpu_r[29], cpu_r[28]); } -static void gen_set_zaddr(TCGv addr) +static void gen_set_zaddr(DisasContext *ctx, TCGv addr, bool ram) { - gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]); + if (!ram || avr_feature(ctx->env, AVR_FEATURE_LARGE_RAM)) { + gen_set_addr(addr, cpu_rampZ, cpu_r[31], cpu_r[30]); + } else { + gen_set_addr_short(addr, cpu_r[31], cpu_r[30]); + } } static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L) @@ -1588,9 +1596,16 @@ static TCGv gen_get_yaddr(void) return gen_get_addr(cpu_rampY, cpu_r[29], cpu_r[28]); } -static TCGv gen_get_zaddr(void) +static TCGv gen_get_zaddr(DisasContext *ctx, bool ram) { - return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]); + if (!ram || avr_feature(ctx->env, AVR_FEATURE_LARGE_RAM)) { + return gen_get_addr(cpu_rampZ, cpu_r[31], cpu_r[30]); + } else { + TCGv zero = tcg_const_i32(0); + TCGv res = gen_get_addr(zero, cpu_r[31], cpu_r[30]); + tcg_temp_free_i32(zero); + return res; + } } /* @@ -1868,12 +1883,12 @@ static bool trans_LDDY(DisasContext *ctx, arg_LDDY *a) static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); gen_data_load(ctx, Rd, addr); tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ - gen_set_zaddr(addr); + gen_set_zaddr(ctx, addr, true); tcg_temp_free_i32(addr); @@ -1883,12 +1898,12 @@ static bool trans_LDZ2(DisasContext *ctx, arg_LDZ2 *a) static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ gen_data_load(ctx, Rd, addr); - gen_set_zaddr(addr); + gen_set_zaddr(ctx, addr, true); tcg_temp_free_i32(addr); @@ -1898,7 +1913,7 @@ static bool trans_LDZ3(DisasContext *ctx, arg_LDZ3 *a) static bool trans_LDDZ(DisasContext *ctx, arg_LDDZ *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ gen_data_load(ctx, Rd, addr); @@ -2088,12 +2103,12 @@ static bool trans_STDY(DisasContext *ctx, arg_STDY *a) static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); gen_data_store(ctx, Rd, addr); tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ - gen_set_zaddr(addr); + gen_set_zaddr(ctx, addr, true); tcg_temp_free_i32(addr); @@ -2103,12 +2118,12 @@ static bool trans_STZ2(DisasContext *ctx, arg_STZ2 *a) static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); tcg_gen_subi_tl(addr, addr, 1); /* addr = addr - 1 */ gen_data_store(ctx, Rd, addr); - gen_set_zaddr(addr); + gen_set_zaddr(ctx, addr, true); tcg_temp_free_i32(addr); @@ -2118,7 +2133,7 @@ static bool trans_STZ3(DisasContext *ctx, arg_STZ3 *a) static bool trans_STDZ(DisasContext *ctx, arg_STDZ *a) { TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); tcg_gen_addi_tl(addr, addr, a->imm); /* addr = addr + q */ gen_data_store(ctx, Rd, addr); @@ -2228,7 +2243,7 @@ static bool trans_ELPM1(DisasContext *ctx, arg_ELPM1 *a) } TCGv Rd = cpu_r[0]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, false); tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ @@ -2244,7 +2259,7 @@ static bool trans_ELPM2(DisasContext *ctx, arg_ELPM2 *a) } TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, false); tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ @@ -2260,11 +2275,11 @@ static bool trans_ELPMX(DisasContext *ctx, arg_ELPMX *a) } TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, false); tcg_gen_qemu_ld8u(Rd, addr, MMU_CODE_IDX); /* Rd = mem[addr] */ tcg_gen_addi_tl(addr, addr, 1); /* addr = addr + 1 */ - gen_set_zaddr(addr); + gen_set_zaddr(ctx, addr, false); tcg_temp_free_i32(addr); @@ -2402,7 +2417,7 @@ static bool trans_XCH(DisasContext *ctx, arg_XCH *a) TCGv Rd = cpu_r[a->rd]; TCGv t0 = tcg_temp_new_i32(); - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); gen_data_load(ctx, t0, addr); gen_data_store(ctx, Rd, addr); @@ -2432,7 +2447,7 @@ static bool trans_LAS(DisasContext *ctx, arg_LAS *a) } TCGv Rr = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); TCGv t0 = tcg_temp_new_i32(); TCGv t1 = tcg_temp_new_i32(); @@ -2467,7 +2482,7 @@ static bool trans_LAC(DisasContext *ctx, arg_LAC *a) } TCGv Rr = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); TCGv t0 = tcg_temp_new_i32(); TCGv t1 = tcg_temp_new_i32(); @@ -2502,7 +2517,7 @@ static bool trans_LAT(DisasContext *ctx, arg_LAT *a) } TCGv Rd = cpu_r[a->rd]; - TCGv addr = gen_get_zaddr(); + TCGv addr = gen_get_zaddr(ctx, true); TCGv t0 = tcg_temp_new_i32(); TCGv t1 = tcg_temp_new_i32(); From patchwork Thu Jan 19 09:22:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 13107646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78699C00A5A for ; Thu, 19 Jan 2023 10:01:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIR8n-0004Ht-9z; Thu, 19 Jan 2023 04:23:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8l-0004He-QW for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:23 -0500 Received: from mail.ispras.ru ([83.149.199.84]) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8k-0006E9-AT for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:23 -0500 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id 8B24240737AB; Thu, 19 Jan 2023 09:22:59 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru 8B24240737AB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1674120179; bh=xpL7id23gSs1pJTLmHcwCsMeLdWH+Y9CY6RuXk6OO7U=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=jPJCMaPD9rsCZ9e2D8HFJkAprm1abYNKRJRCjNa0MG7yJ9IfIV3qiq8OzlCWhHImU QSHcizi6Sgkj79PnAW6B/xCJ0s0sbfKcnIk2PAnaRj/G2ZitCV10am7oVntG+WES+3 JF8+pzvnNSI3QFCi8HR2t8VULky87G09tzrszcn0= Subject: [PATCH v2 3/5] target/avr: fix avr features processing From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, mrolnik@gmail.com, philmd@linaro.org, richard.henderson@linaro.org Date: Thu, 19 Jan 2023 12:22:59 +0300 Message-ID: <167412017939.3110454.772171621078654245.stgit@pasha-ThinkPad-X280> In-Reply-To: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> References: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Bit vector for features has 64 bits. This patch fixes bit shifts in avr_feature and set_avr_feature functions to be 64-bit too. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/avr/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 7c3895b65e..280edc495b 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -166,12 +166,12 @@ vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); static inline int avr_feature(CPUAVRState *env, AVRFeature feature) { - return (env->features & (1U << feature)) != 0; + return (env->features & (1ULL << feature)) != 0; } static inline void set_avr_feature(CPUAVRState *env, int feature) { - env->features |= (1U << feature); + env->features |= (1ULL << feature); } #define cpu_list avr_cpu_list From patchwork Thu Jan 19 09:23:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 13107624 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93558C004D4 for ; Thu, 19 Jan 2023 09:29:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIR8p-0004IU-At; Thu, 19 Jan 2023 04:23:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8n-0004I9-JZ for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:25 -0500 Received: from mail.ispras.ru ([83.149.199.84]) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8m-0006F4-4z for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:25 -0500 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id 05D9840737AF; Thu, 19 Jan 2023 09:23:04 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru 05D9840737AF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1674120185; bh=7bAqsqrVbTWaQc+AhA/m5Q6ztD9STpF91vF/3tnrKbs=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=fzUzvuaoGL5609cerAyV94YPboYmFMIeso0DcELBwFXRyS8yrOyWY/g05fUYUsKY9 66RDSajMQhudBepxoGhVqWObNcVU8Ij30/UohVRd1utlPPukbwA/mqe4eW6+sL3iww 6i3C/1WzU2y0romDs6/yZdz0H/j4rTIHzPM2UBkQ= Subject: [PATCH v2 4/5] target/avr: fix interrupt processing From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, mrolnik@gmail.com, philmd@linaro.org, richard.henderson@linaro.org Date: Thu, 19 Jan 2023 12:23:04 +0300 Message-ID: <167412018478.3110454.5407396471034616682.stgit@pasha-ThinkPad-X280> In-Reply-To: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> References: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Interrupt bit vector has 64 bits, but interrupt vector is found with ctz32 function. This patch replaces it with ctz64. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/avr/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index 156dde4e92..61ab6feb25 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -51,7 +51,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request) } if (interrupt_request & CPU_INTERRUPT_HARD) { if (cpu_interrupts_enabled(env) && env->intsrc != 0) { - int index = ctz32(env->intsrc); + int index = ctz64(env->intsrc); cs->exception_index = EXCP_INT(index); avr_cpu_do_interrupt(cs); @@ -78,7 +78,7 @@ void avr_cpu_do_interrupt(CPUState *cs) if (cs->exception_index == EXCP_RESET) { vector = 0; } else if (env->intsrc != 0) { - vector = ctz32(env->intsrc) + 1; + vector = ctz64(env->intsrc) + 1; } if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { From patchwork Thu Jan 19 09:23:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Dovgalyuk X-Patchwork-Id: 13107614 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24709C6379F for ; Thu, 19 Jan 2023 09:28:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pIR8e-0004Gi-Kp; Thu, 19 Jan 2023 04:23:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8c-0004Fr-C1 for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:14 -0500 Received: from mail.ispras.ru ([83.149.199.84]) by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR8a-0006GB-QT for qemu-devel@nongnu.org; Thu, 19 Jan 2023 04:23:14 -0500 Received: from [127.0.1.1] (unknown [85.142.117.226]) by mail.ispras.ru (Postfix) with ESMTPSA id 79B9940737AC; Thu, 19 Jan 2023 09:23:10 +0000 (UTC) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.ispras.ru 79B9940737AC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ispras.ru; s=default; t=1674120190; bh=o/aySluarGl07VSrD5n+eG+q632Cw4z1i55Kl2eM+0w=; h=Subject:From:To:Cc:Date:In-Reply-To:References:From; b=qBKD1+0y7kBIVdZM1SqrydJ0u8hnbFgpgK1H5tnQgLkhorLXX+tTce4k6q1BgNaMg yqLusJRV5O73d+VUICUS4rYZk056ElejZtpa9SWyiKdCTtpxnl2R39VKPm1MPznfaD MXe9nn+5t5zLxpyexT/ZaZ73gf8NxXLBSRG9kad8= Subject: [PATCH v2 5/5] target/avr: enable icount mode From: Pavel Dovgalyuk To: qemu-devel@nongnu.org Cc: pavel.dovgalyuk@ispras.ru, mrolnik@gmail.com, philmd@linaro.org, richard.henderson@linaro.org Date: Thu, 19 Jan 2023 12:23:10 +0300 Message-ID: <167412019026.3110454.15241120845845520583.stgit@pasha-ThinkPad-X280> In-Reply-To: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> References: <167412016297.3110454.15240516964339531097.stgit@pasha-ThinkPad-X280> User-Agent: StGit/0.23 MIME-Version: 1.0 Received-SPF: pass client-ip=83.149.199.84; envelope-from=pavel.dovgalyuk@ispras.ru; helo=mail.ispras.ru X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Icount mode requires correct can_do_io flag management for checking that IO operations are performed only in the last TB instruction. This patch sets this flag before every helper which can lead to virtual hardware access. It enables deterministic execution in icount mode for AVR. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Richard Henderson --- target/avr/translate.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index 40b15d116e..ee137dfe54 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -1406,6 +1406,10 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) { TCGv temp = tcg_const_i32(a->reg); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(temp, cpu_env, temp); tcg_gen_andi_tl(temp, temp, 1 << a->bit); ctx->skip_cond = TCG_COND_EQ; @@ -1424,6 +1428,10 @@ static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) { TCGv temp = tcg_const_i32(a->reg); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(temp, cpu_env, temp); tcg_gen_andi_tl(temp, temp, 1 << a->bit); ctx->skip_cond = TCG_COND_NE; @@ -1621,6 +1629,9 @@ static TCGv gen_get_zaddr(DisasContext *ctx, bool ram) static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) { if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_fullwr(cpu_env, data, addr); } else { tcg_gen_qemu_st8(data, addr, MMU_DATA_IDX); /* mem[addr] = data */ @@ -1630,6 +1641,9 @@ static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } gen_helper_fullrd(data, cpu_env, addr); } else { tcg_gen_qemu_ld8u(data, addr, MMU_DATA_IDX); /* data = mem[addr] */ @@ -2335,6 +2349,10 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) TCGv Rd = cpu_r[a->rd]; TCGv port = tcg_const_i32(a->imm); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(Rd, cpu_env, port); tcg_temp_free_i32(port); @@ -2351,6 +2369,10 @@ static bool trans_OUT(DisasContext *ctx, arg_OUT *a) TCGv Rd = cpu_r[a->rd]; TCGv port = tcg_const_i32(a->imm); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_outb(cpu_env, port, Rd); tcg_temp_free_i32(port); @@ -2651,6 +2673,10 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) TCGv data = tcg_temp_new_i32(); TCGv port = tcg_const_i32(a->reg); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(data, cpu_env, port); tcg_gen_ori_tl(data, data, 1 << a->bit); gen_helper_outb(cpu_env, port, data); @@ -2670,6 +2696,10 @@ static bool trans_CBI(DisasContext *ctx, arg_CBI *a) TCGv data = tcg_temp_new_i32(); TCGv port = tcg_const_i32(a->reg); + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_inb(data, cpu_env, port); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); gen_helper_outb(cpu_env, port, data);