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Ampere Computing erratum AC03_DEBUG_06 describes an Ampere Computing design decision MMIO reads are considered the same as an external debug access. If TRCOSLAR.OSLK is set, the TRCIDR1 access results in a bus fault followed by a kernel panic. A TRCIDR1 read is valid regardless of TRCOSLAR.OSLK provided MMIO access (now deprecated) is supported. AC03_DEBUG_06 is described in the AmpereOne Developer Errata: https://solutions.amperecomputing.com/customer-connect/products/AmpereOne-device-documentation Add Ampere ETM PID required for Coresight ETM driver support. Signed-off-by: Steve Clevenger --- .../coresight/coresight-etm4x-core.c | 36 +++++++++++++++---- drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 1cc052979e01..533be1928a09 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1091,19 +1091,34 @@ static void etm4_init_arch_data(void *info) drvdata = dev_get_drvdata(init_arg->dev); csa = init_arg->csa; + /* Detect the support for OS Lock before we actually use it */ + etm_detect_os_lock(drvdata, csa); + + /* + * For ETM implementations that consider MMIO an external access + * clear TRCOSLAR.OSLK early. + */ + if (drvdata->mmio_external) + etm4_os_unlock_csa(drvdata, csa); + /* * If we are unable to detect the access mechanism, * or unable to detect the trace unit type, fail - * early. + * early. Reset TRCOSLAR.OSLK if cleared. */ - if (!etm4_init_csdev_access(drvdata, csa)) + if (!etm4_init_csdev_access(drvdata, csa)) { + if (drvdata->mmio_external) + etm4_os_lock(drvdata); return; + } - /* Detect the support for OS Lock before we actually use it */ - etm_detect_os_lock(drvdata, csa); + /* + * Make sure all registers are accessible + * TRCOSLAR.OSLK may already be clear + */ + if (!drvdata->mmio_external) + etm4_os_unlock_csa(drvdata, csa); - /* Make sure all registers are accessible */ - etm4_os_unlock_csa(drvdata, csa); etm4_cs_unlock(drvdata, csa); etm4_check_arch_features(drvdata, init_arg->pid); @@ -2027,6 +2042,14 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) init_arg.csa = &access; init_arg.pid = etm_pid; + /* + * Ampere ETM v4.6 considers MMIO access as external. This mask + * isolates the manufacturer JEP106 ID in the PID. + * TRCPIDR2 (JEDC|DES_1) << 16 | TRCPIDR1 (DES_0) << 8) + */ + if ((init_arg.pid & 0x000FF000) == 0x00096000) + drvdata->mmio_external = true; + /* * Serialize against CPUHP callbacks to avoid race condition * between the smp call and saving the delayed probe. @@ -2192,6 +2215,7 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ + CS_AMBA_UCI_ID(0x00096000, uci_id_etm4),/* Ampere ARMv8 */ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */ CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */ diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 4b21bb79f168..cf4f9f2e1807 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1015,6 +1015,7 @@ struct etmv4_save_state { * @skip_power_up: Indicates if an implementation can skip powering up * the trace unit. * @arch_features: Bitmap of arch features of etmv4 devices. + * @mmio_external: True if ETM considers MMIO an external access. */ struct etmv4_drvdata { void __iomem *base; @@ -1067,6 +1068,7 @@ struct etmv4_drvdata { bool state_needs_restore; bool skip_power_up; DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); + bool mmio_external; }; /* Address comparator access types */ From patchwork Fri Jan 20 00:51:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Clevenger X-Patchwork-Id: 13109024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D84DC38142 for ; Fri, 20 Jan 2023 00:54:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Ampere Computing erratum AC03_DEBUG_10 describes a design decision where 64-bit read/write access is not supported for the ETMv4.6 implementation. These 64-bit registers must be accessed as 2 ea. 32-bit registers. AC03_DEBUG_10 is described in the AmpereOne Developer Errata: https://solutions.amperecomputing.com/customer-connect/products/AmpereOne-device-documentation Fix drvdata->nr_addr_cmp for() loop range bug to drvdata->nr_addr_cmp * 2 in etm_enable_hw. Signed-off-by: Steve Clevenger --- .../coresight/coresight-etm4x-core.c | 81 ++++++++++++++----- drivers/hwtracing/coresight/coresight-etm4x.h | 32 ++++++++ 2 files changed, 93 insertions(+), 20 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 533be1928a09..bf4daa649cdf 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -452,18 +452,31 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) if (etm4x_sspcicrn_present(drvdata, i)) etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); } - for (i = 0; i < drvdata->nr_addr_cmp; i++) { - etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); - etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); + for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { + if (drvdata->no_quad_mmio) { + etm4x_split_write64(csa, config->addr_val[i], TRCACVRn(i)); + etm4x_split_write64(csa, config->addr_acc[i], TRCACATRn(i)); + } else { + etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); + etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); + } + } + for (i = 0; i < drvdata->numcidc; i++) { + if (drvdata->no_quad_mmio) + etm4x_split_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); + else + etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); } - for (i = 0; i < drvdata->numcidc; i++) - etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0); if (drvdata->numcidc > 4) etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1); - for (i = 0; i < drvdata->numvmidc; i++) - etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); + for (i = 0; i < drvdata->numvmidc; i++) { + if (drvdata->no_quad_mmio) + etm4x_split_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); + else + etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); + } etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0); if (drvdata->numvmidc > 4) etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1); @@ -1670,8 +1683,13 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) } for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { - state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); - state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); + if (drvdata->no_quad_mmio) { + state->trcacvr[i] = etm4x_split_read64(csa, TRCACVRn(i)); + state->trcacatr[i] = etm4x_split_read64(csa, TRCACATRn(i)); + } else { + state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); + state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); + } } /* @@ -1681,11 +1699,19 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) * unit") of ARM IHI 0064D. */ - for (i = 0; i < drvdata->numcidc; i++) - state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i)); + for (i = 0; i < drvdata->numcidc; i++) { + if (drvdata->no_quad_mmio) + state->trccidcvr[i] = etm4x_split_read64(csa, TRCCIDCVRn(i)); + else + state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i)); + } - for (i = 0; i < drvdata->numvmidc; i++) - state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); + for (i = 0; i < drvdata->numvmidc; i++) { + if (drvdata->no_quad_mmio) + state->trcvmidcvr[i] = etm4x_split_read64(csa, TRCVMIDCVRn(i)); + else + state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); + } state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0); if (drvdata->numcidc > 4) @@ -1799,15 +1825,28 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) } for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { - etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); - etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); + if (drvdata->no_quad_mmio) { + etm4x_split_write64(csa, state->trcacvr[i], TRCACVRn(i)); + etm4x_split_write64(csa, state->trcacatr[i], TRCACATRn(i)); + } else { + etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); + etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); + } } - for (i = 0; i < drvdata->numcidc; i++) - etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); + for (i = 0; i < drvdata->numcidc; i++) { + if (drvdata->no_quad_mmio) + etm4x_split_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); + else + etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); + } - for (i = 0; i < drvdata->numvmidc; i++) - etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); + for (i = 0; i < drvdata->numvmidc; i++) { + if (drvdata->no_quad_mmio) + etm4x_split_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); + else + etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); + } etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0); if (drvdata->numcidc > 4) @@ -2047,8 +2086,10 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) * isolates the manufacturer JEP106 ID in the PID. * TRCPIDR2 (JEDC|DES_1) << 16 | TRCPIDR1 (DES_0) << 8) */ - if ((init_arg.pid & 0x000FF000) == 0x00096000) + if ((init_arg.pid & 0x000FF000) == 0x00096000) { drvdata->mmio_external = true; + drvdata->no_quad_mmio = true; + } /* * Serialize against CPUHP callbacks to avoid race condition diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index cf4f9f2e1807..0650bcdff410 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1016,6 +1016,7 @@ struct etmv4_save_state { * the trace unit. * @arch_features: Bitmap of arch features of etmv4 devices. * @mmio_external: True if ETM considers MMIO an external access. + * @no_quad_mmio: True if ETM does not support 64-bit (quad) access. */ struct etmv4_drvdata { void __iomem *base; @@ -1069,6 +1070,7 @@ struct etmv4_drvdata { bool skip_power_up; DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); bool mmio_external; + bool no_quad_mmio; }; /* Address comparator access types */ @@ -1093,6 +1095,36 @@ void etm4_config_trace_mode(struct etmv4_config *config); u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit); void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit); +/* 64-bit aligned to convert 64-bit access to 2 ea. 32-bit access */ +#pragma pack(push, 8) + +struct etm_quad_split { + u32 lsw; + u32 msw; +}; + +#pragma pack(pop) + +static inline u64 etm4x_split_read64(struct csdev_access *csa, unsigned int offset) +{ + struct etm_quad_split container; + + container.lsw = etm4x_read32(csa, offset); + container.msw = etm4x_read32(csa, offset + sizeof(u32)); + + return *(u64 *) &container; +} + +static inline void etm4x_split_write64(struct csdev_access *csa, u64 quad, unsigned int offset) +{ + struct etm_quad_split container; + + *(u64 *) &container = quad; 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This helped debug an intermittent clock related issue resulting in bad PID/CID values. Signed-off-by: Steve Clevenger --- drivers/amba/bus.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index ff7454a38058..7c432442862c 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -136,6 +136,7 @@ static int amba_read_periphid(struct amba_device *dev) u32 size, pid, cid; void __iomem *tmp; int i, ret; + u32 cid_addr, pid_addr; ret = dev_pm_domain_attach(&dev->dev, true); if (ret) { @@ -178,6 +179,12 @@ static int amba_read_periphid(struct amba_device *dev) for (cid = 0, i = 0; i < 4; i++) cid |= (readl(tmp + size - 0x10 + 4 * i) & 255) << (i * 8); + /* physical address as meaningful */ + cid_addr = (u64)(dev->res.start + size - 0x20); + pid_addr = (u64)(dev->res.start + size - 0x10); + + pr_debug("pid (%llX): %08X cid (%llX): %08X\n", pid_addr, pid, cid_addr, cid); + if (cid == CORESIGHT_CID) { /* set the base to the start of the last 4k block */ void __iomem *csbase = tmp + size - 4096;