From patchwork Fri Jan 20 19:34:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13110445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7CFDFC25B50 for ; Fri, 20 Jan 2023 19:35:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E03410EAFE; Fri, 20 Jan 2023 19:35:19 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 48BBC10E39E; Fri, 20 Jan 2023 19:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674243317; x=1705779317; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PDRZreVYUxY3F2JcBZ+8Vj7vod49Vq8JSDd72Fsl+V4=; b=aKJLJ7umfxZQ9k4JTccTYeoGTM4aF50A/yLlwBpbkPnAyIoQ/5gYOK+5 +0A2sy1ozhCBnlZDzCZ1PF1FTx+I2mcHqz+8PJzIb15xkzOx9VjrIQbbQ 7yWoB0OF9F9S7lk3feL2JP/XjNj1OYAcviMR+wTOPVTF5WaprgyT93IMJ PtuJg6q7uYkhQSFO1SiftbTj4KM8NOjgmKX/M/3DG92iphOOX0N6/QVb7 NI2zrnOYPONQ10U8OUaK6OFJraEX/2TN+DjKjq0F0lK47Vbmu/Mhu4u+B DPBsC0BWkRJTmCJKXwJUnPm2rK3W+7Z7vns8ZTbNE5a6CZZIEI17BfcMi A==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411903528" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="411903528" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:16 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="834518297" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="834518297" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:16 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 20 Jan 2023 11:34:50 -0800 Message-Id: <20230120193457.3295977-2-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120193457.3295977-1-lucas.demarchi@intel.com> References: <20230120193457.3295977-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 1/8] drm/i915: Add _PICK_EVEN_2RANGES() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It's a constant pattern in the driver to need to use 2 ranges of MMIOs based on port, phy, pll, etc. When that happens, instead of using _PICK_EVEN(), _PICK() needs to be used. Using _PICK() is discouraged due to some reasons like: 1) It increases the code size since the array is declared in each call site 2) Developers need to be careful not to incur an out-of-bounds array access 3) Developers need to be careful that the indexes match the table. For that it may be that the table needs to contain holes, making (1) even worse. Add a variant of _PICK_EVEN() that works with 2 ranges and selects which one to use depending on the index value. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_reg_defs.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index be43580a6979..b7ec87464d69 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -119,6 +119,34 @@ */ #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) +/* + * Like _PICK_EVEN(), but supports 2 ranges of evenly spaced address offsets. + * The first range is used for indexes below @__c_index, and the second + * range is used for anything above it. Example:: + * + * #define _FOO_A 0xf000 + * #define _FOO_B 0xf004 + * #define _FOO_C 0xf008 + * #define _SUPER_FOO_A 0xa000 + * #define _SUPER_FOO_B 0xa100 + * #define FOO(x) _MMIO(_PICK_EVEN_RANGES(x, 3, \ + * _FOO_A, _FOO_B, \ + * _SUPER_FOO_A, _SUPER_FOO_B)) + * + * This expands to: + * 0: 0xf000, + * 1: 0xf004, + * 2: 0xf008, + * 3: 0xa100, + * 4: 0xa200, + * 5: 0xa300, + * ... + */ +#define _PICK_EVEN_2RANGES(__index, __c_index, __a, __b, __c, __d) \ + (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) + \ + ((__index) < (__c_index) ? _PICK_EVEN(__index, __a, __b) : \ + _PICK_EVEN((__index) - (__c_index), __c, __d))) + /* * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. * From patchwork Fri Jan 20 19:34:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13110446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E35CFC05027 for ; Fri, 20 Jan 2023 19:35:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 89CD110EAFF; Fri, 20 Jan 2023 19:35:19 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6CC2110E39D; Fri, 20 Jan 2023 19:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674243317; x=1705779317; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m2qH4BxQ5ldd7JJareYs7kXQrvh8VxPnVgLDrLfG+fs=; b=cngmhpNjoGb7SBkhCXI0AuJfMZQWIsJ2eeY+3E9HEzszzZB+dk9+uS8/ bgGYDXHHPerdotbdOmFpx1Sw/HU8keWZYlxnvY7N3XYyaJ4l5dM0oIelz x46OEdP0WPlA5gwINvaQkTCETdr4/EvRrA9Z2kJeTxP+xQK9UTupvcjsL qhOB4zpB7tl15RSqZzGgiPUSE8ydL61YwO/kl6IyTgfVrhctOO8BEvh5r S3zFWZaYg4SEqrk8cdhBhGG6gYAcu13heXnpUQHpyXK1RpiozaUPISF0u b6Kh7aljcnM81t6BFzZEBAcdjTZrILumk2Azy45NoNlUBFExu28ZHx9Fj A==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411903531" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="411903531" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:16 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="834518301" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="834518301" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:16 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 20 Jan 2023 11:34:51 -0800 Message-Id: <20230120193457.3295977-3-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120193457.3295977-1-lucas.demarchi@intel.com> References: <20230120193457.3295977-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 2/8] drm/i915: Fix coding style on DPLL*_ENABLE defines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Abide by the rules in the top of the header: 2 spaces for bitfield, prefix offsets with underscore and prefer the use of REG_BIT(). Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3b2642397b82..8da3546d82fb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7224,20 +7224,20 @@ enum skl_power_gate { ADLS_DPCLKA_DDIK_SEL_MASK) /* ICL PLL */ -#define DPLL0_ENABLE 0x46010 -#define DPLL1_ENABLE 0x46014 +#define _DPLL0_ENABLE 0x46010 +#define _DPLL1_ENABLE 0x46014 #define _ADLS_DPLL2_ENABLE 0x46018 #define _ADLS_DPLL3_ENABLE 0x46030 -#define PLL_ENABLE (1 << 31) -#define PLL_LOCK (1 << 30) -#define PLL_POWER_ENABLE (1 << 27) -#define PLL_POWER_STATE (1 << 26) -#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ +#define PLL_ENABLE REG_BIT(31) +#define PLL_LOCK REG_BIT(30) +#define PLL_POWER_ENABLE REG_BIT(27) +#define PLL_POWER_STATE REG_BIT(26) +#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) #define _DG2_PLL3_ENABLE 0x4601C -#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ +#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE) #define TBT_PLL_ENABLE _MMIO(0x46020) @@ -7246,12 +7246,12 @@ enum skl_power_gate { #define _MG_PLL2_ENABLE 0x46034 #define _MG_PLL3_ENABLE 0x46038 #define _MG_PLL4_ENABLE 0x4603C -/* Bits are the same as DPLL0_ENABLE */ +/* Bits are the same as _DPLL0_ENABLE */ #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ _MG_PLL2_ENABLE) /* DG1 PLL */ -#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ +#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) /* ADL-P Type C PLL */ From patchwork Fri Jan 20 19:34:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13110443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1141BC25B50 for ; Fri, 20 Jan 2023 19:35:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DE06610EAEC; Fri, 20 Jan 2023 19:35:18 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8BCF210E39E; Fri, 20 Jan 2023 19:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674243317; x=1705779317; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6XEEI1FKRKiL/BEIedryEjxch9aMp4GChCxcfO5JYwA=; b=jWibrkBhz6kK0+OwXUBqnUaEv+MSHijh9IBnAw0AYd+gDcTLnRKlFFCU XDPKBD+PLw60AQpVCzOu6HSPQzCFKR64ro6x7WaKwFLKDXd96zLthVfaz Lh+1+qGoqWU07mYydLDZfhu67HHqwMpj1vXbLAjXM3YGWIkpQRkkYxWOO nBXg4NQwGcdFDEBKCBgwgFPiiEG9rR1h7/Kser09V3nLRRym7seSbtuC0 YffUNIAK5XD9tcBc87vhhU3XqERtypGYLg+Cgo3hb9M7ap9RVMBJkv33r oxwpY2bXtdaE01pzVS3LCbVRNalh+T4VUn2oSOnfdBRVMaWvebzabstuf w==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411903533" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="411903533" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:17 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="834518307" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="834518307" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:16 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 20 Jan 2023 11:34:52 -0800 Message-Id: <20230120193457.3295977-4-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120193457.3295977-1-lucas.demarchi@intel.com> References: <20230120193457.3295977-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 3/8] drm/i915: Convert pll macros to _PICK_EVEN_2RANGES X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the array lookup, converting the PLL macros after ICL to _PICK_EVEN_RANGES. This provides the following reduction in code size: $ size build64/drivers/gpu/drm/i915/i915.o{.old,.new} text data bss dec hex filename 4027456 185703 6984 4220143 4064ef build64/drivers/gpu/drm/i915/i915.o.old 4026997 185703 6984 4219684 406324 build64/drivers/gpu/drm/i915/i915.o.new At the same time it's safer, avoiding out-of-bounds array access. This allows to remove _MMIO_PLL3() that is now unused. Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa --- .../drm/i915/display/intel_display_reg_defs.h | 1 - drivers/gpu/drm/i915/i915_reg.h | 59 +++++++++---------- 2 files changed, 29 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index 02605418ff08..a4ed1c530799 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -34,7 +34,6 @@ #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) -#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__)) /* * Device info offset array based helpers for groups of registers with unevenly diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8da3546d82fb..dd1eb8b10e0e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7232,13 +7232,15 @@ enum skl_power_gate { #define PLL_LOCK REG_BIT(30) #define PLL_POWER_ENABLE REG_BIT(27) #define PLL_POWER_STATE REG_BIT(26) -#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ - _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) +#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE)) #define _DG2_PLL3_ENABLE 0x4601C -#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ - _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE) +#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE)) #define TBT_PLL_ENABLE _MMIO(0x46020) @@ -7251,8 +7253,9 @@ enum skl_power_gate { _MG_PLL2_ENABLE) /* DG1 PLL */ -#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \ - _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) +#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _DPLL0_ENABLE, _DPLL1_ENABLE, \ + _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)) /* ADL-P Type C PLL */ #define PORTTC1_PLL_ENABLE 0x46038 @@ -7312,9 +7315,9 @@ enum skl_power_gate { #define _TGL_DPLL0_CFGCR0 0x164284 #define _TGL_DPLL1_CFGCR0 0x16428C #define _TGL_TBTPLL_CFGCR0 0x16429C -#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ - _TGL_DPLL1_CFGCR0, \ - _TGL_TBTPLL_CFGCR0) +#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0)) #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ _TGL_DPLL1_CFGCR0) @@ -7327,40 +7330,36 @@ enum skl_power_gate { #define _TGL_DPLL0_CFGCR1 0x164288 #define _TGL_DPLL1_CFGCR1 0x164290 #define _TGL_TBTPLL_CFGCR1 0x1642A0 -#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ - _TGL_DPLL1_CFGCR1, \ - _TGL_TBTPLL_CFGCR1) +#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1)) #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ _TGL_DPLL1_CFGCR1) #define _DG1_DPLL2_CFGCR0 0x16C284 #define _DG1_DPLL3_CFGCR0 0x16C28C -#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ - _TGL_DPLL1_CFGCR0, \ - _DG1_DPLL2_CFGCR0, \ - _DG1_DPLL3_CFGCR0) +#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0)) #define _DG1_DPLL2_CFGCR1 0x16C288 #define _DG1_DPLL3_CFGCR1 0x16C290 -#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ - _TGL_DPLL1_CFGCR1, \ - _DG1_DPLL2_CFGCR1, \ - _DG1_DPLL3_CFGCR1) +#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1)) /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ -#define _ADLS_DPLL3_CFGCR0 0x1642C0 #define _ADLS_DPLL4_CFGCR0 0x164294 -#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ - _TGL_DPLL1_CFGCR0, \ - _ADLS_DPLL4_CFGCR0, \ - _ADLS_DPLL3_CFGCR0) +#define _ADLS_DPLL3_CFGCR0 0x1642C0 +#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \ + _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0)) -#define _ADLS_DPLL3_CFGCR1 0x1642C4 #define _ADLS_DPLL4_CFGCR1 0x164298 -#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ - _TGL_DPLL1_CFGCR1, \ - _ADLS_DPLL4_CFGCR1, \ - _ADLS_DPLL3_CFGCR1) +#define _ADLS_DPLL3_CFGCR1 0x1642C4 +#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \ + _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \ + _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1)) /* BXT display engine PLL */ #define BXT_DE_PLL_CTL _MMIO(0x6d000) From patchwork Fri Jan 20 19:34:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13110447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3568DC27C76 for ; Fri, 20 Jan 2023 19:35:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5780D10EAF6; Fri, 20 Jan 2023 19:35:21 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0594A10E39E; Fri, 20 Jan 2023 19:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674243318; x=1705779318; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+A6u6Dm+W6VYAnIKR343UApRkptUBLSsC6KlmZwUjTw=; b=BGPuaRaq1XoMRN3o0WTjh9JejfsAiremnRacgS51x2agORsEBMlbOO51 lJyMpf88P1D6az6u/AGogbJBNDtTcx6pQuoEgoiQO4ElQ+B6oit+2NzEk 7SKPkWxQVfEk1xsluJmh4bZrEQDn6+pUjP9JxCOHaRo9X5/x56DlMl0aY rZicjJ88/ejx6oBHPKR1hgYdVCMpmFX05ESAIMFu0KZJhCxHgrM8vqElD EVwXHDuLvs6USjQbos6f+e9/6pkQndZLKYZjOGjbaji7R0Pe3hWMYNQXF F+qt7MKhWzBTb3i9FVfJ6csrEDXf+Crd71qthotexKDgDXNwNMyOT00ab g==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411903538" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="411903538" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:17 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="834518310" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="834518310" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:16 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 20 Jan 2023 11:34:53 -0800 Message-Id: <20230120193457.3295977-5-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120193457.3295977-1-lucas.demarchi@intel.com> References: <20230120193457.3295977-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 4/8] drm/i915: Replace _MMIO_PHY3() with _PICK_EVEN_2RANGES() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As done previously for pll, also convert users of _PHY3() to _PICK_EVEN_2RANGES(). Size comparison of i915.o: $ size build64/drivers/gpu/drm/i915/i915.o{.old,.new} text data bss dec hex filename 4026997 185703 6984 4219684 406324 build64/drivers/gpu/drm/i915/i915.o.old 4026288 185703 6984 4218975 40605f build64/drivers/gpu/drm/i915/i915.o.new Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa --- .../drm/i915/display/intel_display_reg_defs.h | 3 --- drivers/gpu/drm/i915/i915_reg.h | 16 +++++++++------- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index a4ed1c530799..f1681e1396b5 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -29,11 +29,8 @@ #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) -#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) - #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) -#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) /* * Device info offset array based helpers for groups of registers with unevenly diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index dd1eb8b10e0e..fe6385443c4a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -541,9 +541,10 @@ #define _BXT_PHY0_BASE 0x6C000 #define _BXT_PHY1_BASE 0x162000 #define _BXT_PHY2_BASE 0x163000 -#define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ - _BXT_PHY1_BASE, \ - _BXT_PHY2_BASE) +#define BXT_PHY_BASE(phy) \ + _PICK_EVEN_2RANGES(phy, 1, \ + _BXT_PHY0_BASE, _BXT_PHY0_BASE, \ + _BXT_PHY1_BASE, _BXT_PHY2_BASE) #define _BXT_PHY(phy, reg) \ _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) @@ -566,13 +567,14 @@ #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ _BXT_PHY_CTL_DDI_B) -#define _PHY_CTL_FAMILY_EDP 0x64C80 #define _PHY_CTL_FAMILY_DDI 0x64C90 +#define _PHY_CTL_FAMILY_EDP 0x64C80 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 #define COMMON_RESET_DIS (1 << 31) -#define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ - _PHY_CTL_FAMILY_EDP, \ - _PHY_CTL_FAMILY_DDI_C) +#define BXT_PHY_CTL_FAMILY(phy) \ + _MMIO(_PICK_EVEN_2RANGES(phy, 1, \ + _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \ + _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C)) /* BXT PHY PLL registers */ #define _PORT_PLL_A 0x46074 From patchwork Fri Jan 20 19:34:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13110444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7B20C05027 for ; Fri, 20 Jan 2023 19:35:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1C9BF10EAFA; Fri, 20 Jan 2023 19:35:19 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id AD48310E39D; Fri, 20 Jan 2023 19:35:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674243317; x=1705779317; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Nws+b8Tv9yMcVHF4dRTjJJJLwq5I7tBHqORq8QtOAe0=; b=fajn2Z65tbGxQ77OS8dalVA7BNptn/fcTNde9kuuC8F/PTMPUss9XOzt 2hu7Qb2Ux5NS1qgUfbe2Pevpeb4eO5eoMR1Dyd3JTsAonW1n2rzvO58U5 Z425Hne2lPj7QPkzj6fikR6Va7+7UEUIQ3tsdNEv5MJtYh8u/n4W1v2Pv grmmlXdQxizVTocdqOQi5dxE4iC+TriAYUySjxeIqSYqmfCGSKSYCWDV9 xj3/KudIcZHtZLwaSKXjxs0Td/gkyULyQBPqTOh0J1jF/4lvp/iaE8iBJ Fp8MSoHjwiLXdZPbjs+XCJX9ZAKF4DZOqVPY/I6ZZlWgVjeyEtB40XTzW Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411903536" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="411903536" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:17 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="834518314" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="834518314" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:16 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 20 Jan 2023 11:34:54 -0800 Message-Id: <20230120193457.3295977-6-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120193457.3295977-1-lucas.demarchi@intel.com> References: <20230120193457.3295977-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 5/8] drm/i915: Convert PIPE3/PORT3 to _PICK_EVEN_2RANGES() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Like done for when __var_args__ were used, but size-wise it's also benefitial to avoid _PICK() used for 3 ports/pipes: $ size build64/drivers/gpu/drm/i915/i915.o{.old,.new} text data bss dec hex filename 4026288 185703 6984 4218975 40605f build64/drivers/gpu/drm/i915/i915.o.old 4025496 185703 6984 4218183 405d47 build64/drivers/gpu/drm/i915/i915.o.new Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_display_reg_defs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index f1681e1396b5..755c1ea8225c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -13,7 +13,7 @@ #define VLV_DISPLAY_BASE 0x180000 /* - * Named helper wrappers around _PICK_EVEN() and _PICK(). + * Named helper wrappers around _PICK_EVEN() and _PICK_EVEN_2RANGES(). */ #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) @@ -29,8 +29,8 @@ #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) -#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) -#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) +#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) +#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) /* * Device info offset array based helpers for groups of registers with unevenly From patchwork Fri Jan 20 19:34:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13110450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EBEBC05027 for ; Fri, 20 Jan 2023 19:35:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 352B410EB07; Fri, 20 Jan 2023 19:35:35 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 03CAC10EAF8; Fri, 20 Jan 2023 19:35:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674243319; x=1705779319; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K9Rwmr+p+yYte04uXq7uaLaekVzftRt5vKKh8dUuOMI=; b=TMtQNhNGbueocdIDkqzUsCxIEme+ya6x+VO6Ts6sqIGU22ffX9LXUKUO 4BSuBFVevVPD81QMMGCN26D+F/FKXAsACI+Hfrz33b2E8OjosqEZvLZIg hcYvDPaTBfTGMN2ys6ZMlSYHz2aU/H7rk+fjWMrZoXqPv2VN2Yxb5SIiT ZUZ3/P0OPkxV3AenjVRVYizfmVoCJjVCzxYJFoj+V4AVRoNMuIcFJVsX1 /QLN47AdR7q0a0Vm1ijWzH2HZX3iOJgY4YUM91V/0oS/a+eQknjdnSh7d 2o4X91KGq5es4DR1/dXxzXJXRwxdPPokK+9Ym7/WI5zqw11F7wBsEN9ff Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411903540" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="411903540" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:17 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="834518317" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="834518317" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:16 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 20 Jan 2023 11:34:55 -0800 Message-Id: <20230120193457.3295977-7-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120193457.3295977-1-lucas.demarchi@intel.com> References: <20230120193457.3295977-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 6/8] drm/i915: Convert _FIA() to _PICK_EVEN_2RANGES() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" _FIA() can use _PICK_EVEN_2RANGES instead of _PICK, which reduces the size and is safer. Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_mg_phy_regs.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h index 0e8248bce52d..0306ade2bc30 100644 --- a/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_mg_phy_regs.h @@ -142,7 +142,9 @@ #define FIA1_BASE 0x163000 #define FIA2_BASE 0x16E000 #define FIA3_BASE 0x16F000 -#define _FIA(fia) _PICK((fia), FIA1_BASE, FIA2_BASE, FIA3_BASE) +#define _FIA(fia) _PICK_EVEN_2RANGES((fia), 1, \ + FIA1_BASE, FIA1_BASE,\ + FIA2_BASE, FIA3_BASE) #define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off)) /* ICL PHY DFLEX registers */ From patchwork Fri Jan 20 19:34:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13110448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37E2EC27C76 for ; Fri, 20 Jan 2023 19:35:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E30C10EB01; Fri, 20 Jan 2023 19:35:26 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2BB3A10EAFC; Fri, 20 Jan 2023 19:35:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674243319; x=1705779319; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RmHp35HZdITzZMST9XxXP5+dDBzZpKoMgvb3vxaufVA=; b=ZCVPObySSsBqmFVO66OA2vyzu9Bq+AJQ3WUF4Ze2KnmMSDWaTO+qvycH K5LHe1cTCMhWFNb3quGPnSQXC7PgITVUnZlKHwPaof0zjWYTz/71jQnjL pR8JnONOMnIxj3RrfxhNDsukXGPAX8/ebQCr65LEgtlrBPkIeXdbHxVBx QFMaYGaW8mkMSmhxA12Y7LZmFGsQv4ORfQa0LzejVQMSXskynDdJcFrsQ aNalsxWduR7FfQaUyacU8vVgCQKrGL23XZEybp9BouNZrRhn0jiTIQkjX fQ7yo2h6J7WfKZU/ZGw6gmKPYRKLRexVtcBfMZqj8hHXg7q0HFzM/qtYo w==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411903545" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="411903545" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:18 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="834518320" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="834518320" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:16 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 20 Jan 2023 11:34:56 -0800 Message-Id: <20230120193457.3295977-8-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120193457.3295977-1-lucas.demarchi@intel.com> References: <20230120193457.3295977-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 7/8] drm/i915: Convert MBUS_ABOX_CTL() to _PICK_EVEN_2RANGES() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" MBUS_ABOX_CTL() can use _PICK_EVEN_2RANGES instead of _PICK, which reduces the size and is safer. Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_reg.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fe6385443c4a..3d6ad4424265 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1040,9 +1040,11 @@ #define _MBUS_ABOX0_CTL 0x45038 #define _MBUS_ABOX1_CTL 0x45048 #define _MBUS_ABOX2_CTL 0x4504C -#define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ - _MBUS_ABOX1_CTL, \ - _MBUS_ABOX2_CTL)) +#define MBUS_ABOX_CTL(x) \ + _MMIO(_PICK_EVEN_2RANGES(x, 2, \ + _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \ + _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL)) + #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) From patchwork Fri Jan 20 19:34:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 13110449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BEAAC25B50 for ; Fri, 20 Jan 2023 19:35:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 034C110EB04; Fri, 20 Jan 2023 19:35:30 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4EDE310EAFD; Fri, 20 Jan 2023 19:35:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1674243319; x=1705779319; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JZy+a1wh/irdNN2NOvJaI18iXOd/CkgSTUrviirubLQ=; b=e8pX+0kZu0jNushX+pN/PZ9E8X9ynnPOuWEh0ruRZxpj4kL46wSvw/7Z YNGOPsy0EN04LRJItCMIuPaSBA6Bqwd5nzGamqArLrE3l/gstM2+tOqzw Y9RY3HQttmrUWv4jAFzsTbaM2kb1G/Rjk/wlr5WxGQcwBcXXm3erspOLI aBamjNAu6/5tjOjX+nC4RvY6PX1yj4A7IV8mbDNG2F9fT7TcEYwDwyABi eCYdFDQlovzPz7zk4Sl1tpInAHqKrPfrmM7E3eC+LfZG345QAyygyKuDC sppUDJ92wuSF25XG1dCgcFVj0XnBPhQgf8zyWUy1BBcmKelrsKghG/N20 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="411903546" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="411903546" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:18 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10596"; a="834518325" X-IronPort-AV: E=Sophos;i="5.97,233,1669104000"; d="scan'208";a="834518325" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2023 11:35:16 -0800 From: Lucas De Marchi To: intel-gfx@lists.freedesktop.org Date: Fri, 20 Jan 2023 11:34:57 -0800 Message-Id: <20230120193457.3295977-9-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120193457.3295977-1-lucas.demarchi@intel.com> References: <20230120193457.3295977-1-lucas.demarchi@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 8/8] drm/i915: Convert PALETTE() to _PICK_EVEN_2RANGES() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" PALETTE() can use _PICK_EVEN_2RANGES instead of _PICK, which reduces the size and is safer. Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_reg.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3d6ad4424265..b134a1f357c8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1734,10 +1734,11 @@ #define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) #define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) #define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) -#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ - _PICK((pipe), _PALETTE_A, \ - _PALETTE_B, _CHV_PALETTE_C) + \ - (i) * 4) +#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ + _PICK_EVEN_2RANGES(pipe, 2, \ + _PALETTE_A, _PALETTE_B, \ + _CHV_PALETTE_C, _CHV_PALETTE_C) + \ + (i) * 4) #define PEG_BAND_GAP_DATA _MMIO(0x14d68)