From patchwork Thu Jan 26 14:40:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13117249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE886C05027 for ; Thu, 26 Jan 2023 14:40:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231664AbjAZOks (ORCPT ); Thu, 26 Jan 2023 09:40:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229491AbjAZOkr (ORCPT ); Thu, 26 Jan 2023 09:40:47 -0500 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1449A618B for ; Thu, 26 Jan 2023 06:40:46 -0800 (PST) Received: by mail-ej1-x62e.google.com with SMTP id bk15so5562807ejb.9 for ; Thu, 26 Jan 2023 06:40:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IrFPxpcXauUCjSJ1xRyDF+r/rVJ2enA59bYfUgUOYx4=; b=c57OUNlBNlPoR81q5Kb6sg4ldd4EFJxzQZrQs41VRo35h+2vGnFoC6Mclal18r4HzM hwwnA2lKx4/r/WaMGJA33e6DNtr6+EF6mRQUJQFCvuguEaqeSCgimepGRmU21OY8aHls uaOydfzy9+IKVVoSUq41GlMifkUSnFiy2wdbe2YgQPbvAchTrtlUPN73yaniHfSPS1fL aGK4b5deIOqYdSZBR4oc+jo7x/DFC3cjI3b1lkLBzDDlVopfZxfbACV9DcQlxPttJXVn gBkayUKUSmdM6YYNPGEdLwuiOHdWbg3rbU7wcKG9DnTOuY1O9gXBtmCFuAUsa5dX94TD nZoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IrFPxpcXauUCjSJ1xRyDF+r/rVJ2enA59bYfUgUOYx4=; b=Ul0UIKcoQWpknrlCn4VDTNo8OwBR6Atz9lwzhnKMOZmT6Xcy1Ph6Ra3ouFQpVHYnYY UoQqGOC2VjuHFBhPZWM6InDhL0wZSJPdao6gRIlEUimxsaVexXLWrxgd9wueX+0/fvmZ EpHsfMxSldWz7QqGP8hRxXgrWSJkmxRgjw9ylCl9LzrwegmJzpXfvjal54nzCMvCQjbT dzs2rrv0SRzwTdifgkpBD+HzbNo3pVFm6mfPnCWXd/2LqbVgmaPpsVnXMOFJVhM7K7R/ 1DfCRksYK4xcbq02EmAGJwSSJMm0CMC9zS2XpTvj9Nlt7xqyO4Dwa6pcVhfB9K1jAbAC di1A== X-Gm-Message-State: AFqh2kpt23HycH0OMwfSDr/RuBFOEVrgvYKSW3ug4lapWvHxZkKX36ew hUVhuKeZRJlX2DXLkhvyg1cEBA== X-Google-Smtp-Source: AMrXdXuG1NCHlDPWwadVs+e4B6jOmjWWgqY2QmZDIehqUBVhKvLAs1qnxMSM+s5AMIukIWSjRr+SZA== X-Received: by 2002:a17:906:2402:b0:874:e17e:2526 with SMTP id z2-20020a170906240200b00874e17e2526mr32612934eja.72.1674744044643; Thu, 26 Jan 2023 06:40:44 -0800 (PST) Received: from localhost.localdomain (abyk108.neoplus.adsl.tpnet.pl. [83.9.30.108]) by smtp.gmail.com with ESMTPSA id s19-20020a1709060c1300b008699bacc03csm697547ejf.14.2023.01.26.06.40.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 06:40:44 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] dt-bindings: clock: Add Qcom SM6125 GPUCC Date: Thu, 26 Jan 2023 15:40:28 +0100 Message-Id: <20230126144033.216206-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126144033.216206-1-konrad.dybcio@linaro.org> References: <20230126144033.216206-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6125 SoCs. Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,sm6125-gpucc.yaml | 64 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6125-gpucc.h | 31 +++++++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6125-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml new file mode 100644 index 000000000000..374a1844a159 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6125 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks and power domains on + Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6125-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6125-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6125-gpucc.h b/include/dt-bindings/clock/qcom,sm6125-gpucc.h new file mode 100644 index 000000000000..ce5bd920f2c4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6125-gpucc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H + +/* Clocks */ +#define GPU_CC_PLL0_OUT_AUX2 0 +#define GPU_CC_PLL1_OUT_AUX2 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GFX3D_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_SLEEP_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_AHB_CLK 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Thu Jan 26 14:40:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13117250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38764C05027 for ; Thu, 26 Jan 2023 14:40:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232281AbjAZOky (ORCPT ); Thu, 26 Jan 2023 09:40:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229491AbjAZOku (ORCPT ); Thu, 26 Jan 2023 09:40:50 -0500 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D604E2724 for ; Thu, 26 Jan 2023 06:40:48 -0800 (PST) Received: by mail-ej1-x62e.google.com with SMTP id bk15so5563388ejb.9 for ; Thu, 26 Jan 2023 06:40:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l7zcErxqlxqs6kCMd6LtTu3Ww8CQfRK8SEJg/YZ2bS8=; b=KIA+X1O8rDbJJRjKiRV+UktRHucHl2/RaKbeeecs4sfPVn8JGjzeOMQtB/v5BX7+Ii JFrVPu5IosqMW47jYFHIDQLHyBjOXLJWKkCPRG8otpBz0UBuDjItfRFr92yZHdJhps/8 SM2xKjcB/pqTNc3tdUIOHDVpQwwm8Z98vQmjgQhsisCcL/LbBHzMy5CO76+Oz8+dNEid IpwGsFo9PEUFMWMBNNSBAV47nVsbHZxz8N3YY4Y85GNQ7N9Za3B4SjdWPiSIIW/wrq3z ME5CZaYFGmUlR98cmwf0UPf7Qzd0q4H2fmG8QqtjEK/5vssoltEUx9YuzTFdUcyCXQd9 4Q7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l7zcErxqlxqs6kCMd6LtTu3Ww8CQfRK8SEJg/YZ2bS8=; b=BOBmx4tQQN6JivPtl2cLkNijYeVTUTTjU46pRX1BTCvV/CVzhDU8Owp1QNucFRp0Z1 9v8ZIz5+mzSHDlz9U4MA1h44kvE3UBgw7QE/7X4EBNhn72G/MQnxJX4MKNaTjF6iO8Jx NnBik5ahhZsfrjWaRmZ1d0vW2SHnU87uPQey8qCkcqPDPvCAFyyeUufildvzLcQcFdF8 RX4pO+85ZE3Wbq9wAgbzKWgr6GAJlsKOqEB0/Spg47X2wPcyRzecK5vvsH7+aKsNvK+i J/0LzANtdrbpPe5E+MOYb1nL8VkwK/NY8HoqzdglpIlfxQqoTWE3hDkAbnFjm5uinXV5 jpYA== X-Gm-Message-State: AFqh2kqb0HB8v7Vmy2AsZL07+IbLGiXymXB+9OcTKllfeLFiZ6seosOj XqUHCwik6YnJ9lSWoLlNCHQ7XA== X-Google-Smtp-Source: AMrXdXsXYC9ZSNByHYw628weMYfX3xwDM6OzV4jamZoxvUTepoG47rmZqheJmJdmcEYqFGk5p+6eVg== X-Received: by 2002:a17:906:5e09:b0:7c1:727c:5f70 with SMTP id n9-20020a1709065e0900b007c1727c5f70mr36822136eju.46.1674744048399; Thu, 26 Jan 2023 06:40:48 -0800 (PST) Received: from localhost.localdomain (abyk108.neoplus.adsl.tpnet.pl. [83.9.30.108]) by smtp.gmail.com with ESMTPSA id s19-20020a1709060c1300b008699bacc03csm697547ejf.14.2023.01.26.06.40.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 06:40:47 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/6] clk: qcom: Add GPU clock controller driver for SM6125 Date: Thu, 26 Jan 2023 15:40:29 +0100 Message-Id: <20230126144033.216206-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126144033.216206-1-konrad.dybcio@linaro.org> References: <20230126144033.216206-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add support for the GPU clock controller found on SM6125. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm6125.c | 444 ++++++++++++++++++++++++++++++++ 3 files changed, 453 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm6125.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ca6c7d2ada6c..ca2c83ecc6a6 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -798,6 +798,14 @@ config SM_GCC_8550 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. +config SM_GPUCC_6125 + tristate "SM6125 Graphics Clock Controller" + select SM_GCC_6125 + help + Support for the graphics clock controller on SM6125 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_GPUCC_6350 tristate "SM6350 Graphics Clock Controller" select SM_GCC_6350 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index e41ea0efe8c4..14405ccf1992 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o +obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o diff --git a/drivers/clk/qcom/gpucc-sm6125.c b/drivers/clk/qcom/gpucc-sm6125.c new file mode 100644 index 000000000000..34cd8459c121 --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm6125.c @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +#define CX_GMU_CBCR_SLEEP_MASK 0xf +#define CX_GMU_CBCR_SLEEP_SHIFT 4 +#define CX_GMU_CBCR_WAKE_MASK 0xf +#define CX_GMU_CBCR_WAKE_SHIFT 8 + +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPU_CC_PLL0_2X_CLK, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL1_OUT_AUX, + P_GPU_CC_PLL1_OUT_AUX2, +}; + +static struct pll_vco gpu_cc_pll_vco[] = { + { 1000000000, 2000000000, 0 }, + { 500000000, 1000000000, 2 }, +}; + +/* 1020MHz configuration */ +static const struct alpha_pll_config gpu_pll0_config = { + .l = 0x35, + .config_ctl_val = 0x4001055b, + .alpha_hi = 0x20, + .alpha = 0x00, + .alpha_en_mask = BIT(24), + .vco_val = 0x0 << 20, + .vco_mask = 0x3 << 20, + .aux2_output_mask = BIT(2), +}; + +/* 930MHz configuration */ +static const struct alpha_pll_config gpu_pll1_config = { + .l = 0x30, + .config_ctl_val = 0x4001055b, + .alpha_hi = 0x70, + .alpha = 0x00, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .aux2_output_mask = BIT(2), +}; + +static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = { + .offset = 0x0, + .vco_table = gpu_cc_pll_vco, + .num_vco = ARRAY_SIZE(gpu_cc_pll_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0_out_aux2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = { + .offset = 0x100, + .vco_table = gpu_cc_pll_vco, + .num_vco = ARRAY_SIZE(gpu_cc_pll_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1_out_aux2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL1_OUT_AUX2, 4 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0_out_aux2.clkr.hw }, + { .hw = &gpu_cc_pll1_out_aux2.clkr.hw }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(320000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0), + F(465000000, P_GPU_CC_PLL1_OUT_AUX2, 2, 0, 0), + F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_apb_clk = { + .halt_reg = 0x1088, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1088, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_apb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &gpu_cc_gx_gfx3d_clk.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_data = &(const struct clk_parent_data) { + .hw = &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .pd = { + .name = "gpu_gx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm6125_clocks[] = { + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr, + [GPU_CC_PLL1_OUT_AUX2] = &gpu_cc_pll1_out_aux2.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, +}; + +static struct gdsc *gpucc_sm6125_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm6125_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm6125_desc = { + .config = &gpu_cc_sm6125_regmap_config, + .clks = gpu_cc_sm6125_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm6125_clocks), + .gdscs = gpucc_sm6125_gdscs, + .num_gdscs = ARRAY_SIZE(gpucc_sm6125_gdscs), +}; + +static const struct of_device_id gpu_cc_sm6125_match_table[] = { + { .compatible = "qcom,sm6125-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm6125_match_table); + +static int gpu_cc_sm6125_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + unsigned int value, mask; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm6125_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&gpu_cc_pll0_out_aux2, regmap, &gpu_pll0_config); + clk_alpha_pll_configure(&gpu_cc_pll1_out_aux2, regmap, &gpu_pll1_config); + + /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ + mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; + mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; + value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; + regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg, mask, value); + + /* Set up PERIPH/MEM retain on the GPU core clock */ + regmap_update_bits(regmap, gpu_cc_gx_gfx3d_clk.halt_reg, + (BIT(14) | BIT(13)), (BIT(14) | BIT(13))); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm6125_desc, regmap); +} + +static struct platform_driver gpu_cc_sm6125_driver = { + .probe = gpu_cc_sm6125_probe, + .driver = { + .name = "gpucc-sm6125", + .of_match_table = gpu_cc_sm6125_match_table, + }, +}; + +static int __init gpu_cc_sm6125_init(void) +{ + return platform_driver_register(&gpu_cc_sm6125_driver); +} +subsys_initcall(gpu_cc_sm6125_init); + +static void __exit gpu_cc_sm6125_exit(void) +{ + platform_driver_unregister(&gpu_cc_sm6125_driver); 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[83.9.30.108]) by smtp.gmail.com with ESMTPSA id s19-20020a1709060c1300b008699bacc03csm697547ejf.14.2023.01.26.06.40.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 06:40:51 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] dt-bindings: clock: Add Qcom SM6375 GPUCC Date: Thu, 26 Jan 2023 15:40:30 +0100 Message-Id: <20230126144033.216206-4-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126144033.216206-1-konrad.dybcio@linaro.org> References: <20230126144033.216206-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6375 SoCs. Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,sm6375-gpucc.yaml | 60 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6375-gpucc.h | 36 +++++++++++ 2 files changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6375-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml new file mode 100644 index 000000000000..b480ead5bd69 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6375 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6375-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + - description: SNoC DVM GFX source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,sm6375-gpucc"; + reg = <0 0x05990000 0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6375-gpucc.h b/include/dt-bindings/clock/qcom,sm6375-gpucc.h new file mode 100644 index 000000000000..0887ac03825e --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6375-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H + +/* GPU CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CX_GFX3D_CLK 3 +#define GPU_CC_CX_GFX3D_SLV_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GX_CXO_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_SLEEP_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +/* Resets */ +#define GPU_GX_BCR 0 +#define GPU_ACD_BCR 1 +#define GPU_GX_ACD_MISC_BCR 2 + +#endif From patchwork Thu Jan 26 14:40:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13117252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFDAEC05027 for ; Thu, 26 Jan 2023 14:41:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231773AbjAZOlG (ORCPT ); Thu, 26 Jan 2023 09:41:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232299AbjAZOlC (ORCPT ); Thu, 26 Jan 2023 09:41:02 -0500 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 270D46950E for ; Thu, 26 Jan 2023 06:40:56 -0800 (PST) Received: by mail-ej1-x62f.google.com with SMTP id hw16so5539214ejc.10 for ; Thu, 26 Jan 2023 06:40:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GmWy1d9ZN85PRAgpwumJAKrWc+3DCxaaFeh9n9Uk7E4=; b=DA7wTivwmIrEuRnuyycH8xkka3p9pj53TtyjNSJ15c3m7un9nt+wnRimrt0QGlmxDR 0nmLet61vdnz2Q37LUTunROjPt04NyAv1dqXmYT4id5yDQbUAhgXvmxNeDrprpTfaNEc 9mO5mnYLiUL1wha1VBNUoeyO38FjxbPdG4prqA9aMbua3XyLZb9SflziAAhbSRSMNY9j wzB28WPEnIydx8iBStOCWZT3nnToVrNDEX3FB9jKw5IOD6AYnyslsrrue7QJlonIi2uW g1PaBpiypRnsmL71DE/+KvcYuQqJ5MCMQCCNn6rAllRoGUuW5bM2znLq00gl94keD3kz zBkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GmWy1d9ZN85PRAgpwumJAKrWc+3DCxaaFeh9n9Uk7E4=; b=dCJn6LP5xk5URCNC+ZkGbsGxUcezKxU5p0YeLV6ZAGTeQAqQMo798hcVJN5UtTOn1j ShhKGkVo3ufTF+exf5qOJb2MhVBGqU74iyoGoazYVVNZ3bTRSlaKvnYgWnLqGEOWP93W YP7xH1Riac3FEZ0JcFSyn6oBwZtr1cEGqOjlb9lk8lVHXAM1vsGyfhZtJDjs3FNkRqk8 ATajUN8VYrcpGzpVsqNQqaJd9UqcexUcmR7p3snsAf28HjyVlkO66VXcWhF5D370nPol /I0VLwK17fTC2IJNb3OGdX17eyzAhnWNyh5CDpO8V+6k+yNwsSoSIA5B1pW2oy6otgMf gCtw== X-Gm-Message-State: AFqh2krtZewaKj+kVLGM43yfuGJfcdUNmQpBjzDPoubSJ+Ifi67gXOIT 4SpHEug/P3vUYgG8ua602pO+/w== X-Google-Smtp-Source: AMrXdXsyfOobIEAqAH6tpCEN6bkiAhTT02BfniZxEdrVxmml9je5vx2GKAyejohsL4QFUJz5j922hQ== X-Received: by 2002:a17:907:c243:b0:872:84dd:8903 with SMTP id tj3-20020a170907c24300b0087284dd8903mr40137973ejc.59.1674744054636; Thu, 26 Jan 2023 06:40:54 -0800 (PST) Received: from localhost.localdomain (abyk108.neoplus.adsl.tpnet.pl. [83.9.30.108]) by smtp.gmail.com with ESMTPSA id s19-20020a1709060c1300b008699bacc03csm697547ejf.14.2023.01.26.06.40.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 06:40:54 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 4/6] clk: qcom: Add GPU clock controller driver for SM6375 Date: Thu, 26 Jan 2023 15:40:31 +0100 Message-Id: <20230126144033.216206-5-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126144033.216206-1-konrad.dybcio@linaro.org> References: <20230126144033.216206-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add support for the GPU clock controller found on SM6375. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm6375.c | 480 ++++++++++++++++++++++++++++++++ 3 files changed, 489 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm6375.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ca2c83ecc6a6..c1af43c51a3e 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -806,6 +806,14 @@ config SM_GPUCC_6125 Say Y if you want to support graphics controller devices and functionality such as 3D graphics. +config SM_GPUCC_6375 + tristate "SM6375 Graphics Clock Controller" + select SM_GCC_6375 + help + Support for the graphics clock controller on SM6375 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_GPUCC_6350 tristate "SM6350 Graphics Clock Controller" select SM_GCC_6350 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 14405ccf1992..5a1b65b2ac05 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -114,6 +114,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o +obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c new file mode 100644 index 000000000000..9be3827acfae --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -0,0 +1,480 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, + DT_GCC_GPU_SNOC_DVM_GFX_CLK, +}; + +enum { + P_BI_TCXO, + P_GCC_GPU_GPLL0_CLK_SRC, + P_GCC_GPU_GPLL0_DIV_CLK_SRC, + P_GPU_CC_PLL0_OUT_EVEN, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL0_OUT_ODD, + P_GPU_CC_PLL1_OUT_EVEN, + P_GPU_CC_PLL1_OUT_MAIN, + P_GPU_CC_PLL1_OUT_ODD, +}; + +static struct pll_vco lucid_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +/* 532MHz Configuration */ +static const struct alpha_pll_config gpucc_pll0_config = { + .l = 0x1b, + .alpha = 0xb555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329a299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpucc_pll0 = { + .offset = 0x0, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpucc_pll0", + .parent_data = &(const struct clk_parent_data){ + .index = P_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +/* 514MHz Configuration */ +static const struct alpha_pll_config gpucc_pll1_config = { + .l = 0x1a, + .alpha = 0xc555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00002261, + .config_ctl_hi1_val = 0x329a299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000805, + .user_ctl_hi1_val = 0x00000000, +}; + +static struct clk_alpha_pll gpucc_pll1 = { + .offset = 0x100, + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpucc_pll1", + .parent_data = &(const struct clk_parent_data){ + .index = P_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_ops, + }, + }, +}; + +static const struct parent_map gpucc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GCC_GPU_GPLL0_CLK_SRC, 5 }, + { P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 }, +}; + +static const struct clk_parent_data gpucc_parent_data_0[] = { + { .index = P_BI_TCXO }, + { .hw = &gpucc_pll0.clkr.hw }, + { .hw = &gpucc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpucc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_EVEN, 1 }, + { P_GPU_CC_PLL0_OUT_ODD, 2 }, + { P_GPU_CC_PLL1_OUT_EVEN, 3 }, + { P_GPU_CC_PLL1_OUT_ODD, 4 }, + { P_GCC_GPU_GPLL0_CLK_SRC, 5 }, +}; + +static const struct clk_parent_data gpucc_parent_data_1[] = { + { .index = P_BI_TCXO }, + { .hw = &gpucc_pll0.clkr.hw }, + { .hw = &gpucc_pll0.clkr.hw }, + { .hw = &gpucc_pll1.clkr.hw }, + { .hw = &gpucc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, +}; + +static const struct parent_map gpucc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GCC_GPU_GPLL0_CLK_SRC, 5 }, + { P_GCC_GPU_GPLL0_DIV_CLK_SRC, 6 }, +}; + +static const struct clk_parent_data gpucc_parent_data_2[] = { + { .index = P_BI_TCXO }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct freq_tbl ftbl_gpucc_gmu_clk_src[] = { + F(200000000, P_GCC_GPU_GPLL0_DIV_CLK_SRC, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpucc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpucc_parent_map_0, + .freq_tbl = ftbl_gpucc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpucc_gmu_clk_src", + .parent_data = gpucc_parent_data_0, + .num_parents = ARRAY_SIZE(gpucc_parent_data_0), + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpucc_gx_gfx3d_clk_src[] = { + F(266000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(390000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(490000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(650000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(770000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(840000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(900000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpucc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpucc_parent_map_1, + .freq_tbl = ftbl_gpucc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_gfx3d_clk_src", + .parent_data = gpucc_parent_data_1, + .num_parents = ARRAY_SIZE(gpucc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpucc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpucc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_gfx3d_slv_clk = { + .halt_reg = 0x10a8, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_gfx3d_slv_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpucc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_gmu_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpucc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cx_snoc_dvm_clk", + .parent_data = &(const struct clk_parent_data){ + .index = DT_GCC_GPU_SNOC_DVM_GFX_CLK, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_gx_cxo_clk = { + .halt_reg = 0x1060, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_cxo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpucc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_gx_gmu_clk = { + .halt_reg = 0x1064, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1064, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_gx_gmu_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpucc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpucc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpucc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .resets = (unsigned int []){ GPU_GX_BCR, GPU_ACD_BCR, GPU_GX_ACD_MISC_BCR }, + .reset_count = 3, + .pd = { + .name = "gpu_gx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | SW_RESET | AON_RESET, +}; + +static struct clk_regmap *gpucc_sm6375_clocks[] = { + [GPU_CC_AHB_CLK] = &gpucc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpucc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GFX3D_SLV_CLK] = &gpucc_cx_gfx3d_slv_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpucc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpucc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpucc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpucc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpucc_gmu_clk_src.clkr, + [GPU_CC_GX_CXO_CLK] = &gpucc_gx_cxo_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpucc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpucc_gx_gfx3d_clk_src.clkr, + [GPU_CC_GX_GMU_CLK] = &gpucc_gx_gmu_clk.clkr, + [GPU_CC_PLL0] = &gpucc_pll0.clkr, + [GPU_CC_PLL1] = &gpucc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpucc_sleep_clk.clkr, +}; + +static const struct qcom_reset_map gpucc_sm6375_resets[] = { + [GPU_GX_BCR] = { 0x1008 }, + [GPU_ACD_BCR] = { 0x1160 }, + [GPU_GX_ACD_MISC_BCR] = { 0x8004 }, +}; + +static struct gdsc *gpucc_sm6375_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpucc_sm6375_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpucc_sm6375_desc = { + .config = &gpucc_sm6375_regmap_config, + .clks = gpucc_sm6375_clocks, + .num_clks = ARRAY_SIZE(gpucc_sm6375_clocks), + .resets = gpucc_sm6375_resets, + .num_resets = ARRAY_SIZE(gpucc_sm6375_resets), + .gdscs = gpucc_sm6375_gdscs, + .num_gdscs = ARRAY_SIZE(gpucc_sm6375_gdscs), +}; + +static const struct of_device_id gpucc_sm6375_match_table[] = { + { .compatible = "qcom,sm6375-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpucc_sm6375_match_table); + +static int gpucc_sm6375_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpucc_sm6375_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config); + clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config); + + return qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); +} + +static struct platform_driver gpucc_sm6375_driver = { + .probe = gpucc_sm6375_probe, + .driver = { + .name = "gpucc-sm6375", + .of_match_table = gpucc_sm6375_match_table, + }, +}; + +static int __init gpucc_sm6375_init(void) +{ + return platform_driver_register(&gpucc_sm6375_driver); +} +subsys_initcall(gpucc_sm6375_init); + +static void __exit gpucc_sm6375_exit(void) +{ + platform_driver_unregister(&gpucc_sm6375_driver); +} +module_exit(gpucc_sm6375_exit); + +MODULE_DESCRIPTION("QTI GPUCC SM6375 Driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Jan 26 14:40:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13117253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BB22C61DA2 for ; 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[83.9.30.108]) by smtp.gmail.com with ESMTPSA id s19-20020a1709060c1300b008699bacc03csm697547ejf.14.2023.01.26.06.40.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 06:40:57 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] dt-bindings: clock: Add Qcom SM6115 GPUCC Date: Thu, 26 Jan 2023 15:40:32 +0100 Message-Id: <20230126144033.216206-6-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126144033.216206-1-konrad.dybcio@linaro.org> References: <20230126144033.216206-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6115 SoCs. Signed-off-by: Konrad Dybcio --- .../bindings/clock/qcom,sm6115-gpucc.yaml | 71 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6115-gpucc.h | 36 ++++++++++ 2 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6115-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml new file mode 100644 index 000000000000..abf4e87359a3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6115 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks and power domains on + Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6115-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 main div source + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + '#reset-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6115-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6115-gpucc.h b/include/dt-bindings/clock/qcom,sm6115-gpucc.h new file mode 100644 index 000000000000..945f21a7d745 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6115-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL0_OUT_AUX2 1 +#define GPU_CC_PLL1 2 +#define GPU_CC_PLL1_OUT_AUX 3 +#define GPU_CC_AHB_CLK 4 +#define GPU_CC_CRC_AHB_CLK 5 +#define GPU_CC_CX_GFX3D_CLK 6 +#define GPU_CC_CX_GMU_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_CXO_CLK 12 +#define GPU_CC_GX_GFX3D_CLK 13 +#define GPU_CC_GX_GFX3D_CLK_SRC 14 +#define GPU_CC_SLEEP_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Thu Jan 26 14:40:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13117254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8535C05027 for ; Thu, 26 Jan 2023 14:41:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232290AbjAZOlX (ORCPT ); Thu, 26 Jan 2023 09:41:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232294AbjAZOlK (ORCPT ); Thu, 26 Jan 2023 09:41:10 -0500 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 918BA6BBE5 for ; Thu, 26 Jan 2023 06:41:02 -0800 (PST) Received: by mail-ej1-x630.google.com with SMTP id v6so5612269ejg.6 for ; Thu, 26 Jan 2023 06:41:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JluVtNgM6cGdpuX3lAwMhdOI0q7TEhGXOOIr3nGReeI=; b=ixRMq9H2sOxwKxwnElcDtvfXlGGK/sEv1WRq1TKGdJHtJmb1TXsHefKfZrmGf1ewrk NTYO5uY2uzIcz0cxXxJSKe+fbkTVC318E6rUVzEfnAWnFcS0MEYC8MqjVhoeFXkXzuLa MpTZLMpjw8rbMkatka7Ghxv/ZxEsxuQfDZft5GcGmHigBIjvQk+gfUucRnZjCk9fhXIr zzRYK9yKcXFSNIQ/hQEdyJ0QyFy5ttX41C080xtJ/y7JLnPaHEGSJ01b4LfM6jzgt/9D I5BkcChPqNfckA3JPbyCk96Ljucoghg9NEXm8Ucj7PxJbyMcPlOFfiaodh0LT9bhiFCl 0/bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JluVtNgM6cGdpuX3lAwMhdOI0q7TEhGXOOIr3nGReeI=; b=A9CbcSbAunwEnjDzoQ5i4HCGtKQyel20byoZheelH6GKxpuaU+jxQuQZbmrrEP7Hwb xcUqnPP0WjsGdgGnskGqvsEO6rQNWXUh1JevyrU8ZEyhgdxk7aDCDPMrkLbygQyhoNKH qVZooY4xMJlPyGCkQY1lWc/evGB+WBdb0FJBNi1Xn6HCEOKu7zYO77Y/cxw8OJPRr1eJ XUdpfzbU/fB0h1TQfwRGGa8YyUoMnXQL7mehUvr11K0NB3xiBWroDYzJoEXMsVTXPGSF c57ca9P65VXHN7st+gF4EIQ6SetkcQPS0wolvvYvVKAtvMohi4EzO3vLOWR9h6KU3wx5 4x9g== X-Gm-Message-State: AFqh2koZetOyo4mizYUAV1Pwaz8xyIBsUEFuKOKVb5q7dR8VRahZMLIl wyKlbCwAF3QikZ17+J9ICGkRgA== X-Google-Smtp-Source: AMrXdXszl+hs5tRC3RLNHnPB2Gi7HIikl/kZplNyGuSiLVmoWWjISazItT2BE70CoU8jjWDnilrXJg== X-Received: by 2002:a17:906:40cc:b0:870:45ec:3125 with SMTP id a12-20020a17090640cc00b0087045ec3125mr39618111ejk.46.1674744060587; Thu, 26 Jan 2023 06:41:00 -0800 (PST) Received: from localhost.localdomain (abyk108.neoplus.adsl.tpnet.pl. [83.9.30.108]) by smtp.gmail.com with ESMTPSA id s19-20020a1709060c1300b008699bacc03csm697547ejf.14.2023.01.26.06.40.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 06:41:00 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: marijn.suijten@somainline.org, Konrad Dybcio , Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 6/6] clk: qcom: Add GPU clock controller driver for SM6115 Date: Thu, 26 Jan 2023 15:40:33 +0100 Message-Id: <20230126144033.216206-7-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126144033.216206-1-konrad.dybcio@linaro.org> References: <20230126144033.216206-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add support for the GPU clock controller found on SM6115. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sm6115.c | 523 ++++++++++++++++++++++++++++++++ 3 files changed, 532 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sm6115.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index c1af43c51a3e..f3a0469788b8 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -798,6 +798,14 @@ config SM_GCC_8550 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, SD/UFS, PCIe etc. +config SM_GPUCC_6115 + tristate "SM6125 Graphics Clock Controller" + select SM_GCC_6125 + help + Support for the graphics clock controller on SM6115 devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SM_GPUCC_6125 tristate "SM6125 Graphics Clock Controller" select SM_GCC_6125 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 5a1b65b2ac05..9f6b93698ef2 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -112,6 +112,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o +obj-$(CONFIG_SM_GPUCC_6115) += gpucc-sm6115.o obj-$(CONFIG_SM_GPUCC_6125) += gpucc-sm6125.o obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o obj-$(CONFIG_SM_GPUCC_6375) += gpucc-sm6375.o diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c new file mode 100644 index 000000000000..0a1bb9dbf9ff --- /dev/null +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "clk-regmap-phy-mux.h" +#include "gdsc.h" +#include "reset.h" + +#define CX_GMU_CBCR_SLEEP_MASK 0xf +#define CX_GMU_CBCR_SLEEP_SHIFT 4 +#define CX_GMU_CBCR_WAKE_MASK 0xf +#define CX_GMU_CBCR_WAKE_SHIFT 8 + +enum { + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_AUX2, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_AUX, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static struct pll_vco default_vco[] = { + { 1000000000, 2000000000, 0 }, +}; + +static struct pll_vco pll1_vco[] = { + { 500000000, 1000000000, 2 }, +}; + +static const struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x3e, + .alpha = 0, + .alpha_hi = 0x80, + .vco_val = 0x0 << 20, + .vco_mask = GENMASK(21, 20), + .alpha_en_mask = BIT(24), + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .aux2_output_mask = BIT(2), + .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, +}; + +/* 1200MHz configuration */ +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = default_vco, + .num_vco = ARRAY_SIZE(default_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll0_out_aux2[] = { + { 0x0, 1 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_aux2 = { + .offset = 0x0, + .post_div_shift = 8, + .post_div_table = post_div_table_gpu_cc_pll0_out_aux2, + .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll0_out_aux2), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll0_out_aux2", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ops, + }, +}; + +/* 640MHz configuration */ +static const struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x21, + .alpha = 0x55555555, + .alpha_hi = 0x55, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = GENMASK(21, 20), + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x100, + .vco_table = pll1_vco, + .num_vco = ARRAY_SIZE(pll1_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &(const struct clk_parent_data){ + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpu_cc_pll1_out_aux[] = { + { 0x0, 1 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpu_cc_pll1_out_aux = { + .offset = 0x100, + .post_div_shift = 15, + .post_div_table = post_div_table_gpu_cc_pll1_out_aux, + .num_post_div = ARRAY_SIZE(post_div_table_gpu_cc_pll1_out_aux), + .width = 3, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1_out_aux", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ops, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = P_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_AUX2, 2 }, + { P_GPU_CC_PLL1_OUT_AUX, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = P_BI_TCXO }, + { .hw = &gpu_cc_pll0_out_aux2.clkr.hw }, + { .hw = &gpu_cc_pll1_out_aux.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { + F(320000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0), + F(465000000, P_GPU_CC_PLL1_OUT_AUX, 2, 0, 0), + F(600000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(745000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(820000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(900000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(950000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + F(980000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { + .cmd_rcgr = 0x101c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x1078, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1078, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gfx3d_clk = { + .halt_reg = 0x10a4, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x10a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_cxo_clk = { + .halt_reg = 0x1060, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_cxo_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_gx_gfx3d_clk = { + .halt_reg = 0x1054, + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x1054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gx_gfx3d_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gx_gfx3d_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x1090, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x1090, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x5000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc gpu_cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "gpu_cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE, +}; + +static struct gdsc gpu_gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .resets = (unsigned int []){ GPU_GX_BCR }, + .reset_count = 1, + .pd = { + .name = "gpu_gx_gdsc", + }, + .parent = &gpu_cx_gdsc.pd, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO | SW_RESET | VOTABLE, +}; + +static struct clk_regmap *gpu_cc_sm6115_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr, + [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, + [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL0_OUT_AUX2] = &gpu_cc_pll0_out_aux2.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_PLL1_OUT_AUX] = &gpu_cc_pll1_out_aux.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, +}; + +static const struct qcom_reset_map gpu_cc_sm6115_resets[] = { + [GPU_GX_BCR] = { 0x1008 }, +}; + +static struct gdsc *gpu_cc_sm6115_gdscs[] = { + [GPU_CX_GDSC] = &gpu_cx_gdsc, + [GPU_GX_GDSC] = &gpu_gx_gdsc, +}; + +static const struct regmap_config gpu_cc_sm6115_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sm6115_desc = { + .config = &gpu_cc_sm6115_regmap_config, + .clks = gpu_cc_sm6115_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sm6115_clocks), + .resets = gpu_cc_sm6115_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sm6115_resets), + .gdscs = gpu_cc_sm6115_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sm6115_gdscs), +}; + +static const struct of_device_id gpu_cc_sm6115_match_table[] = { + { .compatible = "qcom,sm6115-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table); + +static int gpu_cc_sm6115_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + unsigned int value, mask; + + regmap = qcom_cc_map(pdev, &gpu_cc_sm6115_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ + mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT; + mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT; + value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; + regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg, mask, value); + + /* Set up PERIPH/MEM retain on the GPU core clock */ + regmap_update_bits(regmap, gpu_cc_gx_gfx3d_clk.halt_reg, + (BIT(14) | BIT(13)), (BIT(14) | BIT(13))); + + return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); +} + +static struct platform_driver gpu_cc_sm6115_driver = { + .probe = gpu_cc_sm6115_probe, + .driver = { + .name = "sm6115-gpucc", + .of_match_table = gpu_cc_sm6115_match_table, + }, +}; + +static int __init gpu_cc_sm6115_init(void) +{ + return platform_driver_register(&gpu_cc_sm6115_driver); +} +subsys_initcall(gpu_cc_sm6115_init); + +static void __exit gpu_cc_sm6115_exit(void) +{ + platform_driver_unregister(&gpu_cc_sm6115_driver); +} +module_exit(gpu_cc_sm6115_exit); + +MODULE_DESCRIPTION("QTI GPU_CC SM6115 Driver"); +MODULE_LICENSE("GPL");