From patchwork Wed Feb 1 02:09:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiangsheng Hou X-Patchwork-Id: 13123640 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC92FC636D3 for ; Wed, 1 Feb 2023 02:09:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231614AbjBACJ5 (ORCPT ); Tue, 31 Jan 2023 21:09:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231590AbjBACJz (ORCPT ); Tue, 31 Jan 2023 21:09:55 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB6B8564B1; Tue, 31 Jan 2023 18:09:33 -0800 (PST) X-UUID: 74a15b1ea1d511ed945fc101203acc17-20230201 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mt32S3LwKdem0E64IVk6P3PMnbE8zfDO1YzBQ7//4fc=; b=tw75+pTEnK5b1gEZNMDcxab41ADNgpzHSmrBzf0NeILJ4Ru1VZRIUrjnccYSEJfwQi1EiakOJdaLZicFml3LSw4vvjq57zoXQ/pV90O2fcT2h524of8D4/fSJYNzBbdw4XNSiNcd0e/6gLFvbXuSQt5Uofjfdy0xcAnoETckkuI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:2f119a25-b13d-484e-9026-ca3b6dc67ce3,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.18,REQID:2f119a25-b13d-484e-9026-ca3b6dc67ce3,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:3ca2d6b,CLOUDID:9a0114f7-ff42-4fb0-b929-626456a83c14,B ulkID:230201100928ZSAAM11O,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0 X-CID-BVR: 0,NGT X-UUID: 74a15b1ea1d511ed945fc101203acc17-20230201 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1156624859; Wed, 01 Feb 2023 10:09:27 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 1 Feb 2023 10:09:26 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 1 Feb 2023 10:09:25 +0800 From: Xiangsheng Hou To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Chuanhong Guo , Xiangsheng Hou , , , , , , , Subject: [PATCH v6 1/5] spi: mtk-snfi: Change default page format to setup default setting Date: Wed, 1 Feb 2023 10:09:17 +0800 Message-ID: <20230201020921.26712-2-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230201020921.26712-1-xiangsheng.hou@mediatek.com> References: <20230201020921.26712-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Change default page format to setup default setting since the sector size 1024 on MT7986 will lead to probe fail. Signed-off-by: Xiangsheng Hou --- drivers/spi/spi-mtk-snfi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index fa8412ba20e2..719fc6f53ab1 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -1430,8 +1430,7 @@ static int mtk_snand_probe(struct platform_device *pdev) // setup an initial page format for ops matching page_cache_op template // before ECC is called. - ret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size, - ms->caps->spare_sizes[0]); + ret = mtk_snand_setup_pagefmt(ms, SZ_2K, SZ_64); if (ret) { dev_err(ms->dev, "failed to set initial page format\n"); goto disable_clk; From patchwork Wed Feb 1 02:09:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiangsheng Hou X-Patchwork-Id: 13123639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8544DC38142 for ; Wed, 1 Feb 2023 02:09:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231600AbjBACJ4 (ORCPT ); Tue, 31 Jan 2023 21:09:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231591AbjBACJz (ORCPT ); Tue, 31 Jan 2023 21:09:55 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C68C3CE17; Tue, 31 Jan 2023 18:09:33 -0800 (PST) X-UUID: 7557e104a1d511eda06fc9ecc4dadd91-20230201 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=FNzZA4Rvah6EiOVCThpkNxdRZy233GREfbroF6vG1AY=; b=IR3PEf7bQ3dlUiqJwm1RsWl7bVTnQZpmu0HgByriE89dBoytMObZPUpDNwJ+MGq4eQYd630JQ39TPTLZ6q5TjPBEK2Ezl3PY+BDRr9WO+EL8b69D7C3Pl/+opEI+Y4Kt4rYh8OfsD6wIkOXYNJ2OOM7BSABbhttLmbO753NQ0vA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:b7aafe76-3ee7-4df5-a571-d82336581beb,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:3ca2d6b,CLOUDID:b637ea55-dd49-462e-a4be-2143a3ddc739,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: 7557e104a1d511eda06fc9ecc4dadd91-20230201 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 424479762; Wed, 01 Feb 2023 10:09:28 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 1 Feb 2023 10:09:27 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 1 Feb 2023 10:09:26 +0800 From: Xiangsheng Hou To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Chuanhong Guo , Xiangsheng Hou , , , , , , , , "AngeloGioacchino Del Regno" Subject: [PATCH v6 2/5] spi: mtk-snfi: Add optional nfi_hclk which is needed for MT7986 Date: Wed, 1 Feb 2023 10:09:18 +0800 Message-ID: <20230201020921.26712-3-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230201020921.26712-1-xiangsheng.hou@mediatek.com> References: <20230201020921.26712-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add optional nfi_hclk which is needed for MT7986. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno --- drivers/spi/spi-mtk-snfi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index 719fc6f53ab1..85644308df23 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -297,6 +297,7 @@ struct mtk_snand { struct device *dev; struct clk *nfi_clk; struct clk *pad_clk; + struct clk *nfi_hclk; void __iomem *nfi_base; int irq; struct completion op_done; @@ -1339,7 +1340,16 @@ static int mtk_snand_enable_clk(struct mtk_snand *ms) dev_err(ms->dev, "unable to enable pad clk\n"); goto err1; } + ret = clk_prepare_enable(ms->nfi_hclk); + if (ret) { + dev_err(ms->dev, "unable to enable nfi hclk\n"); + goto err2; + } + return 0; + +err2: + clk_disable_unprepare(ms->pad_clk); err1: clk_disable_unprepare(ms->nfi_clk); return ret; @@ -1347,6 +1357,7 @@ static int mtk_snand_enable_clk(struct mtk_snand *ms) static void mtk_snand_disable_clk(struct mtk_snand *ms) { + clk_disable_unprepare(ms->nfi_hclk); clk_disable_unprepare(ms->pad_clk); clk_disable_unprepare(ms->nfi_clk); } @@ -1401,6 +1412,13 @@ static int mtk_snand_probe(struct platform_device *pdev) goto release_ecc; } + ms->nfi_hclk = devm_clk_get_optional(&pdev->dev, "nfi_hclk"); + if (IS_ERR(ms->nfi_hclk)) { + ret = PTR_ERR(ms->nfi_hclk); + dev_err(&pdev->dev, "unable to get nfi_hclk, err = %d\n", ret); + goto release_ecc; + } + ret = mtk_snand_enable_clk(ms); if (ret) goto release_ecc; From patchwork Wed Feb 1 02:09:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiangsheng Hou X-Patchwork-Id: 13123641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 382A5C636D3 for ; Wed, 1 Feb 2023 02:10:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231653AbjBACKD (ORCPT ); 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Wed, 01 Feb 2023 10:09:30 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 1 Feb 2023 10:09:29 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 1 Feb 2023 10:09:27 +0800 From: Xiangsheng Hou To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Chuanhong Guo , Xiangsheng Hou , , , , , , , , Krzysztof Kozlowski , AngeloGioacchino Del Regno Subject: [PATCH v6 3/5] dt-bindings: spi: mtk-snfi: Add compatible for MT7986 Date: Wed, 1 Feb 2023 10:09:19 +0800 Message-ID: <20230201020921.26712-4-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230201020921.26712-1-xiangsheng.hou@mediatek.com> References: <20230201020921.26712-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add dt-bindings documentation of SPI NAND controller for MediaTek MT7986 SoC platform. And add optional nfi_hclk property which is needed for MT7986. Signed-off-by: Xiangsheng Hou Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/spi/mediatek,spi-mtk-snfi.yaml | 51 +++++++++++++++---- 1 file changed, 42 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml index 6e6e02c91780..bab23f1b11fd 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -18,14 +18,12 @@ description: | using the accompanying ECC engine. There should be only one spi slave device following generic spi bindings. -allOf: - - $ref: /schemas/spi/spi-controller.yaml# - properties: compatible: enum: - mediatek,mt7622-snand - mediatek,mt7629-snand + - mediatek,mt7986-snand reg: items: @@ -36,14 +34,12 @@ properties: - description: NFI interrupt clocks: - items: - - description: clock used for the controller - - description: clock used for the SPI bus + minItems: 2 + maxItems: 3 clock-names: - items: - - const: nfi_clk - - const: pad_clk + minItems: 2 + maxItems: 3 nand-ecc-engine: description: device-tree node of the accompanying ECC engine. @@ -57,6 +53,43 @@ required: - clock-names - nand-ecc-engine +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + - if: + properties: + compatible: + enum: + - mediatek,mt7622-snand + - mediatek,mt7629-snand + then: + properties: + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + clock-names: + items: + - const: nfi_clk + - const: pad_clk + + - if: + properties: + compatible: + enum: + - mediatek,mt7986-snand + then: + properties: + clocks: + items: + - description: clock used for the controller + - description: clock used for the SPI bus + - description: clock used for the AHB bus + clock-names: + items: + - const: nfi_clk + - const: pad_clk + - const: nfi_hclk + unevaluatedProperties: false examples: From patchwork Wed Feb 1 02:09:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiangsheng Hou X-Patchwork-Id: 13123643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E899C64EC3 for ; Wed, 1 Feb 2023 02:10:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231670AbjBACKF (ORCPT ); Tue, 31 Jan 2023 21:10:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231634AbjBACKC (ORCPT ); Tue, 31 Jan 2023 21:10:02 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A325658678; Tue, 31 Jan 2023 18:09:38 -0800 (PST) X-UUID: 77265e02a1d511ed945fc101203acc17-20230201 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=v0RLYJNNjOaZwIF3K4Tu0NmZq0XJJx6TB5aHEi73l4Y=; b=M9G3DXjNqRIou93ppeyELlWNgaIB0hz137+/bbjixulZyKapeapkUwZrkAr7PfAlOc6SC5NAVFCRfB3KkKMVT0+oTmDMMx9KW+w4GoBbPqmfW+WEj3V8tvdN7MM6+ymb1OtqKsCqCbkL2Auc3Y0lXDk543xsJfrAbuojogxzFQ8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.18,REQID:2032cd59-f9a8-46cc-bcb1-56425e4a293b,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:3ca2d6b,CLOUDID:f103858d-8530-4eff-9f77-222cf6e2895b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0 X-CID-BVR: 0 X-UUID: 77265e02a1d511ed945fc101203acc17-20230201 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1251141084; Wed, 01 Feb 2023 10:09:31 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 1 Feb 2023 10:09:30 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 1 Feb 2023 10:09:29 +0800 From: Xiangsheng Hou To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Chuanhong Guo , Xiangsheng Hou , , , , , , , , AngeloGioacchino Del Regno Subject: [PATCH v6 4/5] spi: mtk-snfi: Add snfi sample delay and read latency adjustment Date: Wed, 1 Feb 2023 10:09:20 +0800 Message-ID: <20230201020921.26712-5-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230201020921.26712-1-xiangsheng.hou@mediatek.com> References: <20230201020921.26712-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add snfi sample delay and read latency adjustment which can get from dts property. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno --- drivers/spi/spi-mtk-snfi.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/spi/spi-mtk-snfi.c b/drivers/spi/spi-mtk-snfi.c index 85644308df23..f3f95eb37365 100644 --- a/drivers/spi/spi-mtk-snfi.c +++ b/drivers/spi/spi-mtk-snfi.c @@ -195,6 +195,8 @@ #define DATA_READ_MODE_X4 2 #define DATA_READ_MODE_DUAL 5 #define DATA_READ_MODE_QUAD 6 +#define DATA_READ_LATCH_LAT GENMASK(9, 8) +#define DATA_READ_LATCH_LAT_S 8 #define PG_LOAD_CUSTOM_EN BIT(7) #define DATARD_CUSTOM_EN BIT(6) #define CS_DESELECT_CYC_S 0 @@ -205,6 +207,9 @@ #define SNF_DLY_CTL3 0x548 #define SFCK_SAM_DLY_S 0 +#define SFCK_SAM_DLY GENMASK(5, 0) +#define SFCK_SAM_DLY_TOTAL 9 +#define SFCK_SAM_DLY_RANGE 47 #define SNF_STA_CTL1 0x550 #define CUS_PG_DONE BIT(28) @@ -1368,6 +1373,8 @@ static int mtk_snand_probe(struct platform_device *pdev) const struct of_device_id *dev_id; struct spi_controller *ctlr; struct mtk_snand *ms; + unsigned long spi_freq; + u32 val = 0; int ret; dev_id = of_match_node(mtk_snand_ids, np); @@ -1446,6 +1453,19 @@ static int mtk_snand_probe(struct platform_device *pdev) // switch to SNFI mode nfi_write32(ms, SNF_CFG, SPI_MODE); + ret = of_property_read_u32(np, "rx-sample-delay-ns", &val); + if (!ret) + nfi_rmw32(ms, SNF_DLY_CTL3, SFCK_SAM_DLY, + val * SFCK_SAM_DLY_RANGE / SFCK_SAM_DLY_TOTAL); + + ret = of_property_read_u32(np, "mediatek,rx-latch-latency-ns", &val); + if (!ret) { + spi_freq = clk_get_rate(ms->pad_clk); + val = DIV_ROUND_CLOSEST(val, NSEC_PER_SEC / spi_freq); + nfi_rmw32(ms, SNF_MISC_CTL, DATA_READ_LATCH_LAT, + val << DATA_READ_LATCH_LAT_S); + } + // setup an initial page format for ops matching page_cache_op template // before ECC is called. ret = mtk_snand_setup_pagefmt(ms, SZ_2K, SZ_64); From patchwork Wed Feb 1 02:09:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiangsheng Hou X-Patchwork-Id: 13123642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20D79C63797 for ; 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Wed, 1 Feb 2023 10:09:30 +0800 From: Xiangsheng Hou To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: Chuanhong Guo , Xiangsheng Hou , , , , , , , , Krzysztof Kozlowski , AngeloGioacchino Del Regno Subject: [PATCH v6 5/5] dt-bindings: spi: mtk-snfi: Add read latch latency property Date: Wed, 1 Feb 2023 10:09:21 +0800 Message-ID: <20230201020921.26712-6-xiangsheng.hou@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230201020921.26712-1-xiangsheng.hou@mediatek.com> References: <20230201020921.26712-1-xiangsheng.hou@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add mediatek,rx-latch-latency-ns property which adjust data read latch latency in the unit of nanoseconds. Signed-off-by: Xiangsheng Hou Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml index bab23f1b11fd..1e5e89a693c3 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml @@ -45,6 +45,9 @@ properties: description: device-tree node of the accompanying ECC engine. $ref: /schemas/types.yaml#/definitions/phandle + mediatek,rx-latch-latency-ns: + description: Data read latch latency, unit is nanoseconds. + required: - compatible - reg