From patchwork Wed Feb 1 17:02:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Green X-Patchwork-Id: 13124752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D026C38142 for ; Wed, 1 Feb 2023 17:02:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6AFB210E42E; Wed, 1 Feb 2023 17:02:27 +0000 (UTC) Received: from mail-qt1-x835.google.com (mail-qt1-x835.google.com [IPv6:2607:f8b0:4864:20::835]) by gabe.freedesktop.org (Postfix) with ESMTPS id 69E6E10E42C for ; Wed, 1 Feb 2023 17:02:25 +0000 (UTC) Received: by mail-qt1-x835.google.com with SMTP id s4so17637317qtx.6 for ; Wed, 01 Feb 2023 09:02:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FvVBHvYo5PCvL4M3dFLxsMPnjamk2TTn3KNNyLW5LSk=; b=M0a1pmBer5GIgXXylsq3Cm7BSd2VfrNxQrjGOBLNUAy3DglS5mXejimyxKmDQdd5oI aEI8gr5yC2v8m5AelHuJF+U8aYYOgmyrfiLAXuvwcZ9cGxAsgSAlw4TvPZxizjtwHdgE 5hB2BQyzDcCGAi7Y91ZKV8Ey5eLKp5igIWUfM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FvVBHvYo5PCvL4M3dFLxsMPnjamk2TTn3KNNyLW5LSk=; b=G6v7+i8tJrVxYDsQRFw2VCdIQOQTvbEyICaG7cd+cCLbNNByMBpeRgsgsDofrC52IF urb5jfocEKzJDHx6cFl7QSpVqrLs6leEkDw0OHwrnVoJrKuWx/nFZDSELb2tQxip+3NP aj+vhV1AzXsWYwWX1Q7vZkVyv1M51/0PJSlKYVckPMmMKBloLixcCatLrB0B8Rc2OSdC Sa5dN6iwwqCjbSDhK+1O7jgad+AZM5Suj1AiMGmPSRBDZ6V6qd96NOpCxg4jZbJ+6b0g X7l3Ff6UzkNwpery7pRJpkG6/z6j4gKQaiapmGA5FbnmF9QYv8JIWH2dgWcCVqKocI5Y Hthw== X-Gm-Message-State: AO0yUKUWc01+Si+l+4m1qgEtan8iviVMJBfTFN5dm8KyVMW53Rps3spC EXJP1+OI+/d1HNN8TWypzZBf+g== X-Google-Smtp-Source: AK7set/o+yvday5QZEd3+f0ht/eH1BBnG1upe8lTmKFq34hKLevJqngBEuWMzf7yN8KzOYgxlQAuEQ== X-Received: by 2002:ac8:4559:0:b0:3b9:bc8c:c200 with SMTP id z25-20020ac84559000000b003b9bc8cc200mr1591800qtn.11.1675270944262; Wed, 01 Feb 2023 09:02:24 -0800 (PST) Received: from greenjustin3.nyc.corp.google.com ([2620:0:1003:314:9334:99d8:1f91:70a]) by smtp.gmail.com with ESMTPSA id z15-20020ac8430f000000b003b646a99aa6sm5549543qtm.77.2023.02.01.09.02.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 09:02:23 -0800 (PST) From: Justin Green To: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org Subject: [PATCH 1/3] drm/mediatek: Refactor pixel format logic Date: Wed, 1 Feb 2023 12:02:08 -0500 Message-Id: <20230201170210.1253505-2-greenjustin@chromium.org> X-Mailer: git-send-email 2.39.1.456.gfc5497dd1b-goog In-Reply-To: <20230201170210.1253505-1-greenjustin@chromium.org> References: <20230201170210.1253505-1-greenjustin@chromium.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chunkuang.hu@kernel.org, Justin Green , airlied@linux.ie, jason-jh.lin@mediatek.com, justin.yeh@mediatek.com, wenst@chromium.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add an DDP component interface for querying pixel format support and move list of supported pixel formats into DDP components instead of mtk_drm_plane.c Tested by running Chrome on an MT8195. Signed-off-by: Justin Green --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 ++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 44 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 38 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 20 ++++++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.c | 24 ++++------- drivers/gpu/drm/mediatek/mtk_drm_plane.h | 3 +- 8 files changed, 123 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 33e61a136bbc..0df6a06defb8 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -96,6 +96,8 @@ void mtk_ovl_register_vblank_cb(struct device *dev, void mtk_ovl_unregister_vblank_cb(struct device *dev); void mtk_ovl_enable_vblank(struct device *dev); void mtk_ovl_disable_vblank(struct device *dev); +const u32 *mtk_ovl_get_formats(struct device *dev); +size_t mtk_ovl_get_num_formats(struct device *dev); void mtk_rdma_bypass_shadow(struct device *dev); int mtk_rdma_clk_enable(struct device *dev); @@ -115,6 +117,8 @@ void mtk_rdma_register_vblank_cb(struct device *dev, void mtk_rdma_unregister_vblank_cb(struct device *dev); void mtk_rdma_enable_vblank(struct device *dev); void mtk_rdma_disable_vblank(struct device *dev); +const u32 *mtk_rdma_get_formats(struct device *dev); +size_t mtk_rdma_get_num_formats(struct device *dev); int mtk_mdp_rdma_clk_enable(struct device *dev); void mtk_mdp_rdma_clk_disable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 84daeaffab6a..8743c8047dc9 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -66,6 +66,20 @@ #define OVL_CON_VIRT_FLIP BIT(9) #define OVL_CON_HORZ_FLIP BIT(10) +static const u32 mt8173_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -73,6 +87,8 @@ struct mtk_disp_ovl_data { bool fmt_rgb565_is_0; bool smi_id_en; bool supports_afbc; + const u32 *formats; + size_t num_formats; }; /* @@ -138,6 +154,20 @@ void mtk_ovl_disable_vblank(struct device *dev) writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); } +const u32 *mtk_ovl_get_formats(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + return ovl->data->formats; +} + +size_t mtk_ovl_get_num_formats(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + return ovl->data->num_formats; +} + int mtk_ovl_clk_enable(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); @@ -495,6 +525,8 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { .gmc_bits = 8, .layer_nr = 4, .fmt_rgb565_is_0 = false, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { @@ -502,6 +534,8 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { .gmc_bits = 8, .layer_nr = 4, .fmt_rgb565_is_0 = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { @@ -509,6 +543,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { .gmc_bits = 10, .layer_nr = 4, .fmt_rgb565_is_0 = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { @@ -516,6 +552,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { .gmc_bits = 10, .layer_nr = 2, .fmt_rgb565_is_0 = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { @@ -524,6 +562,8 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { .layer_nr = 4, .fmt_rgb565_is_0 = true, .smi_id_en = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { @@ -532,6 +572,8 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { .layer_nr = 2, .fmt_rgb565_is_0 = true, .smi_id_en = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { @@ -541,6 +583,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { .fmt_rgb565_is_0 = true, .smi_id_en = true, .supports_afbc = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 0ec2e4049e07..cf92df845160 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -54,8 +54,24 @@ #define RDMA_MEM_GMC 0x40402020 +static const u32 mt8173_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + struct mtk_disp_rdma_data { unsigned int fifo_size; + const u32 *formats; + size_t num_formats; }; /* @@ -126,6 +142,20 @@ void mtk_rdma_disable_vblank(struct device *dev) rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0); } +const u32 *mtk_rdma_get_formats(struct device *dev) +{ + struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); + + return rdma->data->formats; +} + +size_t mtk_rdma_get_num_formats(struct device *dev) +{ + struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); + + return rdma->data->num_formats; +} + int mtk_rdma_clk_enable(struct device *dev) { struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); @@ -360,18 +390,26 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = { .fifo_size = SZ_4K, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { .fifo_size = SZ_8K, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .fifo_size = 5 * SZ_1K, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = { .fifo_size = 1920, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 112615817dcb..2ba01c484228 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -856,7 +856,9 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, BIT(pipe), mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, num_planes), - mtk_ddp_comp_supported_rotations(comp)); + mtk_ddp_comp_supported_rotations(comp), + mtk_ddp_comp_get_formats(comp), + mtk_ddp_comp_get_num_formats(comp)); if (ret) return ret; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 6b6d5335c834..4a4c1928f83d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -359,6 +359,8 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .layer_config = mtk_ovl_layer_config, .bgclr_in_on = mtk_ovl_bgclr_in_on, .bgclr_in_off = mtk_ovl_bgclr_in_off, + .get_formats = mtk_ovl_get_formats, + .get_num_formats = mtk_ovl_get_num_formats, }; static const struct mtk_ddp_comp_funcs ddp_postmask = { @@ -381,6 +383,8 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = { .disable_vblank = mtk_rdma_disable_vblank, .layer_nr = mtk_rdma_layer_nr, .layer_config = mtk_rdma_layer_config, + .get_formats = mtk_rdma_get_formats, + .get_num_formats = mtk_rdma_get_num_formats, }; static const struct mtk_ddp_comp_funcs ddp_ufoe = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 2d0052c23dcb..7f2e638cfdc2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -71,6 +71,8 @@ struct mtk_ddp_comp_funcs { void (*bgclr_in_off)(struct device *dev); void (*ctm_set)(struct device *dev, struct drm_crtc_state *state); + const u32 *(*get_formats)(struct device *dev); + size_t (*get_num_formats)(struct device *dev); }; struct mtk_ddp_comp { @@ -203,6 +205,24 @@ static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, comp->funcs->ctm_set(comp->dev, state); } +static inline +const u32 *mtk_ddp_comp_get_formats(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->get_formats) + return comp->funcs->get_formats(comp->dev); + + return NULL; +} + +static inline +size_t mtk_ddp_comp_get_num_formats(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->get_num_formats) + return comp->funcs->get_num_formats(comp->dev); + + return 0; +} + int mtk_ddp_comp_get_id(struct device_node *node, enum mtk_ddp_comp_type comp_type); unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index d54fbf34b000..31f9420aff6f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -19,20 +19,6 @@ #include "mtk_drm_gem.h" #include "mtk_drm_plane.h" -static const u32 formats[] = { - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, - DRM_FORMAT_BGRX8888, - DRM_FORMAT_BGRA8888, - DRM_FORMAT_ABGR8888, - DRM_FORMAT_XBGR8888, - DRM_FORMAT_RGB888, - DRM_FORMAT_BGR888, - DRM_FORMAT_RGB565, - DRM_FORMAT_UYVY, - DRM_FORMAT_YUYV, -}; - static const u64 modifiers[] = { DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | @@ -315,13 +301,19 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = { int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations) + unsigned int supported_rotations, const u32 *formats, + size_t num_formats) { int err; + if (!formats || !num_formats) { + DRM_ERROR("no formats for plane\n"); + return -EINVAL; + } + err = drm_universal_plane_init(dev, plane, possible_crtcs, &mtk_plane_funcs, formats, - ARRAY_SIZE(formats), modifiers, type, NULL); + num_formats, modifiers, type, NULL); if (err) { DRM_ERROR("failed to initialize plane\n"); return err; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h b/drivers/gpu/drm/mediatek/mtk_drm_plane.h index 8f39011cdbfc..99aff7da0831 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h @@ -48,6 +48,7 @@ to_mtk_plane_state(struct drm_plane_state *state) int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations); + unsigned int supported_rotations, const u32 *formats, + size_t num_formats); #endif From patchwork Wed Feb 1 17:02:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Green X-Patchwork-Id: 13124753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D5B5C38142 for ; Wed, 1 Feb 2023 17:02:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2FD1310E430; Wed, 1 Feb 2023 17:02:28 +0000 (UTC) Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4A3E410E42D for ; Wed, 1 Feb 2023 17:02:26 +0000 (UTC) Received: by mail-qt1-x829.google.com with SMTP id m12so6204872qth.4 for ; Wed, 01 Feb 2023 09:02:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/cc1vOdWtwzxjB8Itoebo3PGpOUY7+SB1sP8jgG5BLo=; b=Vx4yU+Sj4JFqsfCfjWK/W6R96a4AK2AznqfWmnIWtfkW6PsajbnDfuTpGP7tMZ04S/ M1/HXtoMh/wA9pivy2Rnw0Ac5NJBcq5mEJzJOjv2ZO0+CXMmGueor7lWFQtkDdvKJBy4 /4jnd6hpZP4eDq9yBZd4NQI0m0eyo5+ADvUrM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/cc1vOdWtwzxjB8Itoebo3PGpOUY7+SB1sP8jgG5BLo=; b=4GqQGsyBC3ZJ6fHFs2RinK3e6kvL34t0WFYrmFF+ZlFcSZCbdlRyDtXCxDLcFZELUq gqIq9s2OA6GvJnKzsHNmgchb4eARNoCXpvQ/meSOIIx/Nz4CWN9fMuviwmimsZvHyp21 A89HGjDlFOh+StEKGeuZJw91idm9cNZOdVXCYqf0ljKG7uGQwAP4sUgnnnegtVJSMe/A SN5mp86ja5g5zFx1E1oU6aZpzRAwaPC9ns5+rrHMaJbfaQgHi/iBi8v4tMe252bRec+r JxPB+z84H0mEdZ2Lk1Eep+55Q1Qr7HhvsXVBFFjSqv0IjKT8LYYkXLRMSM2P5hgYlfxp V9wQ== X-Gm-Message-State: AO0yUKXQKDsh6UbrqUQZDgDLUSFitmfbGkqgbB1AG6z+PNsNWqN7kBP8 yPXF+Quq96NkqFvZKJ954d4VnA== X-Google-Smtp-Source: AK7set9RwiJUfNVKI3TuTIMqUyXDZ5F4xiGpr/SUlKizJWISqA3RG4SDl2/gk8bLulVeqTwUsZDSHg== X-Received: by 2002:a05:622a:134c:b0:3af:ba3b:db80 with SMTP id w12-20020a05622a134c00b003afba3bdb80mr5199215qtk.33.1675270945250; Wed, 01 Feb 2023 09:02:25 -0800 (PST) Received: from greenjustin3.nyc.corp.google.com ([2620:0:1003:314:9334:99d8:1f91:70a]) by smtp.gmail.com with ESMTPSA id z15-20020ac8430f000000b003b646a99aa6sm5549543qtm.77.2023.02.01.09.02.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 09:02:24 -0800 (PST) From: Justin Green To: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org Subject: [PATCH 2/3] drm/mediatek: Add support for AR30 and BA30 overlays Date: Wed, 1 Feb 2023 12:02:09 -0500 Message-Id: <20230201170210.1253505-3-greenjustin@chromium.org> X-Mailer: git-send-email 2.39.1.456.gfc5497dd1b-goog In-Reply-To: <20230201170210.1253505-1-greenjustin@chromium.org> References: <20230201170210.1253505-1-greenjustin@chromium.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chunkuang.hu@kernel.org, Justin Green , airlied@linux.ie, jason-jh.lin@mediatek.com, justin.yeh@mediatek.com, wenst@chromium.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Tested using "modetest -P" on an MT8195 device. Signed-off-by: Justin Green --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 8743c8047dc9..a6255e847104 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -41,6 +41,7 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 +#define DISP_REG_OVL_CLRFMT_EXT 0x02D0 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) @@ -61,6 +62,10 @@ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ OVL_CON_CLRFMT_RGB : 0) +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl)) +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl)) +#define OVL_CON_CLRFMT_8_BIT 0x00 +#define OVL_CON_CLRFMT_10_BIT 0x01 #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff #define OVL_CON_VIRT_FLIP BIT(9) @@ -89,6 +94,7 @@ struct mtk_disp_ovl_data { bool supports_afbc; const u32 *formats; size_t num_formats; + bool supports_clrfmt_ext; }; /* @@ -218,6 +224,30 @@ static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx)); } +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, + struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + unsigned int reg; + unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; + + if (!ovl->data->supports_clrfmt_ext) + return; + + reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); + reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); + + if (format == DRM_FORMAT_RGBA1010102 || + format == DRM_FORMAT_BGRA1010102 || + format == DRM_FORMAT_ARGB2101010) + bit_depth = OVL_CON_CLRFMT_10_BIT; + + reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); + + mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, + ovl->regs, DISP_REG_OVL_CLRFMT_EXT); +} + void mtk_ovl_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -332,9 +362,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: @@ -418,6 +450,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); } + mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt); mtk_ovl_layer_on(dev, idx, cmdq_pkt); } From patchwork Wed Feb 1 17:02:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Green X-Patchwork-Id: 13124754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1FC6BC05027 for ; Wed, 1 Feb 2023 17:02:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8933110E42F; Wed, 1 Feb 2023 17:02:30 +0000 (UTC) Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5B42C10E42D for ; Wed, 1 Feb 2023 17:02:27 +0000 (UTC) Received: by mail-qt1-x829.google.com with SMTP id h24so9543236qtr.0 for ; Wed, 01 Feb 2023 09:02:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rd0pXPWFNXejSLhEyKT2rFb5IqInkH4mtznmiVegFkA=; b=nT67bw8rr56CM1gJrp7X+DVshgnEKa/ljhXldr+SD384iSPkj35RP2X96fvOeQnsgm T14b9hW8ntxRYCEpR8GsxRX+9r/UCUhnVOF2MAuPq1dJ/DyHInDPNZJk18PxtOhMd24s 2r9N9Mx3zTN478qLt3UhkKbfNoV6h8c1mPRHw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rd0pXPWFNXejSLhEyKT2rFb5IqInkH4mtznmiVegFkA=; b=BSqB/ibrWMM8uFz21iOf2HtQOWIoddlok+gFlWjkJr2bgtEYSq8f1xum/QdHlOLmrm R86Tpv7bwfdQUTy2VaAdYCegxdLE/YPBUcXf6UjLIFC7f2fQDP864ZS6Z2Q0BdkuS2U0 aWxrUqOL/ErZZndi+piv8j+nJN/ZYJ4Bie9C0u4yh6uQk0bb4zNFc5Q5ARD69ZJLZkg+ eggGa1yGlrm0KhgOje/afSZyCEorQyXxdp8rHWVookdGRZCIOUCsUhjdRfcz8sCmWYo2 IKpBMfJ9Jpa3xTdUrj8fKcdHjzBlzGrzdDnOyZV4LbvtdfeZa8zo/MsVvoiIDrzAXcZW IIBQ== X-Gm-Message-State: AO0yUKWEdZ2M4M+yKCDCkrR69uRAmXRT783AIv1JB0CJhDFMBe7z2ooz fR/hJwC+PYLSgg0uBDdufPjI+w== X-Google-Smtp-Source: AK7set+eO7ODvJ08hC6MTpYiPVvqg1nPK4IXKW7BUiehW11cQYcoERJgOYb16hSR0vDxX1XFqa0lEg== X-Received: by 2002:ac8:7fc3:0:b0:3b0:98c3:217c with SMTP id b3-20020ac87fc3000000b003b098c3217cmr6229659qtk.6.1675270946173; Wed, 01 Feb 2023 09:02:26 -0800 (PST) Received: from greenjustin3.nyc.corp.google.com ([2620:0:1003:314:9334:99d8:1f91:70a]) by smtp.gmail.com with ESMTPSA id z15-20020ac8430f000000b003b646a99aa6sm5549543qtm.77.2023.02.01.09.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 09:02:25 -0800 (PST) From: Justin Green To: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org Subject: [PATCH 3/3] drm/mediatek: Enable AR30 and BA30 overlays on MT8195 Date: Wed, 1 Feb 2023 12:02:10 -0500 Message-Id: <20230201170210.1253505-4-greenjustin@chromium.org> X-Mailer: git-send-email 2.39.1.456.gfc5497dd1b-goog In-Reply-To: <20230201170210.1253505-1-greenjustin@chromium.org> References: <20230201170210.1253505-1-greenjustin@chromium.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chunkuang.hu@kernel.org, Justin Green , airlied@linux.ie, jason-jh.lin@mediatek.com, justin.yeh@mediatek.com, wenst@chromium.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Tested using "modetest -P" on an MT8195 device. Signed-off-by: Justin Green --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index a6255e847104..7d26f7055751 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -85,6 +85,22 @@ static const u32 mt8173_formats[] = { DRM_FORMAT_YUYV, }; +static const u32 mt8195_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRA1010102, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -616,8 +632,9 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { .fmt_rgb565_is_0 = true, .smi_id_en = true, .supports_afbc = true, - .formats = mt8173_formats, - .num_formats = ARRAY_SIZE(mt8173_formats), + .formats = mt8195_formats, + .num_formats = ARRAY_SIZE(mt8195_formats), + .supports_clrfmt_ext = true, }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {