From patchwork Wed Feb 1 22:28:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13125051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0470C05027 for ; Wed, 1 Feb 2023 22:28:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F036910E1A8; Wed, 1 Feb 2023 22:28:38 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2BA5610E1A3; Wed, 1 Feb 2023 22:28:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675290517; x=1706826517; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=q5zCMQ8i+T+NLbdI+kb3KovMphPiz+ZVDmw6YhoUWyE=; b=PDaMEQJYLTAG/hU6/OatZEojI2EP+7ko7DPQJ1qJWyJicTiWOsBoYG/l nb+Jy5lfHKrVBfqLj/UlSorZNvwmRK1jZr2NY+CZUOoWBL9MxiiX7w+2z HUxOyJbg21JFBfhV+goQTxjIo5NrInHYVv9nzYoLGsRkAsBCkCdFiIvt8 dgD2IfWsdvRQS6QVC4+/oA0fOsTTomdP1IoJzn+qX5yL/rixnK0J/pJic LMcQzW7AiIraUF8eOEEifkJGRqO1sgdGt7Q1+TR/tzB9jSrOxHOh53kI/ kXLvf1fQJtzVXQhP4UqNU4dPjpthmYQLmRecfvU/UgktJgA3obXuIpP9p Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="355626145" X-IronPort-AV: E=Sophos;i="5.97,265,1669104000"; d="scan'208";a="355626145" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2023 14:28:36 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807733572" X-IronPort-AV: E=Sophos;i="5.97,265,1669104000"; d="scan'208";a="807733572" Received: from mdroper-desk1.fm.intel.com ([10.1.27.134]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2023 14:28:36 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Feb 2023 14:28:28 -0800 Message-Id: <20230201222831.608281-1-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/pvc: Annotate two more workaround/tuning registers as MCR X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" XEHPC_LNCFMISCCFGREG0 and XEHPC_L3SCRUB are both in MCR register ranges on PVC (with HALFBSLICE and L3BANK replication respectively), so they should be explicitly declared as MCR registers and use MCR-aware workaround handlers. The workarounds/tuning settings should still be applied properly on PVC even without the MCR annotation, but readback verification on CONFIG_DRM_I915_DEBUG_GEM builds could potentitally give false positive "workaround lost on load" warnings on parts fused such that a unicast read targets a terminated register instance. Fixes: a9e69428b1b4 ("drm/i915: Define MCR registers explicitly") Signed-off-by: Matt Roper Reviewed-by: Gustavo Sousa --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +++++++++--- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 7fa18a3b3957..928698c621e5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -979,7 +979,7 @@ #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C #define GEN7_L3AGDIS (1 << 19) -#define XEHPC_LNCFMISCCFGREG0 _MMIO(0xb01c) +#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c) #define XEHPC_HOSTCACHEEN REG_BIT(1) #define XEHPC_OVRLSCCC REG_BIT(0) @@ -1042,7 +1042,7 @@ #define XEHP_L3SCQREG7 MCR_REG(0xb188) #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) -#define XEHPC_L3SCRUB _MMIO(0xb18c) +#define XEHPC_L3SCRUB MCR_REG(0xb18c) #define SCRUB_CL_DWNGRADE_SHARED REG_BIT(12) #define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0) #define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 29718d0595f4..f45ca3d4a07c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -240,6 +240,12 @@ wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) wa_write_clr_set(wal, reg, ~0, set); } +static void +wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) +{ + wa_mcr_write_clr_set(wal, reg, ~0, set); +} + static void wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) { @@ -2892,9 +2898,9 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915, struct i915_wa_list *wal) { if (IS_PONTEVECCHIO(i915)) { - wa_write(wal, XEHPC_L3SCRUB, + wa_mcr_write(wal, XEHPC_L3SCRUB, SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); - wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); + wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); } if (IS_DG2(i915)) { @@ -2984,7 +2990,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li if (IS_PONTEVECCHIO(i915)) { /* Wa_16016694945 */ - wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); + wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); } if (IS_XEHPSDV(i915)) { From patchwork Wed Feb 1 22:28:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13125052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67D11C636D4 for ; Wed, 1 Feb 2023 22:28:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 77A3A10E1AC; Wed, 1 Feb 2023 22:28:39 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id B71A610E1A3; Wed, 1 Feb 2023 22:28:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675290517; x=1706826517; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=74vq66cGI/CTy0tEaC/WPOtRAtPA/2ahr0MfCaEw4xg=; b=kTPePUs2ps72qX2IXZZjfjqOak7x3YKjdB4bHyAcN8dGJ3Et4HyUJ38V lx6j6WcdhvkVI6EoEcHniUjh7yySynW1dOLC9l6POwguKWqrWe2DdxjLd LF2i63+X0iIf38zAQHmPyPEZGgks52Co5i9U6nigZWUdJyDIqLOegz9Ln x6Mk/zeLyocR46P2BMm46mxUGJXOOOmKbEpyMtAqrr03MYD/aSsMFAke5 VDbLzhmqh3mIKBNlNXep+cmKdQhTM7437/eSX2bjx6Llt9ZXrUJabPoXx e4fwVIiZc3lmrRkOiTaxf8eMCcNWKVl9PvGXiG7EgpAa9lbOvDwwZOOun A==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="355626151" X-IronPort-AV: E=Sophos;i="5.97,265,1669104000"; d="scan'208";a="355626151" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2023 14:28:37 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807733576" X-IronPort-AV: E=Sophos;i="5.97,265,1669104000"; d="scan'208";a="807733576" Received: from mdroper-desk1.fm.intel.com ([10.1.27.134]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2023 14:28:37 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Feb 2023 14:28:29 -0800 Message-Id: <20230201222831.608281-2-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201222831.608281-1-matthew.d.roper@intel.com> References: <20230201222831.608281-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/gen11: Wa_1408615072/Wa_1407596294 should be on GT list X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The UNSLICE_UNIT_LEVEL_CLKGATE register programmed by this workaround has 'BUS' style reset, indicating that it does not lose its value on engine resets. Furthermore, this register is part of the GT forcewake domain rather than the RENDER domain, so it should not be impacted by RCS engine resets. As such, we should implement this on the GT workaround list rather than an engine list. Bspec: 19219 Fixes: 3551ff928744 ("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()") Signed-off-by: Matt Roper Reviewed-by: Gustavo Sousa --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index f45ca3d4a07c..7e93ba6b3208 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1405,6 +1405,13 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_L3_COH_PIPE); + /* + * Wa_1408615072:icl,ehl (vsunit) + * Wa_1407596294:icl,ehl (hsunit) + */ + wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, + VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); + /* Wa_1407352427:icl,ehl */ wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, PSDUNIT_CLKGATE_DIS); @@ -2536,13 +2543,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, GEN11_ENABLE_32_PLANE_MODE); - /* - * Wa_1408615072:icl,ehl (vsunit) - * Wa_1407596294:icl,ehl (hsunit) - */ - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, - VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); - /* * Wa_1408767742:icl[a2..forever],ehl[all] * Wa_1605460711:icl[a0..c0] From patchwork Wed Feb 1 22:28:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13125050 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E023BC636D4 for ; Wed, 1 Feb 2023 22:28:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D4CF810E1A4; Wed, 1 Feb 2023 22:28:38 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id D620710E1A4; Wed, 1 Feb 2023 22:28:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675290517; x=1706826517; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qokfoRB6cADqLTl3A7i06TIL/bXq1oR32QMlh1a9VGQ=; b=HCnO73WFMsAKk18HRWH7UbXZFjkhNFA4kbhQrff9MnlddlEz3XStdYCc LYEyngAM0KqwWMGVer38WluxrSgv/IK+UhMVQ9ZJqAqHCbByHe8mLl30V xLI1Gc5u9T11l4TXspm5tFkPeSbvxmn1L6bdFd2aLi2j/FC0TtuqZhYPN KsIemO1d55OyO5qOGAImTYsVZGxF+eRms3FEKcWbTQXCRuY82WyPwGnsj NQQ0IcFI0veyzr3rAFFF2CT3+2+6QBqp5Hy5hh20giO77nX99qfR7Lzyi W8uEWxhnOk7ur4WlLTEhjMqcoyq68HTE7lEygb0ADCuRvrT45AZNxROiz Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="355626152" X-IronPort-AV: E=Sophos;i="5.97,265,1669104000"; d="scan'208";a="355626152" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2023 14:28:37 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807733579" X-IronPort-AV: E=Sophos;i="5.97,265,1669104000"; d="scan'208";a="807733579" Received: from mdroper-desk1.fm.intel.com ([10.1.27.134]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2023 14:28:37 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Feb 2023 14:28:30 -0800 Message-Id: <20230201222831.608281-3-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201222831.608281-1-matthew.d.roper@intel.com> References: <20230201222831.608281-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/xehp: LNCF/LBCF workarounds should be on the GT list X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Although registers in the L3 bank/node configuration ranges are marked as having "DEV" reset characteristics in the bspec, this appears to be a hold-over from pre-Xe_HP platforms. In reality, these registers maintain their values across engine resets, meaning that workarounds and tuning settings targetting them should be placed on the GT workaround list rather than an engine workaround list. Note that an extra clue here is that these registers moved from the RENDER forcewake domain to the GT forcewake domain in Xe_HP; generally RCS/CCS engine resets should not lead to the reset of a register that lives outside the RENDER domain. Re-applying these registers on engine resets wouldn't actually hurt anything, but is unnecessary and just makes it more confusing to anyone trying to decipher how these registers really work. Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 61 +++++++++++++-------- 1 file changed, 38 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 7e93ba6b3208..09c9837458b5 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1499,6 +1499,12 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) /* Wa_1409757795:xehpsdv */ wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); + /* Wa_18011725039:xehpsdv */ + if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { + wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); + wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); + } + /* Wa_16011155590:xehpsdv */ if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, @@ -1548,6 +1554,9 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) /* Wa_14014368820:xehpsdv */ wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS | GLOBAL_INVALIDATION_MODE); + + /* Wa_14010670810:xehpsdv */ + wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); } static void @@ -1684,6 +1693,9 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); + + /* Wa_16016694945 */ + wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); } static void @@ -1724,11 +1736,36 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) debug_dump_steering(gt); } +/* + * The bspec performance guide has recommended MMIO tuning settings. These + * aren't truly "workarounds" but we want to program them through the + * workaround infrastructure to make sure they're (re)applied at the proper + * times. + * + * The settings in this function are for settings that persist through + * engine resets and also are not part of any engine's register state context. + * I.e., settings that only need to be re-applied in the event of a full GT + * reset. + */ +static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) +{ + if (IS_PONTEVECCHIO(gt->i915)) { + wa_mcr_write(wal, XEHPC_L3SCRUB, + SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); + wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); + } + + if (IS_DG2(gt->i915)) + wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); +} + static void gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) { struct drm_i915_private *i915 = gt->i915; + gt_tuning_settings(gt, wal); + if (gt->type == GT_MEDIA) { if (MEDIA_VER(i915) >= 13) xelpmp_gt_workarounds_init(gt, wal); @@ -2897,16 +2934,8 @@ static void add_render_compute_tuning_settings(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_PONTEVECCHIO(i915)) { - wa_mcr_write(wal, XEHPC_L3SCRUB, - SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK); - wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); - } - - if (IS_DG2(i915)) { - wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); + if (IS_DG2(i915)) wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); - } /* * This tuning setting proves beneficial only on ATS-M designs; the @@ -2988,11 +3017,6 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li 0, false); } - if (IS_PONTEVECCHIO(i915)) { - /* Wa_16016694945 */ - wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); - } - if (IS_XEHPSDV(i915)) { /* Wa_1409954639 */ wa_mcr_masked_en(wal, @@ -3004,18 +3028,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li GEN9_ROW_CHICKEN4, GEN12_DISABLE_GRF_CLEAR); - /* Wa_14010670810:xehpsdv */ - wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); - /* Wa_14010449647:xehpsdv */ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); - - /* Wa_18011725039:xehpsdv */ - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) { - wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); - wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); - } } if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) { From patchwork Wed Feb 1 22:28:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 13125053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CE4DC05027 for ; Wed, 1 Feb 2023 22:28:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 595C610E1AA; Wed, 1 Feb 2023 22:28:39 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 00E3E10E1A8; Wed, 1 Feb 2023 22:28:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675290518; x=1706826518; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=udZ1sC3erz45lwqGqSDbAQRZfts5k14B1/wrriD42Zw=; b=jpD6PANUEiq303S5qu4/VNZ3WwdKb+MfdzT1tESfwy+bwR4hfIi0IFsc AzYBNV5HmU2yYl06LoLmESkQnntQ7lntuIyyn438c7kJJHKdagEkcp/GY Amw2Q2t0yvMKh7f4olL0n9Rq/bjCxezuqbXFjTdNlWoxSHxvJE2llFz1A 8wMoVRRpRVjSsO6Smb47CFZczCYxauyzLtg0o6Nxna8UNxBgyL7E+aY4R ZOfoa4OWqp0v700koZyh2C7g5bVeVCPjOtIiv8TffumDvMfWXMLPs2JBO oSqUEDyNBNd5reXFmxl7DcHqE4c1ohKUM2Tla1IO5gjzyhZTwDSS2ERuL Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="355626153" X-IronPort-AV: E=Sophos;i="5.97,265,1669104000"; d="scan'208";a="355626153" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2023 14:28:37 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10608"; a="807733582" X-IronPort-AV: E=Sophos;i="5.97,265,1669104000"; d="scan'208";a="807733582" Received: from mdroper-desk1.fm.intel.com ([10.1.27.134]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2023 14:28:37 -0800 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Feb 2023 14:28:31 -0800 Message-Id: <20230201222831.608281-4-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230201222831.608281-1-matthew.d.roper@intel.com> References: <20230201222831.608281-1-matthew.d.roper@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915/selftest: Use forcewake to sanity check engine wa lists X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Although register information in the bspec includes a field that is supposed to reflect a register's reset characteristics (i.e., whether a register maintains its value through engine resets), it's been discovered that this information is incorrect for some register ranges (i.e., registers that are not affected by engine resets are tagged in a way that indicates they would be). We can sanity check workaround registers placed on the RCS/CCS engine workaround lists (including those placed there via the general_render_compute_wa_init() function) by comparing against the forcewake table. As far as we know, there's never a case where a register that lives outside the RENDER powerwell will be reset by an RCS/CCS engine reset. Signed-off-by: Matt Roper --- .../gpu/drm/i915/gt/selftest_workarounds.c | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 14a8b25b6204..1bc8febc5c1d 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -1362,12 +1362,64 @@ live_engine_reset_workarounds(void *arg) return ret; } +/* + * The bspec's documentation for register reset behavior can be unreliable for + * some MMIO ranges. But in general we do not expect registers outside the + * RENDER forcewake domain to be reset by RCS/CCS engine resets. If we find + * workaround registers on an RCS or CCS engine's list, it likely indicates + * the register is misdocumented in the bspec and the workaround implementation + * should be moved to the GT workaround list instead. + */ +static int +live_check_engine_workarounds_fw(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + struct wa_lists *lists; + enum intel_engine_id id; + int ret = 0; + + lists = kzalloc(sizeof(*lists), GFP_KERNEL); + if (!lists) + return -ENOMEM; + + reference_lists_init(gt, lists); + + for_each_engine(engine, gt, id) { + struct i915_wa_list *wal = &lists->engine[id].wa_list; + struct i915_wa *wa; + int i; + + if (engine->class != RENDER_CLASS && + engine->class != COMPUTE_CLASS) + continue; + + for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { + enum forcewake_domains fw; + + fw = intel_uncore_forcewake_for_reg(gt->uncore, wa->reg, + FW_REG_READ | FW_REG_WRITE); + if ((fw & FORCEWAKE_RENDER) == 0) { + pr_err("%s: Register %#x not in RENDER forcewake domain!\n", + engine->name, i915_mmio_reg_offset(wa->reg)); + ret = -EINVAL; + } + } + } + + reference_lists_fini(gt, lists); + kfree(lists); + + return ret; +} + int intel_workarounds_live_selftests(struct drm_i915_private *i915) { static const struct i915_subtest tests[] = { SUBTEST(live_dirty_whitelist), SUBTEST(live_reset_whitelist), SUBTEST(live_isolated_whitelist), + SUBTEST(live_check_engine_workarounds_fw), SUBTEST(live_gpu_reset_workarounds), SUBTEST(live_engine_reset_workarounds), };