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Thu, 2 Feb 2023 08:18:04 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 2 Feb 2023 08:18:04 -0800 Received: from BUILDSERVER-IO-L4T.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Thu, 2 Feb 2023 08:17:59 -0800 From: Krishna Yarlagadda To: , , , , , , , , , CC: , , , , Krishna Yarlagadda Subject: [PATCH 1/4] dt-bindings: tpm: Add compatible for Tegra TPM Date: Thu, 2 Feb 2023 21:47:47 +0530 Message-ID: <20230202161750.21210-2-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230202161750.21210-1-kyarlagadda@nvidia.com> References: <20230202161750.21210-1-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT045:EE_|MN0PR12MB5858:EE_ X-MS-Office365-Filtering-Correlation-Id: 811f0115-d7d4-4e13-a488-08db053915ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 16:18:14.1043 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 811f0115-d7d4-4e13-a488-08db053915ee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT045.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5858 Precedence: bulk List-ID: X-Mailing-List: linux-integrity@vger.kernel.org Tegra234 and Tegra241 devices have QSPI controller that supports TPM devices. Since the controller only supports half duplex, sw wait polling method implemented in tpm_tis_spi does not suffice. Wait polling as per protocol is a hardware feature. Add compatible for Tegra TPM driver with hardware flow control. Signed-off-by: Krishna Yarlagadda --- .../bindings/security/tpm/nvidia,tegra-tpm-spi.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.txt diff --git a/Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.txt b/Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.txt new file mode 100644 index 000000000000..a2017945c7c0 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.txt @@ -0,0 +1,14 @@ +* Device Tree Bindings for TPM device connected to TEGRA QSPI controller + +Required Properties: + +- compatible: Should be "nvidia,tegra-tpm-spi". + +Example: + +&qspi0 { + tpm@0 { + compatible = "nvidia,tegra-tpm-spi"; + reg = <0>; + }; +}; From patchwork Thu Feb 2 16:17:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 13126513 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCF26C636D4 for ; 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Thu, 2 Feb 2023 08:18:05 -0800 From: Krishna Yarlagadda To: , , , , , , , , , CC: , , , , Krishna Yarlagadda Subject: [PATCH 2/4] tpm: tegra: Support SPI tpm wait state detect Date: Thu, 2 Feb 2023 21:47:48 +0530 Message-ID: <20230202161750.21210-3-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230202161750.21210-1-kyarlagadda@nvidia.com> References: <20230202161750.21210-1-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT020:EE_|DM4PR12MB5865:EE_ X-MS-Office365-Filtering-Correlation-Id: 16d2ee37-8395-4264-3f72-08db0539181a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iyoCI04w4lwaK8Gltb2Ca/d9fvnQaOMXPQNxGETG0CR4owcKXdDqomFai5Z5pDAYUoirsDQi8B9UZRdq+f8MfdoFm998sNK3qVwPmSEVGOLSZlIoVo9FvpP6at5PDvR759XdAeEPKOUnKKvxlx+7MXa5V0mXJonHIjDVFaKHNKakWCB5ZXz5G1G9nUASJMamDns1yHpXh1YY4CNRT8zB4VEWPlstX6aJNOAhnFtFmTL5F7V5t+nex8vbZ1A9f7HYXGwSQSLFr9XccZ2hVoM7Wqmbt62qYsO7H/kfvWm4peik0GxOuDhiaeezDobwm5D9dxdKRKFMsKqKB9Xw96/UCLdMWXzEYx9H5lMzdRghRWXwI1r+eWHD33wvrfH79lq7Bp8g2b/Zv7nHj5JFRdxlKMdI5rKjV2CsSFbowtHed8NlmDZGkV5VBDmDdLHttJf6KDXM2ZGF3Bkl17lu/aiAQ6tsOrJbi/BtpQmy7HGgSR120Be4kNHortPMLiNjXHy4wPw88Iu2AvW1SqKpEl2YylUh6POm9HatRapNVka3IROiM8/fZ7HKN+WDfJLOcYaJ1uKi4StRhTRbnSVfavnO3tLvMQi9JWKHKB7Bsmm8Xk/+2to2Owv9Zi0Pl5zFIjoyrxkg898GIottXsPjfUnuBBhfEY430hxmN8+fHNhNWuycjubmvwJJ5F7ipYurPYQrXGnZFwOXn6Wo7SZ50QcFpwIHhsSxINWoxhD1r4o9XL2DF0pfAop5sW1WIyptDg6QXtZGUSkC78vProVubA0IAQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(396003)(346002)(136003)(376002)(39860400002)(451199018)(46966006)(36840700001)(40470700004)(186003)(26005)(1076003)(83380400001)(70206006)(70586007)(426003)(336012)(921005)(356005)(82310400005)(36756003)(86362001)(40460700003)(47076005)(36860700001)(40480700001)(5660300002)(8936002)(41300700001)(54906003)(110136005)(4326008)(316002)(2616005)(8676002)(107886003)(6666004)(82740400003)(7416002)(7636003)(7696005)(478600001)(2906002)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 16:18:17.7767 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 16d2ee37-8395-4264-3f72-08db0539181a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5865 Precedence: bulk List-ID: X-Mailing-List: linux-integrity@vger.kernel.org Tegra234 and Tegra241 chips have QSPI controller that supports TCG TIS hardware flow control. Since the controller only supports half duplex, sw wait polling method implemented in tpm_tis_spi does not suffice. Added extending driver to disable sw flow control and send all transfers in single message. Signed-off-by: Krishna Yarlagadda --- drivers/char/tpm/Makefile | 1 + drivers/char/tpm/tpm_tis_spi.h | 1 + drivers/char/tpm/tpm_tis_spi_main.c | 4 +- drivers/char/tpm/tpm_tis_spi_tegra.c | 123 +++++++++++++++++++++++++++ 4 files changed, 128 insertions(+), 1 deletion(-) create mode 100644 drivers/char/tpm/tpm_tis_spi_tegra.c diff --git a/drivers/char/tpm/Makefile b/drivers/char/tpm/Makefile index 0222b1ddb310..445b15493cb3 100644 --- a/drivers/char/tpm/Makefile +++ b/drivers/char/tpm/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_TCG_TIS_SYNQUACER) += tpm_tis_synquacer.o obj-$(CONFIG_TCG_TIS_SPI) += tpm_tis_spi.o tpm_tis_spi-y := tpm_tis_spi_main.o +tpm_tis_spi-y += tpm_tis_spi_tegra.o tpm_tis_spi-$(CONFIG_TCG_TIS_SPI_CR50) += tpm_tis_spi_cr50.o obj-$(CONFIG_TCG_TIS_I2C_CR50) += tpm_tis_i2c_cr50.o diff --git a/drivers/char/tpm/tpm_tis_spi.h b/drivers/char/tpm/tpm_tis_spi.h index d0f66f6f1931..feaea14b428b 100644 --- a/drivers/char/tpm/tpm_tis_spi.h +++ b/drivers/char/tpm/tpm_tis_spi.h @@ -31,6 +31,7 @@ extern int tpm_tis_spi_init(struct spi_device *spi, struct tpm_tis_spi_phy *phy, extern int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len, u8 *in, const u8 *out); +extern int tegra_tpm_spi_probe(struct spi_device *spi); #ifdef CONFIG_TCG_TIS_SPI_CR50 extern int cr50_spi_probe(struct spi_device *spi); #else diff --git a/drivers/char/tpm/tpm_tis_spi_main.c b/drivers/char/tpm/tpm_tis_spi_main.c index a0963a3e92bd..5d4502a4461a 100644 --- a/drivers/char/tpm/tpm_tis_spi_main.c +++ b/drivers/char/tpm/tpm_tis_spi_main.c @@ -198,7 +198,7 @@ static int tpm_tis_spi_driver_probe(struct spi_device *spi) const struct spi_device_id *spi_dev_id = spi_get_device_id(spi); tpm_tis_spi_probe_func probe_func; - probe_func = of_device_get_match_data(&spi->dev); + probe_func = device_get_match_data(&spi->dev); if (!probe_func) { if (spi_dev_id) { probe_func = (tpm_tis_spi_probe_func)spi_dev_id->driver_data; @@ -227,6 +227,7 @@ static const struct spi_device_id tpm_tis_spi_id[] = { { "tpm_tis_spi", (unsigned long)tpm_tis_spi_probe }, { "tpm_tis-spi", (unsigned long)tpm_tis_spi_probe }, { "cr50", (unsigned long)cr50_spi_probe }, + { "tegra-tpm-spi", (unsigned long)tegra_tpm_spi_probe }, {} }; MODULE_DEVICE_TABLE(spi, tpm_tis_spi_id); @@ -236,6 +237,7 @@ static const struct of_device_id of_tis_spi_match[] = { { .compatible = "infineon,slb9670", .data = tpm_tis_spi_probe }, { .compatible = "tcg,tpm_tis-spi", .data = tpm_tis_spi_probe }, { .compatible = "google,cr50", .data = cr50_spi_probe }, + { .compatible = "nvidia,tegra-tpm-spi", .data = tegra_tpm_spi_probe }, {} }; MODULE_DEVICE_TABLE(of, of_tis_spi_match); diff --git a/drivers/char/tpm/tpm_tis_spi_tegra.c b/drivers/char/tpm/tpm_tis_spi_tegra.c new file mode 100644 index 000000000000..23f20684513d --- /dev/null +++ b/drivers/char/tpm/tpm_tis_spi_tegra.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 NVIDIA CORPORATION. + * + * This device driver implements TEGRA QSPI hw wait detection for chips + * + * It is based on tpm_tis_spi driver by Peter Huewe and Christophe Ricard. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "tpm_tis_core.h" +#include "tpm_tis_spi.h" + +#define MAX_SPI_FRAMESIZE 64 + +int tpm_tis_spi_tegra_transfer(struct tpm_tis_data *data, u32 addr, u16 len, + u8 *in, const u8 *out) +{ + struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data); + int ret = 0; + struct spi_message m; + struct spi_transfer spi_xfer[3]; + u8 transfer_len; + + spi_bus_lock(phy->spi_device->master); + + while (len) { + transfer_len = min_t(u16, len, MAX_SPI_FRAMESIZE); + + spi_message_init(&m); + phy->iobuf[0] = (in ? 0x80 : 0) | (transfer_len - 1); + phy->iobuf[1] = 0xd4; + phy->iobuf[2] = addr >> 8; + phy->iobuf[3] = addr; + + memset(&spi_xfer, 0, sizeof(spi_xfer)); + + spi_xfer[0].tx_buf = phy->iobuf; + spi_xfer[0].len = 1; + spi_message_add_tail(&spi_xfer[0], &m); + + spi_xfer[1].tx_buf = phy->iobuf + 1; + spi_xfer[1].len = 3; + spi_message_add_tail(&spi_xfer[1], &m); + + if (out) { + spi_xfer[2].tx_buf = &phy->iobuf[4]; + spi_xfer[2].rx_buf = NULL; + memcpy(&phy->iobuf[4], out, transfer_len); + out += transfer_len; + } + if (in) { + spi_xfer[2].tx_buf = NULL; + spi_xfer[2].rx_buf = &phy->iobuf[4]; + } + spi_xfer[2].len = transfer_len; + spi_message_add_tail(&spi_xfer[2], &m); + + reinit_completion(&phy->ready); + ret = spi_sync_locked(phy->spi_device, &m); + if (ret < 0) + goto exit; + + if (in) { + memcpy(in, &phy->iobuf[4], transfer_len); + in += transfer_len; + } + + len -= transfer_len; + } + +exit: + spi_bus_unlock(phy->spi_device->master); + return ret; +} + +static int tpm_tis_spi_tegra_read_bytes(struct tpm_tis_data *data, u32 addr, + u16 len, u8 *result, + enum tpm_tis_io_mode io_mode) +{ + return tpm_tis_spi_tegra_transfer(data, addr, len, result, NULL); +} + +static int tpm_tis_spi_tegra_write_bytes(struct tpm_tis_data *data, u32 addr, + u16 len, const u8 *value, + enum tpm_tis_io_mode io_mode) +{ + return tpm_tis_spi_tegra_transfer(data, addr, len, NULL, value); +} + +static const struct tpm_tis_phy_ops tegra_tpm_spi_phy_ops = { + .read_bytes = tpm_tis_spi_tegra_read_bytes, + .write_bytes = tpm_tis_spi_tegra_write_bytes, +}; + +int tegra_tpm_spi_probe(struct spi_device *dev) +{ + struct tpm_tis_spi_phy *phy; + int irq; + + phy = devm_kzalloc(&dev->dev, sizeof(struct tpm_tis_spi_phy), + GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->flow_control = NULL; + + /* If the SPI device has an IRQ then use that */ + if (dev->irq > 0) + irq = dev->irq; + else + irq = -1; + + init_completion(&phy->ready); + return tpm_tis_spi_init(dev, phy, irq, &tegra_tpm_spi_phy_ops); +} From patchwork Thu Feb 2 16:17:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 13126519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5266C05027 for ; Thu, 2 Feb 2023 16:19:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232370AbjBBQTG (ORCPT ); Thu, 2 Feb 2023 11:19:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232217AbjBBQSf (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 16:18:25.0784 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2fab5523-f88d-4643-8c2d-08db05391c7b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8567 Precedence: bulk List-ID: X-Mailing-List: linux-integrity@vger.kernel.org Add "nvidia,wait-polling" flag to enable TCG TIS hardware flow control. Signed-off-by: Krishna Yarlagadda --- .../bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml index 2c3cada75339..25150d55603e 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad-peripheral-props.yaml @@ -28,5 +28,11 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 255 +properties: + nvidia,wait-polling: + description: + Enable TPM wait polling feature for QSPI as specified in TCG PC Client + Specific TPM Interface Specification (TIS). + $ref: /schemas/types.yaml#/definitions/flag additionalProperties: true From patchwork Thu Feb 2 16:17:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 13126520 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20A69C61DA4 for ; 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Thu, 2 Feb 2023 08:18:15 -0800 From: Krishna Yarlagadda To: , , , , , , , , , CC: , , , , Krishna Yarlagadda Subject: [PATCH 4/4] spi: tegra210-quad: Enable TPM wait polling Date: Thu, 2 Feb 2023 21:47:50 +0530 Message-ID: <20230202161750.21210-5-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230202161750.21210-1-kyarlagadda@nvidia.com> References: <20230202161750.21210-1-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT081:EE_|MN2PR12MB4269:EE_ X-MS-Office365-Filtering-Correlation-Id: cd937f5a-ace5-45a6-cd9f-08db05392231 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OdUFbUzF7wvcgXhPiwfuK4FPttfsHhN5L8I52KjaZTNB3w7yHNYi+tj4bQptwz9xnMkOLoSBZdQQNCF5I/NqnkpSny27oU4S35pBWdGuCPBPNkofbVXD5AN2i9wokhIYMPy25jcsH/2fJoGgktjb0fjqFJcw+GRC9GjoGgcf8d/Fulw26SlpNwebVebVSwdcgqvUwid1nzy4MhCSLJGUs+MqlJ9ym/k/GhBMRVP7OJux0JX3GDJ5W5j1/FzFI1+dJHIhdCcWZQviRZR5Y78vPRPrag0VOGqvsyf6LoGeovzbD0JfL0Qs8scGcXT13imUTFsq3t8MiQRwIlQBCUp4qZw7Yee3FDZ/P62VnYkLjQaUcNBLWFGxzWRwbLPI77bhZwRdm7NMfCKv9bbLC6yHR3DHaotx67brAuZpW4pT6HlsvMIoCvuBs1jTMaFvas9EdEo35ZvVLd/I24JlG3QG3X8uoI+9HZJ/zh5z7+Pz/RHl9dqzN0orZWS+GdOhIdtk5c8wolom7foksTBKlif6zQPtZYuenU23st4l9EwLPtmqM0GuHcoaa/HurjjDb8NVRRZGrL2Op8Dm4EleOEJcYqArN4RGkEMOtQ6Mva1Gz7KC231+4rluc67HVmjHsuu9xbstLM/OYzhgDYOmrkq4z5Px/e4dTWAVgJp0MXY599jvQSIXIwumwDBEXdXGf62vjvKutXpMmNXJwhkqXK6YlUpy20pujIow8JD8gZLGwB1RdkN4jIMS6eAonunfaob3i6bwr3u7a99I55CRY5wmAw== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(346002)(376002)(396003)(136003)(451199018)(46966006)(36840700001)(40470700004)(356005)(921005)(40480700001)(36756003)(36860700001)(47076005)(82310400005)(7636003)(40460700003)(82740400003)(426003)(41300700001)(8676002)(7696005)(2906002)(70586007)(54906003)(4326008)(316002)(110136005)(7416002)(8936002)(70206006)(86362001)(5660300002)(107886003)(26005)(1076003)(186003)(6666004)(478600001)(83380400001)(2616005)(336012)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 16:18:34.7083 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd937f5a-ace5-45a6-cd9f-08db05392231 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT081.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4269 Precedence: bulk List-ID: X-Mailing-List: linux-integrity@vger.kernel.org Trusted Platform Module defines flow control where slave will drive data line at specified clock cycles. Tegra241 has TPM wait state detections support when using combined sequence transfers. Enabling the feature based on device tree flag. Signed-off-by: Krishna Yarlagadda --- drivers/spi/spi-tegra210-quad.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 9f356612ba7e..ea8a08a3d838 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -142,6 +142,7 @@ #define QSPI_GLOBAL_CONFIG 0X1a4 #define QSPI_CMB_SEQ_EN BIT(0) +#define QSPI_TPM_WAIT_POLL_EN BIT(1) #define QSPI_CMB_SEQ_ADDR 0x1a8 #define QSPI_ADDRESS_VALUE_SET(X) (((x) & 0xFFFF) << 0) @@ -170,6 +171,7 @@ struct tegra_qspi_soc_data { struct tegra_qspi_client_data { int tx_clk_tap_delay; int rx_clk_tap_delay; + bool wait_polling; }; struct tegra_qspi { @@ -934,6 +936,8 @@ static struct tegra_qspi_client_data *tegra_qspi_parse_cdata_dt(struct spi_devic &cdata->tx_clk_tap_delay); device_property_read_u32(&spi->dev, "nvidia,rx-clk-tap-delay", &cdata->rx_clk_tap_delay); + cdata->wait_polling = + device_property_read_bool(&spi->dev, "nvidia,wait-polling"); return cdata; } @@ -991,6 +995,14 @@ static void tegra_qspi_dump_regs(struct tegra_qspi *tqspi) dev_dbg(tqspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS), tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS)); + dev_dbg(tqspi->dev, "GLOBAL_CFG: 0x%08x\n", + tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG)); + dev_dbg(tqspi->dev, "CMB_CMD: 0x%08x | CMB_CMD_CFG: 0x%08x\n", + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_CMD), + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_CMD_CFG)); + dev_dbg(tqspi->dev, "CMB_ADDR: 0x%08x | CMB_ADDR_CFG: 0x%08x\n", + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_ADDR), + tegra_qspi_readl(tqspi, QSPI_CMB_SEQ_ADDR_CFG)); } static void tegra_qspi_handle_error(struct tegra_qspi *tqspi) @@ -1056,6 +1068,7 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, bool is_first_msg = true; struct spi_transfer *xfer; struct spi_device *spi = msg->spi; + struct tegra_qspi_client_data *cdata = spi->controller_data; u8 transfer_phase = 0; u32 cmd1 = 0, dma_ctl = 0; int ret = 0; @@ -1065,6 +1078,8 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, /* Enable Combined sequence mode */ val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); + if (cdata->wait_polling) + val |= QSPI_TPM_WAIT_POLL_EN; val |= QSPI_CMB_SEQ_EN; tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); /* Process individual transfer list */ @@ -1192,6 +1207,7 @@ static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, /* Disable Combined sequence mode */ val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); val &= ~QSPI_CMB_SEQ_EN; + val &= ~QSPI_TPM_WAIT_POLL_EN; tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); list_for_each_entry(transfer, &msg->transfers, transfer_list) { struct spi_transfer *xfer = transfer;