From patchwork Thu Feb 2 21:46:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yabin Cui X-Patchwork-Id: 13126751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E567C61DA4 for ; Thu, 2 Feb 2023 21:47:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=F+oOEgdSrYFSxroU73s7/2PTrhq+eEavydCgUJJRioo=; b=XlxMI5j8e+7rEhC8Ak4l3mGDLf 4mQ2QBwWPgdXjmq8RGBbLFlvjSU5ZgP/c6qoiVge/HmNz9TiM0MX4jct6IIMGfn6PaZOm4f+883BI lJXHAXSTFbP/xT5VgP7WfYIvO+nXsdONkXG2rBDH5XLBdrAVNgvzTCz0a+R1W1nPsHFfzcLDmiST2 8FN7vgaBf/XDP9j/4MdZdh5GlsMAQQM9SBLEE6c8s96OsplZa7nuCRhXDAA3xRXhg5vtcIEfeYDBx 4me2wy/+OHTE9VzrsE3CiHte95lF22y/IobhhWffmTRWI3JuU2xua67j55MjYqWqU9njLe06hZzfJ 2cBBedyg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pNhPm-00HG05-Et; Thu, 02 Feb 2023 21:46:42 +0000 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pNhPi-00HFya-7x for linux-arm-kernel@lists.infradead.org; Thu, 02 Feb 2023 21:46:39 +0000 Received: by mail-pj1-x1049.google.com with SMTP id c8-20020a17090a674800b0022cb9c81fb0so3476977pjm.2 for ; Thu, 02 Feb 2023 13:46:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=sqjPMfmLxZrl/TWFcH17PAhRzTWGvIwQzKrdbPB0S9A=; b=CA4CJlGWskzNxH2h8ZMiOPFchibTfurO0Fbgdjihj/R5MzlnFqNXe2yBBFpXwizOUR gHbvQGM0bMarxb5XGfljV2xcFznb8l413rxUe/VLu/B8FessIkKqxgb5aJ+gKYWS30CE nRnsrJbJcOmAr5hCoHQBskcgIBKCW0wTtd5qkZqJ4ECYFOr+JGi4e+WqTsbK8Cd1CZib iuBsLnPekmtvrmNv/q9vxUi3lYqCn+K2rJb53LkUtQ7w5lqeenOhLyV8f8rPpEG92wtf Y1qNmEhYLeEni1mOeUvkLH4wRM+XrrMAOqWDgRTkL4Xh3Elu5jzDAvtmn2tNfw8ARKWE X8fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=sqjPMfmLxZrl/TWFcH17PAhRzTWGvIwQzKrdbPB0S9A=; b=YE3CTsimFjLt65/mFn3XHUHN/npbSEQMo0/LTIy2zv9KE1313pwaaPI6K51ehFAPlp ygGDVmENTTmdfAccC6UmApHUlPbc/VbMv/GMIKkrUjkMQYHFe2DLOidOCCCl0sh61PRh iMUaGs9vN/zr/X7l40ZLw1ceU/h8xJf7+q3ysntdAouBjdhG67hzqw/PypY41Wt+v2GF tS2kEpe7PwMSb8DBrsiL4yoCvoCtIVdcPdoWGQZg5wwGIOmECloTs/ZnqAkoAiv2jBsa tUpz5v0c/kqmUn88fQOFDLFf7AblLu8BFSDqET3eSw0kzKhb5VXYgRAP5zL//Ct4T7sg 0qog== X-Gm-Message-State: AO0yUKUzuWCsNZIXRaLrFmEZlRM0G0oUH/c1SaZ3IwOAHikJzYN++FJu OP5BcXG/EZFKdKLwkcSnHuR5VoBXRQ== X-Google-Smtp-Source: AK7set8TKkCOJWn4gfNwVo2vHevcSDPJfG1Garbim9S45xuvfm1uPUtiwByLC9JT5cuiqONGdhwaL4p5C9k= X-Received: from yabinc3.c.googlers.com ([fda3:e722:ac3:cc00:24:72f4:c0a8:1274]) (user=yabinc job=sendgmr) by 2002:a17:90a:3cc4:b0:230:6d87:390b with SMTP id k4-20020a17090a3cc400b002306d87390bmr160510pjd.99.1675374395962; Thu, 02 Feb 2023 13:46:35 -0800 (PST) Date: Thu, 2 Feb 2023 21:46:32 +0000 In-Reply-To: Mime-Version: 1.0 References: X-Mailer: git-send-email 2.39.1.519.gcb327c4b5f-goog Message-ID: <20230202214633.12584-1-yabinc@google.com> Subject: [PATCH v3] coresight: tmc: Don't enable TMC when it's not ready. From: Yabin Cui To: Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , James Clark Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yabin Cui X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230202_134638_305589_5F55FE02 X-CRM114-Status: GOOD ( 19.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org If TMC ETR is enabled without being ready, in later use we may see AXI bus errors caused by accessing invalid addresses. Signed-off-by: Yabin Cui --- V1 -> V2: Make change to all TMCs instead of just ETR V2 -> V3: Handle etr enable failure in tmc_read_unprepare_etr .../hwtracing/coresight/coresight-tmc-core.c | 4 +- .../hwtracing/coresight/coresight-tmc-etf.c | 43 +++++++++++++++---- .../hwtracing/coresight/coresight-tmc-etr.c | 25 +++++++++-- drivers/hwtracing/coresight/coresight-tmc.h | 2 +- 4 files changed, 59 insertions(+), 15 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 07abf28ad725..c106d142e632 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -31,7 +31,7 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) { struct coresight_device *csdev = drvdata->csdev; struct csdev_access *csa = &csdev->access; @@ -40,7 +40,9 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { dev_err(&csdev->dev, "timeout while waiting for TMC to be Ready\n"); + return -EBUSY; } + return 0; } void tmc_flush_and_stop(struct tmc_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 4c4cbd1f7258..2840227e9135 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -16,12 +16,19 @@ static int tmc_set_etf_buffer(struct coresight_device *csdev, struct perf_output_handle *handle); -static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) { + int rc = 0; + CS_UNLOCK(drvdata->base); /* Wait for TMCSReady bit to be set */ - tmc_wait_for_tmcready(drvdata); + rc = tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, "fails to enable not ready TMC\n"); + CS_LOCK(drvdata->base); + return rc; + } writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | @@ -33,6 +40,7 @@ static void __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) tmc_enable_hw(drvdata); CS_LOCK(drvdata->base); + return rc; } static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) @@ -42,8 +50,10 @@ static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) if (rc) return rc; - __tmc_etb_enable_hw(drvdata); - return 0; + rc = __tmc_etb_enable_hw(drvdata); + if (rc) + coresight_disclaim_device(drvdata->csdev); + return rc; } static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata) @@ -91,12 +101,19 @@ static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata) coresight_disclaim_device(drvdata->csdev); } -static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) { + int rc = 0; + CS_UNLOCK(drvdata->base); /* Wait for TMCSReady bit to be set */ - tmc_wait_for_tmcready(drvdata); + rc = tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, "fails to enable not ready TMC\n"); + CS_LOCK(drvdata->base); + return rc; + } writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE); writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI, @@ -105,6 +122,7 @@ static void __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) tmc_enable_hw(drvdata); CS_LOCK(drvdata->base); + return rc; } static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) @@ -114,8 +132,10 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvdata) if (rc) return rc; - __tmc_etf_enable_hw(drvdata); - return 0; + rc = __tmc_etf_enable_hw(drvdata); + if (rc) + coresight_disclaim_device(drvdata->csdev); + return rc; } static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata) @@ -639,6 +659,7 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) char *buf = NULL; enum tmc_mode mode; unsigned long flags; + int rc = 0; /* config types are set a boot time and never change */ if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETB && @@ -664,7 +685,11 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) * can't be NULL. */ memset(drvdata->buf, 0, drvdata->size); - __tmc_etb_enable_hw(drvdata); + rc = __tmc_etb_enable_hw(drvdata); + if (rc) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; + } } else { /* * The ETB/ETF is not tracing and the buffer was just read. diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 867ad8bb9b0c..4952425dd6e4 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -983,15 +983,21 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata) etr_buf->ops->sync(etr_buf, rrp, rwp); } -static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) +static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) { u32 axictl, sts; struct etr_buf *etr_buf = drvdata->etr_buf; + int rc = 0; CS_UNLOCK(drvdata->base); /* Wait for TMCSReady bit to be set */ - tmc_wait_for_tmcready(drvdata); + rc = tmc_wait_for_tmcready(drvdata); + if (rc) { + dev_err(&drvdata->csdev->dev, "fails to enable not ready TMC\n"); + CS_LOCK(drvdata->base); + return rc; + } writel_relaxed(etr_buf->size / 4, drvdata->base + TMC_RSZ); writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); @@ -1032,6 +1038,7 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) tmc_enable_hw(drvdata); CS_LOCK(drvdata->base); + return rc; } static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, @@ -1060,7 +1067,12 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, rc = coresight_claim_device(drvdata->csdev); if (!rc) { drvdata->etr_buf = etr_buf; - __tmc_etr_enable_hw(drvdata); + rc = __tmc_etr_enable_hw(drvdata); + if (rc) { + drvdata->etr_buf = NULL; + coresight_disclaim_device(drvdata->csdev); + tmc_etr_disable_catu(drvdata); + } } return rc; @@ -1750,6 +1762,7 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata) { unsigned long flags; struct etr_buf *sysfs_buf = NULL; + int rc = 0; /* config types are set a boot time and never change */ if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETR)) @@ -1764,7 +1777,11 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata) * buffer. Since the tracer is still enabled drvdata::buf can't * be NULL. */ - __tmc_etr_enable_hw(drvdata); + rc = __tmc_etr_enable_hw(drvdata); + if (rc) { + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; + } } else { /* * The ETR is not tracing and the buffer was just read. diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 66959557cf39..01c0382a29c0 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -255,7 +255,7 @@ struct tmc_sg_table { }; /* Generic functions */ -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); void tmc_flush_and_stop(struct tmc_drvdata *drvdata); void tmc_enable_hw(struct tmc_drvdata *drvdata); void tmc_disable_hw(struct tmc_drvdata *drvdata);