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Mon, 6 Feb 2023 06:06:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT016.mail.protection.outlook.com (10.13.173.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6064.34 via Frontend Transport; Mon, 6 Feb 2023 06:06:18 +0000 Received: from brahmaputra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 6 Feb 2023 00:05:55 -0600 From: Manali Shukla To: CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH kernel 1/2] perf/x86/amd: Add amd_prevent_hostibs_window() to set per-cpu ibs_flags Date: Mon, 6 Feb 2023 06:05:44 +0000 Message-ID: <20230206060545.628502-2-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230206060545.628502-1-manali.shukla@amd.com> References: <20230206060545.628502-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT016:EE_|IA0PR12MB8205:EE_ X-MS-Office365-Filtering-Correlation-Id: 2593ba35-0b5e-424f-6589-08db08084358 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2023 06:06:18.4903 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2593ba35-0b5e-424f-6589-08db08084358 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8205 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a function to set per-cpu ibs_flags based on an active or inactive PreventHostIBS window. MSR_AMD64_IBSFETCHCTL[IbsFetchEn] and MSR_AMD64_IBSOPCTL[IbsOpEn] bits need to be cleared for PreventHostIBS feature to be enabled before VMRUN is executed. ENABLE bit and VALID bit for MSR_AMD64_IBSFETCHCTL are contained in the same MSR and same is the case with MSR_AMD64_IBSOPCTL. Consider the following scenario: - The IBS MSR which has ENABLE bit set and VALID bit clear is read. - During the process of clearing the ENABLE bit and writing the IBS MSR to disable IBS, an IBS event can occur that sets the VALID bit. - The write operation on IBS MSR can clear the newly set VALID bit. - Since this situation is occurring in the CLGI/STGI window (PreventHostIBS window), the actual NMI is not taken. - Once VMRUN is issued, it will exit with VMEXIT_NMI. As soon as STGI is executed, the pending NMI will trigger. - The IBS NMI handler checks for the VALID bit to determine if the NMI is generated because of IBS. - Since VALID bit is now clear, it doesn't recognize that an IBS event is occurred. Due to this reason, the dazed and confused unknown NMI messages are generated. amd_prevent_hostibs_window() is added to avoid these messages when PreventHostIBS window is active and PreventHostIBS feature is enabled for the guest. Signed-off-by: Manali Shukla Reviewed-by: Ravi Bangoria --- arch/x86/events/amd/ibs.c | 64 +++++++++++++++++++++++++++++++ arch/x86/include/asm/perf_event.h | 20 ++++++++++ 2 files changed, 84 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index da3f5ebac4e1..e96a4c9ff4ba 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -30,7 +30,9 @@ static u32 ibs_caps; #define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT) #define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT +#define PREVENT_HOSTIBS_WINDOW BIT(0) +static DEFINE_PER_CPU(unsigned int, ibs_flags); /* * IBS states: @@ -1035,6 +1037,18 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) if (test_and_clear_bit(IBS_STOPPED, pcpu->state)) return 1; + /* + * Catch NMIs generated in an active PreventHostIBS window: + * incoming NMIs from an active PreventHostIBS window might have + * the VALID bit cleared when it is supposed to be set due to + * a race. The reason for the race is ENABLE and VALID bits for + * MSR_AMD64_IBSFETCHCTL and MSR_AMD64_IBSOPCTL being in their + * same respective MSRs. Ignore all such NMIs and treat them as + * handled. + */ + if (__this_cpu_read(ibs_flags) & PREVENT_HOSTIBS_WINDOW) + return 1; + return 0; } @@ -1540,3 +1554,53 @@ static __init int amd_ibs_init(void) /* Since we need the pci subsystem to init ibs we can't do this earlier: */ device_initcall(amd_ibs_init); + +void amd_prevent_hostibs_window(bool active) +{ + if (active) + __this_cpu_write(ibs_flags, + __this_cpu_read(ibs_flags) | + PREVENT_HOSTIBS_WINDOW); + else + __this_cpu_write(ibs_flags, + __this_cpu_read(ibs_flags) & + ~PREVENT_HOSTIBS_WINDOW); +} +EXPORT_SYMBOL_GPL(amd_prevent_hostibs_window); + +bool amd_disable_ibs_fetch(u64 *ibs_fetch_ctl) +{ + *ibs_fetch_ctl = __rdmsr(MSR_AMD64_IBSFETCHCTL); + if (!(*ibs_fetch_ctl & IBS_FETCH_ENABLE)) + return false; + + native_wrmsrl(MSR_AMD64_IBSFETCHCTL, + *ibs_fetch_ctl & ~IBS_FETCH_ENABLE); + + return true; +} +EXPORT_SYMBOL(amd_disable_ibs_fetch); + +bool amd_disable_ibs_op(u64 *ibs_op_ctl) +{ + *ibs_op_ctl = __rdmsr(MSR_AMD64_IBSOPCTL); + if (!(*ibs_op_ctl & IBS_OP_ENABLE)) + return false; + + native_wrmsrl(MSR_AMD64_IBSOPCTL, *ibs_op_ctl & ~IBS_OP_ENABLE); + + return true; +} +EXPORT_SYMBOL(amd_disable_ibs_op); + +void amd_restore_ibs_fetch(u64 ibs_fetch_ctl) +{ + native_wrmsrl(MSR_AMD64_IBSFETCHCTL, ibs_fetch_ctl); +} +EXPORT_SYMBOL(amd_restore_ibs_fetch); + +void amd_restore_ibs_op(u64 ibs_op_ctl) +{ + native_wrmsrl(MSR_AMD64_IBSOPCTL, ibs_op_ctl); +} +EXPORT_SYMBOL(amd_restore_ibs_op); diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 5d0f6891ae61..1005505e23b1 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -561,6 +561,26 @@ static inline void intel_pt_handle_vmx(int on) } #endif +#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_CPU_SUP_AMD) +extern void amd_prevent_hostibs_window(bool active); +extern bool amd_disable_ibs_fetch(u64 *ibs_fetch_ctl); +extern bool amd_disable_ibs_op(u64 *ibs_op_ctl); +extern void amd_restore_ibs_fetch(u64 ibs_fetch_ctl); +extern void amd_restore_ibs_op(u64 ibs_op_ctl); +#else +static inline void amd_prevent_hostibs_window(bool active) {} +static inline bool amd_disable_ibs_fetch(u64 *ibs_fetch_ctl) +{ + return false; +} +static inline bool amd_disable_ibs_op(u64 *ibs_op_ctl) +{ + return false; +} +static inline void amd_restore_ibs_fetch(u64 ibs_fetch_ctl) {} +static inline void amd_restore_ibs_op(u64 ibs_op_ctl) {} +#endif + #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) extern void amd_pmu_enable_virt(void); extern void amd_pmu_disable_virt(void); From patchwork Mon Feb 6 06:05:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13129339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D71CC61DA4 for ; Mon, 6 Feb 2023 06:06:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229720AbjBFGGg (ORCPT ); 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT094.mail.protection.outlook.com (10.13.172.195) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6064.34 via Frontend Transport; Mon, 6 Feb 2023 06:06:24 +0000 Received: from brahmaputra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 6 Feb 2023 00:06:17 -0600 From: Manali Shukla To: CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH kernel 2/2] KVM: SEV: PreventHostIBS enablement for SEV-ES and SNP guest Date: Mon, 6 Feb 2023 06:05:45 +0000 Message-ID: <20230206060545.628502-3-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230206060545.628502-1-manali.shukla@amd.com> References: <20230206060545.628502-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT094:EE_|DM6PR12MB4484:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d1eed82-6680-4292-83e6-08db080846cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2023 06:06:24.2844 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d1eed82-6680-4292-83e6-08db080846cc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT094.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4484 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Currently, the hypervisor is able to inspect instruction based samples from a guest and gather execution information. SEV-ES and SNP guests can disallow the use of instruction based sampling by hypervisor by enabling the PreventHostIBS feature for the guest. (More information in Section 15.36.17 APM Volume 2) The MSR_AMD64_IBSFETCHCTL[IbsFetchEn] and MSR_AMD64_IBSOPCTL[IbsOpEn] bits need to be disabled before VMRUN is called when PreventHostIBS feature is enabled. If either of these bits are not 0, VMRUN will fail with VMEXIT_INVALID error code. Because of an IBS race condition when disabling IBS, KVM needs to indicate when it is in a PreventHostIBS window. Activate the window based on whether IBS is currently active or inactive. Signed-off-by: Manali Shukla Reviewed-by: Nikunj A Dadhania --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kvm/svm/sev.c | 10 ++++++++ arch/x86/kvm/svm/svm.c | 39 ++++++++++++++++++++++++++++-- arch/x86/kvm/svm/svm.h | 1 + 4 files changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 61012476d66e..1812e74f846a 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -425,6 +425,7 @@ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ +#define X86_FEATURE_PREVENT_HOST_IBS (19*32+15) /* "" AMD prevent host ibs */ /* * BUG word(s) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 86d6897f4806..b348b8931721 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -569,6 +569,12 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) if (svm->vcpu.guest_debug || (svm->vmcb->save.dr7 & ~DR7_FIXED_1)) return -EINVAL; + if (sev_es_guest(svm->vcpu.kvm) && + guest_cpuid_has(&svm->vcpu, X86_FEATURE_PREVENT_HOST_IBS)) { + save->sev_features |= BIT(6); + svm->prevent_hostibs_enabled = true; + } + /* * SEV-ES will use a VMSA that is pointed to by the VMCB, not * the traditional VMSA that is part of the VMCB. Copy the @@ -2158,6 +2164,10 @@ void __init sev_set_cpu_caps(void) kvm_cpu_cap_clear(X86_FEATURE_SEV); if (!sev_es_enabled) kvm_cpu_cap_clear(X86_FEATURE_SEV_ES); + + /* Enable PreventhostIBS feature for SEV-ES and higher guests */ + if (sev_es_enabled) + kvm_cpu_cap_set(X86_FEATURE_PREVENT_HOST_IBS); } void __init sev_hardware_setup(void) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 9a194aa1a75a..47c1e0fff23e 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -3914,10 +3914,39 @@ static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_in guest_state_enter_irqoff(); - if (sev_es_guest(vcpu->kvm)) + if (sev_es_guest(vcpu->kvm)) { + bool ibs_fetch_active, ibs_op_active; + u64 ibs_fetch_ctl, ibs_op_ctl; + + if (svm->prevent_hostibs_enabled) { + /* + * With PreventHostIBS enabled, IBS profiling cannot + * be active when VMRUN is executed. Disable IBS before + * executing VMRUN and, because of a race condition, + * enable the PreventHostIBS window if IBS profiling was + * active. + */ + ibs_fetch_active = + amd_disable_ibs_fetch(&ibs_fetch_ctl); + ibs_op_active = + amd_disable_ibs_op(&ibs_op_ctl); + + amd_prevent_hostibs_window(ibs_fetch_active || + ibs_op_active); + } + __svm_sev_es_vcpu_run(svm, spec_ctrl_intercepted); - else + + if (svm->prevent_hostibs_enabled) { + if (ibs_fetch_active) + amd_restore_ibs_fetch(ibs_fetch_ctl); + + if (ibs_op_active) + amd_restore_ibs_op(ibs_op_ctl); + } + } else { __svm_vcpu_run(svm, spec_ctrl_intercepted); + } guest_state_exit_irqoff(); } @@ -4008,6 +4037,12 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu) /* Any pending NMI will happen here */ + /* + * Disable the PreventHostIBS window since any pending IBS NMIs will + * have been handled. + */ + amd_prevent_hostibs_window(false); + if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) kvm_after_interrupt(vcpu); diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 4826e6cc611b..71f32fcfd219 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -254,6 +254,7 @@ struct vcpu_svm { bool pause_filter_enabled : 1; bool pause_threshold_enabled : 1; bool vgif_enabled : 1; + bool prevent_hostibs_enabled : 1; u32 ldr_reg; u32 dfr_reg;