From patchwork Mon Feb 6 11:38:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Walker Chen X-Patchwork-Id: 13129711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 939D2C05027 for ; Mon, 6 Feb 2023 11:38:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229731AbjBFLid (ORCPT ); Mon, 6 Feb 2023 06:38:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229478AbjBFLib (ORCPT ); Mon, 6 Feb 2023 06:38:31 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E50610D; Mon, 6 Feb 2023 03:38:30 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id D8FFF24E1F4; Mon, 6 Feb 2023 19:38:23 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Feb 2023 19:38:23 +0800 Received: from localhost.localdomain (183.27.96.33) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Feb 2023 19:38:22 +0800 From: Walker Chen To: , , CC: Eugeniy Paltsev , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Palmer Dabbelt" , Emil Renner Berthing , "Walker Chen" , Subject: [PATCH v1 1/3] dt-bindings: dma: snps,dw-axi-dmac: Update resets and add snps,num-hs-if Date: Mon, 6 Feb 2023 19:38:09 +0800 Message-ID: <20230206113811.23133-2-walker.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230206113811.23133-1-walker.chen@starfivetech.com> References: <20230206113811.23133-1-walker.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.96.33] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add two reset items and properties 'snps,num-hs-if'. The DMA controller needs to be reset before being used in JH7110 SoC. Another difference from the original version is that the hardware handshake number of DMA can be up to 56 while the number in original version is less than 16, and different registers are selected according to this. Signed-off-by: Walker Chen --- .../bindings/dma/snps,dw-axi-dmac.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 67aa7bb6d36a..1a8d8c20e254 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -9,6 +9,7 @@ title: Synopsys DesignWare AXI DMA Controller maintainers: - Eugeniy Paltsev - Jee Heng Sia + - Walker Chen description: Synopsys DesignWare AXI DMA Controller DT Binding @@ -21,6 +22,7 @@ properties: enum: - snps,axi-dma-1.01a - intel,kmb-axi-dma + - starfive,axi-dma reg: minItems: 1 @@ -59,7 +61,12 @@ properties: maximum: 8 resets: - maxItems: 1 + maxItems: 2 + + reset-names: + items: + - const: axi-rst + - const: ahb-rst snps,dma-masters: description: | @@ -74,6 +81,14 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3, 4, 5, 6] + snps,num-hs-if: + description: | + The number of hardware handshake. If it is more than 16, + CHx_CFG2 is used to configure the DMA transfer instead of CHx_CFG. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 256 + snps,priority: description: | Channel priority specifier associated with the DMA channels. From patchwork Mon Feb 6 11:38:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Walker Chen X-Patchwork-Id: 13129712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9D2EC05027 for ; Mon, 6 Feb 2023 11:38:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229889AbjBFLij (ORCPT ); Mon, 6 Feb 2023 06:38:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229727AbjBFLid (ORCPT ); Mon, 6 Feb 2023 06:38:33 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49D8118AA4; Mon, 6 Feb 2023 03:38:31 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 6CA8324E13A; Mon, 6 Feb 2023 19:38:24 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Feb 2023 19:38:24 +0800 Received: from localhost.localdomain (183.27.96.33) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Feb 2023 19:38:23 +0800 From: Walker Chen To: , , CC: Eugeniy Paltsev , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Palmer Dabbelt" , Emil Renner Berthing , "Walker Chen" , Subject: [PATCH v1 2/3] dma: dw-axi-dmac: Add support for StarFive DMA Date: Mon, 6 Feb 2023 19:38:10 +0800 Message-ID: <20230206113811.23133-3-walker.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230206113811.23133-1-walker.chen@starfivetech.com> References: <20230206113811.23133-1-walker.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.96.33] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Adding DMA reset operation in device probe, and using different registers according to the hardware handshake number. Signed-off-by: Walker Chen --- .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 25 ++++++++++++++++--- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index a183d93bd7e2..3581810033d2 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -86,7 +87,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan, cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS | config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS); - if (chan->chip->dw->hdata->reg_map_8_channels) { + if (chan->chip->dw->hdata->reg_map_8_channels && + !chan->chip->dw->hdata->use_cfg2) { cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS | config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS | config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS | @@ -541,8 +543,6 @@ static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set) (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0); - - return; } /* @@ -1136,7 +1136,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan) axi_chan_disable(chan); ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val, - !(val & chan_active), 1000, 10000); + !(val & chan_active), 1000, DMAC_TIMEOUT_US); if (ret == -ETIMEDOUT) dev_warn(dchan2dev(dchan), "%s failed to stop\n", axi_chan_name(chan)); @@ -1323,6 +1323,12 @@ static int parse_device_properties(struct axi_dma_chip *chip) chip->dw->hdata->m_data_width = tmp; + ret = device_property_read_u32(dev, "snps,num-hs-if", &tmp); + if (!ret) { + if (tmp > 16) + chip->dw->hdata->use_cfg2 = true; + } + ret = device_property_read_u32_array(dev, "snps,block-size", carr, chip->dw->hdata->nr_channels); if (ret) @@ -1410,6 +1416,16 @@ static int dw_probe(struct platform_device *pdev) if (IS_ERR(chip->cfgr_clk)) return PTR_ERR(chip->cfgr_clk); + if (of_device_is_compatible(node, "starfive,axi-dma")) { + chip->resets = devm_reset_control_array_get_exclusive(&pdev->dev); + if (IS_ERR(chip->resets)) + return PTR_ERR(chip->resets); + + ret = reset_control_deassert(chip->resets); + if (ret) + return ret; + } + ret = parse_device_properties(chip); if (ret) return ret; @@ -1554,6 +1570,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = { static const struct of_device_id dw_dma_of_id_table[] = { { .compatible = "snps,axi-dma-1.01a" }, { .compatible = "intel,kmb-axi-dma" }, + { .compatible = "starfive,axi-dma" }, {} }; MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h index e9d5eb0fd594..761d95691c02 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h @@ -21,6 +21,7 @@ #define DMAC_MAX_CHANNELS 16 #define DMAC_MAX_MASTERS 2 #define DMAC_MAX_BLK_SIZE 0x200000 +#define DMAC_TIMEOUT_US 200000 struct dw_axi_dma_hcfg { u32 nr_channels; @@ -33,6 +34,7 @@ struct dw_axi_dma_hcfg { /* Register map for DMAX_NUM_CHANNELS <= 8 */ bool reg_map_8_channels; bool restrict_axi_burst_len; + bool use_cfg2; }; struct axi_dma_chan { @@ -70,6 +72,7 @@ struct axi_dma_chip { struct clk *core_clk; struct clk *cfgr_clk; struct dw_axi_dma *dw; + struct reset_control *resets; }; /* LLI == Linked List Item */ From patchwork Mon Feb 6 11:38:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Walker Chen X-Patchwork-Id: 13129713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C514BC61DA4 for ; Mon, 6 Feb 2023 11:38:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229963AbjBFLil (ORCPT ); Mon, 6 Feb 2023 06:38:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229828AbjBFLii (ORCPT ); Mon, 6 Feb 2023 06:38:38 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB2A818ABE; Mon, 6 Feb 2023 03:38:34 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 1E9A424E1C6; Mon, 6 Feb 2023 19:38:25 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Feb 2023 19:38:25 +0800 Received: from localhost.localdomain (183.27.96.33) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Feb 2023 19:38:24 +0800 From: Walker Chen To: , , CC: Eugeniy Paltsev , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Palmer Dabbelt" , Emil Renner Berthing , "Walker Chen" , Subject: [PATCH v1 3/3] riscv: dts: starfive: add dma controller node Date: Mon, 6 Feb 2023 19:38:11 +0800 Message-ID: <20230206113811.23133-4-walker.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230206113811.23133-1-walker.chen@starfivetech.com> References: <20230206113811.23133-1-walker.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.96.33] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Adding the dma controller node for the Starfive JH7110 SoC. Signed-off-by: Walker Chen --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index cfbaff4ea64b..1628c0f33fab 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -412,6 +412,26 @@ #gpio-cells = <2>; }; + dma: dma-controller@16050000 { + compatible = "starfive,axi-dma"; + reg = <0x0 0x16050000 0x0 0x10000>; + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>, + <&stgcrg JH7110_STGCLK_DMA1P_AHB>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>, + <&stgcrg JH7110_STGRST_DMA1P_AHB>; + reset-names = "axi-rst", "ahb-rst"; + interrupts = <73>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <3>; + snps,num-hs-if = <56>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + }; + aoncrg: clock-controller@17000000 { compatible = "starfive,jh7110-aoncrg"; reg = <0x0 0x17000000 0x0 0x10000>;