From patchwork Mon Feb 6 14:57:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13130038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DF46C636D6 for ; Mon, 6 Feb 2023 14:57:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230353AbjBFO5R (ORCPT ); Mon, 6 Feb 2023 09:57:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230388AbjBFO5Q (ORCPT ); Mon, 6 Feb 2023 09:57:16 -0500 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA645234E2 for ; Mon, 6 Feb 2023 06:57:11 -0800 (PST) Received: by mail-ej1-x62c.google.com with SMTP id m2so34938947ejb.8 for ; Mon, 06 Feb 2023 06:57:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lWJTTVfePORcPPcH6H13Fd3H36Ls8G0fdQpwh+iYVeU=; b=fKTqMQIuB7WUG8GgXovc/jz52P/iOoabODFfhKXj0Q3U+SiQVfbNHEJnDxQYvikyFw e4/g0Tp9Rpp/aDwOdkXTnhcBEhQpk8rTu4UvozcZEXJ0Pn+VKnVsLrqgSU/8x8e7sxkq bbepctgsfpX2pCXluEa8ir6GtXae4nFUsByhlKqUFLiWU/uw6CX8i1aosy83vd1getti rr0FcQSqHXvvKBk3GDm2+pYbnsqDJXHL93aywYZoRWKZrV+1F2/CNy357tFeB9BT9zgb WQOI38iOyftOlvKzMdhxxFcASxqFP1vfmQQrG6ZSmLEuKPA6+vyZfnwJR/Csw0CJSj1r 1+bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lWJTTVfePORcPPcH6H13Fd3H36Ls8G0fdQpwh+iYVeU=; b=j4fRTSJbdW8YkgcwNx6RL04xsrp4v4tQDXpKyAWhN8g4HWK2SJpfkf+u2jCFenwWFj 7uwoo4lB4RhOh6Rwbvt+AuLn9/qXG0E9JvjEvp1IqXXREMxapZ0FBAXEmWQriCHk54TT MZFIY0EbYN+4I3JHy9C6IGA241Z8V2SLQPWsHcsOH9I6/JDTkalaMP2t8JlxW+JQLRRt yF6tt0DHC1JHKz1f2K+NHPqRTRlyJ6eCZbJ7vy20/dM/xGsiY2xA82KJj5nomWI1J/EJ N3F3NtkiLofDgxuicGBsnf2MEwyIWuf4pbztU6sm01lvDHQSyybF2TO7Ab1/Fg62SL3k 6eRg== X-Gm-Message-State: AO0yUKUrQl8OyH/hDgkO8cgsdTX52lX7SWTrxhCmn2FWfu8a4iar/6mv GBMpJXU0YPugSOR5pn0efc7DAQ== X-Google-Smtp-Source: AK7set+4HgFJiQjqoladQOeFPQZGQfugQ/vDao8Mt8Efd3ZTknqyhBJdCUmkYIanNZdlUssgTzzeiw== X-Received: by 2002:a17:907:c78a:b0:878:7349:5ce6 with SMTP id tz10-20020a170907c78a00b0087873495ce6mr21754698ejc.71.1675695430407; Mon, 06 Feb 2023 06:57:10 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:10 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 1/8] dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml Date: Mon, 6 Feb 2023 16:57:00 +0200 Message-Id: <20230206145707.122937-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GPU clock controller bindings for the Qualcomm sm8350 platform are not correct. The driver uses .fw_name instead of using indices to bind parent clocks, thus demanding the clock-names usage. With the proper clock-names in place, the bindings becomes equal to the bindings defined by qcom,gpucc.yaml, so it is impractical to keep them in a separate file. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring --- .../bindings/clock/qcom,gpucc-sm8350.yaml | 71 ------------------- .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 + 2 files changed, 2 insertions(+), 71 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml deleted file mode 100644 index fb7ae3d18503..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml +++ /dev/null @@ -1,71 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm Graphics Clock & Reset Controller on SM8350 - -maintainers: - - Robert Foss - -description: | - Qualcomm graphics clock control module provides the clocks, resets and power - domains on Qualcomm SoCs. - - See also:: include/dt-bindings/clock/qcom,gpucc-sm8350.h - -properties: - compatible: - enum: - - qcom,sm8350-gpucc - - clocks: - items: - - description: Board XO source - - description: GPLL0 main branch source - - description: GPLL0 div branch source - - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - '#power-domain-cells': - const: 1 - - reg: - maxItems: 1 - -required: - - compatible - - reg - - clocks - - '#clock-cells' - - '#reset-cells' - - '#power-domain-cells' - -additionalProperties: false - -examples: - - | - #include - #include - - soc { - #address-cells = <2>; - #size-cells = <2>; - - clock-controller@3d90000 { - compatible = "qcom,sm8350-gpucc"; - reg = <0 0x03d90000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - }; -... diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index 7256c438a4cf..db53eb288995 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -21,6 +21,7 @@ description: | include/dt-bindings/clock/qcom,gpucc-sm6350.h include/dt-bindings/clock/qcom,gpucc-sm8150.h include/dt-bindings/clock/qcom,gpucc-sm8250.h + include/dt-bindings/clock/qcom,gpucc-sm8350.h properties: compatible: @@ -33,6 +34,7 @@ properties: - qcom,sm6350-gpucc - qcom,sm8150-gpucc - qcom,sm8250-gpucc + - qcom,sm8350-gpucc clocks: items: From patchwork Mon Feb 6 14:57:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13130039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB222C64EC7 for ; Mon, 6 Feb 2023 14:57:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230393AbjBFO5T (ORCPT ); Mon, 6 Feb 2023 09:57:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230407AbjBFO5S (ORCPT ); Mon, 6 Feb 2023 09:57:18 -0500 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F34A425BAE for ; Mon, 6 Feb 2023 06:57:12 -0800 (PST) Received: by mail-ej1-x629.google.com with SMTP id mf7so34937674ejc.6 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:11 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 2/8] dt-bindings: power: qcom,rpmpd: add RPMH_REGULATOR_LEVEL_LOW_SVS_L1 Date: Mon, 6 Feb 2023 16:57:01 +0200 Message-Id: <20230206145707.122937-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add define for another power saving state used on SM8350 for the GPU. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- include/dt-bindings/power/qcom-rpmpd.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 4a30d10e6b7d..1bf8e87ecd7e 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -211,6 +211,7 @@ #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 #define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 #define RPMH_REGULATOR_LEVEL_LOW_SVS 64 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 #define RPMH_REGULATOR_LEVEL_SVS 128 #define RPMH_REGULATOR_LEVEL_SVS_L0 144 #define RPMH_REGULATOR_LEVEL_SVS_L1 192 From patchwork Mon Feb 6 14:57:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13130040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 385CAC64ED9 for ; Mon, 6 Feb 2023 14:57:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230282AbjBFO5U (ORCPT ); Mon, 6 Feb 2023 09:57:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229874AbjBFO5T (ORCPT ); Mon, 6 Feb 2023 09:57:19 -0500 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E24B25E31 for ; Mon, 6 Feb 2023 06:57:14 -0800 (PST) Received: by mail-ej1-x62a.google.com with SMTP id lu11so34993555ejb.3 for ; Mon, 06 Feb 2023 06:57:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sEaaIXvwNj4Y/ABcyEFSpp75hgY1fYms1s4I3xha300=; b=VT0DIb2218KDtV8LgUx4pLrKPUjw9ZaFe16Z7Em/3TwJGRh63ca6bVtA4lUQoDAwmc RMhElQT3TKKvJmnlOoiorjfI76//wbJtP3F3LdwX5Dw7eaFhCNhHIiuFS3ZHPzN7ykVo NmlXVHhTTwRkdshfWLBPhddHlNVmlqNc0L7ya+ohdj0Lo+17RCPyyOAkxaAqLt+mUY4Q w+jd9/fX4jeabLO2wf/nThycCl6Bvp2AwwGius4MLnU4BTNbXMlVwpXLMymakhgsINSN KQ17iVSnZFR8hc08EqXjujTYmUmG1hZNwOTp+TOR6p+U+C44m38PmdH5kkVZjlScljnJ pvkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sEaaIXvwNj4Y/ABcyEFSpp75hgY1fYms1s4I3xha300=; b=aPaH9iy53XD4eMXhr6PPAKcu6G7WCppiDv65pD54P/UzSoLHNmzEOtsg6J3RIjVmjO o+vD/f1OIYXTqKQIT6lxDjPKkcxSZGzX08Ep7SkaLAL104CTIop+evZY55eqdVEYBB6+ +tRI10Ed34+UVnQvAJR9LiuIE9ZfkwYRht+YZHdSB7hRlC3CfxUdyFbctgQJzFxRF5Bh EgWMtvcu6won/x5gh935RjEMv8M7QzipzUJIlXCE/wcXCl3j0GCrAyHQ1Mw79nVBaCYM 7NQfVkBNoG1cKs5XboRAP+7abIEfErgU+nhFAhFIlfhwlXgQ8NZPbYFAqsVml44jESul ZtMw== X-Gm-Message-State: AO0yUKXed+2xI8SuWQGvTTugC5JOZIPBzmhnLc3VFVe9heAuHLnjjvMf zTLMOXdLnBpR8FrMttIRObNTRQ== X-Google-Smtp-Source: AK7set+ld7Fvjne/Ke0hqBwYqqTXSGFZP0hAmU5HtemMLaDfL1KIGo8qZrRQ8W0ZVVuQb26Um7NGFg== X-Received: by 2002:a17:906:3189:b0:883:ba98:204d with SMTP id 9-20020a170906318900b00883ba98204dmr20445587ejy.65.1675695432717; Mon, 06 Feb 2023 06:57:12 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:12 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 3/8] dt-bindings: display/msm/gmu: add Adreno 660 support Date: Mon, 6 Feb 2023 16:57:02 +0200 Message-Id: <20230206145707.122937-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add Adreno A660 to the A635 clause to define all version-specific properties. There is no need to add it to the top-level clause, since top-level compatible uses pattern to define compatible strings. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring --- Documentation/devicetree/bindings/display/msm/gmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index ab14e81cb050..d5ce0dff4220 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -122,6 +122,7 @@ allOf: contains: enum: - qcom,adreno-gmu-635.0 + - qcom,adreno-gmu-660.1 then: properties: reg: From patchwork Mon Feb 6 14:57:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13130042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D5EAC6379F for ; Mon, 6 Feb 2023 14:57:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230467AbjBFO5Y (ORCPT ); Mon, 6 Feb 2023 09:57:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229776AbjBFO5X (ORCPT ); Mon, 6 Feb 2023 09:57:23 -0500 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88A661E2AC for ; Mon, 6 Feb 2023 06:57:15 -0800 (PST) Received: by mail-ed1-x52a.google.com with SMTP id u21so11956055edv.3 for ; Mon, 06 Feb 2023 06:57:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gYZC4EYPq1YxF9C9RBS62gJEHgsE3Qm/JlSqAe5dCDk=; b=XZ0n/eJelR7hF2+drMQvLbYGt1bXrGPZemXK1iKoyTh0q0FkZ25oWHlbFbR23VFQfq pHdVLoDtLjVERq3227JWdyqzyHssQCyqB5emy3t3RUhVuwvrp0h24EqMUW01sLYYZB/y xnJ1FZLCXksOZw0KPIkDZQHF5/cIiacvw4DVLasmc0YrzUiCBVxinWdu9RwTn76BTa/0 nXEnR3Fxja3iLe2ycpRSXeJHg0QathZMEv3JknHFG2f3Ea4jHfFk2Lv/VHU1mcAWk+zd bHb6b1+SQDax12DNnspgiDajn0h2xZcjLUfYEBv75KSKjUr5gHEr2tnoiq8IovGbGpHH UTtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gYZC4EYPq1YxF9C9RBS62gJEHgsE3Qm/JlSqAe5dCDk=; b=3MI9LIsLf/MVwK/jh+GIuWuueAmxoypOOjONuYK/gUCMOFxWohSer5z9qL5K90CKJC g7zZX0UjVSs+XjtMRT3RQdPKiQhZgDwpMwQD92lFE8OaIAI5d/Tz7YYJyNtg4hgR0bI3 fCbW8b3+nlaB4t9ZgDCIBnNZOmEi3UYjmFJkqYbwsfKArB6A4pAM+ulY4PVrX4qkCl+C x+eQr5k1eUuw4WnO9f4Y+Lz8nOeCo0WzLcrYjZN5eyEUe0pnJoWVF5xlQPpp8rUGqymH NIVNrfxqSWSbW2Qu9C1jkeiHOtbD3sMkTu/i26KJr/0rfP4FB1bm4VWnsHipJ8t3zR9o HMFw== X-Gm-Message-State: AO0yUKVKJS/wGXRYPPAatKj40s1FwkoD2HW4gUOX/dmhcOYuMPY8pEa/ MAgZit//BnnU9c6iaLdrLLsroQ== X-Google-Smtp-Source: AK7set/01AP6kCLOI7eHGp+1O8wXPf+wihK1ZQvQf2VjJcB+/UGSxmxw0lz8CbvgvKyeR72Ybw0eZg== X-Received: by 2002:a05:6402:510a:b0:46f:d386:117d with SMTP id m10-20020a056402510a00b0046fd386117dmr25303631edd.33.1675695433943; Mon, 06 Feb 2023 06:57:13 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:13 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 4/8] arm64: dts: qcom: sm8350: reorder device nodes Date: Mon, 6 Feb 2023 16:57:03 +0200 Message-Id: <20230206145707.122937-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Start ordering DT nodes according to agreed order. Move apps SMMU, GIC, timer, apps RSC, cpufreq ADSP and cDSP nodes to the end to the proper position at the end of /soc/. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1228 +++++++++++++------------- 1 file changed, 614 insertions(+), 614 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 0de42a333d32..061aa3fec1c4 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1423,111 +1423,6 @@ spi13: spi@a94000 { }; }; - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - config_noc: interconnect@1500000 { compatible = "qcom,sm8350-config-noc"; reg = <0 0x01500000 0 0xa580>; @@ -2126,253 +2021,92 @@ rng: rng@10d3000 { clock-names = "core"; }; - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0 0x20000>; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; - }; + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm8350-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; - timer@17c20000 { - compatible = "arm,armv7-timer-mem"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0x20000000>; - reg = <0x0 0x17c20000 0x0 0x1000>; - clock-frequency = <19200000>; + power-domains = <&gcc UFS_PHY_GDSC>; - frame@17c21000 { - frame-number = <0>; - interrupts = , - ; - reg = <0x17c21000 0x1000>, - <0x17c22000 0x1000>; - }; + iommus = <&apps_smmu 0xe0 0x0>; - frame@17c23000 { - frame-number = <1>; - interrupts = ; - reg = <0x17c23000 0x1000>; - status = "disabled"; - }; + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; - frame@17c25000 { - frame-number = <2>; - interrupts = ; - reg = <0x17c25000 0x1000>; - status = "disabled"; - }; + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm8350-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1c4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - frame@17c27000 { - frame-number = <3>; - interrupts = ; - reg = <0x17c27000 0x1000>; - status = "disabled"; - }; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; - frame@17c29000 { - frame-number = <4>; - interrupts = ; - reg = <0x17c29000 0x1000>; - status = "disabled"; + ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x188>, + <0 0x01d87600 0 0x200>, + <0 0x01d87c00 0 0x200>, + <0 0x01d87800 0 0x188>, + <0 0x01d87a00 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; }; + }; - frame@17c2b000 { - frame-number = <5>; - interrupts = ; - reg = <0x17c2b000 0x1000>; - status = "disabled"; - }; + slpi: remoteproc@5c00000 { + compatible = "qcom,sm8350-slpi-pas"; + reg = <0 0x05c00000 0 0x4000>; - frame@17c2d000 { - frame-number = <6>; - interrupts = ; - reg = <0x17c2d000 0x1000>; - status = "disabled"; - }; - }; + interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; - apps_rsc: rsc@18200000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , , - , ; - power-domains = <&CLUSTER_PD>; - - rpmhcc: clock-controller { - compatible = "qcom,sm8350-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8350-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = ; - }; - }; - }; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - }; - - cpufreq_hw: cpufreq@18591000 { - compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0 0x18591000 0 0x1000>, - <0 0x18592000 0 0x1000>, - <0 0x18593000 0 0x1000>; - reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8350-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0xe0 0x0>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8350-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c4>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x188>, - <0 0x01d87600 0 0x200>, - <0 0x01d87c00 0 0x200>, - <0 0x01d87800 0 0x188>, - <0 0x01d87a00 0 0x200>; - #clock-cells = <1>; - #phy-cells = <0>; - }; - }; - - slpi: remoteproc@5c00000 { - compatible = "qcom,sm8350-slpi-pas"; - reg = <0 0x05c00000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; power-domains = <&rpmhpd SM8350_LCX>, <&rpmhpd SM8350_LMX>; @@ -2427,176 +2161,67 @@ compute-cb@3 { }; }; - cdsp: remoteproc@98900000 { - compatible = "qcom,sm8350-cdsp-pas"; - reg = <0 0x98900000 0 0x1400000>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; + sdhc_2: mmc@8804000 { + compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; - power-domains = <&rpmhpd SM8350_CX>, - <&rpmhpd SM8350_MXC>; - power-domain-names = "cx", "mxc"; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + iommus = <&apps_smmu 0x4a0 0x0>; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + bus-width = <4>; + dma-coherent; - interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + status = "disabled"; - memory-region = <&pil_cdsp_mem>; + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; - qcom,qmp = <&aoss_qmp>; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; - qcom,smem-states = <&smp2p_cdsp_out 0>; - qcom,smem-state-names = "stop"; + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8350-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; status = "disabled"; + #phy-cells = <0>; - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; - label = "cdsp"; - qcom,remote-pid = <5>; + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; + usb_2_hsphy: phy@88e4000 { + compatible = "qcom,sm8250-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e4000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x2161 0x0400>, - <&apps_smmu 0x1181 0x0420>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2162 0x0400>, - <&apps_smmu 0x1182 0x0420>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x2163 0x0400>, - <&apps_smmu 0x1183 0x0420>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x2164 0x0400>, - <&apps_smmu 0x1184 0x0420>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x2165 0x0400>, - <&apps_smmu 0x1185 0x0420>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x2166 0x0400>, - <&apps_smmu 0x1186 0x0420>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x2167 0x0400>, - <&apps_smmu 0x1187 0x0420>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x2168 0x0400>, - <&apps_smmu 0x1188 0x0420>; - }; - - /* note: secure cb9 in downstream */ - }; - }; - }; - - sdhc_2: mmc@8804000 { - compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x08804000 0 0x1000>; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "core", "xo"; - resets = <&gcc GCC_SDCC2_BCR>; - interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; - interconnect-names = "sdhc-ddr","cpu-sdhc"; - iommus = <&apps_smmu 0x4a0 0x0>; - power-domains = <&rpmhpd SM8350_CX>; - operating-points-v2 = <&sdhc2_opp_table>; - bus-width = <4>; - dma-coherent; - - status = "disabled"; - - sdhc2_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-202000000 { - opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - }; - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8350-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_2_hsphy: phy@88e4000 { - compatible = "qcom,sm8250-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e4000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; @@ -2987,190 +2612,565 @@ mdss_dsi0_phy: phy@ae94400 { status = "disabled"; }; - mdss_dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae96000 0 0x400>; - reg-names = "dsi_ctrl"; + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi1_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&mdss_dsi1_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-187500000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,sm8350-dsi-phy-5nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + power-domains = <&rpmhpd SM8350_MMCX>; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + adsp: remoteproc@17300000 { + compatible = "qcom,sm8350-adsp-pas"; + reg = <0 0x17300000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&pil_adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1803 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1804 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1805 0x0>; + }; + }; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0 0x20000>; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x20000000>; + reg = <0x0 0x17c20000 0x0 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; - interrupt-parent = <&mdss>; - interrupts = <5>; + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + power-domains = <&CLUSTER_PD>; - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; + rpmhcc: clock-controller { + compatible = "qcom,sm8350-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + rpmhpd: power-controller { + compatible = "qcom,sm8350-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; - operating-points-v2 = <&dsi1_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; - phys = <&mdss_dsi1_phy>; + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; - #address-cells = <1>; - #size-cells = <0>; + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; - status = "disabled"; + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; - dsi1_opp_table: opp-table { - compatible = "operating-points-v2"; + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; - /* TODO: opp-187500000 should work with - * &rpmhpd_opp_low_svs, but one some of - * sm8350_hdk boards reboot using this - * opp. - */ - opp-187500000 { - opp-hz = /bits/ 64 <187500000>; - required-opps = <&rpmhpd_opp_svs>; + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_svs>; + rpmhpd_opp_nom: opp6 { + opp-level = ; }; - opp-358000000 { - opp-hz = /bits/ 64 <358000000>; - required-opps = <&rpmhpd_opp_svs_l1>; + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; }; - }; - ports { - #address-cells = <1>; - #size-cells = <0>; + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; - port@0 { - reg = <0>; - mdss_dsi1_in: endpoint { - remote-endpoint = <&dpu_intf2_out>; - }; + rpmhpd_opp_turbo: opp9 { + opp-level = ; }; - port@1 { - reg = <1>; - mdss_dsi1_out: endpoint { - }; + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; }; }; }; - mdss_dsi1_phy: phy@ae96400 { - compatible = "qcom,sm8350-dsi-phy-5nm"; - reg = <0 0x0ae96400 0 0x200>, - <0 0x0ae96600 0 0x280>, - <0 0x0ae96900 0 0x27c>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; - - status = "disabled"; + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; }; }; - dispcc: clock-controller@af00000 { - compatible = "qcom,sm8350-dispcc"; - reg = <0 0x0af00000 0 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <0>, - <0>; - clock-names = "bi_tcxo", - "dsi0_phy_pll_out_byteclk", - "dsi0_phy_pll_out_dsiclk", - "dsi1_phy_pll_out_byteclk", - "dsi1_phy_pll_out_dsiclk", - "dp_phy_pll_link_clk", - "dp_phy_pll_vco_div_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x18591000 0 0x1000>, + <0 0x18592000 0 0x1000>, + <0 0x18593000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; - power-domains = <&rpmhpd SM8350_MMCX>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; }; - adsp: remoteproc@17300000 { - compatible = "qcom,sm8350-adsp-pas"; - reg = <0 0x17300000 0 0x100>; + cdsp: remoteproc@98900000 { + compatible = "qcom,sm8350-cdsp-pas"; + reg = <0 0x98900000 0 0x1400000>; - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_LCX>, - <&rpmhpd SM8350_LMX>; - power-domain-names = "lcx", "lmx"; + power-domains = <&rpmhpd SM8350_CX>, + <&rpmhpd SM8350_MXC>; + power-domain-names = "cx", "mxc"; - memory-region = <&pil_adsp_mem>; + interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region = <&pil_cdsp_mem>; qcom,qmp = <&aoss_qmp>; - qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-states = <&smp2p_cdsp_out 0>; qcom,smem-state-names = "stop"; status = "disabled"; glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS + mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP>; - label = "lpass"; - qcom,remote-pid = <2>; + label = "cdsp"; + qcom,remote-pid = <5>; fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; + label = "cdsp"; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x2161 0x0400>, + <&apps_smmu 0x1181 0x0420>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x2162 0x0400>, + <&apps_smmu 0x1182 0x0420>; + }; + compute-cb@3 { compatible = "qcom,fastrpc-compute-cb"; reg = <3>; - iommus = <&apps_smmu 0x1803 0x0>; + iommus = <&apps_smmu 0x2163 0x0400>, + <&apps_smmu 0x1183 0x0420>; }; compute-cb@4 { compatible = "qcom,fastrpc-compute-cb"; reg = <4>; - iommus = <&apps_smmu 0x1804 0x0>; + iommus = <&apps_smmu 0x2164 0x0400>, + <&apps_smmu 0x1184 0x0420>; }; compute-cb@5 { compatible = "qcom,fastrpc-compute-cb"; reg = <5>; - iommus = <&apps_smmu 0x1805 0x0>; + iommus = <&apps_smmu 0x2165 0x0400>, + <&apps_smmu 0x1185 0x0420>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x2166 0x0400>, + <&apps_smmu 0x1186 0x0420>; }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x2167 0x0400>, + <&apps_smmu 0x1187 0x0420>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x2168 0x0400>, + <&apps_smmu 0x1188 0x0420>; + }; + + /* note: secure cb9 in downstream */ }; }; }; From patchwork Mon Feb 6 14:57:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13130041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B623C64EC4 for ; Mon, 6 Feb 2023 14:57:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230253AbjBFO5Z (ORCPT ); Mon, 6 Feb 2023 09:57:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229874AbjBFO5Y (ORCPT ); Mon, 6 Feb 2023 09:57:24 -0500 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA50E234E2 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:15 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 5/8] arm64: dts: qcom: sm8350: move more nodes to correct place Date: Mon, 6 Feb 2023 16:57:04 +0200 Message-Id: <20230206145707.122937-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Continue ordering DT nodes. Move RNG, UFS, system NoC and SLPI nodes to the proper position. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 314 +++++++++++++-------------- 1 file changed, 157 insertions(+), 157 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 061aa3fec1c4..c327dc925793 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1423,6 +1423,13 @@ spi13: spi@a94000 { }; }; + rng: rng@10d3000 { + compatible = "qcom,prng-ee"; + reg = <0 0x010d3000 0 0x1000>; + clocks = <&rpmhcc RPMH_HWKM_CLK>; + clock-names = "core"; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8350-config-noc"; reg = <0 0x01500000 0 0xa580>; @@ -1643,18 +1650,76 @@ pcie1_phy: phy@1c0f000 { status = "disabled"; }; - lpass_ag_noc: interconnect@3c40000 { - compatible = "qcom,sm8350-lpass-ag-noc"; - reg = <0 0x03c40000 0 0xf080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm8350-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0xe0 0x0>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; }; - compute_noc: interconnect@a0c0000 { - compatible = "qcom,sm8350-compute-noc"; - reg = <0 0x0a0c0000 0 0xa180>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm8350-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1c4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x188>, + <0 0x01d87600 0 0x200>, + <0 0x01d87c00 0 0x200>, + <0 0x01d87800 0 0x188>, + <0 0x01d87a00 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; }; ipa: ipa@1e40000 { @@ -1702,6 +1767,13 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,sm8350-lpass-ag-noc"; + reg = <0 0x03c40000 0 0xf080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + mpss: remoteproc@4080000 { compatible = "qcom,sm8350-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; @@ -1744,6 +1816,74 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; + slpi: remoteproc@5c00000 { + compatible = "qcom,sm8350-slpi-pas"; + reg = <0 0x05c00000 0 0x4000>; + + interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&pil_slpi_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_slpi_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "slpi"; + qcom,remote-pid = <3>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "sdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0541 0x0>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0542 0x0>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0543 0x0>; + /* note: shared-cb = <4> in downstream */ + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8350-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; @@ -2014,153 +2154,6 @@ qup_i2c19_default: qup-i2c19-default-state { }; }; - rng: rng@10d3000 { - compatible = "qcom,prng-ee"; - reg = <0 0x010d3000 0 0x1000>; - clocks = <&rpmhcc RPMH_HWKM_CLK>; - clock-names = "core"; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8350-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = ; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0xe0 0x0>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8350-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c4>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x188>, - <0 0x01d87600 0 0x200>, - <0 0x01d87c00 0 0x200>, - <0 0x01d87800 0 0x188>, - <0 0x01d87a00 0 0x200>; - #clock-cells = <1>; - #phy-cells = <0>; - }; - }; - - slpi: remoteproc@5c00000 { - compatible = "qcom,sm8350-slpi-pas"; - reg = <0 0x05c00000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8350_LCX>, - <&rpmhpd SM8350_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&pil_slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "slpi"; - qcom,remote-pid = <3>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0541 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0542 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0543 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - sdhc_2: mmc@8804000 { compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -2309,6 +2302,13 @@ system-cache-controller@9200000 { reg-names = "llcc_base", "llcc_broadcast_base"; }; + compute_noc: interconnect@a0c0000 { + compatible = "qcom,sm8350-compute-noc"; + reg = <0 0x0a0c0000 0 0xa180>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; From patchwork Mon Feb 6 14:57:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13130043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9226C64ED6 for ; Mon, 6 Feb 2023 14:57:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229700AbjBFO51 (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:16 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 6/8] arm64: dts: qcom: sm8350: finish reordering nodes Date: Mon, 6 Feb 2023 16:57:05 +0200 Message-Id: <20230206145707.122937-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Finish reordering DT nodes. Move PDC, tsens, AOSS, SRAM, SPMI and TLMM nodes to the proper position. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 764 +++++++++++++-------------- 1 file changed, 382 insertions(+), 382 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index c327dc925793..e5b308957f88 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1884,276 +1884,6 @@ compute-cb@3 { }; }; - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8350-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; - qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, - <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, - <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, - <156 716 12>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1ff>, /* TM */ - <0 0x0c222000 0 0x8>; /* SROT */ - #qcom,sensors = <15>; - interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1ff>, /* TM */ - <0 0x0c223000 0 0x8>; /* SROT */ - #qcom,sensors = <14>; - interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: power-management@c300000 { - compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; - reg = <0 0x0c300000 0 0x400>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - }; - - sram@c3f0000 { - compatible = "qcom,rpmh-stats"; - reg = <0 0x0c3f0000 0 0x400>; - }; - - spmi_bus: spmi@c440000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c440000 0x0 0x1100>, - <0x0 0x0c600000 0x0 0x2000000>, - <0x0 0x0e600000 0x0 0x100000>, - <0x0 0x0e700000 0x0 0xa0000>, - <0x0 0x0c40a000 0x0 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8350-tlmm"; - reg = <0 0x0f100000 0 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 204>; - wakeup-parent = <&pdc>; - - sdc2_default_state: sdc2-default-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <16>; - bias-disable; - }; - - cmd-pins { - pins = "sdc2_cmd"; - drive-strength = <16>; - bias-pull-up; - }; - - data-pins { - pins = "sdc2_data"; - drive-strength = <16>; - bias-pull-up; - }; - }; - - sdc2_sleep_state: sdc2-sleep-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <2>; - bias-disable; - }; - - cmd-pins { - pins = "sdc2_cmd"; - drive-strength = <2>; - bias-pull-up; - }; - - data-pins { - pins = "sdc2_data"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - qup_uart3_default_state: qup-uart3-default-state { - rx-pins { - pins = "gpio18"; - function = "qup3"; - }; - tx-pins { - pins = "gpio19"; - function = "qup3"; - }; - }; - - qup_uart6_default: qup-uart6-default-state { - pins = "gpio30", "gpio31"; - function = "qup6"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart18_default: qup-uart18-default-state { - pins = "gpio58", "gpio59"; - function = "qup18"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c0_default: qup-i2c0-default-state { - pins = "gpio4", "gpio5"; - function = "qup0"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c1_default: qup-i2c1-default-state { - pins = "gpio8", "gpio9"; - function = "qup1"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c2_default: qup-i2c2-default-state { - pins = "gpio12", "gpio13"; - function = "qup2"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c4_default: qup-i2c4-default-state { - pins = "gpio20", "gpio21"; - function = "qup4"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c5_default: qup-i2c5-default-state { - pins = "gpio24", "gpio25"; - function = "qup5"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c6_default: qup-i2c6-default-state { - pins = "gpio28", "gpio29"; - function = "qup6"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c7_default: qup-i2c7-default-state { - pins = "gpio32", "gpio33"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c8_default: qup-i2c8-default-state { - pins = "gpio36", "gpio37"; - function = "qup8"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c9_default: qup-i2c9-default-state { - pins = "gpio40", "gpio41"; - function = "qup9"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c10_default: qup-i2c10-default-state { - pins = "gpio44", "gpio45"; - function = "qup10"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c11_default: qup-i2c11-default-state { - pins = "gpio48", "gpio49"; - function = "qup11"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c12_default: qup-i2c12-default-state { - pins = "gpio52", "gpio53"; - function = "qup12"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c13_default: qup-i2c13-default-state { - pins = "gpio0", "gpio1"; - function = "qup13"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c14_default: qup-i2c14-default-state { - pins = "gpio56", "gpio57"; - function = "qup14"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c15_default: qup-i2c15-default-state { - pins = "gpio60", "gpio61"; - function = "qup15"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c16_default: qup-i2c16-default-state { - pins = "gpio64", "gpio65"; - function = "qup16"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c17_default: qup-i2c17-default-state { - pins = "gpio72", "gpio73"; - function = "qup17"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c19_default: qup-i2c19-default-state { - pins = "gpio76", "gpio77"; - function = "qup19"; - drive-strength = <2>; - bias-disable; - }; - }; - sdhc_2: mmc@8804000 { compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -2593,144 +2323,414 @@ mdss_dsi0_out: endpoint { }; }; - mdss_dsi0_phy: phy@ae94400 { - compatible = "qcom,sm8350-dsi-phy-5nm"; - reg = <0 0x0ae94400 0 0x200>, - <0 0x0ae94600 0 0x280>, - <0 0x0ae94900 0 0x27c>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - #clock-cells = <1>; - #phy-cells = <0>; + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,sm8350-dsi-phy-5nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi1_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&mdss_dsi1_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-187500000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,sm8350-dsi-phy-5nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + power-domains = <&rpmhpd SM8350_MMCX>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8350-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, + <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, + <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, + <156 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x8>; /* SROT */ + #qcom,sensors = <15>; + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x8>; /* SROT */ + #qcom,sensors = <14>; + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8350-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 204>; + wakeup-parent = <&pdc>; + + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; - status = "disabled"; + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; }; - mdss_dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; - reg = <0 0x0ae96000 0 0x400>; - reg-names = "dsi_ctrl"; + qup_uart3_default_state: qup-uart3-default-state { + rx-pins { + pins = "gpio18"; + function = "qup3"; + }; + tx-pins { + pins = "gpio19"; + function = "qup3"; + }; + }; - interrupt-parent = <&mdss>; - interrupts = <5>; + qup_uart6_default: qup-uart6-default-state { + pins = "gpio30", "gpio31"; + function = "qup6"; + drive-strength = <2>; + bias-disable; + }; - clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, - <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK>, - <&dispcc DISP_CC_MDSS_ESC1_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; + qup_uart18_default: qup-uart18-default-state { + pins = "gpio58", "gpio59"; + function = "qup18"; + drive-strength = <2>; + bias-disable; + }; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio4", "gpio5"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; - operating-points-v2 = <&dsi1_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio8", "gpio9"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; - phys = <&mdss_dsi1_phy>; + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio12", "gpio13"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; - #address-cells = <1>; - #size-cells = <0>; + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio20", "gpio21"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; - status = "disabled"; + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio24", "gpio25"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; - dsi1_opp_table: opp-table { - compatible = "operating-points-v2"; + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio28", "gpio29"; + function = "qup6"; + drive-strength = <2>; + bias-pull-up; + }; - /* TODO: opp-187500000 should work with - * &rpmhpd_opp_low_svs, but one some of - * sm8350_hdk boards reboot using this - * opp. - */ - opp-187500000 { - opp-hz = /bits/ 64 <187500000>; - required-opps = <&rpmhpd_opp_svs>; - }; + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio32", "gpio33"; + function = "qup7"; + drive-strength = <2>; + bias-disable; + }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_svs>; - }; + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio36", "gpio37"; + function = "qup8"; + drive-strength = <2>; + bias-pull-up; + }; - opp-358000000 { - opp-hz = /bits/ 64 <358000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - }; + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio40", "gpio41"; + function = "qup9"; + drive-strength = <2>; + bias-pull-up; + }; - ports { - #address-cells = <1>; - #size-cells = <0>; + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio44", "gpio45"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; - port@0 { - reg = <0>; - mdss_dsi1_in: endpoint { - remote-endpoint = <&dpu_intf2_out>; - }; - }; + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio48", "gpio49"; + function = "qup11"; + drive-strength = <2>; + bias-pull-up; + }; - port@1 { - reg = <1>; - mdss_dsi1_out: endpoint { - }; - }; - }; + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio52", "gpio53"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; }; - mdss_dsi1_phy: phy@ae96400 { - compatible = "qcom,sm8350-dsi-phy-5nm"; - reg = <0 0x0ae96400 0 0x200>, - <0 0x0ae96600 0 0x280>, - <0 0x0ae96900 0 0x27c>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio0", "gpio1"; + function = "qup13"; + drive-strength = <2>; + bias-pull-up; + }; - #clock-cells = <1>; - #phy-cells = <0>; + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio56", "gpio57"; + function = "qup14"; + drive-strength = <2>; + bias-disable; + }; - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "ref"; + qup_i2c15_default: qup-i2c15-default-state { + pins = "gpio60", "gpio61"; + function = "qup15"; + drive-strength = <2>; + bias-disable; + }; - status = "disabled"; + qup_i2c16_default: qup-i2c16-default-state { + pins = "gpio64", "gpio65"; + function = "qup16"; + drive-strength = <2>; + bias-disable; }; - }; - dispcc: clock-controller@af00000 { - compatible = "qcom,sm8350-dispcc"; - reg = <0 0x0af00000 0 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <0>, - <0>; - clock-names = "bi_tcxo", - "dsi0_phy_pll_out_byteclk", - "dsi0_phy_pll_out_dsiclk", - "dsi1_phy_pll_out_byteclk", - "dsi1_phy_pll_out_dsiclk", - "dp_phy_pll_link_clk", - "dp_phy_pll_vco_div_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; + qup_i2c17_default: qup-i2c17-default-state { + pins = "gpio72", "gpio73"; + function = "qup17"; + drive-strength = <2>; + bias-disable; + }; - power-domains = <&rpmhpd SM8350_MMCX>; + qup_i2c19_default: qup-i2c19-default-state { + pins = "gpio76", "gpio77"; + function = "qup19"; + drive-strength = <2>; + bias-disable; + }; }; apps_smmu: iommu@15000000 { From patchwork Mon Feb 6 14:57:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13130044 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A146C63797 for ; Mon, 6 Feb 2023 14:57:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231176AbjBFO5c (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:17 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 7/8] arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes Date: Mon, 6 Feb 2023 16:57:06 +0200 Message-Id: <20230206145707.122937-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device nodes required to enable GPU on the SM8350 platform. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 178 +++++++++++++++++++++++++++ 1 file changed, 178 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e5b308957f88..c0992cf54d3a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1767,6 +1768,183 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-660.1", "qcom,adreno"; + + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>, + <0 0x03d61000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + /* note: downstream checks gpu binning for 670 Mhz */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-level = ; + }; + + opp-778000000 { + opp-hz = /bits/ 64 <778000000>; + opp-level = ; + }; + + opp-738000000 { + opp-hz = /bits/ 64 <738000000>; + opp-level = ; + }; + + opp-676000000 { + opp-hz = /bits/ 64 <676000000>; + opp-level = ; + }; + + opp-608000000 { + opp-hz = /bits/ 64 <608000000>; + opp-level = ; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-level = ; + }; + + opp-491000000 { + opp-hz = /bits/ 64 <491000000>; + opp-level = ; + }; + + opp-443000000 { + opp-hz = /bits/ 64 <443000000>; + opp-level = ; + }; + + opp-379000000 { + opp-hz = /bits/ 64 <379000000>; + opp-level = ; + }; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; + + reg = <0 0x03d6a000 0 0x34000>, + <0 0x03de0000 0 0x10000>, + <0 0x0b290000 0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x400>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + reg = <0 0x03da0000 0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "bus", + "iface", + "ahb", + "hlos1_vote_gpu_smmu", + "cx_gmu", + "hub_cx_int", + "hub_aon"; + + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,sm8350-lpass-ag-noc"; reg = <0 0x03c40000 0 0xf080>; From patchwork Mon Feb 6 14:57:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13130045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95151C6379F for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id gw1-20020a170906f14100b0087bd4e34eb8sm5495533ejb.203.2023.02.06.06.57.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:57:18 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Clark , Abhinav Kumar , Sean Paul , dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, David Airlie , Daniel Vetter Subject: [PATCH v2 8/8] arm64: dts: qcom: sm8350-hdk: enable GPU Date: Mon, 6 Feb 2023 16:57:07 +0200 Message-Id: <20230206145707.122937-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> References: <20230206145707.122937-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the GPU on the SM8350-HDK device. The ZAP shader is required for the GPU to function properly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index df841230d1b7..5e744423a673 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -284,6 +284,14 @@ &gpi_dma1 { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8350/a660_zap.mbn"; + }; +}; + &i2c15 { clock-frequency = <400000>; status = "okay";