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([131.107.8.28]) by smtp.gmail.com with ESMTPSA id p24-20020a170902b09800b001992181b5d5sm1672901plr.245.2023.02.06.11.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 11:55:41 -0800 (PST) From: Dave Thaler To: bpf@vger.kernel.org Cc: bpf@ietf.org, Dave Thaler Subject: [PATCH bpf-next] bpf, docs: Add explanation of endianness Date: Mon, 6 Feb 2023 19:55:32 +0000 Message-Id: <20230206195532.2436-1-dthaler1968@googlemail.com> X-Mailer: git-send-email 2.33.4 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net From: Dave Thaler Document the discussion from the email thread on the IETF bpf list, where it was explained that the raw format varies by endianness of the processor. Signed-off-by: Dave Thaler Acked-by: David Vernet --- Documentation/bpf/instruction-set.rst | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 2d3fe59bd26..3358769dc1f 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -33,7 +33,7 @@ eBPF has two instruction encodings: * the wide instruction encoding, which appends a second 64-bit immediate value (imm64) after the basic instruction for a total of 128 bits. -The basic instruction encoding looks as follows: +The basic instruction encoding looks as follows for a little-endian processor: ============= ======= =============== ==================== ============ 32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB) @@ -41,6 +41,17 @@ The basic instruction encoding looks as follows: immediate offset source register destination register opcode ============= ======= =============== ==================== ============ +and as follows for a big-endian processor: + +============= ======= ==================== =============== ============ +32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB) +============= ======= ==================== =============== ============ +immediate offset destination register source register opcode +============= ======= ==================== =============== ============ + +Multi-byte fields ('immediate' and 'offset') are similarly stored in +the byte order of the processor. + Note that most instructions do not use all of the fields. Unused fields shall be cleared to zero.