From patchwork Mon Feb 6 20:14:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 13130558 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D42EAC05027 for ; Mon, 6 Feb 2023 20:15:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Al0dY2aScBW4IjCxtKPozWYp2UQ4DH84lHuYTICTLCY=; b=01S/53LdXlmQnx jyi0rg+9itUVcVTwzEZ1ccQ75HXXIUoV8bsW2ws5mU70vuBGrswSBbMlNyY9pFc2Bo2moG25wfoCa bMtYPE20KpTREnQQYorFwnXPvsjl/zIruuuyvCGAVYpfODABFBZcVmP684iBwLiH6rUZCfwBSrWYU jNz6kmvgEeOgJjUPpBm+xTOd1ee/dEoxPUN+e2pQkBo4Jm8v3aBpqKu/9IOvzREjOSsl6j78vvoKk irVjKY0/HRQsq1LtPyYyZQ9T48z5VB9Lt+Czg9TPiRNQ8ZYkThTL/LIK7QZLJ+dFjFGCJQqsbJK0v pNsvo3iGfdFpAU8vUEoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7tj-009oZa-Uc; Mon, 06 Feb 2023 20:15:31 +0000 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7tf-009oVj-MG for linux-riscv@lists.infradead.org; Mon, 06 Feb 2023 20:15:29 +0000 Received: by mail-pj1-x102e.google.com with SMTP id mi9so12713562pjb.4 for ; Mon, 06 Feb 2023 12:15:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L3E7gTy1SZ/rYCbfPiq6VlVdMXLKt386NsSmOIvpWA4=; b=d7Hb5NLdauK+98+KYLb/5jnKRBJ18m6p1tGFFJIg+5BAzF9yTJrYEN83GG6vZFh36v yr6yVgcyJ0S3/UU5WvW8M1/P37bmvL4Qp6ruOAw+JCf/J5yfqQXc+gcdzmQMVDGFrTIX ajvfH5AbA9VwC8DX/Tz8SjG+NMTj4W8ZCQyWa0DERSaTTLttMrQ+n4U267it20SgXkDw miF94exCJq5BxV7x6FTNeEfXwfzPfrQWoY+YdVLwg5nN9N7XnIOJR77DL4AomYm4z3Hn SPOD+nriiYYT8z1W9e5yUDnA6YrYR7vt0joB6qLOww83G9Z7FYGE8w7rRbAvB21rawh5 A4fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L3E7gTy1SZ/rYCbfPiq6VlVdMXLKt386NsSmOIvpWA4=; b=IbviilmPX/tv3IpkaGXb4M1SePF+Ah3j3fmDxJkFHvZjo7b2cNmLYMw6zdC4kvs2t7 SsCn7B828Ptj4cCYw1fdki0cj1eirOGthQfXul+XPf0NLYdWrFRU6jt5MIHZa+eLQCyO t0a0CkmxoTny98TZ5S9GugY7HpxcA4SXDO9/MOPioapQ40E+0NjqW5bfyYilG+ncfYac b5v25ZA4YmW774easuG/ZIhyl50nWch4dMkGWKO1bINX8+vCIXutQT32SP2Uogds4gw+ 3m3oLx4Pgiak7r9PfJgg6cBV70OFkFhC5OeuyegXCnFeRVCX5wlRYYs1J4TuupAdldKR OyjQ== X-Gm-Message-State: AO0yUKVMQOxitnylusq8PH/TIxhNA9u7zpHHxu3QBR4Wqbvcy5WuQXRa CN1UBkyatV8H+AlhLLEWxKgKvA== X-Google-Smtp-Source: AK7set89wInCODEUg3p17p5zHU1W/mDyBIfYFOL5qrDCXusDtTme4YBO8NalJNVzABW6CNbgFZA8XQ== X-Received: by 2002:a05:6a20:8421:b0:bf:bcfb:1fc2 with SMTP id c33-20020a056a20842100b000bfbcfb1fc2mr884580pzd.45.1675714521714; Mon, 06 Feb 2023 12:15:21 -0800 (PST) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id k10-20020a63ab4a000000b004df4fbb9823sm6425079pgp.68.2023.02.06.12.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 12:15:21 -0800 (PST) From: Evan Green To: Palmer Dabbelt Subject: [PATCH v2 1/6] RISC-V: Move struct riscv_cpuinfo to new header Date: Mon, 6 Feb 2023 12:14:50 -0800 Message-Id: <20230206201455.1790329-2-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230206_121527_732308_9DABE334 X-CRM114-Status: GOOD ( 14.53 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Albert Ou , heiko@sntech.de, Atish Patra , Randy Dunlap , vineetg@rivosinc.com, linux-kernel@vger.kernel.org, Conor Dooley , Conor Dooley , Evan Green , Palmer Dabbelt , slewis@rivosinc.com, Paul Walmsley , Qinglin Pan , linux-riscv@lists.infradead.org Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org In preparation for tracking and exposing microarchitectural details to userspace (like whether or not unaligned accesses are fast), move the riscv_cpuinfo struct out to its own new cpufeatures.h header. It will need to be used by more than just cpu.c. Signed-off-by: Evan Green Reviewed-by: Conor Dooley --- (no changes since v1) arch/riscv/include/asm/cpufeature.h | 21 +++++++++++++++++++++ arch/riscv/kernel/cpu.c | 8 ++------ 2 files changed, 23 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/include/asm/cpufeature.h diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h new file mode 100644 index 000000000000..66c251d98290 --- /dev/null +++ b/arch/riscv/include/asm/cpufeature.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2022 Rivos, Inc + */ + +#ifndef _ASM_CPUFEATURE_H +#define _ASM_CPUFEATURE_H + +/* + * These are probed via a device_initcall(), via either the SBI or directly + * from the cooresponding CSRs. + */ +struct riscv_cpuinfo { + unsigned long mvendorid; + unsigned long marchid; + unsigned long mimpid; +}; + +DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); + +#endif diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 1b9a5a66e55a..684e5419d37d 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -70,12 +71,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) return -1; } -struct riscv_cpuinfo { - unsigned long mvendorid; - unsigned long marchid; - unsigned long mimpid; -}; -static DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); +DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); unsigned long riscv_cached_mvendorid(unsigned int cpu_id) { From patchwork Mon Feb 6 20:14:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 13130559 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64DF5C636D3 for ; Mon, 6 Feb 2023 20:15:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bU6TwdAWZU72Aq1FQOPV+NiJ3h5AsNNyJveg41mV9Fk=; b=m9oNtlmqojH+iF 5LnWFleC99EqZKHFqPQxpXrr1H8h5lN3QuiYEOPP6xhe4bdm1DefYpT4qFeaz5ztTCReWCbzL8y1o nx8uGFOdgR5EhefHDcxV1QjW78ILG2o4WQD9L18gfMoBip6oMte7K3bj5YKNsIUTBZt3i1l37RMe7 GQ17la+4RG7s8jLGDqTHXA4LZcRLIBXlQggpPIQSQkfwguqGABZwCXrB8Az7gf/81ZOd6ge16bhVr xBZWSiY3OIECvY1QBOjc8RYmkKysA/IHyVx7ac0hAh6MwCYo+9tZrpEwe4KjJI5Iq2N/qfmL2aTBK XhdqJRRBbhiqRgxDn2PQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7tl-009oaF-8C; Mon, 06 Feb 2023 20:15:33 +0000 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7tg-009oXF-5c for linux-riscv@lists.infradead.org; Mon, 06 Feb 2023 20:15:30 +0000 Received: by mail-pl1-x631.google.com with SMTP id e19so5485372plc.9 for ; Mon, 06 Feb 2023 12:15:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NQY/ewono7eyJVzIAIVhUKj+GHApr931zg2+4gRqdDM=; b=0EhBKOOJcz9jUXs2WdevqyEvuR6iVGwzmFgp1Hv7Tjj0tjWL8PWkEUtyU/ckx/rloA e4lIKA2K7ZHqKkz00PzOrQOfrugp7S21VPpdDzogAbbwgR9Dd8uebzGvsE8+6SDTVNFH /QeQ8J4euDm7tiLzDN4ly3jtKRQNRV0JvocmRuQsgLmYr2UrJTl/hDfUq0BkisMBl+lN 10iBjLz9SQBvzfluNbZ4i8XHiAJ59p+fHX27Dj67ZYuYv3BLUkVU6KS1erw8uPELLWGA 6Bie4cMfw75oQMjHK9RtXmBq6X9Liko/Hf6hWfuGx/iLye7L4qUprGtnHys66md5NHoX lu3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NQY/ewono7eyJVzIAIVhUKj+GHApr931zg2+4gRqdDM=; b=Ulw9hF9RRc01JInVr1cT9oFUSpvclaHg8XMq4ze6Y3W/DHXnTNniRESnm8f8uK0FjT bBsnEWQmfKV1EdFRXlQAo+PC/h8Oc/qejIH/y0/89ND8cTbjRB2S0Fv5ap81XAR2nF8w ga+CXvXN8dH6Lq+704nTBSI/NnXtR5HXHAVDS9X52VemIqCYHHAdSO171IiqKvsDWWdP Iqslw/ExryaDvMm7IscFRLcHe5aezRl463y7zOTBbG5EJ6OG29JLSKhjt2I4YmL/jnYr QYgkplLflSumVaszlDEuzOBi12+RNX7ObTMZwE1O0i2S4CKIIyy3/6ZrvAJW6HGoxrEB EpyA== X-Gm-Message-State: AO0yUKXsU3VUXZqvL1NgW9BezePpqjiyCuX59bcz+0ok8fentJhPPvE6 mPXOCLf9ZC8tosRmop2Z5YsSUA== X-Google-Smtp-Source: AK7set99lLQ4BVN/k6fBT3UsGI+53df57kc0Bvwei0tHQPb8hAP+F7xZTmU66VcBztxtN+pWGQd9RQ== X-Received: by 2002:a05:6a20:12c9:b0:af:98cd:7df1 with SMTP id v9-20020a056a2012c900b000af98cd7df1mr579279pzg.24.1675714526377; Mon, 06 Feb 2023 12:15:26 -0800 (PST) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id k10-20020a63ab4a000000b004df4fbb9823sm6425079pgp.68.2023.02.06.12.15.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 12:15:25 -0800 (PST) From: Evan Green To: Palmer Dabbelt Subject: [PATCH v2 2/6] RISC-V: Add a syscall for HW probing Date: Mon, 6 Feb 2023 12:14:51 -0800 Message-Id: <20230206201455.1790329-3-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230206_121528_245911_42B94C51 X-CRM114-Status: GOOD ( 35.06 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: heiko@sntech.de, linux-doc@vger.kernel.org, Andrew Bresticker , Atish Patra , Conor Dooley , Celeste Liu , slewis@rivosinc.com, Bagas Sanjaya , linux-riscv@lists.infradead.org, Jonathan Corbet , Tobias Klauser , Andrew Jones , Albert Ou , Arnd Bergmann , vineetg@rivosinc.com, Dao Lu , Paul Walmsley , Ruizhe Pan , Anup Patel , Randy Dunlap , linux-kernel@vger.kernel.org, Conor Dooley , Evan Green , Palmer Dabbelt , Guo Ren Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We don't have enough space for these all in ELF_HWCAP{,2} and there's no system call that quite does this, so let's just provide an arch-specific one to probe for hardware capabilities. This currently just provides m{arch,imp,vendor}id, but with the key-value pairs we can pass more in the future. Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- Changes in v2: - Changed the interface to look more like poll(). Rather than supplying key_offset and getting back an array of values with numerically contiguous keys, have the user pre-fill the key members of the array, and the kernel will fill in the corresponding values. For any key it doesn't recognize, it will set the key of that element to -1. This allows usermode to quickly ask for exactly the elements it cares about, and not get bogged down in a back and forth about newer keys that older kernels might not recognize. In other words, the kernel can communicate that it doesn't recognize some of the keys while still providing the data for the keys it does know. - Added a shortcut to the cpuset parameters that if a size of 0 and NULL is provided for the CPU set, the kernel will use a cpu mask of all online CPUs. This is convenient because I suspect most callers will only want to act on a feature if it's supported on all CPUs, and it's a headache to dynamically allocate an array of all 1s, not to mention a waste to have the kernel loop over all of the offline bits. --- Documentation/riscv/hwprobe.rst | 37 +++++++ Documentation/riscv/index.rst | 1 + arch/riscv/include/asm/hwprobe.h | 13 +++ arch/riscv/include/asm/syscall.h | 3 + arch/riscv/include/uapi/asm/hwprobe.h | 25 +++++ arch/riscv/include/uapi/asm/unistd.h | 8 ++ arch/riscv/kernel/cpu.c | 3 +- arch/riscv/kernel/sys_riscv.c | 146 +++++++++++++++++++++++++- 8 files changed, 234 insertions(+), 2 deletions(-) create mode 100644 Documentation/riscv/hwprobe.rst create mode 100644 arch/riscv/include/asm/hwprobe.h create mode 100644 arch/riscv/include/uapi/asm/hwprobe.h diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst new file mode 100644 index 000000000000..97771090e972 --- /dev/null +++ b/Documentation/riscv/hwprobe.rst @@ -0,0 +1,37 @@ +.. SPDX-License-Identifier: GPL-2.0 + +RISC-V Hardware Probing Interface +--------------------------------- + +The RISC-V hardware probing interface is based around a single syscall, which +is defined in :: + + struct riscv_hwprobe { + __s64 key; + __u64 value; + }; + + long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, + size_t cpu_count, cpu_set_t *cpus, + unsigned long flags); + +The arguments are split into three groups: an array of key-value pairs, a CPU +set, and some flags. The key-value pairs are supplied with a count. Userspace +must prepopulate the key field for each element, and the kernel will fill in the +value if the key is recognized. If a key is unknown to the kernel, its key +field will be cleared to -1, and its value set to 0. The CPU set is defined by +CPU_SET(3), the indicated features will be supported on all CPUs in the set. +Usermode can supply NULL for cpus and 0 for cpu_count as a shortcut for all +online CPUs. There are currently no flags, this value must be zero for future +compatibility. + +On success 0 is returned, on failure a negative error code is returned. + +The following keys are defined: + +* :RISCV_HWPROBE_KEY_MVENDORID:: Contains the value of :mvendorid:, as per the + ISA specifications. +* :RISCV_HWPROBE_KEY_MARCHID:: Contains the value of :marchid:, as per the ISA + specifications. +* :RISCV_HWPROBE_KEY_MIMPLID:: Contains the value of :mimplid:, as per the ISA + specifications. diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst index 2e5b18fbb145..175a91db0200 100644 --- a/Documentation/riscv/index.rst +++ b/Documentation/riscv/index.rst @@ -7,6 +7,7 @@ RISC-V architecture boot-image-header vm-layout + hwprobe patch-acceptance uabi diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h new file mode 100644 index 000000000000..08d1c3bdd78a --- /dev/null +++ b/arch/riscv/include/asm/hwprobe.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright 2022 Rivos, Inc + */ + +#ifndef _ASM_HWPROBE_H +#define _ASM_HWPROBE_H + +#include + +#define RISCV_HWPROBE_MAX_KEY 2 + +#endif diff --git a/arch/riscv/include/asm/syscall.h b/arch/riscv/include/asm/syscall.h index 384a63b86420..78a6302ef711 100644 --- a/arch/riscv/include/asm/syscall.h +++ b/arch/riscv/include/asm/syscall.h @@ -75,4 +75,7 @@ static inline int syscall_get_arch(struct task_struct *task) } asmlinkage long sys_riscv_flush_icache(uintptr_t, uintptr_t, uintptr_t); + +asmlinkage long sys_riscv_hwprobe(uintptr_t, uintptr_t, uintptr_t, uintptr_t, + uintptr_t, uintptr_t); #endif /* _ASM_RISCV_SYSCALL_H */ diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h new file mode 100644 index 000000000000..591802047460 --- /dev/null +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright 2022 Rivos, Inc + */ + +#ifndef _UAPI_ASM_HWPROBE_H +#define _UAPI_ASM_HWPROBE_H + +#include + +/* + * Interface for probing hardware capabilities from userspace, see + * Documentation/riscv/hwprobe.rst for more information. + */ +struct riscv_hwprobe { + __s64 key; + __u64 value; +}; + +#define RISCV_HWPROBE_KEY_MVENDORID 0 +#define RISCV_HWPROBE_KEY_MARCHID 1 +#define RISCV_HWPROBE_KEY_MIMPID 2 +/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ + +#endif diff --git a/arch/riscv/include/uapi/asm/unistd.h b/arch/riscv/include/uapi/asm/unistd.h index 73d7cdd2ec49..37d47302322a 100644 --- a/arch/riscv/include/uapi/asm/unistd.h +++ b/arch/riscv/include/uapi/asm/unistd.h @@ -43,3 +43,11 @@ #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) #endif __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) + +/* + * Allows userspace to probe + */ +#ifndef __NR_riscv_hwprobe +#define __NR_riscv_hwprobe (__NR_arch_specific_syscall + 14) +#endif +__SYSCALL(__NR_riscv_hwprobe, sys_riscv_hwprobe) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 684e5419d37d..d0fb3567cc3d 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -4,15 +4,16 @@ */ #include +#include #include #include #include #include #include #include +#include #include #include -#include /* * Returns the hart ID of the given device tree node, or -ENODEV if the node diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5d3f2fbeb33c..868a12384f5a 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -6,8 +6,11 @@ */ #include -#include #include +#include +#include +#include +#include #include static long riscv_sys_mmap(unsigned long addr, unsigned long len, @@ -69,3 +72,144 @@ SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end, return 0; } + +/* + * The hwprobe interface, for allowing userspace to probe to see which features + * are supported by the hardware. See Documentation/riscv/hwprobe.rst for more + * details. + */ +static int set_hwprobe(struct riscv_hwprobe __user *pair, u64 val) +{ + long ret; + + ret = put_user(val, &pair->value); + if (ret < 0) + return ret; + + return 0; +} + +static long hwprobe_mid(struct riscv_hwprobe __user *pair, size_t key, + cpumask_t *cpus) +{ + long cpu, id; + bool first, valid; + + first = true; + valid = false; + for_each_cpu(cpu, cpus) { + struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu); + long cpu_id; + + switch (key) { + case RISCV_HWPROBE_KEY_MVENDORID: + cpu_id = ci->mvendorid; + break; + case RISCV_HWPROBE_KEY_MIMPID: + cpu_id = ci->mimpid; + break; + case RISCV_HWPROBE_KEY_MARCHID: + cpu_id = ci->marchid; + break; + } + + if (first) { + id = cpu_id; + valid = true; + } + + if (id != cpu_id) + valid = false; + } + + /* + * put_user() returns 0 on success, so use 1 to indicate it wasn't + * called and we should skip having incremented the output. + */ + if (!valid) + return 1; + + return set_hwprobe(pair, id); +} + +static +long do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, long pair_count, + long cpu_count, unsigned long __user *cpus_user, + unsigned long flags) +{ + size_t out; + s64 key; + long ret; + struct cpumask cpus; + + /* Check the reserved flags. */ + if (flags != 0) + return -EINVAL; + + /* + * The only supported values must be the same on all CPUs. Allow + * userspace to specify NULL and 0 as a shortcut to all online CPUs. + */ + cpumask_clear(&cpus); + if ((cpu_count == 0) && (cpus_user == NULL)) { + cpumask_copy(&cpus, cpu_online_mask); + } else { + if (cpu_count > cpumask_size()) + cpu_count = cpumask_size(); + ret = copy_from_user(&cpus, cpus_user, cpu_count); + if (!ret) + return -EFAULT; + + /* + * Userspace must provide at least one online CPU, without that there's + * no way to define what is supported. + */ + cpumask_and(&cpus, &cpus, cpu_online_mask); + if (cpumask_empty(&cpus)) + return -EINVAL; + } + + for (out = 0; out < pair_count; out++, pairs++) { + long ret; + + if (get_user(key, &pairs->key)) + return -EFAULT; + + switch (key) { + case RISCV_HWPROBE_KEY_MVENDORID: + case RISCV_HWPROBE_KEY_MARCHID: + case RISCV_HWPROBE_KEY_MIMPID: + ret = hwprobe_mid(pairs, key, &cpus); + break; + + /* + * For forward compatibility, unknown keys don't fail the whole + * call, but get their element key set to -1 and value set to 0 + * indicating they're unrecognized. + */ + default: + ret = put_user(-1, &pairs->key); + if (ret < 0) + return ret; + + ret = set_hwprobe(pairs, 0); + if (ret) + return ret; + + break; + } + + if (ret < 0) + return ret; + } + + return 0; + +} + +SYSCALL_DEFINE5(riscv_hwprobe, uintptr_t, pairs, uintptr_t, pair_count, + uintptr_t, cpu_count, uintptr_t, cpus, uintptr_t, flags) +{ + return do_riscv_hwprobe((void __user *)pairs, pair_count, cpu_count, + (void __user *)cpus, flags); +} From patchwork Mon Feb 6 20:14:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 13130560 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07B15C636D4 for ; Mon, 6 Feb 2023 20:15:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TMNbdovJjSHHnyH54AXnBqiLdJlWq43/i5z+lMvcCIM=; b=R3d65Vfg3ZkCx4 EAAY+tWxti2KCRPKqW2al/vvWYcckag2STv3IwgdhhNlsNUDvHKD7NXI4SX509wiqLAhsR2TxtSXu XcDaKeET/HiB1wtSvnJiX8gtp+fE3OFocQv+RaDoUqZ/mASqoVR3ycnf0R+M/cV+cFntXSl4zCUgQ hHPerv+ir1iGywlQuboBKjcHSAsyY3HrCHG+DcmpcB+2qQfnMgJA63k2mpnoVu8j4sfnB1EhQyA9O seuMOONWQ/9FRc55DWC0g26TY63va28rVO74V7nOytaohiC46e2LkTU2FnfneYS8gFD8+lXDdROR3 uxgMbmAfwKSNTjBjUDyA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7to-009oc6-Oa; Mon, 06 Feb 2023 20:15:36 +0000 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7tj-009oZ2-2x for linux-riscv@lists.infradead.org; Mon, 06 Feb 2023 20:15:35 +0000 Received: by mail-pj1-x1031.google.com with SMTP id f15-20020a17090ac28f00b00230a32f0c9eso5016353pjt.4 for ; Mon, 06 Feb 2023 12:15:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xCdyPS+smT6LwtNTbkWdnYXrnr2lxZXi1KrwW5rv0l8=; b=0GLh6Tswh2lwBK4eGnHkxqiQk3/zCN33r0fpvbYVbwNsBkNBBokego85RwcWGnn4Xh qka1T0L4j34pN0ybqoxtKmCEaH9G2tnRhdKzSXuOZGuB1r9vg1+LJWENzePU5bBRzAnp nOs75uIRZxj+XkoGKHbGjfmRxgYVvTOWZhuSV+rXzn0tqVC2sK7jEnQksiHaDLJuwmtr Ht3st2UrTUf76v5NU7NUJFln2WcZ1iYaM8xMyeOtfiDtm1Mv4iWTwClcnUP5Pq+7F8a2 yZqpv5Wtp4pxAo942ELL0OyCEwv7RiLeO5INkrNY+2ZyVXemijkNbdQlQXWVZ9fXZpd2 Tzhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xCdyPS+smT6LwtNTbkWdnYXrnr2lxZXi1KrwW5rv0l8=; b=q0OA8f9Ry/bHmmDCO2OiUN3lj1LnG/Cljizv+p+jlNbFOI1+Ne47M1l9FF6+O1UjRs lPpxuaORpuZNKiYBkwbxBRhoaccPxD6xfkej9JlJ7SBpNAPk8Rx5JkHQ6PufTDdM+edS ZLnofYIrVcgPcA17zJexaNbAJWCTpAT766+wLIAmI1Af1rIFwYZuKLohVRMusYVX+Br4 k1ZMRcz8ZaiYmd9TjZjk0NG5gb+Ae528CfQO2PAKY8Dzb4lZFHXzqBJHSrPYs46h2wQa a2Jb5Tt4JgkytlhXDTy4p6qXNR3gxeeNjpKxUe+hoGUTKBIJlgpndRD1Y/ZME6QiJ5vT lehg== X-Gm-Message-State: AO0yUKVWgsh1Gr6X5vrvbhsDiy/rtMZVvRVIHEyLMdvx9rC1NqRvEKrH ZyZlqFDZXrhlcQ/pf53rjerfSg== X-Google-Smtp-Source: AK7set89OKaSr4/YDhhBWoGa5WugP9xjhQ2WRaIN6BchRUc3KvHdtr86clXbC4S8Q6fXuCF04qrlmA== X-Received: by 2002:a05:6a20:54a0:b0:bd:b061:9527 with SMTP id i32-20020a056a2054a000b000bdb0619527mr624694pzk.4.1675714530623; Mon, 06 Feb 2023 12:15:30 -0800 (PST) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id k10-20020a63ab4a000000b004df4fbb9823sm6425079pgp.68.2023.02.06.12.15.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 12:15:30 -0800 (PST) From: Evan Green To: Palmer Dabbelt Cc: Conor Dooley , vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com, Evan Green , Albert Ou , Andrew Bresticker , Celeste Liu , Guo Ren , Jonathan Corbet , Palmer Dabbelt , Paul Walmsley , dram , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 3/6] RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA Date: Mon, 6 Feb 2023 12:14:52 -0800 Message-Id: <20230206201455.1790329-4-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230206_121531_153507_C5CCFD08 X-CRM114-Status: GOOD ( 17.85 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Palmer Dabbelt We have an implicit set of base behaviors that userspace depends on, which are mostly defined in various ISA specifications. Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- (no changes since v1) Documentation/riscv/hwprobe.rst | 16 ++++++++++++++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 6 +++++- arch/riscv/kernel/sys_riscv.c | 23 +++++++++++++++++++++++ 4 files changed, 45 insertions(+), 2 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 97771090e972..ce186967861f 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -35,3 +35,19 @@ The following keys are defined: specifications. * :RISCV_HWPROBE_KEY_MIMPLID:: Contains the value of :mimplid:, as per the ISA specifications. +* :RISCV_HWPROBE_KEY_BASE_BEHAVIOR:: A bitmask containing the base user-visible + behavior that this kernel supports. The following base user ABIs are defined: + * :RISCV_HWPROBE_BASE_BEHAVIOR_IMA:: Support for rv32ima or rv64ima, as + defined by version 2.2 of the user ISA and version 1.10 of the privileged + ISA, with the following known exceptions (more exceptions may be added, + but only if it can be demonstrated that the user ABI is not broken): + * The :fence.i: instruction cannot be directly executed by userspace + programs (it may still be executed in userspace via a + kernel-controlled mechanism such as the vDSO). +* :RISCV_HWPROBE_KEY_IMA_EXT_0:: A bitmask containing the extensions that are + compatible with the :RISCV_HWPROBE_BASE_BEHAVIOR_IMA: base system behavior. + * :RISCV_HWPROBE_IMA_FD:: The F and D extensions are supported, as defined + by commit cd20cee ("FMIN/FMAX now implement minimumNumber/maximumNumber, + not minNum/maxNum") of the RISC-V ISA manual. + * :RISCV_HWPROBE_IMA_C:: The C extension is supported, as defined by + version 2.2 of the RISC-V ISA manual. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 08d1c3bdd78a..7e52f1e1fe10 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ #include -#define RISCV_HWPROBE_MAX_KEY 2 +#define RISCV_HWPROBE_MAX_KEY 4 #endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 591802047460..ce39d6e74103 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -20,6 +20,10 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_MVENDORID 0 #define RISCV_HWPROBE_KEY_MARCHID 1 #define RISCV_HWPROBE_KEY_MIMPID 2 +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ - #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 868a12384f5a..74e0d72c877d 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -182,6 +183,28 @@ long do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, long pair_count, ret = hwprobe_mid(pairs, key, &cpus); break; + /* + * The kernel already assumes that the base single-letter ISA + * extensions are supported on all harts, and only supports the + * IMA base, so just cheat a bit here and tell that to + * userspace. + */ + case RISCV_HWPROBE_KEY_BASE_BEHAVIOR: + ret = set_hwprobe(pairs, RISCV_HWPROBE_BASE_BEHAVIOR_IMA); + break; + + case RISCV_HWPROBE_KEY_IMA_EXT_0: + { + u64 val = 0; + + if (has_fpu()) + val |= RISCV_HWPROBE_IMA_FD; + if (elf_hwcap & RISCV_ISA_EXT_c) + val |= RISCV_HWPROBE_IMA_C; + ret = set_hwprobe(pairs, val); + } + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0 From patchwork Mon Feb 6 20:14:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 13130561 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4FA58C6379F for ; Mon, 6 Feb 2023 20:15:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RtbAUenT2S6F3L711SIsqulMS+oylwitFhpPVxqxuyE=; b=xlKVP0q+a8K+2g ryrVoCnj/MxWqzmL4Zaf22p/1gIGHVNuEXu3DyXpjpOkAQ9kDZKTE1AVI2YoJxAH2j81ooCWVg9Bo GkXvJ+3mOnYVPE3GLPYJ/arS2T8Tjf7Vdc6oYMhqpUa6R1K78ecFvtuPlCHLOSpepgviQ824bm5d6 fg6zs4Dg9NIA7hNek8iF0VAJYYlkAoTZ41j0kPz76yt/a4y9vI+n0l96oOeeWKJdTHKaAri9I/RoC 0A/SGuD6bSh0owPgrBlgAzxat+o8z2gNFEU1S6YJytl/l+i35aM9Ogw+shzHmL0Qf4+WFGwCPDcJz zLf937ouXsuBtZyjmdoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7tr-009ody-ES; Mon, 06 Feb 2023 20:15:39 +0000 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7tm-009oax-QV for linux-riscv@lists.infradead.org; Mon, 06 Feb 2023 20:15:36 +0000 Received: by mail-pj1-x1034.google.com with SMTP id ge21-20020a17090b0e1500b002308aac5b5eso6523257pjb.4 for ; Mon, 06 Feb 2023 12:15:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ggzc1GTHoLiBAu4kfMHEm/fbizYyfDbBZlVMBkPr/K4=; b=LJTUsmkjEjxAWc1IoFf2wxj/67dVsvTcPqb/jJBjxsyqYyVz3ScQAmEmLk7rLdnoH2 0G+w1w7rUgLxoJG6JGeK3oBnyoikVbeT2iqgsNILC3XuFyOKGDcmP6bbCSZGhfVOECgU 3sXnzYhBeGAERqormKcypgWG9XWhAAPUpOh4F6QyBmnObP3SI24BGHjffKmGOd2C6h6M nFlREjaXPwWSA4WBnjQF1PYXsDM8gl0fe+zFGdgbvHUSF0tQ9pj4/mXQRf2gDg9e6iTA ZA4SYFH9Hgm45V+ECqXetPqrjaeYznz677JdCHLdnP+AJ8p2xJmxcea26IMGvNKEjbXU 86dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ggzc1GTHoLiBAu4kfMHEm/fbizYyfDbBZlVMBkPr/K4=; b=q2ZaHmAdmBN0uFeDa6ltC1t6vf+FPJJqfj0VJZxJ2SzdoEs0Aak9CaCgSNSwW54IBc zpG/gwEw14P14gfZ9l2mCzfVsdYH9eiSJyhy3TPj+dV51kHbZbr3vZiU9frkkHzDiiuz jq+fD3qF9dPg8BbEpZX+YPuTRVTPbnDCz4byu72jM4CiUZOlIqjpqJIWNWOfj7Hd1mE9 FWAFNc5u+RuSnvrfFzuhtLvj+kq3XoPvltqpOnFix47wFBQ+kIwh2mb8nLexRYN5Mgul bekJf0zAzYjvPLkf7Gkg5Z4uTdPiCUxIri4lhu/1L/JB2Q9+3u2p5EgmM+yRIy7tK07s tYPw== X-Gm-Message-State: AO0yUKUA0lobgau+TWVSsNpWPknSCDOZnHIe3VgKk1ZAvM+wO9krzEX2 hgoOYc+tDgue6soAD9JTHAiZFA== X-Google-Smtp-Source: AK7set/bTb9lu1cNF6xPBp2fVUYIdNuGgf1zzRTNh18SIWd68l70lafUBIHe2ViUvh3qp2wqLmLP9w== X-Received: by 2002:a17:90a:54:b0:230:acb2:e3f0 with SMTP id 20-20020a17090a005400b00230acb2e3f0mr840256pjb.33.1675714534354; Mon, 06 Feb 2023 12:15:34 -0800 (PST) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id k10-20020a63ab4a000000b004df4fbb9823sm6425079pgp.68.2023.02.06.12.15.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 12:15:33 -0800 (PST) From: Evan Green To: Palmer Dabbelt Cc: Conor Dooley , vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com, Evan Green , Albert Ou , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 4/6] dt-bindings: Add RISC-V misaligned access performance Date: Mon, 6 Feb 2023 12:14:53 -0800 Message-Id: <20230206201455.1790329-5-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230206_121534_882488_2B54D0F8 X-CRM114-Status: UNSURE ( 9.67 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Palmer Dabbelt This key allows device trees to specify the performance of misaligned accesses to main memory regions from each CPU in the system. Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- (no changes since v1) Documentation/devicetree/bindings/riscv/cpus.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6720764e765..2c09bd6f2927 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -85,6 +85,21 @@ properties: $ref: "/schemas/types.yaml#/definitions/string" pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + riscv,misaligned-access-performance: + description: + Identifies the performance of misaligned memory accesses to main memory + regions. There are three flavors of unaligned access performance: "emulated" + means that misaligned accesses are emulated via software and thus + extremely slow, "slow" means that misaligned accesses are supported by + hardware but still slower that aligned accesses sequences, and "fast" + means that misaligned accesses are as fast or faster than the + cooresponding aligned accesses sequences. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - emulated + - slow + - fast + # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false From patchwork Mon Feb 6 20:14:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 13130562 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF478C636D3 for ; Mon, 6 Feb 2023 20:15:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GmQXyOvEKKBYtmDkqeHT4bM4+XU9HEGD9rrkHB29wH8=; b=rB1+6tdnASfG5d M6pJfLvhY+rudOoQNfKD32lBZMs0A5rjOrSpqJg7Lp7SLhqi79SPqRA/8VzSdFxYIp3P0tIhDPscB XdIfQuzBNnux1v19xQBysgGBvuuqIdxr66Z01druVPCFVp2jg6u8Z76wT2tmuLzQePJm0D7fSDqQG xhY/WQbX+JIBeJnjGVsXbvsvD02cB4waqPaitBLiLKDBICmTIBUdofTffcV2h/HDlBa4vdT8IIaEa SCG/RoQZmdwhH5sRWqFVFspaAVy79H0pK8yWUFyu3k70/P/FQIW+I03AmMeFyjbnieLJ+cuUwkXEv nj0Gih9AsaLpB2EfoEVw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7ty-009oj9-CT; Mon, 06 Feb 2023 20:15:46 +0000 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7ts-009odS-Bs for linux-riscv@lists.infradead.org; Mon, 06 Feb 2023 20:15:44 +0000 Received: by mail-pl1-x62b.google.com with SMTP id be8so13405358plb.7 for ; Mon, 06 Feb 2023 12:15:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4NHVkmDL1+Nl1bWyENrxaEG8nDhTyqPy5db4QyUwgAo=; b=e8e+hue89xD8AFuDM03gwXKPLXaajuv/b6VKDvoCoBf/iT/zGbXP5ooZz6ZYbxq6Ol pRMgq09e2uQzEmi3gW2ANefxMoKxdin+1LUdy2mn4NylyIUDGaTWDxyjf1oczOmGaopv ndd3dltEwWjxIEDp1GgserBBoHjJv3C9Pc6EWZJRz/RZNmqctSUvEAebndq63RXZ+k7V /m63PZ0vyxSC7rZCehQpF0Svw1z8LboRIPAztWTftiwt30MEirNTJr2AMxI+5Tj7uC5w Tl2CfBrbUBvVi8ZqW29uwBXyWdzGmZ0ZA5goqX/HCZIg74rzSCOVCE2WwS2IAOgVugOP uEVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4NHVkmDL1+Nl1bWyENrxaEG8nDhTyqPy5db4QyUwgAo=; b=kZSg+4bOPNg8ok0M+bsaccHS80JW2iYWJSQEAwlcgfnydUG5icvD/H0HrDByD4mzP4 PaJkADDw1/7LPvdR9LYxDkOkjzK9+pNk3L23ukFduXCrZeaGAFjl0F9YT4ReIWpco4Mo CPH+vXrpHE6qfu712FSVCZCRjE4f5w5jhTYZAvhwe2izKaOPk2fszigLvtIxCF3SWs9m xQzKEVzk0/8pC4kvVLNmpuGCqfT+6MFyMX94btGRrpGyNl2ZK641cfr7u1Z4INORbYf8 TQtPDuTUXnnGT6Wf2SoFYz0btoNMjkdf86xn7xmdDtXENKt90MUoRq1aF0lWYyJyJ4XS CIOw== X-Gm-Message-State: AO0yUKXzuDkaM2sioopuWnSRGRaq9hxRc+BxwGEEftCl5B/52V9bM3ZX YaGDltT2p6/x8qK0QEee8EJniQ== X-Google-Smtp-Source: AK7set+JVHNnFfvIUBCDQKktjW0TUQczLdFGPbSNh2d9L/P8+GzUJBG4uu0TKecEvC/h+y8Fy8TFlQ== X-Received: by 2002:a17:90b:3ecc:b0:22b:fff0:f80c with SMTP id rm12-20020a17090b3ecc00b0022bfff0f80cmr1033780pjb.1.1675714538280; Mon, 06 Feb 2023 12:15:38 -0800 (PST) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id k10-20020a63ab4a000000b004df4fbb9823sm6425079pgp.68.2023.02.06.12.15.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 12:15:37 -0800 (PST) From: Evan Green To: Palmer Dabbelt Subject: [PATCH v2 5/6] RISC-V: hwprobe: Support probing of misaligned access performance Date: Mon, 6 Feb 2023 12:14:54 -0800 Message-Id: <20230206201455.1790329-6-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230206_121540_441425_BE4A2012 X-CRM114-Status: GOOD ( 19.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: heiko@sntech.de, Jisheng Zhang , linux-doc@vger.kernel.org, Andrew Bresticker , Atish Patra , Celeste Liu , slewis@rivosinc.com, linux-riscv@lists.infradead.org, Jonathan Corbet , Xianting Tian , Tsukasa OI , Andrew Jones , Albert Ou , Arnd Bergmann , vineetg@rivosinc.com, Paul Walmsley , Anup Patel , linux-kernel@vger.kernel.org, Conor Dooley , Evan Green , Palmer Dabbelt , Heinrich Schuchardt , Guo Ren Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This allows userspace to select various routines to use based on the performance of misaligned access on the target hardware. Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- Changes in v2: - Fixed logic error in if(of_property_read_string...) that caused crash - Include cpufeature.h in cpufeature.h to avoid undeclared variable warning. - Added a _MASK define - Fix random checkpatch complaints Documentation/riscv/hwprobe.rst | 13 +++++++++++ arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/asm/smp.h | 9 ++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 6 ++++++ arch/riscv/kernel/cpufeature.c | 31 +++++++++++++++++++++++++-- arch/riscv/kernel/sys_riscv.c | 23 ++++++++++++++++++++ 7 files changed, 83 insertions(+), 3 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index ce186967861f..0dc75e83e127 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -51,3 +51,16 @@ The following keys are defined: not minNum/maxNum") of the RISC-V ISA manual. * :RISCV_HWPROBE_IMA_C:: The C extension is supported, as defined by version 2.2 of the RISC-V ISA manual. +* :RISCV_HWPROBE_KEY_PERF_0:: A bitmask that contains performance information + about the selected set of processors. + * :RISCV_HWPROBE_MISALIGNED_UNKNOWN:: The performance of misaligned + accesses is unknown. + * :RISCV_HWPROBE_MISALIGNED_EMULATED:: Misaligned accesses are emulated via + software, either in or below the kernel. These accesses are always + extremely slow. + * :RISCV_HWPROBE_MISALIGNED_SLOW:: Misaligned accesses are supported in + hardware, but are slower than the cooresponding aligned accesses + sequences. + * :RISCV_HWPROBE_MISALIGNED_FAST:: Misaligned accesses are supported in + hardware and are faster than the cooresponding aligned accesses + sequences. diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 66c251d98290..ac51a9e6387a 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -18,4 +18,6 @@ struct riscv_cpuinfo { DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); +DECLARE_PER_CPU(long, misaligned_access_speed); + #endif diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 7e52f1e1fe10..4e45e33015bc 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ #include -#define RISCV_HWPROBE_MAX_KEY 4 +#define RISCV_HWPROBE_MAX_KEY 5 #endif diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 3831b638ecab..6c1759091e44 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -26,6 +26,15 @@ struct riscv_ipi_ops { */ extern unsigned long __cpuid_to_hartid_map[NR_CPUS]; #define cpuid_to_hartid_map(cpu) __cpuid_to_hartid_map[cpu] +static inline long hartid_to_cpuid_map(unsigned long hartid) +{ + long i; + + for (i = 0; i < NR_CPUS; ++i) + if (cpuid_to_hartid_map(i) == hartid) + return i; + return -1; +} /* print IPI stats */ void show_ipi_stats(struct seq_file *p, int prec); diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index ce39d6e74103..5d55e2da2b1f 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -25,5 +25,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_KEY_CPUPERF_0 5 +#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) +#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) +#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) +#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) +#define RISCV_HWPROBE_MISALIGNED_MASK (3 << 0) /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 93e45560af30..12af6f7a2f53 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -14,8 +14,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -32,6 +34,9 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); EXPORT_SYMBOL(riscv_isa_ext_keys); +/* Performance information */ +DEFINE_PER_CPU(long, misaligned_access_speed); + /** * riscv_isa_extension_base() - Get base extension word * @@ -89,11 +94,11 @@ static bool riscv_isa_extension_check(int id) void __init riscv_fill_hwcap(void) { struct device_node *node; - const char *isa; + const char *isa, *misaligned; char print_str[NUM_ALPHA_EXTS + 1]; int i, j, rc; unsigned long isa2hwcap[26] = {0}; - unsigned long hartid; + unsigned long hartid, cpu; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; @@ -246,6 +251,28 @@ void __init riscv_fill_hwcap(void) bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); else bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + + /* + * Check for the performance of misaligned accesses. + */ + cpu = hartid_to_cpuid_map(hartid); + if (cpu < 0) + continue; + + if (!of_property_read_string(node, "riscv,misaligned-access-performance", + &misaligned)) { + if (strcmp(misaligned, "emulated") == 0) + per_cpu(misaligned_access_speed, cpu) = + RISCV_HWPROBE_MISALIGNED_EMULATED; + + if (strcmp(misaligned, "slow") == 0) + per_cpu(misaligned_access_speed, cpu) = + RISCV_HWPROBE_MISALIGNED_SLOW; + + if (strcmp(misaligned, "fast") == 0) + per_cpu(misaligned_access_speed, cpu) = + RISCV_HWPROBE_MISALIGNED_FAST; + } } /* We don't support systems with F but without D, so mask those out diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 74e0d72c877d..73d937c54f4e 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -133,6 +133,25 @@ static long hwprobe_mid(struct riscv_hwprobe __user *pair, size_t key, return set_hwprobe(pair, id); } +static long hwprobe_misaligned(cpumask_t *cpus) +{ + long cpu, perf = -1; + + for_each_cpu(cpu, cpus) { + long this_perf = per_cpu(misaligned_access_speed, cpu); + + if (perf == -1) + perf = this_perf; + + if (perf != this_perf) + perf = RISCV_HWPROBE_MISALIGNED_UNKNOWN; + } + + if (perf == -1) + return RISCV_HWPROBE_MISALIGNED_UNKNOWN; + return perf; +} + static long do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, long pair_count, long cpu_count, unsigned long __user *cpus_user, @@ -205,6 +224,10 @@ long do_riscv_hwprobe(struct riscv_hwprobe __user *pairs, long pair_count, } break; + case RISCV_HWPROBE_KEY_CPUPERF_0: + ret = set_hwprobe(pairs, hwprobe_misaligned(&cpus)); + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0 From patchwork Mon Feb 6 20:14:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Evan Green X-Patchwork-Id: 13130563 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B330C05027 for ; Mon, 6 Feb 2023 20:15:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+rEzyQdU0tT4kxAywMUkipXkwr+Z2zuEzuMh9R/AgLI=; b=Cz1DxWQe5qzgSw FNvADe7nTVmVsAOR1X3gFB11KI9id4I1q89tmaM5QPrcIucaamnioh8y2TupEeB4mHeIr2lRbBOSK VKz/cbHHCIJV2UrqehYdisDJtWo4gVquCN8y6TyNlXk+vj8Q5UrLZlo0gnq64xcxQtqG+Z9H35l9n 41mppiTxFnOkM7AcmHAq3SY++wA7eau6GAPUlqoMtETz7OJ0EHJxvEwd8bMjV0+QalQx3mGuigunz n2O4lMPzp6H4D8kxuFg3LWzckWW7vb52KTwLXfyGrl1NCJSid3nKAEGNXrbA5t/z85oYqRMX66e+e ZoibJB0HpA/X+JJYBTyQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7u0-009okM-1v; Mon, 06 Feb 2023 20:15:48 +0000 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pP7tv-009ofx-GV for linux-riscv@lists.infradead.org; Mon, 06 Feb 2023 20:15:46 +0000 Received: by mail-pj1-x102b.google.com with SMTP id on9-20020a17090b1d0900b002300a96b358so12547838pjb.1 for ; Mon, 06 Feb 2023 12:15:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5QMxDhZ75IYuxFalbrxLxVMgMvXcbdvnhnkaLqUhc+4=; b=h/K1xPkYuAladagqvnqdEObwLc3I++hRM7ygnQ2FWJr4dQ+NkKfwjCYv4AZW0J/fwi LQISa+kgp1HPMijrVjeord7FE0i5YBU63rWz5ruKW+VR6fz0mKm4sPzzDQ3b7sHqAJqu 5s5FHCgSboqFOPi6+2mRfBVjb6ruhIRiLlcmgbtSOBcG3ugdpGU4nLDiyh5rS6NQjWtG kQKYfhoKgsFC1y4IuUgzY6yhKDZrzXd+Cd50qfizClaXRGR75Ot0gyTLgmirP0lhYesJ 0ufnay2uR7KlqVSrC2Gw4rTerieNxMHekKe2rLvJWZHLTB4m0NJU5BYtvJ2l9lgJ2Nsf 6lpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5QMxDhZ75IYuxFalbrxLxVMgMvXcbdvnhnkaLqUhc+4=; b=BGVAYrmeBEewGGMHXOi6Il2kVIlwCoQNjwZzcrfX5HVvmYTKQHeS1yYVuxL5gFxMP2 zCUtZ1ltPaqqijBvs5IXPneb9rhiUjs12Cpgej+vWoPNxLVSf7q7ZMM6fwPzG5P5bebm spdg7JBfOPdRKYQ6jt1xYDkD9flAyFiNbBIebIIt01n/zuX6OvYKR8cz2neGjKwSqcTl W/EEDcetrqlKKBrnRbZ06CPUCIpxSmOfsnNGGf0W++uLqqqeVF+HWC7PHI5SM1Tonob1 UrnfApOC+zv8WYZrkts9fh2DnViAlbEPv99J+tHChy2kB148C7zDgzsuh/Ikbla+Z9cQ y1vw== X-Gm-Message-State: AO0yUKWM5KDxz2u4AK9GXwTL/f8VpGnRWxXCG1RaRX/pOmEIY0a/bd49 kQlQf65wCjligM4uJL3Bvlkq1g== X-Google-Smtp-Source: AK7set85zbKwtw5aODIZ5cYO4p8jjvMu57n9mPKmID0sKGJht50D5yMZ8ibBp4s5msYzjPdKfqyc8A== X-Received: by 2002:a05:6a20:e688:b0:bc:92cd:1536 with SMTP id mz8-20020a056a20e68800b000bc92cd1536mr259465pzb.61.1675714541445; Mon, 06 Feb 2023 12:15:41 -0800 (PST) Received: from evan.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id k10-20020a63ab4a000000b004df4fbb9823sm6425079pgp.68.2023.02.06.12.15.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 12:15:41 -0800 (PST) From: Evan Green To: Palmer Dabbelt Cc: Conor Dooley , vineetg@rivosinc.com, heiko@sntech.de, slewis@rivosinc.com, Evan Green , Albert Ou , Catalin Marinas , Mark Brown , Palmer Dabbelt , Paul Walmsley , Shuah Khan , linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 6/6] selftests: Test the new RISC-V hwprobe interface Date: Mon, 6 Feb 2023 12:14:55 -0800 Message-Id: <20230206201455.1790329-7-evan@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230206201455.1790329-1-evan@rivosinc.com> References: <20230206201455.1790329-1-evan@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230206_121543_575527_77C739D2 X-CRM114-Status: GOOD ( 27.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This adds a test for the recently added RISC-V interface for probing hardware capabilities. It happens to be the first selftest we have for RISC-V, so I've added some infrastructure for those as well. The build stuff looks pretty straight-forward, but there's also a tiny C library to avoid coupling this to any userspace implementation. Co-developed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt Signed-off-by: Evan Green --- Changes in v2: - Updated the selftests to the new API and added some more. - Fixed indentation, comments in .S, and general checkpatch complaints. --- tools/testing/selftests/Makefile | 1 + tools/testing/selftests/riscv/Makefile | 58 ++++++++++++ .../testing/selftests/riscv/hwprobe/Makefile | 10 +++ .../testing/selftests/riscv/hwprobe/hwprobe.c | 89 +++++++++++++++++++ .../selftests/riscv/hwprobe/sys_hwprobe.S | 12 +++ tools/testing/selftests/riscv/libc.S | 46 ++++++++++ 6 files changed, 216 insertions(+) create mode 100644 tools/testing/selftests/riscv/Makefile create mode 100644 tools/testing/selftests/riscv/hwprobe/Makefile create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.c create mode 100644 tools/testing/selftests/riscv/hwprobe/sys_hwprobe.S create mode 100644 tools/testing/selftests/riscv/libc.S diff --git a/tools/testing/selftests/Makefile b/tools/testing/selftests/Makefile index 41b649452560..a599ef726310 100644 --- a/tools/testing/selftests/Makefile +++ b/tools/testing/selftests/Makefile @@ -62,6 +62,7 @@ TARGETS += pstore TARGETS += ptrace TARGETS += openat2 TARGETS += resctrl +TARGETS += riscv TARGETS += rlimits TARGETS += rseq TARGETS += rtc diff --git a/tools/testing/selftests/riscv/Makefile b/tools/testing/selftests/riscv/Makefile new file mode 100644 index 000000000000..32a72902d045 --- /dev/null +++ b/tools/testing/selftests/riscv/Makefile @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +# Originally tools/testing/arm64/Makefile + +# When ARCH not overridden for crosscompiling, lookup machine +ARCH ?= $(shell uname -m 2>/dev/null || echo not) + +ifneq (,$(filter $(ARCH),riscv)) +RISCV_SUBTARGETS ?= hwprobe +else +RISCV_SUBTARGETS := +endif + +CFLAGS := -Wall -O2 -g + +# A proper top_srcdir is needed by KSFT(lib.mk) +top_srcdir = $(realpath ../../../../) + +# Additional include paths needed by kselftest.h and local headers +CFLAGS += -I$(top_srcdir)/tools/testing/selftests/ + +CFLAGS += $(KHDR_INCLUDES) + +export CFLAGS +export top_srcdir + +all: + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=$(OUTPUT)/$$DIR; \ + mkdir -p $$BUILD_TARGET; \ + $(MAKE) OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ + done + +install: all + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ + done + +run_tests: all + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ + done + +# Avoid any output on non riscv on emit_tests +emit_tests: all + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ + done + +clean: + @for DIR in $(RISCV_SUBTARGETS); do \ + BUILD_TARGET=$(OUTPUT)/$$DIR; \ + $(MAKE) OUTPUT=$$BUILD_TARGET -C $$DIR $@; \ + done + +.PHONY: all clean install run_tests emit_tests diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile b/tools/testing/selftests/riscv/hwprobe/Makefile new file mode 100644 index 000000000000..614501584803 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2021 ARM Limited +# Originally tools/testing/arm64/abi/Makefile + +TEST_GEN_PROGS := hwprobe + +include ../../lib.mk + +$(OUTPUT)/hwprobe: hwprobe.c ../libc.S sys_hwprobe.S + $(CC) -o$@ $(CFLAGS) $(LDFLAGS) -nostdlib $^ diff --git a/tools/testing/selftests/riscv/hwprobe/hwprobe.c b/tools/testing/selftests/riscv/hwprobe/hwprobe.c new file mode 100644 index 000000000000..ddfb61de2938 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/hwprobe.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include + +/* + * Rather than relying on having a new enough libc to define this, just do it + * ourselves. This way we don't need to be coupled to a new-enough libc to + * contain the call. + */ +long riscv_hwprobe(struct riscv_hwprobe *pairs, long pair_count, + long cpu_count, unsigned long *cpus, unsigned long flags); + +int main(int argc, char **argv) +{ + struct riscv_hwprobe pairs[8]; + unsigned long cpus; + long out; + + /* Fake the CPU_SET ops. */ + cpus = -1; + + /* + * Just run a basic test: pass enough pairs to get up to the base + * behavior, and then check to make sure it's sane. + */ + for (long i = 0; i < 8; i++) + pairs[i].key = i; + out = riscv_hwprobe(pairs, 8, 1, &cpus, 0); + if (out != 0) + return -1; + for (long i = 0; i < 4; ++i) { + /* Fail if the kernel claims not to recognize a base key. */ + if ((i < 4) && (pairs[i].key != i)) + return -2; + + if (pairs[i].key != RISCV_HWPROBE_KEY_BASE_BEHAVIOR) + continue; + + if (pairs[i].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA) + continue; + + return -3; + } + + /* + * This should also work with a NULL CPU set, but should not work + * with an improperly supplied CPU set. + */ + out = riscv_hwprobe(pairs, 8, 0, 0, 0); + if (out != 0) + return -4; + + out = riscv_hwprobe(pairs, 8, 0, &cpus, 0); + if (out == 0) + return -5; + + out = riscv_hwprobe(pairs, 8, 1, 0, 0); + if (out == 0) + return -6; + + /* + * Check that keys work by providing one that we know exists, and + * checking to make sure the resultig pair is what we asked for. + */ + pairs[0].key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR; + out = riscv_hwprobe(pairs, 1, 1, &cpus, 0); + if (out != 0) + return -7; + if (pairs[0].key != RISCV_HWPROBE_KEY_BASE_BEHAVIOR) + return -8; + + /* + * Check that an unknown key gets overwritten with -1, + * but doesn't block elements after it. + */ + pairs[0].key = 0x5555; + pairs[1].key = 1; + pairs[1].value = 0xAAAA; + out = riscv_hwprobe(pairs, 2, 0, 0, 0); + if (out != 0) + return -9; + + if (pairs[0].key != -1) + return -10; + + if ((pairs[1].key != 1) || (pairs[1].value == 0xAAAA)) + return -11; + + return 0; +} diff --git a/tools/testing/selftests/riscv/hwprobe/sys_hwprobe.S b/tools/testing/selftests/riscv/hwprobe/sys_hwprobe.S new file mode 100644 index 000000000000..ed8d28863b27 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/sys_hwprobe.S @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2022 Rivos, Inc */ + +.text +.global riscv_hwprobe +riscv_hwprobe: + # Put __NR_riscv_hwprobe in the syscall number register, then just shim + # back the kernel's return. This doesn't do any sort of errno + # handling, the caller can deal with it. + li a7, 258 + ecall + ret diff --git a/tools/testing/selftests/riscv/libc.S b/tools/testing/selftests/riscv/libc.S new file mode 100644 index 000000000000..1041bbea9b6b --- /dev/null +++ b/tools/testing/selftests/riscv/libc.S @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2022 Rivos, Inc */ +/* A C library */ + +#if __riscv_xlen == 64 +# define REG_S sd +#else +# define REG_S sw +#endif + +.text +.global _start +_start: +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + la sp, stack + + la t0, heap + la t1, brk + REG_S t0, 0(t1) + + li a0, 0 + li a1, 0 + + call main + + li a7, 93 + ecall + +1: + j 1b + +.data +brk: + .long 0 + +.global heap +heap: +.rep 65536 +.byte 0 +.endr +.global stack +stack: