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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v3 1/9] xen/ns16550: Remove unneeded truncation check in the DT init code Date: Wed, 8 Feb 2023 12:05:21 +0000 Message-ID: <20230208120529.22313-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208120529.22313-1-ayan.kumar.halder@amd.com> References: <20230208120529.22313-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT084:EE_|DM8PR12MB5448:EE_ X-MS-Office365-Filtering-Correlation-Id: bae3aa70-476c-4ad6-afde-08db09ccd5e2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eI9tbLPm9f+EnhW+YS1sZ+F/5hto17sTKLboransAphD69Kc6hjvwhzhoJKWseDrZgJ5bTTn/G0ubLLbWnfc/Q6C4TTTOOkTTeaejcFmgW6k4hQoVpLmwZeUiTDqLVzuImIIV1L6FI7zHyW2uLxlGCl5PamcVSXt1gE/8RrZHq0+/y7A4Mj/g9cfZaboPSCjqy6JlE420mdGfTQBjsYtUqqPDc/olTb3dGBIKyXjFmfGT27hTV8Dl4pVnK8ZHItfA6YjmD6VUiFo6ffGIiJzYlRVZK7pXeaqakxDq43x3YteZNe8Cf5eGn/Q5Qlvayk5bxIVau5oc27CwOfhYjG9bGwVU0mZpKi6uhIfaQXgO2Glqhg1RiHUblY3zN20EGN5GTW0CmYi60qj9As4XcRnKlOTpMsbzH/UZIdWzgZZQmTQVxZadK2TDjDcUMW9u5b+t+gUwq1KWbgIJmM3FCVnFeNYQBYWpaABAf4kEDH3m8mU7BJvYX03UtTPxH0yLnL1adiQJWWyxw37wnmk2sFR/uuenzQcQjtKm7MuWMEyMfQrdLHWN+QTzR2bgqjognFEd5KUrBjcAOCHhUf6xxmw+bNj/I1kgsigqosKJDxPCi3yUvPIsRlRylbzc/CK4aRln3BA9PW/8Mi4sSUPQqlugI1PxaHn3IT88WpoutSGRf4SMdkGWmU6GTKq9+2oquLqknbgFrAP13Q4JWalOuBoP5HhUB6GlnN+5+4sj4A6heY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(376002)(346002)(396003)(136003)(39860400002)(451199018)(36840700001)(40470700004)(46966006)(356005)(81166007)(40480700001)(1076003)(36756003)(86362001)(6666004)(478600001)(40460700003)(82310400005)(47076005)(36860700001)(26005)(186003)(2616005)(82740400003)(426003)(83380400001)(336012)(8936002)(41300700001)(8676002)(316002)(5660300002)(54906003)(7416002)(70206006)(70586007)(2906002)(103116003)(4326008)(6916009)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 12:05:56.7876 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bae3aa70-476c-4ad6-afde-08db09ccd5e2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT084.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5448 In an earlier commit (7c1de0038895), "ns16550.io_size" was u32 and "io_size" was u64. Thus, the ASSERT() was needed to check if the values are the same. However, in a later commit (c9f8e0aee507), "ns16550.io_size" was changed to u64. Thus, the ASSERT() became redundant. So, now as "io_size" and "uart->io_size" are both u64, there will be no truncation. Thus, one can remove the ASSERT() and extra assignment. Signed-off-by: Ayan Kumar Halder Reviewed-by: Jan Beulich Acked-by: Julien Grall --- Changes from : v1 - 1. Updated commit message/title. 2. Added Rb. v2 - No change. xen/drivers/char/ns16550.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 4ce74b3cd3..092f6b9c4b 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1747,7 +1747,6 @@ static int __init ns16550_uart_dt_init(struct dt_device_node *dev, struct ns16550 *uart; int res; u32 reg_shift, reg_width; - u64 io_size; uart = &ns16550_com[0]; @@ -1758,14 +1757,10 @@ static int __init ns16550_uart_dt_init(struct dt_device_node *dev, uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &uart->io_base, &io_size); + res = dt_device_get_address(dev, 0, &uart->io_base, &uart->io_size); if ( res ) return res; - uart->io_size = io_size; - - ASSERT(uart->io_size == io_size); /* Detect truncation */ - res = dt_property_read_u32(dev, "reg-shift", ®_shift); if ( !res ) uart->reg_shift = 0; From patchwork Wed Feb 8 12:05:22 2023 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v3 2/9] xen/arm: Typecast the DT values into paddr_t Date: Wed, 8 Feb 2023 12:05:22 +0000 Message-ID: <20230208120529.22313-3-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208120529.22313-1-ayan.kumar.halder@amd.com> References: <20230208120529.22313-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT034:EE_|BL3PR12MB6570:EE_ X-MS-Office365-Filtering-Correlation-Id: f3d5b161-4b80-4449-1244-08db09ccd761 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cK1l4WaKlaywofelyy6RJ+RTF3I9JRpKsgTFq2V8usSL6xJ0+XxIurE0thc/D1Beq8MFPh60GeW89rlbozKwr5aqc994tPXG0TqOTaVP73OPMbp/j2le8hbPcBqhTdDJxV9625vUsmod4K+1g1+P1lS/0FbZxRIw/k4IvrgoMwBaahSy9sTTJmhmUm4df2SPxSEtDTs80+xe7MYZzQKOPQ9DM8s6Xq+WVDrCJd2/EQ+E3W0QWP1QNwlH+VhahcPZWkNPfB53iHPx3AVSy7hVvbta/D/AZNt+f3ETl4wUsaIuhQC9dPkPNCfVshv0/ddBbmwt00WyE9fnIXvAJWudUlscxX4ie4rU9Ozl8XkIf5D6NafbEXEahwjneGzW5xlhngaLEVVhDzmC6YBPG3JdzzAw3MzNuLhfB/ptbbrFJZwvs9EjdRzCEjbRtbag6CjhMg2hC5MgP0r27MutLaApMEkAnYiotX2T87HL2ah8lSazcJrBW1p4R1CJ61OZXKkmZmJniHyBm4suzQfkkJoIvJla8QkeQAL7hexdfuKY38ye35Ys/091wvuIKBBb0ne4EHsxpeF586VIr9+73JxzmrpdvpILaYroewpPECc1UtjAfg41bTlrUq3h2LpIGbjIcRlDYbNPZTjeRrMc5sP//asJbZ25C4a2cAgx+CUf9mGYWAVQBucANqdMGgT9SeOqnCXQmmti06mGoprMYaPAoxixSozEtde/J45Yuhp62R4= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(396003)(376002)(136003)(346002)(451199018)(36840700001)(40470700004)(46966006)(5660300002)(47076005)(30864003)(36756003)(7416002)(2906002)(426003)(81166007)(83380400001)(1076003)(40480700001)(2616005)(336012)(356005)(82740400003)(8676002)(36860700001)(4326008)(70206006)(70586007)(54906003)(6916009)(316002)(8936002)(103116003)(41300700001)(6666004)(186003)(82310400005)(26005)(40460700003)(478600001)(86362001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 12:05:59.4186 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f3d5b161-4b80-4449-1244-08db09ccd761 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6570 In future, we wish to support 32 bit physical address. However, the current dt and fdt functions can only read u64 values. We wish to make the DT functions read u64 as well u32 values (depending on the width of physical address). Also, we wish to detect if any truncation has occurred (ie while reading u32 physical addresses from u64 values read from DT). device_tree_get_reg() should now be able to return paddr_t. This is invoked by various callers to get DT address and size. For fdt_get_mem_rsv(), we have introduced wrapper ie fdt_get_mem_rsv_paddr() while will invoke fdt_get_mem_rsv() and translate u64 to paddr_t. The reason being we cannot modify fdt_get_mem_rsv() as it has been imported from external source. For dt_read_number(), we have also introduced a wrapper ie dt_read_paddr() to read physical addresses. We chose not to modify the original function as it been used in places where it needs to specifically u64 values from dt (For eg dt_property_read_u64()). Xen prints an error when it detects a truncation (during typecast between u64 and paddr_t). It is not possible to return an error in all scenarios. So, it is user's responsibility to check the error logs. To detect truncation, we right shift physical address by "PADDR_BITS - 1" and then if the resulting number is greater than 1, we know that truncation has occurred and an appropriate error log is printed. Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. Dropped "[XEN v1 2/9] xen/arm: Define translate_dt_address_size() for the translation between u64 and paddr_t" and "[XEN v1 4/9] xen/arm: Use translate_dt_address_size() to translate between device tree addr/size and paddr_t", instead this approach achieves the same purpose. 2. No need to check for truncation while converting values from u64 to paddr_t. v2 - 1. Use "( (dt_start >> (PADDR_SHIFT - 1)) > 1 )" to detect truncation. 2. Introduced libfdt_xen.h to implement fdt_get_mem_rsv_paddr 3. Logged error messages in case truncation is detected. xen/arch/arm/bootfdt.c | 38 ++++++++++++++++----- xen/arch/arm/domain_build.c | 2 +- xen/arch/arm/include/asm/setup.h | 2 +- xen/arch/arm/setup.c | 14 ++++---- xen/arch/arm/smpboot.c | 2 +- xen/include/xen/device_tree.h | 21 ++++++++++++ xen/include/xen/libfdt/libfdt_xen.h | 52 +++++++++++++++++++++++++++++ xen/include/xen/types.h | 2 ++ 8 files changed, 115 insertions(+), 18 deletions(-) create mode 100644 xen/include/xen/libfdt/libfdt_xen.h diff --git a/xen/arch/arm/bootfdt.c b/xen/arch/arm/bootfdt.c index 0085c28d74..f63da3e831 100644 --- a/xen/arch/arm/bootfdt.c +++ b/xen/arch/arm/bootfdt.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include @@ -53,10 +53,30 @@ static bool __init device_tree_node_compatible(const void *fdt, int node, } void __init device_tree_get_reg(const __be32 **cell, u32 address_cells, - u32 size_cells, u64 *start, u64 *size) + u32 size_cells, paddr_t *start, paddr_t *size) { - *start = dt_next_cell(address_cells, cell); - *size = dt_next_cell(size_cells, cell); + u64 dt_start, dt_size; + + /* + * dt_next_cell will return u64 whereas paddr_t may be u64 or u32. Thus, + * there is an implicit cast from u64 to paddr_t. + */ + dt_start = dt_next_cell(address_cells, cell); + dt_size = dt_next_cell(size_cells, cell); + + if ( (dt_start >> (PADDR_SHIFT - 1)) > 1 ) + printk("Error: Physical address greater than max width supported\n"); + + if ( (dt_size >> (PADDR_SHIFT - 1)) > 1 ) + printk("Error: Physical size greater than max width supported\n"); + + /* + * Note: It is user's responsibility to check for the error messages. + * Xen will sliently truncate in case if the address/size is greater than + * the max supported width. + */ + *start = dt_start; + *size = dt_size; } static int __init device_tree_get_meminfo(const void *fdt, int node, @@ -326,7 +346,7 @@ static int __init process_chosen_node(const void *fdt, int node, printk("linux,initrd-start property has invalid length %d\n", len); return -EINVAL; } - start = dt_read_number((void *)&prop->data, dt_size_to_cells(len)); + start = dt_read_paddr((void *)&prop->data, dt_size_to_cells(len)); prop = fdt_get_property(fdt, node, "linux,initrd-end", &len); if ( !prop ) @@ -339,7 +359,7 @@ static int __init process_chosen_node(const void *fdt, int node, printk("linux,initrd-end property has invalid length %d\n", len); return -EINVAL; } - end = dt_read_number((void *)&prop->data, dt_size_to_cells(len)); + end = dt_read_paddr((void *)&prop->data, dt_size_to_cells(len)); if ( start >= end ) { @@ -594,9 +614,11 @@ static void __init early_print_info(void) for ( i = 0; i < nr_rsvd; i++ ) { paddr_t s, e; - if ( fdt_get_mem_rsv(device_tree_flattened, i, &s, &e) < 0 ) + + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, i, &s, &e) < 0 ) continue; - /* fdt_get_mem_rsv returns length */ + + /* fdt_get_mem_rsv_paddr returns length */ e += s; printk(" RESVD[%u]: %"PRIpaddr" - %"PRIpaddr"\n", i, s, e); } diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index a798e0b256..4d7e67560f 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -949,7 +949,7 @@ static int __init process_shm(struct domain *d, struct kernel_info *kinfo, BUG_ON(!prop); cells = (const __be32 *)prop->value; device_tree_get_reg(&cells, addr_cells, addr_cells, &pbase, &gbase); - psize = dt_read_number(cells, size_cells); + psize = dt_read_paddr(cells, size_cells); if ( !IS_ALIGNED(pbase, PAGE_SIZE) || !IS_ALIGNED(gbase, PAGE_SIZE) ) { printk("%pd: physical address 0x%"PRIpaddr", or guest address 0x%"PRIpaddr" is not suitably aligned.\n", diff --git a/xen/arch/arm/include/asm/setup.h b/xen/arch/arm/include/asm/setup.h index a926f30a2b..6105e5cae3 100644 --- a/xen/arch/arm/include/asm/setup.h +++ b/xen/arch/arm/include/asm/setup.h @@ -158,7 +158,7 @@ extern uint32_t hyp_traps_vector[]; void init_traps(void); void device_tree_get_reg(const __be32 **cell, u32 address_cells, - u32 size_cells, u64 *start, u64 *size); + u32 size_cells, paddr_t *start, paddr_t *size); u32 device_tree_get_u32(const void *fdt, int node, const char *prop_name, u32 dflt); diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 1f26f67b90..5ade20e6e7 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include @@ -222,11 +222,11 @@ static void __init dt_unreserved_regions(paddr_t s, paddr_t e, { paddr_t r_s, r_e; - if ( fdt_get_mem_rsv(device_tree_flattened, i, &r_s, &r_e ) < 0 ) + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, i, &r_s, &r_e ) < 0 ) /* If we can't read it, pretend it doesn't exist... */ continue; - r_e += r_s; /* fdt_get_mem_rsv returns length */ + r_e += r_s; /* fdt_get_mem_rsv_paddr returns length */ if ( s < r_e && r_s < e ) { @@ -502,13 +502,13 @@ static paddr_t __init consider_modules(paddr_t s, paddr_t e, { paddr_t mod_s, mod_e; - if ( fdt_get_mem_rsv(device_tree_flattened, - i - mi->nr_mods, - &mod_s, &mod_e ) < 0 ) + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, + i - mi->nr_mods, + &mod_s, &mod_e ) < 0 ) /* If we can't read it, pretend it doesn't exist... */ continue; - /* fdt_get_mem_rsv returns length */ + /* fdt_get_mem_rsv_paddr returns length */ mod_e += mod_s; if ( s < mod_e && mod_s < e ) diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index 412ae22869..c15c177487 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -159,7 +159,7 @@ static void __init dt_smp_init_cpus(void) continue; } - addr = dt_read_number(prop, dt_n_addr_cells(cpu)); + addr = dt_read_paddr(prop, dt_n_addr_cells(cpu)); hwid = addr; if ( hwid != addr ) diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index a28937d12a..b61bac2931 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -244,6 +244,27 @@ static inline u64 dt_read_number(const __be32 *cell, int size) return r; } +/* Wrapper for dt_read_number() to return paddr_t (instead of u64) */ +static inline paddr_t dt_read_paddr(const __be32 *cell, int size) +{ + u64 dt_r = 0; + paddr_t r; + + dt_r = dt_read_number(cell, size); + + if ( (dt_r >> (PADDR_SHIFT - 1)) > 1 ) + printk("Error: Physical address greater than max width supported\n"); + + /* + * Note: It is user's responsibility to check for the error messages. + * Xen will sliently truncate in case if the address/size is greater than + * the max supported width. + */ + r = dt_r; + + return r; +} + /* Helper to convert a number of cells to bytes */ static inline int dt_cells_to_size(int size) { diff --git a/xen/include/xen/libfdt/libfdt_xen.h b/xen/include/xen/libfdt/libfdt_xen.h new file mode 100644 index 0000000000..a3196dd96c --- /dev/null +++ b/xen/include/xen/libfdt/libfdt_xen.h @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * xen/include/xen/libfdt/libfdt_xen.h + * + * Wrapper functions for device tree. This helps to convert dt values + * between u64 and paddr_t. + * + * Copyright (C) 2023, Advanced Micro Devices, Inc. All Rights Reserved. + */ + +#ifndef LIBFDT_XEN_H +#define LIBFDT_XEN_H + +#include + +inline int fdt_get_mem_rsv_paddr(const void *fdt, int n, + paddr_t *address, + paddr_t *size) +{ + uint64_t dt_addr; + uint64_t dt_size; + int ret = 0; + + ret = fdt_get_mem_rsv(fdt, n, &dt_addr, &dt_size); + + if ( (dt_addr >> (PADDR_SHIFT - 1)) > 1 ) + { + printk("Error: Physical address greater than max width supported\n"); + return -1; + } + + if ( (dt_size >> (PADDR_SHIFT - 1)) > 1 ) + { + printk("Error: Physical size greater than max width supported\n"); + return -1; + } + + *address = dt_addr; + *size = dt_size; + + return ret; +} + +#endif /* LIBFDT_XEN_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/xen/types.h b/xen/include/xen/types.h index 6aba80500a..b7255c7c38 100644 --- a/xen/include/xen/types.h +++ b/xen/include/xen/types.h @@ -71,4 +71,6 @@ typedef bool bool_t; #define test_and_set_bool(b) xchg(&(b), true) #define test_and_clear_bool(b) xchg(&(b), false) +#define PADDR_SHIFT PADDR_BITS + #endif /* __TYPES_H__ */ From patchwork Wed Feb 8 12:05:23 2023 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v3 3/9] xen/drivers: ns16550: Use paddr_t for io_base/io_size Date: Wed, 8 Feb 2023 12:05:23 +0000 Message-ID: <20230208120529.22313-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208120529.22313-1-ayan.kumar.halder@amd.com> References: <20230208120529.22313-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT089:EE_|BL0PR12MB4945:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e1095b2-76eb-4466-6ea2-08db09ccd8af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /79enLjL8WxVA0/UJrwt8ZvoUxa8j8rNcwzU5P4VC1Zo9ckjdjeuuc03dPPrvYe9jXzID1jFbqvvsVOwc374QY5oIEY6Ju82M+iOf+68okQMV6P/EPZLtOeCGD69Dm10+A8E+enI0WKeLBHRfLY8aS8HulEi0/3FYNpXW1h95FIErfpnG/t8/hfl8MlLFg3AYTOcEbZ2sx6nj25lE5v/5a4QQ7oOEti9X125GtwIcmIwL7rbQa/GLlOLR6qMdTjPAenRPWyUNS+3L2wRprRYZKlCFrlLlpKHBI0sUdItQHFxe5PZt5mP6KrnAZih2WlgtX9RUTIERzRrFENSlm1eEW2wcSVQPZks+DB0s1QORf2xhrEiOnVKszJ9ynJxx5YdOFelTsxhz4kp59+UkMMbCp3y9qTg83+j9XgUilyIu67yo70LeBIATpluVz5gfJ3D25qAPhqVJKIArf1bq8aXK3DHx7xmNcL1j0jggcqorD1i46gv3uHsaIZ2pHXZwuTpIGBsw0d3114xiwoIIz5IYLMcJQx6Lc2W+2z3GV5FAstx42MZ0NavkZ4gvstcq4antpo2crSoquJ6fyoMgPsAdgATaDpVw9Jk0ocKE6zpzWSmKWF+wWgr5eT5WWGBrUNWeLbdgJ3QU1x7YpRyhvPldaWL/kppjk8Wi2C118xmJzt/vqFtsn2ufuWbsdNP+tCVmJczixvRvYIrtyg83C6++nGx55FwrZmBriBVKCkulyw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(346002)(376002)(136003)(396003)(451199018)(40470700004)(46966006)(36840700001)(103116003)(36756003)(86362001)(356005)(2906002)(82310400005)(7416002)(41300700001)(5660300002)(8936002)(83380400001)(81166007)(82740400003)(36860700001)(478600001)(186003)(26005)(40480700001)(40460700003)(316002)(336012)(70586007)(1076003)(6666004)(8676002)(6916009)(54906003)(70206006)(426003)(4326008)(47076005)(2616005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 12:06:01.5942 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e1095b2-76eb-4466-6ea2-08db09ccd8af X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4945 io_base and io_size represent physical addresses. So they should use paddr_t (instead of u64). However in future, paddr_t may be defined as u32. So when typecasting values from u64 to paddr_t, one should always check for any possible truncation. If any truncation is discovered, Xen needs to raise a BUG for this (as the address is provided either by reading the PCIE registers or parsing parameters from string, so the error is unrecoverable). Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - NA v2 - 1. Extracted the patch from "[XEN v2 05/11] xen/arm: Use paddr_t instead of u64 for address/size" into a separate patch of its own. xen/drivers/char/ns16550.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 092f6b9c4b..2aee5642f9 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -42,8 +42,8 @@ static struct ns16550 { int baud, clock_hz, data_bits, parity, stop_bits, fifo_size, irq; - u64 io_base; /* I/O port or memory-mapped I/O address. */ - u64 io_size; + paddr_t io_base; /* I/O port or memory-mapped I/O address. */ + paddr_t io_size; int reg_shift; /* Bits to shift register offset by */ int reg_width; /* Size of access to use, the registers * themselves are still bytes */ @@ -1166,8 +1166,9 @@ static const struct ns16550_config __initconst uart_config[] = static int __init pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) { - u64 orig_base = uart->io_base; + paddr_t orig_base = uart->io_base; unsigned int b, d, f, nextf, i; + u64 pci_uart_io_base; /* NB. Start at bus 1 to avoid AMT: a plug-in card cannot be on bus 0. */ for ( b = skip_amt ? 1 : 0; b < 0x100; b++ ) @@ -1259,8 +1260,13 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) else size = len & PCI_BASE_ADDRESS_MEM_MASK; - uart->io_base = ((u64)bar_64 << 32) | - (bar & PCI_BASE_ADDRESS_MEM_MASK); + pci_uart_io_base = ((u64)bar_64 << 32) | + (bar & PCI_BASE_ADDRESS_MEM_MASK); + + /* Truncation detected while converting to paddr_t */ + BUG_ON((pci_uart_io_base >> (PADDR_SHIFT - 1)) > 1); + + uart->io_base = pci_uart_io_base; } /* IO based */ else if ( !param->mmio && (bar & PCI_BASE_ADDRESS_SPACE_IO) ) @@ -1468,6 +1474,7 @@ static bool __init parse_positional(struct ns16550 *uart, char **str) int baud; const char *conf; char *name_val_pos; + u64 uart_io_base; conf = *str; name_val_pos = strchr(conf, '='); @@ -1532,7 +1539,12 @@ static bool __init parse_positional(struct ns16550 *uart, char **str) else #endif { - uart->io_base = simple_strtoull(conf, &conf, 0); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 12:06:04.5823 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e5b6317-4d6b-4ff8-11a8-08db09ccda88 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT103.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5054 dt_device_get_address() can accept u64 only for address and size. However, the address/size denotes physical addresses. Thus, they should be represented by 'paddr_t'. Consequently, we introduce a wrapper for dt_device_get_address() ie dt_device_get_paddr() which accepts address/size as paddr_t and inturn invokes dt_device_get_address() after converting address/size to u64. The reason for introducing doing this is that in future 'paddr_t' may be defined as u32. Thus, we need an explicit wrapper to do the type conversion and return an error in case of truncation. With this, callers now invoke dt_device_get_paddr(). dt_device_get_address() is invoked by dt_device_get_paddr() only. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. New patch. v2 - 1. Extracted part of "[XEN v2 05/11] xen/arm: Use paddr_t instead of u64 for address/size" into this patch. 2. dt_device_get_address() callers now invoke dt_device_get_paddr() instead. 3. Logged error in case of truncation. xen/arch/arm/domain_build.c | 10 +++--- xen/arch/arm/gic-v2.c | 10 +++--- xen/arch/arm/gic-v3-its.c | 4 +-- xen/arch/arm/gic-v3.c | 10 +++--- xen/arch/arm/pci/pci-host-common.c | 6 ++-- xen/arch/arm/platforms/brcm-raspberry-pi.c | 2 +- xen/arch/arm/platforms/brcm.c | 4 +-- xen/arch/arm/platforms/exynos5.c | 32 +++++++++---------- xen/arch/arm/platforms/sunxi.c | 2 +- xen/arch/arm/platforms/xgene-storm.c | 2 +- xen/common/device_tree.c | 36 ++++++++++++++++++++-- xen/drivers/char/cadence-uart.c | 4 +-- xen/drivers/char/exynos4210-uart.c | 4 +-- xen/drivers/char/imx-lpuart.c | 4 +-- xen/drivers/char/meson-uart.c | 4 +-- xen/drivers/char/mvebu-uart.c | 4 +-- xen/drivers/char/ns16550.c | 2 +- xen/drivers/char/omap-uart.c | 4 +-- xen/drivers/char/pl011.c | 6 ++-- xen/drivers/char/scif-uart.c | 4 +-- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 8 ++--- xen/drivers/passthrough/arm/smmu-v3.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 8 ++--- xen/include/xen/device_tree.h | 6 ++-- 24 files changed, 105 insertions(+), 73 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 4d7e67560f..c7e88f5011 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1692,13 +1692,13 @@ static int __init find_memory_holes(const struct kernel_info *kinfo, dt_for_each_device_node( dt_host, np ) { unsigned int naddr; - u64 addr, size; + paddr_t addr, size; naddr = dt_number_of_address(np); for ( i = 0; i < naddr; i++ ) { - res = dt_device_get_address(np, i, &addr, &size); + res = dt_device_get_paddr(np, i, &addr, &size); if ( res ) { printk(XENLOG_ERR "Unable to retrieve address %u for %s\n", @@ -2471,7 +2471,7 @@ static int __init handle_device(struct domain *d, struct dt_device_node *dev, unsigned int naddr; unsigned int i; int res; - u64 addr, size; + paddr_t addr, size; bool own_device = !dt_device_for_passthrough(dev); /* * We want to avoid mapping the MMIO in dom0 for the following cases: @@ -2526,7 +2526,7 @@ static int __init handle_device(struct domain *d, struct dt_device_node *dev, /* Give permission and map MMIOs */ for ( i = 0; i < naddr; i++ ) { - res = dt_device_get_address(dev, i, &addr, &size); + res = dt_device_get_paddr(dev, i, &addr, &size); if ( res ) { printk(XENLOG_ERR "Unable to retrieve address %u for %s\n", @@ -2957,7 +2957,7 @@ static int __init handle_passthrough_prop(struct kernel_info *kinfo, if ( res ) { printk(XENLOG_ERR "Unable to permit to dom%d access to" - " 0x%"PRIx64" - 0x%"PRIx64"\n", + " 0x%"PRIpaddr" - 0x%"PRIpaddr"\n", kinfo->d->domain_id, mstart & PAGE_MASK, PAGE_ALIGN(mstart + size) - 1); return res; diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 5d4d298b86..6476ff4230 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -993,7 +993,7 @@ static void gicv2_extension_dt_init(const struct dt_device_node *node) continue; /* Get register frame resource from DT. */ - if ( dt_device_get_address(v2m, 0, &addr, &size) ) + if ( dt_device_get_paddr(v2m, 0, &addr, &size) ) panic("GICv2: Cannot find a valid v2m frame address\n"); /* @@ -1018,19 +1018,19 @@ static void __init gicv2_dt_init(void) paddr_t vsize; const struct dt_device_node *node = gicv2_info.node; - res = dt_device_get_address(node, 0, &dbase, NULL); + res = dt_device_get_paddr(node, 0, &dbase, NULL); if ( res ) panic("GICv2: Cannot find a valid address for the distributor\n"); - res = dt_device_get_address(node, 1, &cbase, &csize); + res = dt_device_get_paddr(node, 1, &cbase, &csize); if ( res ) panic("GICv2: Cannot find a valid address for the CPU\n"); - res = dt_device_get_address(node, 2, &hbase, NULL); + res = dt_device_get_paddr(node, 2, &hbase, NULL); if ( res ) panic("GICv2: Cannot find a valid address for the hypervisor\n"); - res = dt_device_get_address(node, 3, &vbase, &vsize); + res = dt_device_get_paddr(node, 3, &vbase, &vsize); if ( res ) panic("GICv2: Cannot find a valid address for the virtual CPU\n"); diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 1ec9934191..3aa4edda10 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -1004,12 +1004,12 @@ static void gicv3_its_dt_init(const struct dt_device_node *node) */ dt_for_each_child_node(node, its) { - uint64_t addr, size; + paddr_t addr, size; if ( !dt_device_is_compatible(its, "arm,gic-v3-its") ) continue; - if ( dt_device_get_address(its, 0, &addr, &size) ) + if ( dt_device_get_paddr(its, 0, &addr, &size) ) panic("GICv3: Cannot find a valid ITS frame address\n"); add_to_host_its_list(addr, size, its); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index bb59ea94cd..4e6c98bada 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1377,7 +1377,7 @@ static void __init gicv3_dt_init(void) int res, i; const struct dt_device_node *node = gicv3_info.node; - res = dt_device_get_address(node, 0, &dbase, NULL); + res = dt_device_get_paddr(node, 0, &dbase, NULL); if ( res ) panic("GICv3: Cannot find a valid distributor address\n"); @@ -1393,9 +1393,9 @@ static void __init gicv3_dt_init(void) for ( i = 0; i < gicv3.rdist_count; i++ ) { - uint64_t rdist_base, rdist_size; + paddr_t rdist_base, rdist_size; - res = dt_device_get_address(node, 1 + i, &rdist_base, &rdist_size); + res = dt_device_get_paddr(node, 1 + i, &rdist_base, &rdist_size); if ( res ) panic("GICv3: No rdist base found for region %d\n", i); @@ -1417,10 +1417,10 @@ static void __init gicv3_dt_init(void) * For GICv3 supporting GICv2, GICC and GICV base address will be * provided. */ - res = dt_device_get_address(node, 1 + gicv3.rdist_count, + res = dt_device_get_paddr(node, 1 + gicv3.rdist_count, &cbase, &csize); if ( !res ) - dt_device_get_address(node, 1 + gicv3.rdist_count + 2, + dt_device_get_paddr(node, 1 + gicv3.rdist_count + 2, &vbase, &vsize); } diff --git a/xen/arch/arm/pci/pci-host-common.c b/xen/arch/arm/pci/pci-host-common.c index a8ece94303..5550f9478d 100644 --- a/xen/arch/arm/pci/pci-host-common.c +++ b/xen/arch/arm/pci/pci-host-common.c @@ -93,7 +93,7 @@ gen_pci_init(struct dt_device_node *dev, const struct pci_ecam_ops *ops) cfg_reg_idx = 0; /* Parse our PCI ecam register address */ - err = dt_device_get_address(dev, cfg_reg_idx, &addr, &size); + err = dt_device_get_paddr(dev, cfg_reg_idx, &addr, &size); if ( err ) goto err_exit; @@ -349,10 +349,10 @@ int __init pci_host_bridge_mappings(struct domain *d) for ( i = 0; i < dt_number_of_address(dev); i++ ) { - uint64_t addr, size; + paddr_t addr, size; int err; - err = dt_device_get_address(dev, i, &addr, &size); + err = dt_device_get_paddr(dev, i, &addr, &size); if ( err ) { printk(XENLOG_ERR diff --git a/xen/arch/arm/platforms/brcm-raspberry-pi.c b/xen/arch/arm/platforms/brcm-raspberry-pi.c index 811b40b1a6..407ec07f63 100644 --- a/xen/arch/arm/platforms/brcm-raspberry-pi.c +++ b/xen/arch/arm/platforms/brcm-raspberry-pi.c @@ -64,7 +64,7 @@ static void __iomem *rpi4_map_watchdog(void) if ( !node ) return NULL; - ret = dt_device_get_address(node, 0, &start, &len); + ret = dt_device_get_paddr(node, 0, &start, &len); if ( ret ) { printk("Cannot read watchdog register address\n"); diff --git a/xen/arch/arm/platforms/brcm.c b/xen/arch/arm/platforms/brcm.c index d481b2c60f..4310feee73 100644 --- a/xen/arch/arm/platforms/brcm.c +++ b/xen/arch/arm/platforms/brcm.c @@ -40,7 +40,7 @@ static __init int brcm_get_dt_node(char *compat_str, u32 *reg_base) { const struct dt_device_node *node; - u64 reg_base_64; + paddr_t reg_base_64; int rc; node = dt_find_compatible_node(NULL, NULL, compat_str); @@ -50,7 +50,7 @@ static __init int brcm_get_dt_node(char *compat_str, return -ENOENT; } - rc = dt_device_get_address(node, 0, ®_base_64, NULL); + rc = dt_device_get_paddr(node, 0, ®_base_64, NULL); if ( rc ) { dprintk(XENLOG_ERR, "%s: missing \"reg\" prop\n", __func__); diff --git a/xen/arch/arm/platforms/exynos5.c b/xen/arch/arm/platforms/exynos5.c index 6560507092..c48093cd4f 100644 --- a/xen/arch/arm/platforms/exynos5.c +++ b/xen/arch/arm/platforms/exynos5.c @@ -42,8 +42,8 @@ static int exynos5_init_time(void) void __iomem *mct; int rc; struct dt_device_node *node; - u64 mct_base_addr; - u64 size; + paddr_t mct_base_addr; + paddr_t size; node = dt_find_compatible_node(NULL, NULL, "samsung,exynos4210-mct"); if ( !node ) @@ -52,14 +52,14 @@ static int exynos5_init_time(void) return -ENXIO; } - rc = dt_device_get_address(node, 0, &mct_base_addr, &size); + rc = dt_device_get_paddr(node, 0, &mct_base_addr, &size); if ( rc ) { dprintk(XENLOG_ERR, "Error in \"samsung,exynos4210-mct\"\n"); return -ENXIO; } - dprintk(XENLOG_INFO, "mct_base_addr: %016llx size: %016llx\n", + dprintk(XENLOG_INFO, "mct_base_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"\n", mct_base_addr, size); mct = ioremap_nocache(mct_base_addr, size); @@ -97,9 +97,9 @@ static int __init exynos5_smp_init(void) struct dt_device_node *node; void __iomem *sysram; char *compatible; - u64 sysram_addr; - u64 size; - u64 sysram_offset; + paddr_t sysram_addr; + paddr_t size; + paddr_t sysram_offset; int rc; node = dt_find_compatible_node(NULL, NULL, "samsung,secure-firmware"); @@ -125,13 +125,13 @@ static int __init exynos5_smp_init(void) return -ENXIO; } - rc = dt_device_get_address(node, 0, &sysram_addr, &size); + rc = dt_device_get_paddr(node, 0, &sysram_addr, &size); if ( rc ) { dprintk(XENLOG_ERR, "Error in %s\n", compatible); return -ENXIO; } - dprintk(XENLOG_INFO, "sysram_addr: %016llx size: %016llx offset: %016llx\n", + dprintk(XENLOG_INFO,"sysram_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"offset: 0x%"PRIpaddr"\n", sysram_addr, size, sysram_offset); sysram = ioremap_nocache(sysram_addr, size); @@ -189,7 +189,7 @@ static int exynos5_cpu_power_up(void __iomem *power, int cpu) return 0; } -static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) +static int exynos5_get_pmu_baseandsize(paddr_t *power_base_addr, paddr_t *size) { struct dt_device_node *node; int rc; @@ -208,14 +208,14 @@ static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) return -ENXIO; } - rc = dt_device_get_address(node, 0, power_base_addr, size); + rc = dt_device_get_paddr(node, 0, power_base_addr, size); if ( rc ) { dprintk(XENLOG_ERR, "Error in \"samsung,exynos5XXX-pmu\"\n"); return -ENXIO; } - dprintk(XENLOG_DEBUG, "power_base_addr: %016llx size: %016llx\n", + dprintk(XENLOG_DEBUG, "power_base_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"\n", *power_base_addr, *size); return 0; @@ -223,8 +223,8 @@ static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) static int exynos5_cpu_up(int cpu) { - u64 power_base_addr; - u64 size; + paddr_t power_base_addr; + paddr_t size; void __iomem *power; int rc; @@ -256,8 +256,8 @@ static int exynos5_cpu_up(int cpu) static void exynos5_reset(void) { - u64 power_base_addr; - u64 size; + paddr_t power_base_addr; + paddr_t size; void __iomem *pmu; int rc; diff --git a/xen/arch/arm/platforms/sunxi.c b/xen/arch/arm/platforms/sunxi.c index e8e4d88bef..2b2c215f20 100644 --- a/xen/arch/arm/platforms/sunxi.c +++ b/xen/arch/arm/platforms/sunxi.c @@ -50,7 +50,7 @@ static void __iomem *sunxi_map_watchdog(bool *new_wdt) return NULL; } - ret = dt_device_get_address(node, 0, &wdt_start, &wdt_len); + ret = dt_device_get_paddr(node, 0, &wdt_start, &wdt_len); if ( ret ) { dprintk(XENLOG_ERR, "Cannot read watchdog register address\n"); diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c index befd0c3c2d..6fc2f9679e 100644 --- a/xen/arch/arm/platforms/xgene-storm.c +++ b/xen/arch/arm/platforms/xgene-storm.c @@ -50,7 +50,7 @@ static void __init xgene_check_pirq_eoi(void) if ( !node ) panic("%s: Can not find interrupt controller node\n", __func__); - res = dt_device_get_address(node, 0, &dbase, NULL); + res = dt_device_get_paddr(node, 0, &dbase, NULL); if ( res ) panic("%s: Cannot find a valid address for the distributor\n", __func__); diff --git a/xen/common/device_tree.c b/xen/common/device_tree.c index 6c9712ab7b..d0f19d5cfc 100644 --- a/xen/common/device_tree.c +++ b/xen/common/device_tree.c @@ -934,8 +934,9 @@ bail: } /* dt_device_address - Translate device tree address and return it */ -int dt_device_get_address(const struct dt_device_node *dev, unsigned int index, - u64 *addr, u64 *size) +static int dt_device_get_address(const struct dt_device_node *dev, + unsigned int index, + u64 *addr, u64 *size) { const __be32 *addrp; unsigned int flags; @@ -955,6 +956,37 @@ int dt_device_get_address(const struct dt_device_node *dev, unsigned int index, return 0; } +int dt_device_get_paddr(const struct dt_device_node *dev, unsigned int index, + paddr_t *addr, paddr_t *size) +{ + u64 dt_addr = 0, dt_size = 0; + int ret; + + ret = dt_device_get_address(dev, index, &dt_addr, &dt_size); + + if ( addr ) + { + if ( (dt_addr >> (PADDR_SHIFT - 1)) > 1 ) + { + printk("Error: Physical address greater than max width supported\n"); + return -EINVAL; + } + + *addr = dt_addr; + } + + if ( size ) + { + if ( (dt_size >> (PADDR_SHIFT - 1)) > 1 ) + { + printk("Error: Physical size greater than max width supported\n"); + return -EINVAL; + } + *size = dt_size; + } + + return ret; +} int dt_for_each_range(const struct dt_device_node *dev, int (*cb)(const struct dt_device_node *, diff --git a/xen/drivers/char/cadence-uart.c b/xen/drivers/char/cadence-uart.c index 22905ba66c..c38d7ed143 100644 --- a/xen/drivers/char/cadence-uart.c +++ b/xen/drivers/char/cadence-uart.c @@ -158,14 +158,14 @@ static int __init cuart_init(struct dt_device_node *dev, const void *data) const char *config = data; struct cuart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); uart = &cuart_com; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("cadence: Unable to retrieve the base" diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos4210-uart.c index 43aaf02e18..2503392ccd 100644 --- a/xen/drivers/char/exynos4210-uart.c +++ b/xen/drivers/char/exynos4210-uart.c @@ -303,7 +303,7 @@ static int __init exynos4210_uart_init(struct dt_device_node *dev, const char *config = data; struct exynos4210_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); @@ -316,7 +316,7 @@ static int __init exynos4210_uart_init(struct dt_device_node *dev, uart->parity = PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("exynos4210: Unable to retrieve the base" diff --git a/xen/drivers/char/imx-lpuart.c b/xen/drivers/char/imx-lpuart.c index 9c1f3b71a3..77f70c2719 100644 --- a/xen/drivers/char/imx-lpuart.c +++ b/xen/drivers/char/imx-lpuart.c @@ -204,7 +204,7 @@ static int __init imx_lpuart_init(struct dt_device_node *dev, const char *config = data; struct imx_lpuart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); @@ -216,7 +216,7 @@ static int __init imx_lpuart_init(struct dt_device_node *dev, uart->parity = 0; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("imx8-lpuart: Unable to retrieve the base" diff --git a/xen/drivers/char/meson-uart.c b/xen/drivers/char/meson-uart.c index b1e25e0468..c627328122 100644 --- a/xen/drivers/char/meson-uart.c +++ b/xen/drivers/char/meson-uart.c @@ -209,14 +209,14 @@ static int __init meson_uart_init(struct dt_device_node *dev, const void *data) const char *config = data; struct meson_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); uart = &meson_com; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("meson: Unable to retrieve the base address of the UART\n"); diff --git a/xen/drivers/char/mvebu-uart.c b/xen/drivers/char/mvebu-uart.c index a00618b96f..cc55173513 100644 --- a/xen/drivers/char/mvebu-uart.c +++ b/xen/drivers/char/mvebu-uart.c @@ -231,14 +231,14 @@ static int __init mvebu_uart_init(struct dt_device_node *dev, const void *data) const char *config = data; struct mvebu3700_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); uart = &mvebu3700_com; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("mvebu3700: Unable to retrieve the base address of the UART\n"); diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 2aee5642f9..9a5e26a8d2 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1769,7 +1769,7 @@ static int __init ns16550_uart_dt_init(struct dt_device_node *dev, uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &uart->io_base, &uart->io_size); + res = dt_device_get_paddr(dev, 0, &uart->io_base, &uart->io_size); if ( res ) return res; diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c index d6a5d59aa2..8e643cb039 100644 --- a/xen/drivers/char/omap-uart.c +++ b/xen/drivers/char/omap-uart.c @@ -324,7 +324,7 @@ static int __init omap_uart_init(struct dt_device_node *dev, struct omap_uart *uart; u32 clkspec; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); @@ -344,7 +344,7 @@ static int __init omap_uart_init(struct dt_device_node *dev, uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("omap-uart: Unable to retrieve the base" diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index be67242bc0..052a651251 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -222,7 +222,7 @@ static struct uart_driver __read_mostly pl011_driver = { .vuart_info = pl011_vuart, }; -static int __init pl011_uart_init(int irq, u64 addr, u64 size, bool sbsa) +static int __init pl011_uart_init(int irq, paddr_t addr, paddr_t size, bool sbsa) { struct pl011 *uart; @@ -258,14 +258,14 @@ static int __init pl011_dt_uart_init(struct dt_device_node *dev, { const char *config = data; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) { printk("WARNING: UART configuration is not supported\n"); } - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("pl011: Unable to retrieve the base" diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 2fccafe340..1b28ba90e9 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -311,14 +311,14 @@ static int __init scif_uart_init(struct dt_device_node *dev, const char *config = data; struct scif_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); uart = &scif_com; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("scif-uart: Unable to retrieve the base" diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index 091f09b217..611d9eeba5 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -794,7 +794,7 @@ static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) static __init bool ipmmu_stage2_supported(void) { struct dt_device_node *np; - uint64_t addr, size; + paddr_t addr, size; void __iomem *base; uint32_t product, cut; bool stage2_supported = false; @@ -806,7 +806,7 @@ static __init bool ipmmu_stage2_supported(void) return false; } - if ( dt_device_get_address(np, 0, &addr, &size) ) + if ( dt_device_get_paddr(np, 0, &addr, &size) ) { printk(XENLOG_ERR "ipmmu: Failed to get PRR MMIO\n"); return false; @@ -884,7 +884,7 @@ static int ipmmu_probe(struct dt_device_node *node) { const struct dt_device_match *match; struct ipmmu_vmsa_device *mmu; - uint64_t addr, size; + paddr_t addr, size; uint32_t reg; int irq, ret; @@ -905,7 +905,7 @@ static int ipmmu_probe(struct dt_device_node *node) bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); /* Map I/O memory and request IRQ. */ - ret = dt_device_get_address(node, 0, &addr, &size); + ret = dt_device_get_paddr(node, 0, &addr, &size); if ( ret ) { dev_err(&node->dev, "Failed to get MMIO\n"); diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index d58c5cd0bf..79d20eed20 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -2451,7 +2451,7 @@ static int arm_smmu_device_probe(struct platform_device *pdev) } /* Base address */ - ret = dt_device_get_address(dev_to_dt(pdev), 0, &ioaddr, &iosize); + ret = dt_device_get_paddr(dev_to_dt(pdev), 0, &ioaddr, &iosize); if (ret) goto out_free_smmu; diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 0a514821b3..79281075ba 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -73,8 +73,8 @@ /* Xen: Helpers to get device MMIO and IRQs */ struct resource { - u64 addr; - u64 size; + paddr_t addr; + paddr_t size; unsigned int type; }; @@ -101,7 +101,7 @@ static struct resource *platform_get_resource(struct platform_device *pdev, switch (type) { case IORESOURCE_MEM: - ret = dt_device_get_address(pdev, num, &res.addr, &res.size); + ret = dt_device_get_paddr(pdev, num, &res.addr, &res.size); return ((ret) ? NULL : &res); @@ -169,7 +169,7 @@ static void __iomem *devm_ioremap_resource(struct device *dev, ptr = ioremap_nocache(res->addr, res->size); if (!ptr) { dev_err(dev, - "ioremap failed (addr 0x%"PRIx64" size 0x%"PRIx64")\n", + "ioremap failed (addr 0x%"PRIpaddr" size 0x%"PRIpaddr")\n", res->addr, res->size); return ERR_PTR(-ENOMEM); } diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index b61bac2931..04aa43e0ee 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -583,7 +583,7 @@ int dt_find_node_by_gpath(XEN_GUEST_HANDLE(char) u_path, uint32_t u_plen, const struct dt_device_node *dt_get_parent(const struct dt_device_node *node); /** - * dt_device_get_address - Resolve an address for a device + * dt_device_get_paddr - Resolve an address for a device * @device: the device whose address is to be resolved * @index: index of the address to resolve * @addr: address filled by this function @@ -592,8 +592,8 @@ const struct dt_device_node *dt_get_parent(const struct dt_device_node *node); * This function resolves an address, walking the tree, for a give * device-tree node. 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bh=wNZiAudurUH10oR6SRddjZkqMj7xmnDFdnkT/K607Xk=; b=dI2JpUNyWf5zpLherLQpQXl7UM7flk+nGB3cAuswJJcGCdaRwPluoR9G2C6clArGRDGumfDR6UYljcXEXNq3aFpc0cKzkBMii7y4PoQNfd5N9mcQvsATCpEi0wK/2ZBJPdaAQl8+0WSj0icZYjyn2USYWLIKPFGBXunRiU8AlCg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v3 5/9] xen/arm: smmu: Use writeq_relaxed_non_atomic() for writing to SMMU_CBn_TTBR0 Date: Wed, 8 Feb 2023 12:05:25 +0000 Message-ID: <20230208120529.22313-6-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208120529.22313-1-ayan.kumar.halder@amd.com> References: <20230208120529.22313-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT068:EE_|SJ1PR12MB6220:EE_ X-MS-Office365-Filtering-Correlation-Id: eaf8e6d7-befb-4405-9b73-08db09ccdb67 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 12:06:06.1567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eaf8e6d7-befb-4405-9b73-08db09ccdb67 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6220 Refer ARM IHI 0062D.c ID070116 (SMMU 2.0 spec), 17-360, 17.3.9, SMMU_CBn_TTBR0 is a 64 bit register. Thus, one can use writeq_relaxed_non_atomic() to write to it instead of invoking writel_relaxed() twice for lower half and upper half of the register. This also helps us as p2maddr is 'paddr_t' (which may be u32 in future). Thus, one can assign p2maddr to a 64 bit register and do the bit manipulations on it, to generate the value for SMMU_CBn_TTBR0. Signed-off-by: Ayan Kumar Halder Reviewed-by: Stefano Stabellini --- Changes from - v1 - 1. Extracted the patch from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". Use writeq_relaxed_non_atomic() to write u64 register in a non-atomic fashion. v2 - 1. Added R-b. xen/drivers/passthrough/arm/smmu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 79281075ba..c8ef2a925f 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -499,8 +499,7 @@ enum arm_smmu_s2cr_privcfg { #define ARM_SMMU_CB_SCTLR 0x0 #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_CB_TTBCR2 0x10 -#define ARM_SMMU_CB_TTBR0_LO 0x20 -#define ARM_SMMU_CB_TTBR0_HI 0x24 +#define ARM_SMMU_CB_TTBR0 0x20 #define ARM_SMMU_CB_TTBCR 0x30 #define ARM_SMMU_CB_S1_MAIR0 0x38 #define ARM_SMMU_CB_FSR 0x58 @@ -1083,6 +1082,7 @@ static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) { u32 reg; + u64 reg64; bool stage1; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; struct arm_smmu_device *smmu = smmu_domain->smmu; @@ -1177,12 +1177,13 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) dev_notice(smmu->dev, "d%u: p2maddr 0x%"PRIpaddr"\n", smmu_domain->cfg.domain->domain_id, p2maddr); - reg = (p2maddr & ((1ULL << 32) - 1)); - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); - reg = (p2maddr >> 32); + reg64 = p2maddr; + if (stage1) - reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); + reg64 |= (((uint64_t) (ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT)) + << 32); + + writeq_relaxed_non_atomic(reg64, cb_base + ARM_SMMU_CB_TTBR0); /* * TTBCR From patchwork Wed Feb 8 12:05:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13133022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6960C05027 for ; Wed, 8 Feb 2023 12:06:35 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.491727.761044 (Exim 4.92) (envelope-from ) id 1pPjDQ-0007gb-HL; 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bh=V2VJmiFZsrpDpPGNogHFDiYO4zGiLQ4UiSa+V9iwHmw=; b=zUlzT1qF3JNeDtu5CSpfKvgAEaJkusMXWCwW4ga0vTKitWoW3uEeHICuRE5Vnv1veuIUbe41dzBOYSfTNLKFvPF6FXxIvuxs7SALMLg8lOuAEwtIhEBFjEngs2Y6YvdMu2RqT6CI8bn7wbrvcHNaTtlFR62vjvEcSKjPwYSskwQ= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v3 6/9] xen/arm: Introduce choice to enable 64/32 bit physical addressing Date: Wed, 8 Feb 2023 12:05:26 +0000 Message-ID: <20230208120529.22313-7-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208120529.22313-1-ayan.kumar.halder@amd.com> References: <20230208120529.22313-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT103:EE_|SN7PR12MB7155:EE_ X-MS-Office365-Filtering-Correlation-Id: e982044b-afe5-4289-dbf4-08db09ccdeb8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 12:06:11.6130 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e982044b-afe5-4289-dbf4-08db09ccdeb8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT103.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7155 Some Arm based hardware platforms which does not support LPAE (eg Cortex-R52), uses 32 bit physical addresses. Also, users may choose to use 32 bits to represent physical addresses for optimization. To support the above use cases, we have introduced arch independent configs to choose if the physical address can be represented using 32 bits (PHYS_ADDR_32) or 64 bits (PHYS_ADDR_64). For now only ARM_32 provides support to enable 32 bit physical addressing. Signed-off-by: Ayan Kumar Halder Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. Extracted from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". v2 - 1. Introduced Kconfig choice. ARM_64 can select PHYS_ADDR_64 only whereas ARM_32 can select PHYS_ADDR_32 or PHYS_ADDR_64. 2. For CONFIG_ARM_PA_32, paddr_t is defined as 'unsigned long'. (Jan,Julien please let me know if I understood your suggestion about Kconfig correctly). xen/arch/Kconfig | 12 +++++++++++ xen/arch/arm/Kconfig | 31 ++++++++++++++++++++++++++++ xen/arch/arm/include/asm/page-bits.h | 2 ++ xen/arch/arm/include/asm/types.h | 6 ++++++ 4 files changed, 51 insertions(+) diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig index 7028f7b74f..1eff312b51 100644 --- a/xen/arch/Kconfig +++ b/xen/arch/Kconfig @@ -1,6 +1,18 @@ config 64BIT bool +config PHYS_ADDR_32 + bool + help + Select this option if the physical addresses can be represented by + 32 bits. + +config PHYS_ADDR_64 + bool + help + Select this option if the physical addresses can be represented + 64 bits. + config NR_CPUS int "Maximum number of CPUs" range 1 4095 diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 239d3aed3c..0955891e86 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -18,6 +18,37 @@ config ARM select HAS_PDX select HAS_PMAP select IOMMU_FORCE_PT_SHARE + choice + bool "Representative width for any physical address (default 64bit)" + optional + ---help--- + You may want to specify the width to represent the physical + address space. + By default, the physical addresses are represented using + 64 bits. + + However in certain platforms, the physical addresses may be + represented using 32 bits. + Also, the user may decide that the physical addresses can be + represented using 32 bits for a given SoC. In those cases, + user may want to enable 32 bit physical address for + optimization. + For now, we have enabled this choice for ARM_32 only. + + config ARM_PA_64 + select PHYS_ADDR_64 + bool "Select 64 bits to represent physical address" + ---help--- + Use 64 bits to represent physical address. + + config ARM_PA_32 + select PHYS_ADDR_32 + depends on ARM_32 + bool "Select 32 bits to represent physical address" + ---help--- + Use 32 bits to represent physical address. + + endchoice config ARCH_DEFCONFIG string diff --git a/xen/arch/arm/include/asm/page-bits.h b/xen/arch/arm/include/asm/page-bits.h index 5d6477e599..8f4dcebcfd 100644 --- a/xen/arch/arm/include/asm/page-bits.h +++ b/xen/arch/arm/include/asm/page-bits.h @@ -5,6 +5,8 @@ #ifdef CONFIG_ARM_64 #define PADDR_BITS 48 +#elif CONFIG_ARM_PA_32 +#define PADDR_BITS 32 #else #define PADDR_BITS 40 #endif diff --git a/xen/arch/arm/include/asm/types.h b/xen/arch/arm/include/asm/types.h index e218ed77bd..26144bc87e 100644 --- a/xen/arch/arm/include/asm/types.h +++ b/xen/arch/arm/include/asm/types.h @@ -34,9 +34,15 @@ typedef signed long long s64; typedef unsigned long long u64; typedef u32 vaddr_t; #define PRIvaddr PRIx32 +#if defined(CONFIG_ARM_PA_32) +typedef unsigned long paddr_t; +#define INVALID_PADDR (~0UL) +#define PRIpaddr "08lx" +#else typedef u64 paddr_t; #define INVALID_PADDR (~0ULL) #define PRIpaddr "016llx" +#endif typedef u32 register_t; #define PRIregister "08x" #elif defined (CONFIG_ARM_64) From patchwork Wed Feb 8 12:05:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13133023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81E00C636D7 for ; Wed, 8 Feb 2023 12:06:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.491726.761038 (Exim 4.92) (envelope-from ) id 1pPjDQ-0007cK-1c; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 12:06:12.7379 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d4f4065-f167-4b38-1f25-08db09ccdf62 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT103.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6293 In the subsequent patch, we introduce "CONFIG_ARM_PA_32" to support 32 bit physical addresses. Thus, the code specific to "Large Physical Address Extension" (ie LPAE) should be enclosed within "ifndef CONFIG_ARM_PA_32". Refer xen/arch/arm/include/asm/short-desc.h, "short_desc_l1_supersec_t" unsigned int extbase1:4; /* Extended base address, PA[35:32] */ unsigned int extbase2:4; /* Extended base address, PA[39:36] */ Thus, extbase1 and extbase2 are not valid when 32 bit physical addresses are supported. Signed-off-by: Ayan Kumar Halder Acked-by: Stefano Stabellini --- Changes from - v1 - 1. Extracted from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". v2 - 1. Reordered this patch so that it appears after CONFIG_ARM_PA_32 is introduced (in 6/9). xen/arch/arm/guest_walk.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index 43d3215304..0feb7b76ec 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -154,8 +154,10 @@ static bool guest_walk_sd(const struct vcpu *v, mask = (1ULL << L1DESC_SUPERSECTION_SHIFT) - 1; *ipa = gva & mask; *ipa |= (paddr_t)(pte.supersec.base) << L1DESC_SUPERSECTION_SHIFT; +#ifndef CONFIG_ARM_PA_32 *ipa |= (paddr_t)(pte.supersec.extbase1) << L1DESC_SUPERSECTION_EXT_BASE1_SHIFT; *ipa |= (paddr_t)(pte.supersec.extbase2) << L1DESC_SUPERSECTION_EXT_BASE2_SHIFT; +#endif /* CONFIG_ARM_PA_32 */ } /* Set permissions so that the caller can check the flags by herself. */ From patchwork Wed Feb 8 12:05:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13133024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3009C64EC4 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 12:06:13.9409 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 289f0d9c-ef7e-4d17-1278-08db09cce01c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT103.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6336 When 32 bit physical addresses are used (ie ARM_PA_32=y), "va >> ZEROETH_SHIFT" causes an overflow. Also, there is no zeroeth level page table on Arm 32-bit. Also took the opportunity to clean up dump_pt_walk(). One could use DECLARE_OFFSETS() macro instead of declaring the declaring an array of page table offsets. Signed-off-by: Ayan Kumar Halder Reviewed-by: Stefano Stabellini Acked-by: Julien Grall --- Changes from - v1 - Removed the duplicate declaration for DECLARE_OFFSETS. v2 - 1. Reworded the commit message. 2. Use CONFIG_ARM_PA_32 to restrict zeroeth_table_offset. xen/arch/arm/include/asm/lpae.h | 4 ++++ xen/arch/arm/mm.c | 7 +------ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/include/asm/lpae.h b/xen/arch/arm/include/asm/lpae.h index 3fdd5d0de2..998edeed6e 100644 --- a/xen/arch/arm/include/asm/lpae.h +++ b/xen/arch/arm/include/asm/lpae.h @@ -259,7 +259,11 @@ lpae_t mfn_to_xen_entry(mfn_t mfn, unsigned int attr); #define first_table_offset(va) TABLE_OFFSET(first_linear_offset(va)) #define second_table_offset(va) TABLE_OFFSET(second_linear_offset(va)) #define third_table_offset(va) TABLE_OFFSET(third_linear_offset(va)) +#ifdef CONFIG_ARM_PA_32 +#define zeroeth_table_offset(va) 0 +#else #define zeroeth_table_offset(va) TABLE_OFFSET(zeroeth_linear_offset(va)) +#endif /* * Macros to define page-tables: diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index b99806af99..44942c6a4f 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -221,12 +221,7 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr, { static const char *level_strs[4] = { "0TH", "1ST", "2ND", "3RD" }; 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bh=0LXD4lI8ekDQUSE6zCy/ebroVeYXJn+F4RC8ggf+pIc=; b=ErQ4AwfQw4+2h9qn4hteiAL0q68cc6ah+VO5+qp7oBqWstMinN+wyDsMETqjDI+wupSXAKLwhlYVZX7ol8TMkwtO3fR7yjQDcXDp/H3dT6T5C67hSlFykbs0nmbMwxwo7+mt503HAHkUbt5yG7b4UHVVeA1zl8eSzuiZjZD2uHk= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v3 9/9] xen/arm: p2m: Enable support for 32bit IPA Date: Wed, 8 Feb 2023 12:05:29 +0000 Message-ID: <20230208120529.22313-10-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208120529.22313-1-ayan.kumar.halder@amd.com> References: <20230208120529.22313-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT025:EE_|DM6PR12MB4186:EE_ X-MS-Office365-Filtering-Correlation-Id: cb541ae0-5344-43f2-5281-08db09cce097 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 12:06:14.8736 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb541ae0-5344-43f2-5281-08db09cce097 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4186 VTCR.T0SZ should be set as 0x20 to support 32bit IPA. Refer ARM DDI 0487I.a ID081822, G8-9824, G8.2.171, VTCR, "Virtualization Translation Control Register" for the bit descriptions. Signed-off-by: Ayan Kumar Halder Acked-by: Stefano Stabellini --- Changes from - v1 - New patch. v2 - 1. Added Ack. xen/arch/arm/p2m.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 948f199d84..cfdea55e71 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2266,13 +2266,17 @@ void __init setup_virt_paging(void) register_t val = VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WBWA; #ifdef CONFIG_ARM_32 - if ( p2m_ipa_bits < 40 ) + if ( p2m_ipa_bits < PADDR_BITS ) panic("P2M: Not able to support %u-bit IPA at the moment\n", p2m_ipa_bits); - printk("P2M: 40-bit IPA\n"); - p2m_ipa_bits = 40; + printk("P2M: %u-bit IPA\n",PADDR_BITS); + p2m_ipa_bits = PADDR_BITS; +#ifdef CONFIG_ARM_PA_32 + val |= VTCR_T0SZ(0x20); /* 32 bit IPA */ +#else val |= VTCR_T0SZ(0x18); /* 40 bit IPA */ +#endif val |= VTCR_SL0(0x1); /* P2M starts at first level */ #else /* CONFIG_ARM_64 */ static const struct {