From patchwork Wed Feb 8 15:52:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13133197 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEAB4C64EC4 for ; Wed, 8 Feb 2023 15:53:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230425AbjBHPxn (ORCPT ); Wed, 8 Feb 2023 10:53:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230295AbjBHPxm (ORCPT ); Wed, 8 Feb 2023 10:53:42 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07BA34A1D0; Wed, 8 Feb 2023 07:53:23 -0800 (PST) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 318Eoai7027144; Wed, 8 Feb 2023 15:53:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=1a/BErtpHmYZ0oEStrA8oXWYhd8LnuSHP+YOZT49M2k=; b=XkayuXjmksJS7iHiUJmjwAWC+yPMrz7UHa5JAXlTG0HubiQNd3UZU1pZOQLHCuF9dPlo vHwd2OtnO9n9yKOUNY9xXcG8Vj/5oxNXn+PCmLwcKBiPr9KL6cKzVc+ZnsdkCOuFqiaE 9UaXq8+OOEJTj02w37o1EwRHPKNMuEnxtLXUNcMuSBYSXr2jQyGgznlHDgbK/p1K9AOU PgzzGGGNO1VDrpPGU6rj/hwIIQ5e6WrZI2h6IVbnwvxOUpNUWkLpTbm0vkII91rZ3hjp 7vb85v2bT7JfLD5KoBO/1M4REcG3pt/eLR/n2zMi1C8ENXaRxKTa7qJrf3+/j01y/kov lA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3nm8x1ry8b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 08 Feb 2023 15:53:06 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 318Fr4IN032204 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 8 Feb 2023 15:53:04 GMT Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 07:52:57 -0800 From: Kathiravan T To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , Kathiravan T Subject: [PATCH V4 1/7] clk: qcom: Add STROMER PLUS PLL type for IPQ5332 Date: Wed, 8 Feb 2023 21:22:26 +0530 Message-ID: <20230208155232.11500-2-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208155232.11500-1-quic_kathirav@quicinc.com> References: <20230208155232.11500-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 06AOuWpQZuhw-ETWBvvU-89wy8ox1flw X-Proofpoint-ORIG-GUID: 06AOuWpQZuhw-ETWBvvU-89wy8ox1flw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-08_06,2023-02-08_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 mlxscore=0 suspectscore=0 malwarescore=0 mlxlogscore=816 lowpriorityscore=0 spamscore=0 impostorscore=0 adultscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302080141 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add the support for stromer plus pll, which is found on the IPQ5332 SoCs. Programming sequence is same as the stromer pll, so we can re-use the same. Reviewed-by: Stephen Boyd Signed-off-by: Kathiravan T --- Changes in V4: - No changes Changes in V3: - No changes Changes in V2: - Added the Reviewed-by tag drivers/clk/qcom/clk-alpha-pll.c | 11 +++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 14f9436b62fc..b9f6535a7ba7 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -216,6 +216,17 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x34, [PLL_OFF_STATUS] = 0x28, }, + [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_USER_CTL] = 0x08, + [PLL_OFF_USER_CTL_U] = 0x0c, + [PLL_OFF_CONFIG_CTL] = 0x10, + [PLL_OFF_TEST_CTL] = 0x14, + [PLL_OFF_TEST_CTL_U] = 0x18, + [PLL_OFF_STATUS] = 0x1c, + [PLL_OFF_ALPHA_VAL] = 0x24, + [PLL_OFF_ALPHA_VAL_U] = 0x28, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index ff25c7f7b43e..d07b17186b90 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -27,6 +27,7 @@ enum { CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, CLK_ALPHA_PLL_TYPE_STROMER, + CLK_ALPHA_PLL_TYPE_STROMER_PLUS, CLK_ALPHA_PLL_TYPE_MAX, }; From patchwork Wed Feb 8 15:52:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13133199 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9577CC64EC5 for ; Wed, 8 Feb 2023 15:53:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231536AbjBHPxu (ORCPT ); Wed, 8 Feb 2023 10:53:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230388AbjBHPxp (ORCPT ); Wed, 8 Feb 2023 10:53:45 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63C9323C5A; Wed, 8 Feb 2023 07:53:29 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 318DmIrE006825; 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Wed, 8 Feb 2023 15:53:12 GMT Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 07:53:04 -0800 From: Kathiravan T To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , Kathiravan T Subject: [PATCH V4 2/7] dt-bindings: clock: Add Qualcomm IPQ5332 GCC Date: Wed, 8 Feb 2023 21:22:27 +0530 Message-ID: <20230208155232.11500-3-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208155232.11500-1-quic_kathirav@quicinc.com> References: <20230208155232.11500-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: CUTorMh9SkmFCBrBemulwDIkxWwQvsfd X-Proofpoint-GUID: CUTorMh9SkmFCBrBemulwDIkxWwQvsfd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-08_06,2023-02-08_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 impostorscore=0 mlxscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 suspectscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302080141 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add binding for the Qualcomm IPQ5332 Global Clock Controller. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T --- Changes in V4: - Pick up the R-b tag Changes in V3: - Actually I missed to remove the clocks in V2 which are supposed to be removed. In V3 I have removed those and they are GCC_APSS_AHB_CLK, GCC_APSS_AHB_CLK_SRC, GCC_APSS_AXI_CLK - For the same, didn't add the Reviewed-By tags from Stephen and Krzysztof Changes in V2: - property 'clocks' is marked required - Renamed the include file name to match with compatible .../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +++ include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++ 2 files changed, 417 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml new file mode 100644 index 000000000000..961311af400c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ5332 + +maintainers: + - Stephen Boyd + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ5332. + + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,ipq5332-gcc + + clocks: + items: + - description: Board XO clock source + - description: Sleep clock source + - description: PCIE 2lane PHY pipe clock source + - description: PCIE 2lane x1 PHY pipe clock source (For second lane) + - description: USB PCIE wrapper pipe clock source + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: pcie_2lane_phy_pipe_clk + - const: pcie_2lane_phy_pipe_clk_x1 + - const: usb_pcie_wrapper_pipe_clk + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq5332-gcc"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board>, + <&sleep_clk>, + <&pcie_2lane_phy_pipe_clk>, + <&pcie_2lane_phy_pipe_clk_x1>, + <&usb_pcie_wrapper_pipe_clk>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h new file mode 100644 index 000000000000..8a405a0a96d0 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -0,0 +1,356 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H +#define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H + +#define GPLL0_MAIN 0 +#define GPLL0 1 +#define GPLL2_MAIN 2 +#define GPLL2 3 +#define GPLL4_MAIN 4 +#define GPLL4 5 +#define GCC_ADSS_PWM_CLK 6 +#define GCC_ADSS_PWM_CLK_SRC 7 +#define GCC_AHB_CLK 8 +#define GCC_APSS_AXI_CLK_SRC 9 +#define GCC_BLSP1_AHB_CLK 10 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 11 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 15 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 16 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 17 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 18 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 19 +#define GCC_BLSP1_SLEEP_CLK 20 +#define GCC_BLSP1_UART1_APPS_CLK 21 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 22 +#define GCC_BLSP1_UART2_APPS_CLK 23 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 24 +#define GCC_BLSP1_UART3_APPS_CLK 25 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 26 +#define GCC_CE_AHB_CLK 27 +#define GCC_CE_AXI_CLK 28 +#define GCC_CE_PCNOC_AHB_CLK 29 +#define GCC_CMN_12GPLL_AHB_CLK 30 +#define GCC_CMN_12GPLL_APU_CLK 31 +#define GCC_CMN_12GPLL_SYS_CLK 32 +#define GCC_GP1_CLK 33 +#define GCC_GP1_CLK_SRC 34 +#define GCC_GP2_CLK 35 +#define GCC_GP2_CLK_SRC 36 +#define GCC_LPASS_CORE_AXIM_CLK 37 +#define GCC_LPASS_SWAY_CLK 38 +#define GCC_LPASS_SWAY_CLK_SRC 39 +#define GCC_MDIO_AHB_CLK 40 +#define GCC_MDIO_SLAVE_AHB_CLK 41 +#define GCC_MEM_NOC_Q6_AXI_CLK 42 +#define GCC_MEM_NOC_TS_CLK 43 +#define GCC_NSS_TS_CLK 44 +#define GCC_NSS_TS_CLK_SRC 45 +#define GCC_NSSCC_CLK 46 +#define GCC_NSSCFG_CLK 47 +#define GCC_NSSNOC_ATB_CLK 48 +#define GCC_NSSNOC_NSSCC_CLK 49 +#define GCC_NSSNOC_QOSGEN_REF_CLK 50 +#define GCC_NSSNOC_SNOC_1_CLK 51 +#define GCC_NSSNOC_SNOC_CLK 52 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 53 +#define GCC_NSSNOC_XO_DCD_CLK 54 +#define GCC_PCIE3X1_0_AHB_CLK 55 +#define GCC_PCIE3X1_0_AUX_CLK 56 +#define GCC_PCIE3X1_0_AXI_CLK_SRC 57 +#define GCC_PCIE3X1_0_AXI_M_CLK 58 +#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK 59 +#define GCC_PCIE3X1_0_AXI_S_CLK 60 +#define GCC_PCIE3X1_0_PIPE_CLK 61 +#define GCC_PCIE3X1_0_RCHG_CLK 62 +#define GCC_PCIE3X1_0_RCHG_CLK_SRC 63 +#define GCC_PCIE3X1_1_AHB_CLK 64 +#define GCC_PCIE3X1_1_AUX_CLK 65 +#define GCC_PCIE3X1_1_AXI_CLK_SRC 66 +#define GCC_PCIE3X1_1_AXI_M_CLK 67 +#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK 68 +#define GCC_PCIE3X1_1_AXI_S_CLK 69 +#define GCC_PCIE3X1_1_PIPE_CLK 70 +#define GCC_PCIE3X1_1_RCHG_CLK 71 +#define GCC_PCIE3X1_1_RCHG_CLK_SRC 72 +#define GCC_PCIE3X1_PHY_AHB_CLK 73 +#define GCC_PCIE3X2_AHB_CLK 74 +#define GCC_PCIE3X2_AUX_CLK 75 +#define GCC_PCIE3X2_AXI_M_CLK 76 +#define GCC_PCIE3X2_AXI_M_CLK_SRC 77 +#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK 78 +#define GCC_PCIE3X2_AXI_S_CLK 79 +#define GCC_PCIE3X2_AXI_S_CLK_SRC 80 +#define GCC_PCIE3X2_PHY_AHB_CLK 81 +#define GCC_PCIE3X2_PIPE_CLK 82 +#define GCC_PCIE3X2_RCHG_CLK 83 +#define GCC_PCIE3X2_RCHG_CLK_SRC 84 +#define GCC_PCIE_AUX_CLK_SRC 85 +#define GCC_PCNOC_AT_CLK 86 +#define GCC_PCNOC_BFDCD_CLK_SRC 87 +#define GCC_PCNOC_LPASS_CLK 88 +#define GCC_PRNG_AHB_CLK 89 +#define GCC_Q6_AHB_CLK 90 +#define GCC_Q6_AHB_S_CLK 91 +#define GCC_Q6_AXIM_CLK 92 +#define GCC_Q6_AXIM_CLK_SRC 93 +#define GCC_Q6_AXIS_CLK 94 +#define GCC_Q6_TSCTR_1TO2_CLK 95 +#define GCC_Q6SS_ATBM_CLK 96 +#define GCC_Q6SS_PCLKDBG_CLK 97 +#define GCC_Q6SS_TRIG_CLK 98 +#define GCC_QDSS_AT_CLK 99 +#define GCC_QDSS_AT_CLK_SRC 100 +#define GCC_QDSS_CFG_AHB_CLK 101 +#define GCC_QDSS_DAP_AHB_CLK 102 +#define GCC_QDSS_DAP_CLK 103 +#define GCC_QDSS_DAP_DIV_CLK_SRC 104 +#define GCC_QDSS_ETR_USB_CLK 105 +#define GCC_QDSS_EUD_AT_CLK 106 +#define GCC_QDSS_TSCTR_CLK_SRC 107 +#define GCC_QPIC_AHB_CLK 108 +#define GCC_QPIC_CLK 109 +#define GCC_QPIC_IO_MACRO_CLK 110 +#define GCC_QPIC_IO_MACRO_CLK_SRC 111 +#define GCC_QPIC_SLEEP_CLK 112 +#define GCC_SDCC1_AHB_CLK 113 +#define GCC_SDCC1_APPS_CLK 114 +#define GCC_SDCC1_APPS_CLK_SRC 115 +#define GCC_SLEEP_CLK_SRC 116 +#define GCC_SNOC_LPASS_CFG_CLK 117 +#define GCC_SNOC_NSSNOC_1_CLK 118 +#define GCC_SNOC_NSSNOC_CLK 119 +#define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120 +#define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121 +#define GCC_SNOC_PCIE3_1LANE_M_CLK 122 +#define GCC_SNOC_PCIE3_1LANE_S_CLK 123 +#define GCC_SNOC_PCIE3_2LANE_M_CLK 124 +#define GCC_SNOC_PCIE3_2LANE_S_CLK 125 +#define GCC_SNOC_USB_CLK 126 +#define GCC_SYS_NOC_AT_CLK 127 +#define GCC_SYS_NOC_WCSS_AHB_CLK 128 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129 +#define GCC_UNIPHY0_AHB_CLK 130 +#define GCC_UNIPHY0_SYS_CLK 131 +#define GCC_UNIPHY1_AHB_CLK 132 +#define GCC_UNIPHY1_SYS_CLK 133 +#define GCC_UNIPHY_SYS_CLK_SRC 134 +#define GCC_USB0_AUX_CLK 135 +#define GCC_USB0_AUX_CLK_SRC 136 +#define GCC_USB0_EUD_AT_CLK 137 +#define GCC_USB0_LFPS_CLK 138 +#define GCC_USB0_LFPS_CLK_SRC 139 +#define GCC_USB0_MASTER_CLK 140 +#define GCC_USB0_MASTER_CLK_SRC 141 +#define GCC_USB0_MOCK_UTMI_CLK 142 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 143 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 144 +#define GCC_USB0_PHY_CFG_AHB_CLK 145 +#define GCC_USB0_PIPE_CLK 146 +#define GCC_USB0_SLEEP_CLK 147 +#define GCC_WCSS_AHB_CLK_SRC 148 +#define GCC_WCSS_AXIM_CLK 149 +#define GCC_WCSS_AXIS_CLK 150 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 151 +#define GCC_WCSS_DBG_IFC_APB_CLK 152 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 153 +#define GCC_WCSS_DBG_IFC_ATB_CLK 154 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 155 +#define GCC_WCSS_DBG_IFC_NTS_CLK 156 +#define GCC_WCSS_ECAHB_CLK 157 +#define GCC_WCSS_MST_ASYNC_BDG_CLK 158 +#define GCC_WCSS_SLV_ASYNC_BDG_CLK 159 +#define GCC_XO_CLK 160 +#define GCC_XO_CLK_SRC 161 +#define GCC_XO_DIV4_CLK 162 +#define GCC_IM_SLEEP_CLK 163 +#define GCC_NSSNOC_PCNOC_1_CLK 164 +#define GCC_MEM_NOC_AHB_CLK 165 +#define GCC_MEM_NOC_APSS_AXI_CLK 166 +#define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC 167 +#define GCC_MEM_NOC_QOSGEN_EXTREF_CLK 168 +#define GCC_PCIE3X2_PIPE_CLK_SRC 169 +#define GCC_PCIE3X1_0_PIPE_CLK_SRC 170 +#define GCC_PCIE3X1_1_PIPE_CLK_SRC 171 +#define GCC_USB0_PIPE_CLK_SRC 172 + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_CLK_ARES 1 +#define GCC_AHB_CLK_ARES 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 3 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 4 +#define GCC_APSS_AHB_CLK_ARES 5 +#define GCC_APSS_AXI_CLK_ARES 6 +#define GCC_BLSP1_AHB_CLK_ARES 7 +#define GCC_BLSP1_BCR 8 +#define GCC_BLSP1_QUP1_BCR 9 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES 10 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES 11 +#define GCC_BLSP1_QUP2_BCR 12 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES 13 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES 14 +#define GCC_BLSP1_QUP3_BCR 15 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES 16 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES 17 +#define GCC_BLSP1_SLEEP_CLK_ARES 18 +#define GCC_BLSP1_UART1_APPS_CLK_ARES 19 +#define GCC_BLSP1_UART1_BCR 20 +#define GCC_BLSP1_UART2_APPS_CLK_ARES 21 +#define GCC_BLSP1_UART2_BCR 22 +#define GCC_BLSP1_UART3_APPS_CLK_ARES 23 +#define GCC_BLSP1_UART3_BCR 24 +#define GCC_CE_BCR 25 +#define GCC_CMN_BLK_BCR 26 +#define GCC_CMN_LDO0_BCR 27 +#define GCC_CMN_LDO1_BCR 28 +#define GCC_DCC_BCR 29 +#define GCC_GP1_CLK_ARES 30 +#define GCC_GP2_CLK_ARES 31 +#define GCC_LPASS_BCR 32 +#define GCC_LPASS_CORE_AXIM_CLK_ARES 33 +#define GCC_LPASS_SWAY_CLK_ARES 34 +#define GCC_MDIOM_BCR 35 +#define GCC_MDIOS_BCR 36 +#define GCC_NSS_BCR 37 +#define GCC_NSS_TS_CLK_ARES 38 +#define GCC_NSSCC_CLK_ARES 39 +#define GCC_NSSCFG_CLK_ARES 40 +#define GCC_NSSNOC_ATB_CLK_ARES 41 +#define GCC_NSSNOC_NSSCC_CLK_ARES 42 +#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 43 +#define GCC_NSSNOC_SNOC_1_CLK_ARES 44 +#define GCC_NSSNOC_SNOC_CLK_ARES 45 +#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 46 +#define GCC_NSSNOC_XO_DCD_CLK_ARES 47 +#define GCC_PCIE3X1_0_AHB_CLK_ARES 48 +#define GCC_PCIE3X1_0_AUX_CLK_ARES 49 +#define GCC_PCIE3X1_0_AXI_M_CLK_ARES 50 +#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES 51 +#define GCC_PCIE3X1_0_AXI_S_CLK_ARES 52 +#define GCC_PCIE3X1_0_BCR 53 +#define GCC_PCIE3X1_0_LINK_DOWN_BCR 54 +#define GCC_PCIE3X1_0_PHY_BCR 55 +#define GCC_PCIE3X1_0_PHY_PHY_BCR 56 +#define GCC_PCIE3X1_1_AHB_CLK_ARES 57 +#define GCC_PCIE3X1_1_AUX_CLK_ARES 58 +#define GCC_PCIE3X1_1_AXI_M_CLK_ARES 59 +#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES 60 +#define GCC_PCIE3X1_1_AXI_S_CLK_ARES 61 +#define GCC_PCIE3X1_1_BCR 62 +#define GCC_PCIE3X1_1_LINK_DOWN_BCR 63 +#define GCC_PCIE3X1_1_PHY_BCR 64 +#define GCC_PCIE3X1_1_PHY_PHY_BCR 65 +#define GCC_PCIE3X1_PHY_AHB_CLK_ARES 66 +#define GCC_PCIE3X2_AHB_CLK_ARES 67 +#define GCC_PCIE3X2_AUX_CLK_ARES 68 +#define GCC_PCIE3X2_AXI_M_CLK_ARES 69 +#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES 70 +#define GCC_PCIE3X2_AXI_S_CLK_ARES 71 +#define GCC_PCIE3X2_BCR 72 +#define GCC_PCIE3X2_LINK_DOWN_BCR 73 +#define GCC_PCIE3X2_PHY_AHB_CLK_ARES 74 +#define GCC_PCIE3X2_PHY_BCR 75 +#define GCC_PCIE3X2PHY_PHY_BCR 76 +#define GCC_PCNOC_BCR 77 +#define GCC_PCNOC_LPASS_CLK_ARES 78 +#define GCC_PRNG_AHB_CLK_ARES 79 +#define GCC_PRNG_BCR 80 +#define GCC_Q6_AHB_CLK_ARES 81 +#define GCC_Q6_AHB_S_CLK_ARES 82 +#define GCC_Q6_AXIM_CLK_ARES 83 +#define GCC_Q6_AXIS_CLK_ARES 84 +#define GCC_Q6_TSCTR_1TO2_CLK_ARES 85 +#define GCC_Q6SS_ATBM_CLK_ARES 86 +#define GCC_Q6SS_PCLKDBG_CLK_ARES 87 +#define GCC_Q6SS_TRIG_CLK_ARES 88 +#define GCC_QDSS_APB2JTAG_CLK_ARES 89 +#define GCC_QDSS_AT_CLK_ARES 90 +#define GCC_QDSS_BCR 91 +#define GCC_QDSS_CFG_AHB_CLK_ARES 92 +#define GCC_QDSS_DAP_AHB_CLK_ARES 93 +#define GCC_QDSS_DAP_CLK_ARES 94 +#define GCC_QDSS_ETR_USB_CLK_ARES 95 +#define GCC_QDSS_EUD_AT_CLK_ARES 96 +#define GCC_QDSS_STM_CLK_ARES 97 +#define GCC_QDSS_TRACECLKIN_CLK_ARES 98 +#define GCC_QDSS_TS_CLK_ARES 99 +#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 100 +#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 101 +#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 102 +#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 103 +#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 104 +#define GCC_QPIC_AHB_CLK_ARES 105 +#define GCC_QPIC_CLK_ARES 106 +#define GCC_QPIC_BCR 107 +#define GCC_QPIC_IO_MACRO_CLK_ARES 108 +#define GCC_QPIC_SLEEP_CLK_ARES 109 +#define GCC_QUSB2_0_PHY_BCR 110 +#define GCC_SDCC1_AHB_CLK_ARES 111 +#define GCC_SDCC1_APPS_CLK_ARES 112 +#define GCC_SDCC_BCR 113 +#define GCC_SNOC_BCR 114 +#define GCC_SNOC_LPASS_CFG_CLK_ARES 115 +#define GCC_SNOC_NSSNOC_1_CLK_ARES 116 +#define GCC_SNOC_NSSNOC_CLK_ARES 117 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES 118 +#define GCC_SYS_NOC_WCSS_AHB_CLK_ARES 119 +#define GCC_UNIPHY0_AHB_CLK_ARES 120 +#define GCC_UNIPHY0_BCR 121 +#define GCC_UNIPHY0_SYS_CLK_ARES 122 +#define GCC_UNIPHY1_AHB_CLK_ARES 123 +#define GCC_UNIPHY1_BCR 124 +#define GCC_UNIPHY1_SYS_CLK_ARES 125 +#define GCC_USB0_AUX_CLK_ARES 126 +#define GCC_USB0_EUD_AT_CLK_ARES 127 +#define GCC_USB0_LFPS_CLK_ARES 128 +#define GCC_USB0_MASTER_CLK_ARES 129 +#define GCC_USB0_MOCK_UTMI_CLK_ARES 130 +#define GCC_USB0_PHY_BCR 131 +#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 132 +#define GCC_USB0_SLEEP_CLK_ARES 133 +#define GCC_USB3PHY_0_PHY_BCR 134 +#define GCC_USB_BCR 135 +#define GCC_WCSS_AXIM_CLK_ARES 136 +#define GCC_WCSS_AXIS_CLK_ARES 137 +#define GCC_WCSS_BCR 138 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES 139 +#define GCC_WCSS_DBG_IFC_APB_CLK_ARES 140 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES 141 +#define GCC_WCSS_DBG_IFC_ATB_CLK_ARES 142 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES 143 +#define GCC_WCSS_DBG_IFC_NTS_CLK_ARES 144 +#define GCC_WCSS_ECAHB_CLK_ARES 145 +#define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES 146 +#define GCC_WCSS_Q6_BCR 147 +#define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES 148 +#define GCC_XO_CLK_ARES 149 +#define GCC_XO_DIV4_CLK_ARES 150 +#define GCC_Q6SS_DBG_ARES 151 +#define GCC_WCSS_DBG_BDG_ARES 152 +#define GCC_WCSS_DBG_ARES 153 +#define GCC_WCSS_AXI_S_ARES 154 +#define GCC_WCSS_AXI_M_ARES 155 +#define GCC_WCSSAON_ARES 156 +#define GCC_PCIE3X2_PIPE_ARES 157 +#define GCC_PCIE3X2_CORE_STICKY_ARES 158 +#define GCC_PCIE3X2_AXI_S_STICKY_ARES 159 +#define GCC_PCIE3X2_AXI_M_STICKY_ARES 160 +#define GCC_PCIE3X1_0_PIPE_ARES 161 +#define GCC_PCIE3X1_0_CORE_STICKY_ARES 162 +#define GCC_PCIE3X1_0_AXI_S_STICKY_ARES 163 +#define GCC_PCIE3X1_0_AXI_M_STICKY_ARES 164 +#define GCC_PCIE3X1_1_PIPE_ARES 165 +#define GCC_PCIE3X1_1_CORE_STICKY_ARES 166 +#define GCC_PCIE3X1_1_AXI_S_STICKY_ARES 167 +#define GCC_PCIE3X1_1_AXI_M_STICKY_ARES 168 +#define GCC_IM_SLEEP_CLK_ARES 169 +#define GCC_NSSNOC_PCNOC_1_CLK_ARES 170 +#define GCC_UNIPHY0_XPCS_ARES 171 +#define GCC_UNIPHY1_XPCS_ARES 172 +#endif From patchwork Wed Feb 8 15:52:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13133200 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D688C05027 for ; Wed, 8 Feb 2023 15:54:18 +0000 (UTC) Received: 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Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 07:53:20 -0800 From: Kathiravan T To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , Kathiravan T Subject: [PATCH V4 4/7] dt-bindings: qcom: add ipq5332 boards Date: Wed, 8 Feb 2023 21:22:29 +0530 Message-ID: <20230208155232.11500-5-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208155232.11500-1-quic_kathirav@quicinc.com> References: <20230208155232.11500-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: wZCc0YLEr22YwdTo3kVTKPWJeIYf2khA X-Proofpoint-ORIG-GUID: wZCc0YLEr22YwdTo3kVTKPWJeIYf2khA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-08_06,2023-02-08_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 clxscore=1015 suspectscore=0 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302080141 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Document the new ipq5332 SoC/board device tree bindings Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T --- Changes in V4: - Pick up R-b tag Changes in V3: - Sorted the board name Changes in V2: - No changes Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 8b90b8d7e858..b74d63b17f5f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -30,6 +30,7 @@ description: | apq8084 apq8096 ipq4018 + ipq5332 ipq6018 ipq8074 mdm9615 @@ -79,6 +80,7 @@ description: | The 'board' element must be one of the following strings: adp + ap-mi01.2 cdp cp01-c1 dragonboard @@ -316,6 +318,11 @@ properties: - qcom,ipq4019-dk04.1-c1 - const: qcom,ipq4019 + - items: + - enum: + - qcom,ipq5332-ap-mi01.2 + - const: qcom,ipq5332 + - items: - enum: - mikrotik,rb3011 From patchwork Wed Feb 8 15:52:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13133201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D814C64EC7 for ; Wed, 8 Feb 2023 15:54:51 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Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 07:53:28 -0800 From: Kathiravan T To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , Kathiravan T Subject: [PATCH V4 5/7] dt-bindings: firmware: qcom,scm: document IPQ5332 SCM Date: Wed, 8 Feb 2023 21:22:30 +0530 Message-ID: <20230208155232.11500-6-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208155232.11500-1-quic_kathirav@quicinc.com> References: <20230208155232.11500-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Hp1WT_Li2AxgTngKCgFAc98ivY8KrC9i X-Proofpoint-ORIG-GUID: Hp1WT_Li2AxgTngKCgFAc98ivY8KrC9i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-08_06,2023-02-08_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 malwarescore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 adultscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302080141 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Document the compatible for IPQ5332 SCM. Acked-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T --- Changes in V4: - No changes Changes in V3: - No changes Changes in V2: - Added the 'Acked-by' tag Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 4193492ba73e..02354d06e054 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -24,6 +24,7 @@ properties: - qcom,scm-apq8064 - qcom,scm-apq8084 - qcom,scm-ipq4019 + - qcom,scm-ipq5332 - qcom,scm-ipq6018 - qcom,scm-ipq806x - qcom,scm-ipq8074 From patchwork Wed Feb 8 15:52:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13133202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF307C636D4 for ; Wed, 8 Feb 2023 15:54:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231817AbjBHPyU (ORCPT ); Wed, 8 Feb 2023 10:54:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231749AbjBHPyN (ORCPT ); Wed, 8 Feb 2023 10:54:13 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38ED34B751; Wed, 8 Feb 2023 07:54:01 -0800 (PST) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 318Dx1GE006150; Wed, 8 Feb 2023 15:53:45 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=ylibF7WCkGiQ4f8yNm6r7qjwPcadFSkgL0ozVfTr+Bw=; b=CLufxmGpbw1tzD3wnoz4TJeCorPPbL/Itdnjir4ucHz2a6PoGiBQKGpeiTg7NQtj4t1j ZmtZLiYqQBvN4z8PhlDZ9aGTXdAokKXF+RRgeJrQE/AQgprck50S2TaPrmTIcwSTSU4q 1xahJyIxLWK4EEaSPnq5m1kgPA37tPmFCqNT+yHr9XRYfkfPzjy8oaAf6TjzUFjAoTBf 1ZV5ARxEqBMI7G5oAeAD96NI+cEuibbrB1zcOF+SkIRoC4SBP5jwX7ROL6jXAUd6929b IEFP1SZNSsj6ObPGA0r8m7/rCTDwGGwDlq2n9FQvavIBWP7svmvdOTnX8zedZpzfoefO Gw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3nmb8jrms4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 08 Feb 2023 15:53:44 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 318Frits015370 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 8 Feb 2023 15:53:44 GMT Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 07:53:36 -0800 From: Kathiravan T To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , Kathiravan T Subject: [PATCH V4 6/7] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support Date: Wed, 8 Feb 2023 21:22:31 +0530 Message-ID: <20230208155232.11500-7-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208155232.11500-1-quic_kathirav@quicinc.com> References: <20230208155232.11500-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: QiVR_tCqPe0fVv3EZ44oHnHoSc2y8lmp X-Proofpoint-GUID: QiVR_tCqPe0fVv3EZ44oHnHoSc2y8lmp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-08_06,2023-02-08_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 mlxscore=0 spamscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302080141 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add initial device tree support for the Qualcomm IPQ5332 SoC and MI01.2 board. Signed-off-by: Kathiravan T --- Changes in V4: - No changes Changes in V3: - Updated the V2M node name to reflect the proper address - In reserved-memory node, changed the order of the 'reg' and 'no-map' property - Moved the below properties to the board DTS bus-width = <4>; max-frequency = <192000000>; mmc-ddr-1_8v; mmc-hs200-1_8v; Changes in V2: - Changed the license to BSD3 in the file ipq5332-mi01.2.dts - Updated the model name, not to include the foundry ID - Used the decimal notation instead of hex for 'cache-level' property - Dropped the blank line - Updated the node name for the TZ reserved region - Moved the 'compatible' property as first one in the node, wherever applicable - Used the decimal notation for *-cells property insrtead of hex - Reorganised the properties of memory mapped timer node as below - reg - interrupts - frame-number - Fixed the indentation in timer node arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 75 ++++++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 ++++++++++++++++++++ 3 files changed, 344 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 359e428e49b3..11f0f16cbb9a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts new file mode 100644 index 000000000000..702013b867d7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 AP-MI01.2 board device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; + compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc { + bus-width = <4>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi new file mode 100644 index 000000000000..bdf33ef30e10 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-ipq5332", "qcom,scm"; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x40000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_mem: tz@4a600000 { + reg = <0x0 0x4a600000 0x0 0x200000>; + no-map; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5332-tlmm"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 53>; + interrupt-controller; + #interrupt-cells = <2>; + + serial_0_pins: serial0-state { + pins = "gpio18", "gpio19"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,ipq5332-gcc"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "xo", + "sleep_clk", + "pcie_2lane_phy_pipe_clk", + "pcie_2lane_phy_pipe_clk_x1", + "usb_pcie_wrapper_pipe_clk"; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>; + }; + + sdhc: mmc@7804000 { + compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x07804000 0x1000>, <0x07805000 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + status = "disabled"; + }; + + blsp1_uart0: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ + <0x0b002000 0x1000>, /* GICC */ + <0x0b001000 0x1000>, /* GICH */ + <0x0b004000 0x1000>; /* GICV */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0b00c000 0x3000>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00000000 0xffd>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00001000 0xffd>; + msi-controller; + }; + + v2m2: v2m@2000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00002000 0xffd>; + msi-controller; + }; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b120000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From patchwork Wed Feb 8 15:52:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13133203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8098FC636D4 for ; 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Wed, 08 Feb 2023 15:53:52 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 318FrpHO015402 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 8 Feb 2023 15:53:51 GMT Received: from kathirav-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 07:53:44 -0800 From: Kathiravan T To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , Kathiravan T Subject: [PATCH V4 7/7] arm64: defconfig: Enable IPQ5332 SoC base configs Date: Wed, 8 Feb 2023 21:22:32 +0530 Message-ID: <20230208155232.11500-8-quic_kathirav@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230208155232.11500-1-quic_kathirav@quicinc.com> References: <20230208155232.11500-1-quic_kathirav@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hsSeNqW_wQWVU9YcEIUCSsSXIyPb7sWc X-Proofpoint-GUID: hsSeNqW_wQWVU9YcEIUCSsSXIyPb7sWc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-02-08_06,2023-02-08_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 mlxlogscore=848 lowpriorityscore=0 priorityscore=1501 phishscore=0 impostorscore=0 mlxscore=0 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302080141 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Enable the clock and pinctrl configs for Qualcomm IPQ5332 SoC Reviewed-by: Dmitry Baryshkov Signed-off-by: Kathiravan T --- Changed in V4: - Pick up R-b tag Changes in V3: - Updated the commit message Changed in V2: - No changes arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 695c4e44d241..8a5ec6093c7d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -555,6 +555,7 @@ CONFIG_PINCTRL_IMX8ULP=y CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ8074=y +CONFIG_PINCTRL_IPQ5332=y CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_MSM8953=y @@ -1131,6 +1132,7 @@ CONFIG_QCOM_CLK_APCS_MSM8916=y CONFIG_QCOM_CLK_APCC_MSM8996=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y +CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y CONFIG_MSM_GCC_8916=y