From patchwork Wed Feb 8 20:00:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 13133656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90C08C636D6 for ; Wed, 8 Feb 2023 20:00:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231549AbjBHUAs (ORCPT ); Wed, 8 Feb 2023 15:00:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231330AbjBHUAr (ORCPT ); Wed, 8 Feb 2023 15:00:47 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E726139CD1 for ; Wed, 8 Feb 2023 12:00:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675886443; x=1707422443; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=KaRzxRlvB9BcP0nu0QZVD/lvIYofxBcR+epWn7ufvY0=; b=DDdyLqe0nCpRWGcOUg0isPhZG0fimNd/K7DB0Jyf88ZeztXfrBuwjF+q ySzKJ6IaJIW+Z/S8U+WROHZmerCLzuJrhpsGvt6FZIx82YVcTU9IfIb9Y yLc1o0aTa3JXVJbPROq4GCVDKokn5eoyCv2C7ehfztufyiI3UcsAB+9Cs QP09oYbx7i29CG8EoVXpu0ZOn4JOAJjthA5VSgi661n4DsRy5DNEuqhlM VRXjD8k5TG8lmCYjgRSbez0dM79DmS+cSV70anss5vAwnc9bw0dAzACgx V4Qx2VxBRcZG+Znh5Ss6zeb+t/a/7HhjKCN4FOvk0v9uCZvVrKSPOkP7c Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="329935452" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="329935452" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:42 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="776174665" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="776174665" Received: from laarmstr-mobl.amr.corp.intel.com (HELO vverma7-desk1.local) ([10.251.6.109]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:42 -0800 From: Vishal Verma Date: Wed, 08 Feb 2023 13:00:29 -0700 Subject: [PATCH ndctl v2 1/7] cxl/region: skip region_actions for region creation MIME-Version: 1.0 Message-Id: <20230120-vv-volatile-regions-v2-1-4ea6253000e5@intel.com> References: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> In-Reply-To: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> To: linux-cxl@vger.kernel.org Cc: Gregory Price , Jonathan Cameron , Davidlohr Bueso , Dan Williams , Vishal Verma , nvdimm@lists.linux.dev, Ira Weiny X-Mailer: b4 0.13-dev-ada30 X-Developer-Signature: v=1; a=openpgp-sha256; l=1701; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=KaRzxRlvB9BcP0nu0QZVD/lvIYofxBcR+epWn7ufvY0=; b=owGbwMvMwCXGf25diOft7jLG02pJDMmP/2cuedrLONf39nU/2YL5sonFfCbeCpF3/KT3at06p Sn4NSS4o5SFQYyLQVZMkeXvno+Mx+S25/MEJjjCzGFlAhnCwMUpABMpFGL4pyWlv2i3kMLrrD7P 4pjEiafu7Uk2v2F2ePscu7n97/nmTmdk+Pdd2UVPRk3J+5nENMcDOZM8dx5s6vDg/mmUZjhz1pN vHAA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Commit 3d6cd829ec08 ("cxl/region: Use cxl_filter_walk() to gather create-region targets") removed the early return for create-region, and this caused a create-region operation to unnecessarily loop through buses and root decoders only to EINVAL out because ACTION_CREATE is handled outside of the other actions. This results in confusing messages such as: # cxl create-region -t ram -d 0.0 -m 0,4 { "region":"region7", "resource":"0xf030000000", "size":"512.00 MiB (536.87 MB)", ... } cxl region: decoder_region_action: region0: failed: Invalid argument cxl region: region_action: one or more failures, last failure: Invalid argument cxl region: cmd_create_region: created 1 region Since there's no need to walk through the topology after creating a region, and especially not to perform an invalid 'action', switch back to returning early for create-region. Fixes: 3d6cd829ec08 ("cxl/region: Use cxl_filter_walk() to gather create-region targets") Cc: Dan Williams Reviewed-by: Dan Williams Reviewed-by: Ira Weiny Signed-off-by: Vishal Verma --- cxl/region.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cxl/region.c b/cxl/region.c index efe05aa..38aa142 100644 --- a/cxl/region.c +++ b/cxl/region.c @@ -789,7 +789,7 @@ static int region_action(int argc, const char **argv, struct cxl_ctx *ctx, return rc; if (action == ACTION_CREATE) - rc = create_region(ctx, count, p); + return create_region(ctx, count, p); cxl_bus_foreach(ctx, bus) { struct cxl_decoder *decoder; From patchwork Wed Feb 8 20:00:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 13133657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A14D7C636D3 for ; Wed, 8 Feb 2023 20:00:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229582AbjBHUAw (ORCPT ); Wed, 8 Feb 2023 15:00:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231330AbjBHUAv (ORCPT ); Wed, 8 Feb 2023 15:00:51 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 231B532506 for ; Wed, 8 Feb 2023 12:00:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675886445; x=1707422445; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=8hK5Al9UALbv4ZwmwWP/1InDqHqxyjYu1ZTySNiyJ7g=; b=BiWkGiQUCDqiaPBMTU0dhraM28eFK8YN9aXA8MUdryMQmaX+tzkYOr87 VynQbPUB3vMfB+j8D1ZBwQ/P1Jb2qhcbYzqTAnUr3faVlOwdNG3Tq3OCI 9GD0Rh30zMyc9Os3AjBwDlkQ+cEj+ONMPv42Nqmr5jvtya3cRYDQQHw+N abDVvXCSdz1gaj+XVuoN2VufWwQ/95OQfAODRGODTwoQTf/Eg0yypDGxq qGe2bvTroMhbEtc0tN9kMLqEczE6Ewjws79GAi6J8aQ7IVoega4+XYhVK RwIwZjWbJx0YJ7KdAkS2Xo5nvXK6C/RifPFRmJCFntd5BeKfdj2mxNEU9 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="329935458" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="329935458" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:43 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="776174670" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="776174670" Received: from laarmstr-mobl.amr.corp.intel.com (HELO vverma7-desk1.local) ([10.251.6.109]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:42 -0800 From: Vishal Verma Date: Wed, 08 Feb 2023 13:00:30 -0700 Subject: [PATCH ndctl v2 2/7] cxl: add a type attribute to region listings MIME-Version: 1.0 Message-Id: <20230120-vv-volatile-regions-v2-2-4ea6253000e5@intel.com> References: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> In-Reply-To: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> To: linux-cxl@vger.kernel.org Cc: Gregory Price , Jonathan Cameron , Davidlohr Bueso , Dan Williams , Vishal Verma , nvdimm@lists.linux.dev, Ira Weiny X-Mailer: b4 0.13-dev-ada30 X-Developer-Signature: v=1; a=openpgp-sha256; l=4978; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=8hK5Al9UALbv4ZwmwWP/1InDqHqxyjYu1ZTySNiyJ7g=; b=owGbwMvMwCXGf25diOft7jLG02pJDMmP/2c6656+onzyV5iv6veYmj/uyj1SU7+KLhR52/Go+ XWrwIGejlIWBjEuBlkxRZa/ez4yHpPbns8TmOAIM4eVCWQIAxenAEyk9iDD/5D7K9bPbvPSK2aq ORx+7TlDpvqT9BNTWDu+7HhXZ9O+7ygjw52zFukdbGvWv2VfPyNCL9eo8Un1hSfLr8trNWw6feX pWk4A X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org In preparation for enumerating and creating 'volatile' or 'ram' type regions, add a 'type' attribute to region listings, so these can be distinguished from 'pmem' type regions easily. This depends on a new 'mode' attribute for region objects in sysfs. For older kernels that lack this, region listings will simply omit emitting this attribute, but otherwise not treat it as a failure. Cc: Dan Williams Reviewed-by: Dan Williams Reviewed-by: Ira Weiny Signed-off-by: Vishal Verma --- Documentation/cxl/lib/libcxl.txt | 1 + cxl/lib/private.h | 1 + cxl/lib/libcxl.c | 11 +++++++++++ cxl/libcxl.h | 1 + cxl/json.c | 7 +++++++ cxl/lib/libcxl.sym | 5 +++++ 6 files changed, 26 insertions(+) diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt index f9af376..dbc4b56 100644 --- a/Documentation/cxl/lib/libcxl.txt +++ b/Documentation/cxl/lib/libcxl.txt @@ -550,6 +550,7 @@ int cxl_region_get_id(struct cxl_region *region); const char *cxl_region_get_devname(struct cxl_region *region); void cxl_region_get_uuid(struct cxl_region *region, uuid_t uu); unsigned long long cxl_region_get_size(struct cxl_region *region); +enum cxl_decoder_mode cxl_region_get_mode(struct cxl_region *region); unsigned long long cxl_region_get_resource(struct cxl_region *region); unsigned int cxl_region_get_interleave_ways(struct cxl_region *region); unsigned int cxl_region_get_interleave_granularity(struct cxl_region *region); diff --git a/cxl/lib/private.h b/cxl/lib/private.h index f8871bd..306dc3a 100644 --- a/cxl/lib/private.h +++ b/cxl/lib/private.h @@ -149,6 +149,7 @@ struct cxl_region { unsigned int interleave_ways; unsigned int interleave_granularity; enum cxl_decode_state decode_state; + enum cxl_decoder_mode mode; struct kmod_module *module; struct list_head mappings; }; diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index 4205a58..83f628b 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -561,6 +561,12 @@ static void *add_cxl_region(void *parent, int id, const char *cxlregion_base) else region->decode_state = strtoul(buf, NULL, 0); + sprintf(path, "%s/mode", cxlregion_base); + if (sysfs_read_attr(ctx, path, buf) < 0) + region->mode = CXL_DECODER_MODE_NONE; + else + region->mode = cxl_decoder_mode_from_ident(buf); + sprintf(path, "%s/modalias", cxlregion_base); if (sysfs_read_attr(ctx, path, buf) == 0) region->module = util_modalias_to_module(ctx, buf); @@ -686,6 +692,11 @@ CXL_EXPORT unsigned long long cxl_region_get_resource(struct cxl_region *region) return region->start; } +CXL_EXPORT enum cxl_decoder_mode cxl_region_get_mode(struct cxl_region *region) +{ + return region->mode; +} + CXL_EXPORT unsigned int cxl_region_get_interleave_ways(struct cxl_region *region) { diff --git a/cxl/libcxl.h b/cxl/libcxl.h index d699af8..e6cca11 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -273,6 +273,7 @@ const char *cxl_region_get_devname(struct cxl_region *region); void cxl_region_get_uuid(struct cxl_region *region, uuid_t uu); unsigned long long cxl_region_get_size(struct cxl_region *region); unsigned long long cxl_region_get_resource(struct cxl_region *region); +enum cxl_decoder_mode cxl_region_get_mode(struct cxl_region *region); unsigned int cxl_region_get_interleave_ways(struct cxl_region *region); unsigned int cxl_region_get_interleave_granularity(struct cxl_region *region); struct cxl_decoder *cxl_region_get_target_decoder(struct cxl_region *region, diff --git a/cxl/json.c b/cxl/json.c index 0fc44e4..16b6cb8 100644 --- a/cxl/json.c +++ b/cxl/json.c @@ -827,6 +827,7 @@ void util_cxl_mappings_append_json(struct json_object *jregion, struct json_object *util_cxl_region_to_json(struct cxl_region *region, unsigned long flags) { + enum cxl_decoder_mode mode = cxl_region_get_mode(region); const char *devname = cxl_region_get_devname(region); struct json_object *jregion, *jobj; u64 val; @@ -853,6 +854,12 @@ struct json_object *util_cxl_region_to_json(struct cxl_region *region, json_object_object_add(jregion, "size", jobj); } + if (mode != CXL_DECODER_MODE_NONE) { + jobj = json_object_new_string(cxl_decoder_mode_name(mode)); + if (jobj) + json_object_object_add(jregion, "type", jobj); + } + val = cxl_region_get_interleave_ways(region); if (val < INT_MAX) { jobj = json_object_new_int(val); diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index 6bc0810..9832d09 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -242,3 +242,8 @@ global: cxl_target_get_firmware_node; cxl_dport_get_firmware_node; } LIBCXL_3; + +LIBCXL_5 { +global: + cxl_region_get_mode; +} LIBCXL_4; From patchwork Wed Feb 8 20:00:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 13133658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87F7BC05027 for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="329935465" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="329935465" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:44 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="776174674" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="776174674" Received: from laarmstr-mobl.amr.corp.intel.com (HELO vverma7-desk1.local) ([10.251.6.109]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:43 -0800 From: Vishal Verma Date: Wed, 08 Feb 2023 13:00:31 -0700 Subject: [PATCH ndctl v2 3/7] cxl: add core plumbing for creation of ram regions MIME-Version: 1.0 Message-Id: <20230120-vv-volatile-regions-v2-3-4ea6253000e5@intel.com> References: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> In-Reply-To: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> To: linux-cxl@vger.kernel.org Cc: Gregory Price , Jonathan Cameron , Davidlohr Bueso , Dan Williams , Vishal Verma , nvdimm@lists.linux.dev X-Mailer: b4 0.13-dev-ada30 X-Developer-Signature: v=1; a=openpgp-sha256; l=5741; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=tj30CiWrHmwuRBIF22lg+gB169wt098YpkJ/DZ2p6XY=; b=owGbwMvMwCXGf25diOft7jLG02pJDMmP/2eWPd3+KPLgsaJYJaWtq/meN+SctNusq/k+7XXTV KG/dVsvdJSyMIhxMciKKbL83fOR8Zjc9nyewARHmDmsTCBDGLg4BWAiRRmMDPPm8ale6cq9u/X6 DZnslcd29Ff4mJXePt7C0/Sj8NFWwWuMDMcispVmqzi/k2gxnGK17+CZLS5ZeznnLvNXmyWoNHG dBy8A X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Add support in libcxl to create ram regions through a new cxl_decoder_create_ram_region() API, which works similarly to its pmem sibling. Enable ram region creation in cxl-cli, with the only differences from the pmem flow being: 1/ Use the above create_ram_region API, and 2/ Elide setting the UUID, since ram regions don't have one Cc: Dan Williams Reviewed-by: Dan Williams Signed-off-by: Vishal Verma Reviewed-by: Ira Weiny Reviewed-by: Fan Ni --- Documentation/cxl/cxl-create-region.txt | 3 ++- cxl/lib/libcxl.c | 22 +++++++++++++++++++--- cxl/libcxl.h | 1 + cxl/region.c | 28 ++++++++++++++++++++++++---- cxl/lib/libcxl.sym | 1 + 5 files changed, 47 insertions(+), 8 deletions(-) diff --git a/Documentation/cxl/cxl-create-region.txt b/Documentation/cxl/cxl-create-region.txt index 286779e..ada0e52 100644 --- a/Documentation/cxl/cxl-create-region.txt +++ b/Documentation/cxl/cxl-create-region.txt @@ -80,7 +80,8 @@ include::bus-option.txt[] -U:: --uuid=:: Specify a UUID for the new region. This shouldn't usually need to be - specified, as one will be generated by default. + specified, as one will be generated by default. Only applicable to + pmem regions. -w:: --ways=:: diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index 83f628b..c5b9b18 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -2234,8 +2234,8 @@ cxl_decoder_get_region(struct cxl_decoder *decoder) return NULL; } -CXL_EXPORT struct cxl_region * -cxl_decoder_create_pmem_region(struct cxl_decoder *decoder) +static struct cxl_region *cxl_decoder_create_region(struct cxl_decoder *decoder, + enum cxl_decoder_mode mode) { struct cxl_ctx *ctx = cxl_decoder_get_ctx(decoder); char *path = decoder->dev_buf; @@ -2243,7 +2243,11 @@ cxl_decoder_create_pmem_region(struct cxl_decoder *decoder) struct cxl_region *region; int rc; - sprintf(path, "%s/create_pmem_region", decoder->dev_path); + if (mode == CXL_DECODER_MODE_PMEM) + sprintf(path, "%s/create_pmem_region", decoder->dev_path); + else if (mode == CXL_DECODER_MODE_RAM) + sprintf(path, "%s/create_ram_region", decoder->dev_path); + rc = sysfs_read_attr(ctx, path, buf); if (rc < 0) { err(ctx, "failed to read new region name: %s\n", @@ -2282,6 +2286,18 @@ cxl_decoder_create_pmem_region(struct cxl_decoder *decoder) return region; } +CXL_EXPORT struct cxl_region * +cxl_decoder_create_pmem_region(struct cxl_decoder *decoder) +{ + return cxl_decoder_create_region(decoder, CXL_DECODER_MODE_PMEM); +} + +CXL_EXPORT struct cxl_region * +cxl_decoder_create_ram_region(struct cxl_decoder *decoder) +{ + return cxl_decoder_create_region(decoder, CXL_DECODER_MODE_RAM); +} + CXL_EXPORT int cxl_decoder_get_nr_targets(struct cxl_decoder *decoder) { return decoder->nr_targets; diff --git a/cxl/libcxl.h b/cxl/libcxl.h index e6cca11..904156c 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -213,6 +213,7 @@ cxl_decoder_get_interleave_granularity(struct cxl_decoder *decoder); unsigned int cxl_decoder_get_interleave_ways(struct cxl_decoder *decoder); struct cxl_region *cxl_decoder_get_region(struct cxl_decoder *decoder); struct cxl_region *cxl_decoder_create_pmem_region(struct cxl_decoder *decoder); +struct cxl_region *cxl_decoder_create_ram_region(struct cxl_decoder *decoder); struct cxl_decoder *cxl_decoder_get_by_name(struct cxl_ctx *ctx, const char *ident); struct cxl_memdev *cxl_decoder_get_memdev(struct cxl_decoder *decoder); diff --git a/cxl/region.c b/cxl/region.c index 38aa142..c69cb9a 100644 --- a/cxl/region.c +++ b/cxl/region.c @@ -380,7 +380,18 @@ static void collect_minsize(struct cxl_ctx *ctx, struct parsed_params *p) struct json_object *jobj = json_object_array_get_idx(p->memdevs, i); struct cxl_memdev *memdev = json_object_get_userdata(jobj); - u64 size = cxl_memdev_get_pmem_size(memdev); + u64 size = 0; + + switch(p->mode) { + case CXL_DECODER_MODE_RAM: + size = cxl_memdev_get_ram_size(memdev); + break; + case CXL_DECODER_MODE_PMEM: + size = cxl_memdev_get_pmem_size(memdev); + break; + default: + /* Shouldn't ever get here */ ; + } if (!p->ep_min_size) p->ep_min_size = size; @@ -589,8 +600,15 @@ static int create_region(struct cxl_ctx *ctx, int *count, param.root_decoder); return -ENXIO; } + } else if (p->mode == CXL_DECODER_MODE_RAM) { + region = cxl_decoder_create_ram_region(p->root_decoder); + if (!region) { + log_err(&rl, "failed to create region under %s\n", + param.root_decoder); + return -ENXIO; + } } else { - log_err(&rl, "region type '%s' not supported yet\n", + log_err(&rl, "region type '%s' is not supported\n", param.type); return -EOPNOTSUPP; } @@ -602,10 +620,12 @@ static int create_region(struct cxl_ctx *ctx, int *count, goto out; granularity = rc; - uuid_generate(uuid); try(cxl_region, set_interleave_granularity, region, granularity); try(cxl_region, set_interleave_ways, region, p->ways); - try(cxl_region, set_uuid, region, uuid); + if (p->mode == CXL_DECODER_MODE_PMEM) { + uuid_generate(uuid); + try(cxl_region, set_uuid, region, uuid); + } try(cxl_region, set_size, region, size); for (i = 0; i < p->ways; i++) { diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index 9832d09..84f60ad 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -246,4 +246,5 @@ global: LIBCXL_5 { global: cxl_region_get_mode; + cxl_decoder_create_ram_region; } LIBCXL_4; From patchwork Wed Feb 8 20:00:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 13133659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE1C2C636D6 for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="329935471" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="329935471" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:44 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="776174678" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="776174678" Received: from laarmstr-mobl.amr.corp.intel.com (HELO vverma7-desk1.local) ([10.251.6.109]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:44 -0800 From: Vishal Verma Date: Wed, 08 Feb 2023 13:00:32 -0700 Subject: [PATCH ndctl v2 4/7] cxl/region: accept user-supplied UUIDs for pmem regions MIME-Version: 1.0 Message-Id: <20230120-vv-volatile-regions-v2-4-4ea6253000e5@intel.com> References: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> In-Reply-To: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> To: linux-cxl@vger.kernel.org Cc: Gregory Price , Jonathan Cameron , Davidlohr Bueso , Dan Williams , Vishal Verma , nvdimm@lists.linux.dev, Ira Weiny X-Mailer: b4 0.13-dev-ada30 X-Developer-Signature: v=1; a=openpgp-sha256; l=3186; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=7L/lAAG8yThVoZsO9V1nVeSvNDX9fTaRIBY0YDNX1d4=; b=owGbwMvMwCXGf25diOft7jLG02pJDMmP/2fyyJ28N2PRsweuT19G7my6EOaTlGllf8pbV+dq6 sGHEaWTO0pZGMS4GGTFFFn+7vnIeExuez5PYIIjzBxWJpAhDFycAjCR9reMDJe/SLNeX+LtsS2/ KXXtTbFK/6szD57dPM39SKtwc3rD900M/32rD52fyxZQ7jFD2nz6i8N9lmL7slisyk4m7ltWLmb 0lh8A X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Attempting to add additional checking around user-supplied UUIDs against 'ram' type regions revealed that commit 21b089025178 ("cxl: add a 'create-region' command") completely neglected to add the requisite support for accepting user-supplied UUIDs, even though the man page for cxl-create-region advertised the option. Fix this by actually adding this option now, and add checks to validate the user-supplied UUID, and refuse it for ram regions. Cc: Dan Williams Reviewed-by: Dan Williams Reviewed-by: Ira Weiny Signed-off-by: Vishal Verma --- cxl/region.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/cxl/region.c b/cxl/region.c index c69cb9a..5c908bb 100644 --- a/cxl/region.c +++ b/cxl/region.c @@ -22,6 +22,7 @@ static struct region_params { const char *bus; const char *size; const char *type; + const char *uuid; const char *root_decoder; const char *region; int ways; @@ -40,6 +41,7 @@ struct parsed_params { u64 ep_min_size; int ways; int granularity; + uuid_t uuid; struct json_object *memdevs; int num_memdevs; int argc; @@ -74,6 +76,8 @@ OPT_INTEGER('g', "granularity", ¶m.granularity, \ "granularity of the interleave set"), \ OPT_STRING('t', "type", ¶m.type, \ "region type", "region type - 'pmem' or 'ram'"), \ +OPT_STRING('U', "uuid", ¶m.uuid, \ + "region uuid", "uuid for the new region (default: autogenerate)"), \ OPT_BOOLEAN('m', "memdevs", ¶m.memdevs, \ "non-option arguments are memdevs"), \ OPT_BOOLEAN('u', "human", ¶m.human, "use human friendly number formats") @@ -293,6 +297,11 @@ static int parse_create_options(struct cxl_ctx *ctx, int count, if (param.type) { p->mode = cxl_decoder_mode_from_ident(param.type); + if (p->mode == CXL_DECODER_MODE_RAM && param.uuid) { + log_err(&rl, + "can't set UUID for ram / volatile regions"); + return -EINVAL; + } if (p->mode == CXL_DECODER_MODE_NONE) { log_err(&rl, "unsupported type: %s\n", param.type); return -EINVAL; @@ -341,6 +350,13 @@ static int parse_create_options(struct cxl_ctx *ctx, int count, } } + if (param.uuid) { + if (uuid_parse(param.uuid, p->uuid)) { + error("failed to parse uuid: '%s'\n", param.uuid); + return -EINVAL; + } + } + return 0; } @@ -562,7 +578,6 @@ static int create_region(struct cxl_ctx *ctx, int *count, int i, rc, granularity; u64 size, max_extent; const char *devname; - uuid_t uuid; rc = create_region_validate_config(ctx, p); if (rc) @@ -623,8 +638,9 @@ static int create_region(struct cxl_ctx *ctx, int *count, try(cxl_region, set_interleave_granularity, region, granularity); try(cxl_region, set_interleave_ways, region, p->ways); if (p->mode == CXL_DECODER_MODE_PMEM) { - uuid_generate(uuid); - try(cxl_region, set_uuid, region, uuid); + if (!param.uuid) + uuid_generate(p->uuid); + try(cxl_region, set_uuid, region, p->uuid); } try(cxl_region, set_size, region, size); From patchwork Wed Feb 8 20:00:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 13133661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 849CBC636D3 for ; Wed, 8 Feb 2023 20:01:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231624AbjBHUBA (ORCPT ); Wed, 8 Feb 2023 15:01:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231718AbjBHUA7 (ORCPT ); Wed, 8 Feb 2023 15:00:59 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 774953BDBA for ; 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a="776174683" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="776174683" Received: from laarmstr-mobl.amr.corp.intel.com (HELO vverma7-desk1.local) ([10.251.6.109]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:44 -0800 From: Vishal Verma Date: Wed, 08 Feb 2023 13:00:33 -0700 Subject: [PATCH ndctl v2 5/7] cxl/region: determine region type based on root decoder capability MIME-Version: 1.0 Message-Id: <20230120-vv-volatile-regions-v2-5-4ea6253000e5@intel.com> References: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> In-Reply-To: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> To: linux-cxl@vger.kernel.org Cc: Gregory Price , Jonathan Cameron , Davidlohr Bueso , Dan Williams , Vishal Verma , nvdimm@lists.linux.dev, Ira Weiny X-Mailer: b4 0.13-dev-ada30 X-Developer-Signature: v=1; a=openpgp-sha256; l=2392; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=8SlrqThetKyI2i29+UXfRivo5MP/riXdL060oZwi9S4=; b=owGbwMvMwCXGf25diOft7jLG02pJDMmP/2fypDt8uPD4q/j5RRv3nrWOUJYpv8BoJ6Hxho3nc 73Q1TKljlIWBjEuBlkxRZa/ez4yHpPbns8TmOAIM4eVCWQIAxenAEykWZ3hf/5anSiNP2WHj2Z6 V3c+LFTO/HBpt1PWU1OuKf/DuqevYGL475My2fpM66+mT9fqWGd6x2i8lZob+sfZ4N/6TZY3ruw 5wAYA X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org In the common case, root decoders are expected to be either pmem capable, or volatile capable, but not necessarily both simultaneously. If a decoder only has one of pmem or volatile capabilities, cxl-create-region should just infer the type of the region (pmem or ram) based on this capability. Maintain the default behavior of cxl-create-region to choose type=pmem, but only as a fallback if the selected root decoder has multiple capabilities. If it is only capable of either pmem, or ram, then infer region type from this without requiring it to be specified explicitly. Cc: Dan Williams Reviewed-by: Ira Weiny Signed-off-by: Vishal Verma --- Documentation/cxl/cxl-create-region.txt | 3 ++- cxl/region.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/Documentation/cxl/cxl-create-region.txt b/Documentation/cxl/cxl-create-region.txt index ada0e52..f11a412 100644 --- a/Documentation/cxl/cxl-create-region.txt +++ b/Documentation/cxl/cxl-create-region.txt @@ -75,7 +75,8 @@ include::bus-option.txt[] -t:: --type=:: - Specify the region type - 'pmem' or 'ram'. Defaults to 'pmem'. + Specify the region type - 'pmem' or 'ram'. Default to root decoder + capability, and if that is ambiguous, default to 'pmem'. -U:: --uuid=:: diff --git a/cxl/region.c b/cxl/region.c index 5c908bb..07ce4a3 100644 --- a/cxl/region.c +++ b/cxl/region.c @@ -444,6 +444,22 @@ static int validate_decoder(struct cxl_decoder *decoder, return 0; } +static void set_type_from_decoder(struct cxl_ctx *ctx, struct parsed_params *p) +{ + /* if param.type was explicitly specified, nothing to do here */ + if (param.type) + return; + + /* + * default to pmem if both types are set, otherwise the single + * capability dominates. + */ + if (cxl_decoder_is_volatile_capable(p->root_decoder)) + p->mode = CXL_DECODER_MODE_RAM; + if (cxl_decoder_is_pmem_capable(p->root_decoder)) + p->mode = CXL_DECODER_MODE_PMEM; +} + static int create_region_validate_config(struct cxl_ctx *ctx, struct parsed_params *p) { @@ -477,6 +493,8 @@ found: return -ENXIO; } + set_type_from_decoder(ctx, p); + rc = validate_decoder(p->root_decoder, p); if (rc) return rc; From patchwork Wed Feb 8 20:00:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 13133660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B00EC636D6 for ; Wed, 8 Feb 2023 20:01:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231330AbjBHUBB (ORCPT ); Wed, 8 Feb 2023 15:01:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231697AbjBHUA7 (ORCPT ); Wed, 8 Feb 2023 15:00:59 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 347111E1F6 for ; Wed, 8 Feb 2023 12:00:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675886452; x=1707422452; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=fAX98Edco08kfSF7rWrzM8w/+1K3xvv+FOGwue7EYAU=; b=FyqX2A2+Xf0Mb5q/i5q12ZxkUP7+/JvDAdyqEgkOvT1ld9RXk4qQBiPN 1Jmot4BoPhFdFNL1AwvZoLrQYg/rtWK3VJHLQpJeKZTXGXHIenyuFWr8K 3sJaV062n0XzZyuO/kzTbykQfsbTCOi0h4XM+iWJ2db3hsOoMVrn5AsOg 7PkGVukivSp/d4yC9ycB3b/SrLJq25arcDwybZrprAW+LO46md+gc44xm UtPxguLZErza0fcZDSupeDIykBigWH0Y7LpCnw+0zuyvTGG7fDkC99ZtK HHhskR2b6ofj2inyegJenXuZNzwHHb7PJp+EUIFtKk7/DoLn3ZQ/32IuR g==; X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="329935488" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="329935488" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:46 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="776174686" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="776174686" Received: from laarmstr-mobl.amr.corp.intel.com (HELO vverma7-desk1.local) ([10.251.6.109]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:45 -0800 From: Vishal Verma Date: Wed, 08 Feb 2023 13:00:34 -0700 Subject: [PATCH ndctl v2 6/7] cxl/list: Include regions in the verbose listing MIME-Version: 1.0 Message-Id: <20230120-vv-volatile-regions-v2-6-4ea6253000e5@intel.com> References: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> In-Reply-To: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> To: linux-cxl@vger.kernel.org Cc: Gregory Price , Jonathan Cameron , Davidlohr Bueso , Dan Williams , Vishal Verma , nvdimm@lists.linux.dev, Ira Weiny X-Mailer: b4 0.13-dev-ada30 X-Developer-Signature: v=1; a=openpgp-sha256; l=678; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=D7UqXnSXmnYe3Bfxk/zLNeSNw21I6tydyTN5ZJBJa10=; b=owGbwMvMwCXGf25diOft7jLG02pJDMmP/2fKTJ/3QP3My1t17q6vXz245xbas+3BkqkbvOKaZ 59yurPCs6OUhUGMi0FWTJHl756PjMfktufzBCY4wsxhZQIZwsDFKQAT0Tdg+GenyxWTuPNqTl+2 ctDVyJnxgSaeZUeuGhrfTzBuzVXOW83IcC7kzA7x6FBXv1SnFL0CvgePKuvERE/Krv+oZPpePn0 VFwA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Dan Williams When verbose listing was added, region listing support was not available, so it got missed. Add it now. Signed-off-by: Dan Williams Reviewed-by: Ira Weiny Signed-off-by: Vishal Verma --- cxl/list.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cxl/list.c b/cxl/list.c index e3ef1fb..4e77aeb 100644 --- a/cxl/list.c +++ b/cxl/list.c @@ -126,6 +126,7 @@ int cmd_list(int argc, const char **argv, struct cxl_ctx *ctx) param.endpoints = true; param.decoders = true; param.targets = true; + param.regions = true; /*fallthrough*/ case 0: break; From patchwork Wed Feb 8 20:00:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Verma, Vishal L" X-Patchwork-Id: 13133662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3722BC636D7 for ; Wed, 8 Feb 2023 20:01:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230462AbjBHUBD (ORCPT ); Wed, 8 Feb 2023 15:01:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231665AbjBHUBC (ORCPT ); Wed, 8 Feb 2023 15:01:02 -0500 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D269B30E9D for ; Wed, 8 Feb 2023 12:00:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675886455; x=1707422455; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=lHdaaP3j56IfBkO1PcpWmCpy5y7MPV/7nJrSpKJOhiU=; b=Jq+lj/NKUO8o3TeKSA6hZtyFFXB5qu43eRLGJrmAmbyVTJuEUw/xAyUZ Q+lsTF/S2LO3Av62nLNiIoBba/KIoAmruveO+XleLUoVpmGIZnwsHDGCO KASrenRpPxacGvyU9MZ3Vqfa/Ula1U4dK4FX7on+AlkJ1UnSLAjVD/JGX ukhRxdK5DrpY1sICqX9CxBlmBDx40sIwp6iw7XHdDJWaejocEyomyWYDN OHUppit5dTuVvJJA6quEukUmcvZ0oJBaoIuri724EyGKqNyyQnZLVb42j 4ubenaSpyjzq1/EST2gtnTMZTOtt94oAt3YRm7l1RLfwHVIQf0uOtXhzW Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="329935494" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="329935494" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:46 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10615"; a="776174690" X-IronPort-AV: E=Sophos;i="5.97,281,1669104000"; d="scan'208";a="776174690" Received: from laarmstr-mobl.amr.corp.intel.com (HELO vverma7-desk1.local) ([10.251.6.109]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Feb 2023 12:00:45 -0800 From: Vishal Verma Date: Wed, 08 Feb 2023 13:00:35 -0700 Subject: [PATCH ndctl v2 7/7] cxl/list: Enumerate device-dax properties for regions MIME-Version: 1.0 Message-Id: <20230120-vv-volatile-regions-v2-7-4ea6253000e5@intel.com> References: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> In-Reply-To: <20230120-vv-volatile-regions-v2-0-4ea6253000e5@intel.com> To: linux-cxl@vger.kernel.org Cc: Gregory Price , Jonathan Cameron , Davidlohr Bueso , Dan Williams , Vishal Verma , nvdimm@lists.linux.dev, Ira Weiny X-Mailer: b4 0.13-dev-ada30 X-Developer-Signature: v=1; a=openpgp-sha256; l=10285; i=vishal.l.verma@intel.com; h=from:subject:message-id; bh=spSIKbypUoC4kgERe+Twmnpqj6OXI7+1BKPa5hQARBw=; b=owGbwMvMwCXGf25diOft7jLG02pJDMmP/2em2104WZiUZWX1yb4u9fwtoR6eTF/3YEWDe3PsQ tyaVHg6SlkYxLgYZMUUWf7u+ch4TG57Pk9ggiPMHFYmkCEMXJwCMJGPGxj+V7FO3rLJQOvISd15 19/ztVvqPw4/EHyyyiZjxmWR7ItPexgZJhuEtz6e92ru62a1Mv/6q5HKi409FY42Sj/wvOKbvzW GDwA= X-Developer-Key: i=vishal.l.verma@intel.com; a=openpgp; fpr=F8682BE134C67A12332A2ED07AFA61BEA3B84DFF Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Dan Williams Recently the kernel added support for routing newly mapped CXL regions to device-dax. Include the json representation of a DAX region beneath its host CXL region. Signed-off-by: Dan Williams [vishal: move the daxctl/json.h include from cxl/filter.c to cxl/json.c] Reviewed-by: Ira Weiny Signed-off-by: Vishal Verma --- Documentation/cxl/cxl-list.txt | 31 +++++++++++++++++++++++++++++++ Documentation/cxl/lib/libcxl.txt | 7 +++++++ cxl/lib/private.h | 1 + cxl/lib/libcxl.c | 39 +++++++++++++++++++++++++++++++++++++++ cxl/filter.h | 3 +++ cxl/libcxl.h | 1 + cxl/json.c | 16 ++++++++++++++++ cxl/list.c | 2 ++ cxl/lib/libcxl.sym | 1 + cxl/lib/meson.build | 1 + cxl/meson.build | 3 +++ 11 files changed, 105 insertions(+) diff --git a/Documentation/cxl/cxl-list.txt b/Documentation/cxl/cxl-list.txt index 3410d49..c64d65d 100644 --- a/Documentation/cxl/cxl-list.txt +++ b/Documentation/cxl/cxl-list.txt @@ -380,6 +380,37 @@ OPTIONS --regions:: Include region objects in the listing. +-X:: +--dax:: + Append DAX information to region listings +---- +# cxl list -RXu +{ + "region":"region4", + "resource":"0xf010000000", + "size":"512.00 MiB (536.87 MB)", + "interleave_ways":2, + "interleave_granularity":4096, + "decode_state":"commit", + "daxregion":{ + "id":4, + "size":"512.00 MiB (536.87 MB)", + "align":2097152, + "devices":[ + { + "chardev":"dax4.0", + "size":"512.00 MiB (536.87 MB)", + "target_node":0, + "align":2097152, + "mode":"system-ram", + "online_memblocks":0, + "total_memblocks":4 + } + ] + } +} +---- + -r:: --region:: Specify CXL region device name(s), or device id(s), to filter the listing. diff --git a/Documentation/cxl/lib/libcxl.txt b/Documentation/cxl/lib/libcxl.txt index dbc4b56..31bc855 100644 --- a/Documentation/cxl/lib/libcxl.txt +++ b/Documentation/cxl/lib/libcxl.txt @@ -568,6 +568,7 @@ int cxl_region_clear_target(struct cxl_region *region, int position); int cxl_region_clear_all_targets(struct cxl_region *region); int cxl_region_decode_commit(struct cxl_region *region); int cxl_region_decode_reset(struct cxl_region *region); +struct daxctl_region *cxl_region_get_daxctl_region(struct cxl_region *region); ---- A region's resource attribute is the Host Physical Address at which the region's @@ -587,6 +588,12 @@ The 'decode_commit' and 'decode_reset' attributes reserve and free DPA space on a given memdev by allocating an endpoint decoder, and programming it based on the region's interleave geometry. +Once a region is active it is attached to either the NVDIMM subsystem +where its properties can be interrogated by ndctl, or the DAX subsystem +where its properties can be interrogated by daxctl. The helper +cxl_region_get_daxctl_region() returns an 'struct daxctl_region *' that +can be used with other libdaxctl APIs. + include::../../copyright.txt[] SEE ALSO diff --git a/cxl/lib/private.h b/cxl/lib/private.h index 306dc3a..d648992 100644 --- a/cxl/lib/private.h +++ b/cxl/lib/private.h @@ -150,6 +150,7 @@ struct cxl_region { unsigned int interleave_granularity; enum cxl_decode_state decode_state; enum cxl_decoder_mode mode; + struct daxctl_region *dax_region; struct kmod_module *module; struct list_head mappings; }; diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index c5b9b18..81855f4 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "private.h" /** @@ -49,6 +50,7 @@ struct cxl_ctx { struct list_head memdevs; struct list_head buses; struct kmod_ctx *kmod_ctx; + struct daxctl_ctx *daxctl_ctx; void *private_data; }; @@ -231,6 +233,7 @@ CXL_EXPORT void *cxl_get_private_data(struct cxl_ctx *ctx) */ CXL_EXPORT int cxl_new(struct cxl_ctx **ctx) { + struct daxctl_ctx *daxctl_ctx; struct udev_queue *udev_queue; struct kmod_ctx *kmod_ctx; struct udev *udev; @@ -241,6 +244,10 @@ CXL_EXPORT int cxl_new(struct cxl_ctx **ctx) if (!c) return -ENOMEM; + rc = daxctl_new(&daxctl_ctx); + if (rc) + goto err_daxctl; + kmod_ctx = kmod_new(NULL, NULL); if (check_kmod(kmod_ctx) != 0) { rc = -ENXIO; @@ -267,6 +274,7 @@ CXL_EXPORT int cxl_new(struct cxl_ctx **ctx) list_head_init(&c->memdevs); list_head_init(&c->buses); c->kmod_ctx = kmod_ctx; + c->daxctl_ctx = daxctl_ctx; c->udev = udev; c->udev_queue = udev_queue; c->timeout = 5000; @@ -278,6 +286,8 @@ err_udev_queue: err_udev: kmod_unref(kmod_ctx); err_kmod: + daxctl_unref(daxctl_ctx); +err_daxctl: free(c); return rc; } @@ -321,6 +331,7 @@ CXL_EXPORT void cxl_unref(struct cxl_ctx *ctx) udev_queue_unref(ctx->udev_queue); udev_unref(ctx->udev); kmod_unref(ctx->kmod_ctx); + daxctl_unref(ctx->daxctl_ctx); info(ctx, "context %p released\n", ctx); free(ctx); } @@ -746,6 +757,34 @@ cxl_region_get_target_decoder(struct cxl_region *region, int position) return decoder; } +CXL_EXPORT struct daxctl_region * +cxl_region_get_daxctl_region(struct cxl_region *region) +{ + const char *devname = cxl_region_get_devname(region); + struct cxl_ctx *ctx = cxl_region_get_ctx(region); + char *path = region->dev_buf; + int len = region->buf_len; + uuid_t uuid = { 0 }; + struct stat st; + + if (region->dax_region) + return region->dax_region; + + if (snprintf(region->dev_buf, len, "%s/dax_region%d", region->dev_path, + region->id) >= len) { + err(ctx, "%s: buffer too small!\n", devname); + return NULL; + } + + if (stat(path, &st) < 0) + return NULL; + + region->dax_region = + daxctl_new_region(ctx->daxctl_ctx, region->id, uuid, path); + + return region->dax_region; +} + CXL_EXPORT int cxl_region_set_size(struct cxl_region *region, unsigned long long size) { diff --git a/cxl/filter.h b/cxl/filter.h index b9f1350..c486514 100644 --- a/cxl/filter.h +++ b/cxl/filter.h @@ -28,6 +28,7 @@ struct cxl_filter_params { bool health; bool partition; bool alert_config; + bool dax; int verbose; struct log_ctx ctx; }; @@ -80,6 +81,8 @@ static inline unsigned long cxl_filter_to_flags(struct cxl_filter_params *param) flags |= UTIL_JSON_PARTITION; if (param->alert_config) flags |= UTIL_JSON_ALERT_CONFIG; + if (param->dax) + flags |= UTIL_JSON_DAX | UTIL_JSON_DAX_DEVS; return flags; } diff --git a/cxl/libcxl.h b/cxl/libcxl.h index 904156c..54d9f10 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -279,6 +279,7 @@ unsigned int cxl_region_get_interleave_ways(struct cxl_region *region); unsigned int cxl_region_get_interleave_granularity(struct cxl_region *region); struct cxl_decoder *cxl_region_get_target_decoder(struct cxl_region *region, int position); +struct daxctl_region *cxl_region_get_daxctl_region(struct cxl_region *region); int cxl_region_set_size(struct cxl_region *region, unsigned long long size); int cxl_region_set_uuid(struct cxl_region *region, uuid_t uu); int cxl_region_set_interleave_ways(struct cxl_region *region, diff --git a/cxl/json.c b/cxl/json.c index 16b6cb8..e87bdd4 100644 --- a/cxl/json.c +++ b/cxl/json.c @@ -10,6 +10,7 @@ #include "filter.h" #include "json.h" +#include "../daxctl/json.h" static struct json_object *util_cxl_memdev_health_to_json( struct cxl_memdev *memdev, unsigned long flags) @@ -891,7 +892,22 @@ struct json_object *util_cxl_region_to_json(struct cxl_region *region, util_cxl_mappings_append_json(jregion, region, flags); + if (flags & UTIL_JSON_DAX) { + struct daxctl_region *dax_region; + + dax_region = cxl_region_get_daxctl_region(region); + if (dax_region) { + jobj = util_daxctl_region_to_json(dax_region, NULL, + flags); + if (jobj) + json_object_object_add(jregion, "daxregion", + jobj); + } + } + json_object_set_userdata(jregion, region, NULL); + + return jregion; } diff --git a/cxl/list.c b/cxl/list.c index 4e77aeb..c01154e 100644 --- a/cxl/list.c +++ b/cxl/list.c @@ -45,6 +45,7 @@ static const struct option options[] = { OPT_STRING('r', "region", ¶m.region_filter, "region name", "filter by CXL region name(s)"), OPT_BOOLEAN('R', "regions", ¶m.regions, "include CXL regions"), + OPT_BOOLEAN('X', "dax", ¶m.dax, "include CXL DAX region enumeration"), OPT_BOOLEAN('i', "idle", ¶m.idle, "include disabled devices"), OPT_BOOLEAN('u', "human", ¶m.human, "use human friendly number formats"), @@ -116,6 +117,7 @@ int cmd_list(int argc, const char **argv, struct cxl_ctx *ctx) param.health = true; param.partition = true; param.alert_config = true; + param.dax = true; /* fallthrough */ case 2: param.idle = true; diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index 84f60ad..1c6177c 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -247,4 +247,5 @@ LIBCXL_5 { global: cxl_region_get_mode; cxl_decoder_create_ram_region; + cxl_region_get_daxctl_region; } LIBCXL_4; diff --git a/cxl/lib/meson.build b/cxl/lib/meson.build index 60b9de7..422a351 100644 --- a/cxl/lib/meson.build +++ b/cxl/lib/meson.build @@ -16,6 +16,7 @@ cxl = library('cxl', uuid, kmod, libudev, + daxctl_dep, ], version : libcxl_version, install : true, diff --git a/cxl/meson.build b/cxl/meson.build index f2474aa..4ead163 100644 --- a/cxl/meson.build +++ b/cxl/meson.build @@ -7,6 +7,8 @@ cxl_src = [ 'memdev.c', 'json.c', 'filter.c', + '../daxctl/json.c', + '../daxctl/filter.c', ] cxl_tool = executable('cxl', @@ -14,6 +16,7 @@ cxl_tool = executable('cxl', include_directories : root_inc, dependencies : [ cxl_dep, + daxctl_dep, util_dep, uuid, kmod,