From patchwork Thu Feb 9 15:26:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13134742 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89510C636D6 for ; Thu, 9 Feb 2023 15:26:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tV5pfBtOskjEvdvPMI4XkXQnboca0BHsG4UJmG2zWuM=; b=ro/YwdSiTAUhyf L+4udddnCip3t/vczdurS+HH3gB7ljETp/H7RqVXIegBV1MdZJ0+A8Y40twjMjtj4iXbT2sh5k7VC EVW+OQRCyHdboCiuuzlh6bx5HNLiDcFJhehySVu1iSevfjThiBdPvt+JY4ta5sJ5OBxzMJYIVggl+ a8kQC3jDfEJPIFnBKTRsGQj/Aj0SzoZm9WaevB0ZGaqb7sYs94nwQ1x/rIoYOKEgJ3c48BqiIIOn4 LadSwA5Yjqubc7bwTAh7rG3tlnIGjKFr0ycCNmk0xdrxc3CxolzzBl2HY6Lh4ak9ODnHb67bqAbFX z5FJykZInxmR7Zj9CgHg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pQ8oq-002Cdr-Rp; Thu, 09 Feb 2023 15:26:40 +0000 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pQ8oo-002CZ5-Ec for linux-riscv@lists.infradead.org; Thu, 09 Feb 2023 15:26:39 +0000 Received: by mail-ej1-x62c.google.com with SMTP id p26so7347803ejx.13 for ; Thu, 09 Feb 2023 07:26:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZPEogwNPGzb9EX437UPsSVPibcKNUNGdrZDqrYRtR30=; b=b3sCue6n3RjE4xqJgkD8qN0AkCyEMJ0emnA4KWOHkceg0c7oQlYBKxB7Uo7VnTO3MW cInYWY4opfY5bPb+nTa1VuySJS6bOTeuEE1jbujvb6MU3yj0QPoTYK1369WJGGbOPDlE vZbDrXc8B42YIUIOXlKMgxkVlYtaPiw8CDMMR5mCh+YL5kcWBTladvqMEVbdUIhCQk70 AlvQJ7wH0haSh2Dw7iEqPc4XlDMj6CN+BnL7+r4Uj91pcZOfKvEJRwL+ak9PxD0aIYL4 7p7ZTAbFn1MH9xdtxvSqT8NPZdNa9uXsuXyqFZD2OM3y9kSMeejD4iEVOLT71BGHIEHw IVIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZPEogwNPGzb9EX437UPsSVPibcKNUNGdrZDqrYRtR30=; b=bPT+5N1fVxGEaWKDNs+5ibjsOR+Ez5dQm9OO2uyvvP2BxBIdeAERsD8+ME8lNEKOVk 3NO3XB/KVBXJjXlep98esaf/gbA655JBzxYBTQirklUoJApSY23n0+lQwjGAulCid2Xk r3/eA9x6BXgLGcGfSDdqcGFSFpmszfIcWuywp6VIWs4qNaA6U3XQFLKdch/w1gqz8h4m 1TeHElwfighoCqkI8GhP/qslvFSsASKQYWf4VHTO31r5ZCW+18K6pEDTqDm1ng7fT219 sxoe32Y07LZDOP9sHbFtrozBERwKbaPy1y08tNfzt8BtvefYt9EnG3Tsy0U+bmXpZ0Ri PdYQ== X-Gm-Message-State: AO0yUKXWTBSHFf76PsBL7mSmDp/aLiUlOAuw+cMBRuctYMjiDJajOsLZ x+NBUT/77Es20MA2nVtbBBw8Gfkge5OU2/uR X-Google-Smtp-Source: AK7set+hdCra0whyCsMluYeqc8tO2CxHPuvkqNX0x30WRYplOKw+jW6GPyEK/mp5aPgrGqkjjDDXFg== X-Received: by 2002:a17:906:fa18:b0:878:54e3:e3e1 with SMTP id lo24-20020a170906fa1800b0087854e3e3e1mr12568946ejb.73.1675956392240; Thu, 09 Feb 2023 07:26:32 -0800 (PST) Received: from localhost (cst2-173-16.cust.vodafone.cz. [31.30.173.16]) by smtp.gmail.com with ESMTPSA id z23-20020a170906075700b008ab84430157sm980266ejb.200.2023.02.09.07.26.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 07:26:31 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Anup Patel ' , 'Palmer Dabbelt ' , 'Paul Walmsley ' , 'Krzysztof Kozlowski ' , 'Atish Patra ' , 'Heiko Stuebner ' , 'Jisheng Zhang ' , 'Rob Herring ' , 'Albert Ou ' , 'Conor Dooley ' Subject: [PATCH v4 1/8] RISC-V: alternatives: Support patching multiple insns in assembly Date: Thu, 9 Feb 2023 16:26:21 +0100 Message-Id: <20230209152628.129914-2-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209152628.129914-1-ajones@ventanamicro.com> References: <20230209152628.129914-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230209_072638_587629_D35E699F X-CRM114-Status: UNSURE ( 8.47 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org As pointed out in commit d374a16539b1 ("RISC-V: fix compile error from deduplicated __ALTERNATIVE_CFG_2"), we need quotes around parameters passed to macros within macros to avoid spaces being interpreted as separators. ALT_NEW_CONTENT was trying to handle this by defining new_c has a vararg, but this isn't sufficient for calling ALTERNATIVE() from assembly with multiple instructions in the new/old sequences. Remove the vararg "hack" and use quotes. Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/include/asm/alternative-macros.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index 51c6867e02f3..7bc52f33f95f 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -14,7 +14,7 @@ .4byte \errata_id .endm -.macro ALT_NEW_CONTENT vendor_id, errata_id, enable = 1, new_c : vararg +.macro ALT_NEW_CONTENT vendor_id, errata_id, enable = 1, new_c .if \enable .pushsection .alternative, "a" ALT_ENTRY 886b, 888f, \vendor_id, \errata_id, 889f - 888f @@ -41,13 +41,13 @@ \old_c .option pop 887 : - ALT_NEW_CONTENT \vendor_id, \errata_id, \enable, \new_c + ALT_NEW_CONTENT \vendor_id, \errata_id, \enable, "\new_c" .endm .macro ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1, \ new_c_2, vendor_id_2, errata_id_2, enable_2 ALTERNATIVE_CFG "\old_c", "\new_c_1", \vendor_id_1, \errata_id_1, \enable_1 - ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2 + ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, "\new_c_2" .endm #define __ALTERNATIVE_CFG(...) ALTERNATIVE_CFG __VA_ARGS__ From patchwork Thu Feb 9 15:26:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13134741 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40952C61DA4 for ; Thu, 9 Feb 2023 15:26:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lLJ9EEhHsunDc+WJ100hoicqJRYxRyx6/MEyf7CpG4Y=; b=oO4Z/W+lXMCbL+ tErDAmH5F/iuZgWU7T22pxTDRRhkCmv8pKgYxut8h+ou9785WbXfWaSSYLTXZTDWwSyq/J38M2GSH gBe99ztBW3F/l6uEkWyOLQ2WIHgHQyYxsUX7qLWeWvcohnMU0tENfZtpkzzlgAPBmC3kRBEYKvzOa Hfov7150TOOeLeOc+IlpArkDbrztuBSAPuKp7reFKlqnDmqvbimXPxooxzoQdJQrBiQvrKgLT8VCt AVRrS5N2kMIrXAME5puuVxc6AOxMSg22zZprXhLRZJ6WCUHhdqLxHeOT51Ez6ZXpkv73qnQ+SaxfI 0O9KeUH5yuItrmvnHdeA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pQ8oo-002Cb3-5J; Thu, 09 Feb 2023 15:26:38 +0000 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pQ8ol-002CZn-CC for linux-riscv@lists.infradead.org; Thu, 09 Feb 2023 15:26:37 +0000 Received: by mail-ej1-x636.google.com with SMTP id p26so7348029ejx.13 for ; Thu, 09 Feb 2023 07:26:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K7rGW7hYEauj0lEHNx054QYhURQUQQG6A8fMOX9HH84=; b=kuIJXFR63EQ+fYmP7C1wA1MzvOqIjuDSDqVG2N1SeYPvzknN2OX74nqtDcH5iQ4O4w oH3qSb7v0I+VZZd/CjCOYvBRZGYgp+zK1T9sv0ApvXDRvAzfOC2Ben/6jkogWxMXNQz0 aetA/zZlAd9PoTpsYYheKpSlwBx6yuvDMyf2kubQPduawwIVE+SKBmPTtrOuHwoCyJYE D9Hk44LVUDlBKqNHQkNL4QjmKOVvinr4QsUH8f91xeqLHLXX1aG8FIhlflTVILQxtqFV F2SQZlhfZWkvt56hm5lOjbDCbpyh1FbyAyMwa3BMCZNyvDHX72oopJvRu2+Ktd6cuYrq GbdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K7rGW7hYEauj0lEHNx054QYhURQUQQG6A8fMOX9HH84=; b=sT1nJ5wV0C6JKO32XivXugzAGxZkmZXcP3p5WeCEqNomRqaeFra6edhghxCc/PBDAQ DE7nDaMsJ1F9Z+U94PSBj/b+Fn60BK5XMbhf3RzOEB6obkK1WxEc/pgGKB3f1bDClCr5 G7huwNyy6U5cciZltFgXIuJndt+Vsyxuzoo2gohcD4slko7RQQf681OeK46vyNyZBWMR HTIOyQHj5xUo1ugSB6pCCzoJ8SiZwRaJBFd2ZDyjyD9cCxVGEpwB0ba9JymCUOMNgPMm PTfPJuqvZ8s1zi1Nf5N7B2r36w2XdMU/8swRMxGNPM4193YijZzeTmaon3a56BtnXHeK 6RJQ== X-Gm-Message-State: AO0yUKWVYyodEZUMBNBdJz5eJrx4w6cQNNh6jaYmoShYPDSYaAkZS6JA nU/0ovlhQ3coTlVm+TN0zYJ0VsrUP+C8yO1X X-Google-Smtp-Source: AK7set9+Nl/jBXYA+zwzA2NVsfR8qmH3lTKNUYYH8/tWdL/5pN+drLs1/B01bKiO1aUH0oDc9xAR9A== X-Received: by 2002:a17:906:34cf:b0:88a:673e:3669 with SMTP id h15-20020a17090634cf00b0088a673e3669mr14582760ejb.15.1675956393820; Thu, 09 Feb 2023 07:26:33 -0800 (PST) Received: from localhost (cst2-173-16.cust.vodafone.cz. [31.30.173.16]) by smtp.gmail.com with ESMTPSA id ch9-20020a170906c2c900b0088dc98e4510sm999864ejb.112.2023.02.09.07.26.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 07:26:33 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Anup Patel ' , 'Palmer Dabbelt ' , 'Paul Walmsley ' , 'Krzysztof Kozlowski ' , 'Atish Patra ' , 'Heiko Stuebner ' , 'Jisheng Zhang ' , 'Rob Herring ' , 'Albert Ou ' , 'Conor Dooley ' Subject: [PATCH v4 2/8] RISC-V: Factor out body of riscv_init_cbom_blocksize loop Date: Thu, 9 Feb 2023 16:26:22 +0100 Message-Id: <20230209152628.129914-3-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209152628.129914-1-ajones@ventanamicro.com> References: <20230209152628.129914-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230209_072635_435144_DC7AC4A5 X-CRM114-Status: GOOD ( 10.86 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Refactor riscv_init_cbom_blocksize() to prepare for it to be used for both cbom block size and cboz block size. Signed-off-by: Andrew Jones Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley --- arch/riscv/mm/cacheflush.c | 45 +++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 3cc07ed45aeb..eaf23fc14966 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -98,34 +98,39 @@ void flush_icache_pte(pte_t pte) unsigned int riscv_cbom_block_size; EXPORT_SYMBOL_GPL(riscv_cbom_block_size); +static void cbo_get_block_size(struct device_node *node, + const char *name, u32 *block_size, + unsigned long *first_hartid) +{ + unsigned long hartid; + u32 val; + + if (riscv_of_processor_hartid(node, &hartid)) + return; + + if (of_property_read_u32(node, name, &val)) + return; + + if (!*block_size) { + *block_size = val; + *first_hartid = hartid; + } else if (*block_size != val) { + pr_warn("%s mismatched between harts %lu and %lu\n", + name, *first_hartid, hartid); + } +} + void riscv_init_cbom_blocksize(void) { struct device_node *node; unsigned long cbom_hartid; - u32 val, probed_block_size; - int ret; + u32 probed_block_size; probed_block_size = 0; for_each_of_cpu_node(node) { - unsigned long hartid; - - ret = riscv_of_processor_hartid(node, &hartid); - if (ret) - continue; - /* set block-size for cbom extension if available */ - ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); - if (ret) - continue; - - if (!probed_block_size) { - probed_block_size = val; - cbom_hartid = hartid; - } else { - if (probed_block_size != val) - pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", - cbom_hartid, hartid); - } + cbo_get_block_size(node, "riscv,cbom-block-size", + &probed_block_size, &cbom_hartid); } if (probed_block_size) From patchwork Thu Feb 9 15:26:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13134745 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C413AC636D6 for ; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id k6-20020a1709065fc600b0081bfc79beaesm987397ejv.75.2023.02.09.07.26.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 07:26:35 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Anup Patel ' , 'Palmer Dabbelt ' , 'Paul Walmsley ' , 'Krzysztof Kozlowski ' , 'Atish Patra ' , 'Heiko Stuebner ' , 'Jisheng Zhang ' , 'Rob Herring ' , 'Albert Ou ' , 'Conor Dooley ' Subject: [PATCH v4 3/8] dt-bindings: riscv: Document cboz-block-size Date: Thu, 9 Feb 2023 16:26:23 +0100 Message-Id: <20230209152628.129914-4-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209152628.129914-1-ajones@ventanamicro.com> References: <20230209152628.129914-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230209_072639_185072_51B1EED7 X-CRM114-Status: UNSURE ( 8.51 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The Zicboz operation (cbo.zero) operates on a block-size defined for the cpu-core. While we already have the riscv,cbom-block-size property, it only provides the block size for Zicbom operations. Even though it's likely Zicboz and Zicbom will use the same size, that's not required by the specification. Create another property specifically for Zicboz. Cc: Rob Herring Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6720764e765..f4ee70f8e1cf 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -72,6 +72,11 @@ properties: description: The blocksize in bytes for the Zicbom cache operations. + riscv,cboz-block-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The blocksize in bytes for the Zicboz cache operations. + riscv,isa: description: Identifies the specific RISC-V instruction set architecture From patchwork Thu Feb 9 15:26:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13134744 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98CF7C61DA4 for ; Thu, 9 Feb 2023 15:26:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PIcgm4JHg6My+Q3o+c2eF3/ZunBH4fX05e0Ia+xjho8=; b=1M7PPS8CbCviPN DcVLs3b4Sy0NQ1UkbI7WXhRbQoyPe/KA3XW10Jpxo20nICPZECGgx8+0QyDKG2kxaFFxaSALxx3v3 rnnkEMepNCIjVpRh/MJdkPDGolJ7tTY9MGz4VVlvvs8Qdt1n8Rf5d+kw/9AJOUHhVJut3gcXJ09l+ nLH2N+78vnTHJ9YKBmQXgXhnPKeukF9GeOnnmAVHTp9l8c7xK3ZP/tIW56xjmd7sGL0POYYB2Il3o a/YLXaXoG3y4mRg4+3XuhzTPC5eznPb+QhVT3D/rIcGFTq1Y7hlXJCHQ0WYTyzD0HSy7B8Dgd8Ob9 60XGziyJQ+7xGr94HTtQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pQ8ow-002Ci6-E6; Thu, 09 Feb 2023 15:26:46 +0000 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pQ8oo-002Cb8-NS for linux-riscv@lists.infradead.org; Thu, 09 Feb 2023 15:26:41 +0000 Received: by mail-ej1-x62b.google.com with SMTP id c26so2636632ejz.10 for ; Thu, 09 Feb 2023 07:26:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qMeRBJuo4fqYS7TRpmnP7RjNarEwOjbeRSUa9SH4O1Y=; b=QqXzxp092VffjCS9HTW5zzCMIK1ZBfps+XqOC9AQ/P6k+pGHPdzHL4s5xq01xrudib baFMFuyuvpgr/1/oDn1ISzW+nfbaDds9LXEig/l3eoSBoddqJG2pVblT0nrxaJmZ5DPH JAFnTMrYWlGW8HJaSJwlCqsXkMC5ziCdKqJRrCz22i5Q8NvUOPEfgzVHwjJTMypWg9se Ce7NAKE8DRv5YBqVM5bXbuaac4gekbKXcs8guFBz8ZPvE9Zs7o+dwlVzBEavNykd7h+e eB9TevZYiV4cuFrL+KOxgv0qCQwo1eZEjB279xDthn5W5iIRh80STNvliOJ4q+DlPFoL S79Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qMeRBJuo4fqYS7TRpmnP7RjNarEwOjbeRSUa9SH4O1Y=; b=FE28VBV7DgbJbgU4XW8CxCR5a4JJI6nCH0DnYrgVqP0xPQtHLfaAAW1JK153dBGfUa UN5A0ktJH3CyiiJrYBSEnCTn4+L0FndP9i8DJ4FEqI0AbF64SmGGTtEBxUkRpPqHnC/m E1fyYqyGI9pUOZiYhMhHM7/tqc+1MkteQnh6xA7UQBm7qT62uGi7/KK5fehwYUjFFqKH XMotUJtPaOnb8paJ3BSqAoSU3Lq1XPxZxk8TSe2dwAbg/NXaV3aO9DdoWYumdKxu+ZbE 0AFalp9hySpfhCfG7UlEn/8gvJw5woYODHMQmCikURBQMGRIS886g2YACrzV9BW1McQK OGgQ== X-Gm-Message-State: AO0yUKXfRpMjXe0pkUaf8qx/zJ2yCC1fqofJWEk8Z08tQjDoKZqGf0oH Vd/tdTPggSR+/a9XSqwBK9yKpkDlH6PoZDL4 X-Google-Smtp-Source: AK7set8zxTfiZrmDj8uI4yGO0HL8NvzN62jMeQ+tuptaQNtBxk7n3/PNBDXdtlxfPq6wc7DsnkbOMg== X-Received: by 2002:a17:906:3810:b0:878:7833:816a with SMTP id v16-20020a170906381000b008787833816amr13075302ejc.43.1675956397438; Thu, 09 Feb 2023 07:26:37 -0800 (PST) Received: from localhost (cst2-173-16.cust.vodafone.cz. [31.30.173.16]) by smtp.gmail.com with ESMTPSA id q17-20020a170906361100b00869f2ca6a87sm983998ejb.135.2023.02.09.07.26.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 07:26:36 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Anup Patel ' , 'Palmer Dabbelt ' , 'Paul Walmsley ' , 'Krzysztof Kozlowski ' , 'Atish Patra ' , 'Heiko Stuebner ' , 'Jisheng Zhang ' , 'Rob Herring ' , 'Albert Ou ' , 'Conor Dooley ' Subject: [PATCH v4 4/8] RISC-V: Add Zicboz detection and block size parsing Date: Thu, 9 Feb 2023 16:26:24 +0100 Message-Id: <20230209152628.129914-5-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209152628.129914-1-ajones@ventanamicro.com> References: <20230209152628.129914-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230209_072638_795703_2D291497 X-CRM114-Status: GOOD ( 14.47 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Parse "riscv,cboz-block-size" from the DT by piggybacking on Zicbom's riscv_init_cbom_blocksize(). Additionally check the DT for the presence of the "zicboz" extension and, when it's present, validate the parsed cboz block size as we do Zicbom's cbom block size with riscv_isa_extension_check(). Signed-off-by: Andrew Jones Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley --- arch/riscv/include/asm/cacheflush.h | 3 ++- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 10 ++++++++++ arch/riscv/kernel/setup.c | 2 +- arch/riscv/mm/cacheflush.c | 23 +++++++++++++++-------- 6 files changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 03e3b95ae6da..8091b8bf4883 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -50,7 +50,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local); #endif /* CONFIG_SMP */ extern unsigned int riscv_cbom_block_size; -void riscv_init_cbom_blocksize(void); +extern unsigned int riscv_cboz_block_size; +void riscv_init_cbo_blocksizes(void); #ifdef CONFIG_RISCV_DMA_NONCOHERENT void riscv_noncoherent_supported(void); diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index ee9c80fe0062..bd025e918a08 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -47,6 +47,7 @@ #define RISCV_ISA_EXT_ZBB 30 #define RISCV_ISA_EXT_ZICBOM 31 #define RISCV_ISA_EXT_ZIHINTPAUSE 32 +#define RISCV_ISA_EXT_ZICBOZ 33 #ifndef __ASSEMBLY__ diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 420228e219f7..7a3065544dcb 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -187,6 +187,7 @@ arch_initcall(riscv_cpuinfo_init); static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 21fb567e1b22..0d2db03cf167 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -78,6 +78,15 @@ static bool riscv_isa_extension_check(int id) return false; } return true; + case RISCV_ISA_EXT_ZICBOZ: + if (!riscv_cboz_block_size) { + pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n"); + return false; + } else if (!is_power_of_2(riscv_cboz_block_size)) { + pr_err("cboz-block-size present, but is not a power-of-2\n"); + return false; + } + return true; } return true; @@ -226,6 +235,7 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); + SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); } #undef SET_ISA_EXT_MAP diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 376d2827e736..5d3184cbf518 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -297,7 +297,7 @@ void __init setup_arch(char **cmdline_p) setup_smp(); #endif - riscv_init_cbom_blocksize(); + riscv_init_cbo_blocksizes(); riscv_fill_hwcap(); apply_boot_alternatives(); if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index eaf23fc14966..ba4832bb949b 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -98,6 +98,9 @@ void flush_icache_pte(pte_t pte) unsigned int riscv_cbom_block_size; EXPORT_SYMBOL_GPL(riscv_cbom_block_size); +unsigned int riscv_cboz_block_size; +EXPORT_SYMBOL_GPL(riscv_cboz_block_size); + static void cbo_get_block_size(struct device_node *node, const char *name, u32 *block_size, unsigned long *first_hartid) @@ -120,19 +123,23 @@ static void cbo_get_block_size(struct device_node *node, } } -void riscv_init_cbom_blocksize(void) +void riscv_init_cbo_blocksizes(void) { + unsigned long cbom_hartid, cboz_hartid; + u32 cbom_block_size = 0, cboz_block_size = 0; struct device_node *node; - unsigned long cbom_hartid; - u32 probed_block_size; - probed_block_size = 0; for_each_of_cpu_node(node) { - /* set block-size for cbom extension if available */ + /* set block-size for cbom and/or cboz extension if available */ cbo_get_block_size(node, "riscv,cbom-block-size", - &probed_block_size, &cbom_hartid); + &cbom_block_size, &cbom_hartid); + cbo_get_block_size(node, "riscv,cboz-block-size", + &cboz_block_size, &cboz_hartid); } - if (probed_block_size) - riscv_cbom_block_size = probed_block_size; + if (cbom_block_size) + riscv_cbom_block_size = cbom_block_size; + + if (cboz_block_size) + riscv_cboz_block_size = cboz_block_size; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id t13-20020a170906268d00b0087bdac06a3bsm1001221ejc.2.2023.02.09.07.26.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 07:26:38 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Anup Patel ' , 'Palmer Dabbelt ' , 'Paul Walmsley ' , 'Krzysztof Kozlowski ' , 'Atish Patra ' , 'Heiko Stuebner ' , 'Jisheng Zhang ' , 'Rob Herring ' , 'Albert Ou ' , 'Conor Dooley ' Subject: [PATCH v4 5/8] RISC-V: cpufeature: Put vendor_id to work Date: Thu, 9 Feb 2023 16:26:25 +0100 Message-Id: <20230209152628.129914-6-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209152628.129914-1-ajones@ventanamicro.com> References: <20230209152628.129914-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230209_152604_933093_E89756A8 X-CRM114-Status: GOOD ( 11.85 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When [ab]using alternatives as cpufeature "static keys", which can be used in assembly, also put vendor_id to work as application- specific data. This will be initially used in Zicboz's application to clear_page(), as Zicboz's block size must also be considered. In that case, vendor_id's role will be to convey the maximum block size which the Zicboz clear_page() implementation supports. cpufeature alternative applications which need to check for the existence or absence of other cpufeatures may also be able to make use of this. Signed-off-by: Andrew Jones --- arch/riscv/kernel/cpufeature.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 0d2db03cf167..74736b4f0624 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -278,6 +278,11 @@ void __init riscv_fill_hwcap(void) } #ifdef CONFIG_RISCV_ALTERNATIVE +static bool riscv_cpufeature_application_check(u32 feature, u16 data) +{ + return data == 0; +} + void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned int stage) @@ -289,8 +294,6 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, return; for (alt = begin; alt < end; alt++) { - if (alt->vendor_id != 0) - continue; if (alt->errata_id >= RISCV_ISA_EXT_MAX) { WARN(1, "This extension id:%d is not in ISA extension list", alt->errata_id); @@ -300,6 +303,9 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, if (!__riscv_isa_extension_available(NULL, alt->errata_id)) continue; + if (!riscv_cpufeature_application_check(alt->errata_id, alt->vendor_id)) + continue; + oldptr = ALT_OLD_PTR(alt); altptr = ALT_ALT_PTR(alt); patch_text_nosync(oldptr, altptr, alt->alt_len); From patchwork Thu Feb 9 15:26:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13134748 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7678AC636D6 for ; Thu, 9 Feb 2023 15:27:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id z15-20020a1709064e0f00b008af424d4d75sm614058eju.194.2023.02.09.07.26.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 07:26:40 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Anup Patel ' , 'Palmer Dabbelt ' , 'Paul Walmsley ' , 'Krzysztof Kozlowski ' , 'Atish Patra ' , 'Heiko Stuebner ' , 'Jisheng Zhang ' , 'Rob Herring ' , 'Albert Ou ' , 'Conor Dooley ' Subject: [PATCH v4 6/8] RISC-V: Use Zicboz in clear_page when available Date: Thu, 9 Feb 2023 16:26:26 +0100 Message-Id: <20230209152628.129914-7-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209152628.129914-1-ajones@ventanamicro.com> References: <20230209152628.129914-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230209_152604_951296_0F437F05 X-CRM114-Status: GOOD ( 19.07 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Using memset() to zero a 4K page takes 563 total instructions, where 20 are branches. clear_page(), with Zicboz and a 64 byte block size, takes 169 total instructions, where 4 are branches and 33 are nops. Even though the block size is a variable, thanks to alternatives, we can still implement a Duff device without having to do any preliminary calculations. This is achieved by taking advantage of 'vendor_id' being used as application-specific data for alternatives, enabling us to stop patching / unrolling when 4K bytes have been zeroed (we would loop and continue after 4K if the page size would be larger) For 4K pages, unrolling 16 times allows block sizes of 64 and 128 to only loop a few times and larger block sizes to not loop at all. Since cbo.zero doesn't take an offset, we also need an 'add' after each instruction, making the loop body 112 to 160 bytes. Hopefully this is small enough to not cause icache misses. Signed-off-by: Andrew Jones Acked-by: Conor Dooley --- arch/riscv/Kconfig | 13 ++++++ arch/riscv/include/asm/insn-def.h | 4 ++ arch/riscv/include/asm/page.h | 6 ++- arch/riscv/kernel/cpufeature.c | 11 +++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/clear_page.S | 71 +++++++++++++++++++++++++++++++ 6 files changed, 105 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/lib/clear_page.S diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 029d1d3b40bd..9590a1661caf 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -456,6 +456,19 @@ config RISCV_ISA_ZICBOM If you don't know what to do here, say Y. +config RISCV_ISA_ZICBOZ + bool "Zicboz extension support for faster zeroing of memory" + depends on !XIP_KERNEL && MMU + select RISCV_ALTERNATIVE + default y + help + Enable the use of the ZICBOZ extension (cbo.zero instruction) + when available. + + The Zicboz extension is used for faster zeroing of memory. + + If you don't know what to do here, say Y. + config TOOLCHAIN_HAS_ZIHINTPAUSE bool default y diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index e01ab51f50d2..6960beb75f32 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -192,4 +192,8 @@ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ RS1(base), SIMM12(2)) +#define CBO_zero(base) \ + INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ + RS1(base), SIMM12(4)) + #endif /* __ASM_INSN_DEF_H */ diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h index 9f432c1b5289..ccd168fe29d2 100644 --- a/arch/riscv/include/asm/page.h +++ b/arch/riscv/include/asm/page.h @@ -49,10 +49,14 @@ #ifndef __ASSEMBLY__ +#ifdef CONFIG_RISCV_ISA_ZICBOZ +void clear_page(void *page); +#else #define clear_page(pgaddr) memset((pgaddr), 0, PAGE_SIZE) +#endif #define copy_page(to, from) memcpy((to), (from), PAGE_SIZE) -#define clear_user_page(pgaddr, vaddr, page) memset((pgaddr), 0, PAGE_SIZE) +#define clear_user_page(pgaddr, vaddr, page) clear_page(pgaddr) #define copy_user_page(vto, vfrom, vaddr, topg) \ memcpy((vto), (vfrom), PAGE_SIZE) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 74736b4f0624..42246bbfa532 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -280,6 +280,17 @@ void __init riscv_fill_hwcap(void) #ifdef CONFIG_RISCV_ALTERNATIVE static bool riscv_cpufeature_application_check(u32 feature, u16 data) { + switch (feature) { + case RISCV_ISA_EXT_ZICBOZ: + /* + * Zicboz alternative applications provide the maximum + * supported block size order, or zero when it doesn't + * matter. If the current block size exceeds the maximum, + * then the alternative cannot be applied. + */ + return data == 0 || riscv_cboz_block_size <= (1U << data); + } + return data == 0; } diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 6c74b0bedd60..26cb2502ecf8 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -8,5 +8,6 @@ lib-y += strlen.o lib-y += strncmp.o lib-$(CONFIG_MMU) += uaccess.o lib-$(CONFIG_64BIT) += tishift.o +lib-$(CONFIG_RISCV_ISA_ZICBOZ) += clear_page.o obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o diff --git a/arch/riscv/lib/clear_page.S b/arch/riscv/lib/clear_page.S new file mode 100644 index 000000000000..5b851e727f7c --- /dev/null +++ b/arch/riscv/lib/clear_page.S @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Ventana Micro Systems Inc. + */ + +#include +#include +#include +#include +#include +#include + +#define CBOZ_ALT(order, old, new) \ + ALTERNATIVE(old, new, order, RISCV_ISA_EXT_ZICBOZ, CONFIG_RISCV_ISA_ZICBOZ) + +/* void clear_page(void *page) */ +ENTRY(__clear_page) +WEAK(clear_page) + li a2, PAGE_SIZE + + /* + * If Zicboz isn't present, or somehow has a block + * size larger than 4K, then fallback to memset. + */ + CBOZ_ALT(12, "j .Lno_zicboz", "nop") + + lw a1, riscv_cboz_block_size + add a2, a0, a2 +.Lzero_loop: + CBO_zero(a0) + add a0, a0, a1 + CBOZ_ALT(11, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") + CBO_zero(a0) + add a0, a0, a1 + CBOZ_ALT(10, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBOZ_ALT(9, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBOZ_ALT(8, "bltu a0, a2, .Lzero_loop; ret", "nop; nop") + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + CBO_zero(a0) + add a0, a0, a1 + bltu a0, a2, .Lzero_loop + ret +.Lno_zicboz: + li a1, 0 + tail __memset +END(__clear_page) From patchwork Thu Feb 9 15:26:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13134839 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1B7CC636D6 for ; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id s6-20020a50d486000000b004aab36ad060sm891945edi.92.2023.02.09.07.26.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 07:26:42 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Anup Patel ' , 'Palmer Dabbelt ' , 'Paul Walmsley ' , 'Krzysztof Kozlowski ' , 'Atish Patra ' , 'Heiko Stuebner ' , 'Jisheng Zhang ' , 'Rob Herring ' , 'Albert Ou ' , 'Conor Dooley ' , Anup Patel Subject: [PATCH v4 7/8] RISC-V: KVM: Provide UAPI for Zicboz block size Date: Thu, 9 Feb 2023 16:26:27 +0100 Message-Id: <20230209152628.129914-8-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209152628.129914-1-ajones@ventanamicro.com> References: <20230209152628.129914-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230209_152605_773709_F49BC996 X-CRM114-Status: GOOD ( 11.08 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org We're about to allow guests to use the Zicboz extension. KVM userspace needs to know the cache block size in order to properly advertise it to the guest. Provide a virtual config register for userspace to get it with the GET_ONE_REG API, but setting it cannot be supported, so disallow SET_ONE_REG. Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 92af6f3f057c..c1a1bb0fa91c 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -52,6 +52,7 @@ struct kvm_riscv_config { unsigned long mvendorid; unsigned long marchid; unsigned long mimpid; + unsigned long zicboz_block_size; }; /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 7c08567097f0..e5126cefbc87 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -276,6 +276,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, return -EINVAL; reg_val = riscv_cbom_block_size; break; + case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size): + if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) + return -EINVAL; + reg_val = riscv_cboz_block_size; + break; case KVM_REG_RISCV_CONFIG_REG(mvendorid): reg_val = vcpu->arch.mvendorid; break; @@ -347,6 +352,8 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, break; case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): return -EOPNOTSUPP; + case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size): + return -EOPNOTSUPP; case KVM_REG_RISCV_CONFIG_REG(mvendorid): if (!vcpu->arch.ran_atleast_once) vcpu->arch.mvendorid = reg_val; From patchwork Thu Feb 9 15:26:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13134746 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22CFFC61DA4 for ; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id z22-20020a17090655d600b00871f66bf354sm976530ejp.204.2023.02.09.07.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Feb 2023 07:26:43 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Anup Patel ' , 'Palmer Dabbelt ' , 'Paul Walmsley ' , 'Krzysztof Kozlowski ' , 'Atish Patra ' , 'Heiko Stuebner ' , 'Jisheng Zhang ' , 'Rob Herring ' , 'Albert Ou ' , 'Conor Dooley ' , Anup Patel Subject: [PATCH v4 8/8] RISC-V: KVM: Expose Zicboz to the guest Date: Thu, 9 Feb 2023 16:26:28 +0100 Message-Id: <20230209152628.129914-9-ajones@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230209152628.129914-1-ajones@ventanamicro.com> References: <20230209152628.129914-1-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230209_072644_897168_32811DE9 X-CRM114-Status: UNSURE ( 9.49 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Guests may use the cbo.zero instruction when the CPU has the Zicboz extension and the hypervisor sets henvcfg.CBZE. Add Zicboz support for KVM guests which may be enabled and disabled from KVM userspace using the ISA extension ONE_REG API. Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index c1a1bb0fa91c..e44c1e90eaa7 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -106,6 +106,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_SVINVAL, KVM_RISCV_ISA_EXT_ZIHINTPAUSE, KVM_RISCV_ISA_EXT_ZICBOM, + KVM_RISCV_ISA_EXT_ZICBOZ, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index e5126cefbc87..198ee86cad38 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -63,6 +63,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(SVPBMT), KVM_ISA_EXT_ARR(ZIHINTPAUSE), KVM_ISA_EXT_ARR(ZICBOM), + KVM_ISA_EXT_ARR(ZICBOZ), }; static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext) @@ -865,6 +866,9 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa) if (riscv_isa_extension_available(isa, ZICBOM)) henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); + if (riscv_isa_extension_available(isa, ZICBOZ)) + henvcfg |= ENVCFG_CBZE; + csr_write(CSR_HENVCFG, henvcfg); #ifdef CONFIG_32BIT csr_write(CSR_HENVCFGH, henvcfg >> 32);