From patchwork Sat Feb 11 01:17:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13136683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6C1DC05027 for ; Sat, 11 Feb 2023 01:18:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229518AbjBKBSD (ORCPT ); Fri, 10 Feb 2023 20:18:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229447AbjBKBSC (ORCPT ); Fri, 10 Feb 2023 20:18:02 -0500 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B25D63A08D; Fri, 10 Feb 2023 17:18:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676078281; x=1707614281; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=4hf1OloHBVcxR02BTOFRj9IkRyZKjqy/ZG29ImkR/mg=; b=ZW/B5D2lbfx5/fy5z2THVTJ2Aqx28uwfiKVRXx9v5U8QcE1RwDwiOm8K BeRN4DEjEf5r42x1nyRR7BBH54H3I2HH1nXPzwuD31YnZ98aqRyCI9m2i oSwKYJIm1Z/bhPdDgKPpqZHag2hjH4mtgVDmlU58uCeguxRLlbuGVd3/V z854/KcBxrsEF9d2xayKXEWVVnFEX4rTcc+1/IfsTVsyarenz+aIO6AIm Cph9oaiK8gIdmHSrD1whVfZHq5d5e3Ab95JCrPPw2/fYQ7MHVzEjEoJvd YGSyiFe7AJUgTOSkGECU5/3wrR4Vy4cRxnAbtriaVqTYN6+oEm0j4gNPy Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10617"; a="314210621" X-IronPort-AV: E=Sophos;i="5.97,287,1669104000"; d="scan'208";a="314210621" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2023 17:18:01 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10617"; a="670188088" X-IronPort-AV: E=Sophos;i="5.97,287,1669104000"; d="scan'208";a="670188088" Received: from qiuxu-clx.sh.intel.com ([10.239.53.105]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2023 17:17:58 -0800 From: Qiuxu Zhuo To: Tony Luck Cc: Qiuxu Zhuo , Borislav Petkov , Aristeu Rozanski , Mauro Carvalho Chehab , Feng Xu , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/1] EDAC/skx: Fix overflows on the DRAM row address mapping arrays Date: Sat, 11 Feb 2023 09:17:28 +0800 Message-Id: <20230211011728.71764-1-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The current DRAM row address mapping arrays skx_{open,close}_row[] only support ranks with sizes up to 16G. Decoding a rank address to a DRAM row address for a 32G rank by using either one of the above arrays by the skx_edac driver, will result in an overflow on the array. For a 32G rank, the most significant DRAM row address bit (the bit17) is mapped from the bit34 of the rank address. Add this new mapping item to both arrays to fix the overflow issue. Fixes: 4ec656bdf43a ("EDAC, skx_edac: Add EDAC driver for Skylake") Reported-by: Feng Xu Tested-by: Feng Xu Signed-off-by: Qiuxu Zhuo --- v1->v2: Fix the Fixes tag in the commit message. drivers/edac/skx_base.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/edac/skx_base.c b/drivers/edac/skx_base.c index 9397abb42c49..0a862336a7ce 100644 --- a/drivers/edac/skx_base.c +++ b/drivers/edac/skx_base.c @@ -510,7 +510,7 @@ static bool skx_rir_decode(struct decoded_addr *res) } static u8 skx_close_row[] = { - 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33 + 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33, 34 }; static u8 skx_close_column[] = { @@ -518,7 +518,7 @@ static u8 skx_close_column[] = { }; static u8 skx_open_row[] = { - 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33 + 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33, 34 }; static u8 skx_open_column[] = {