From patchwork Sat Feb 11 03:18:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89C0DC636D4 for ; Sat, 11 Feb 2023 03:18:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229689AbjBKDSi (ORCPT ); Fri, 10 Feb 2023 22:18:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229540AbjBKDSh (ORCPT ); Fri, 10 Feb 2023 22:18:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8F9F35BC; Fri, 10 Feb 2023 19:18:36 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 68A966602111; Sat, 11 Feb 2023 03:18:35 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085515; bh=wsikCNMiZKFgLF8VxbMNAMN5xcuiLSDwJPFjv5RhtwY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oG7+IzcdTybxpjx0fCajzTllBsTQirmb2YxPbpyMYNXWSRrIAHC7OipNowaNEiehe nsmTXnfkdBTJ0J3ms/SBwjXwha0y8QURPT20tk9pBIRJPSJ6oiJZDjGJdLYtm3/zVq 6pEbMm+dj3Wk8AAPu8hHutHV9oOZKf47dT+dR7nt0LuuUEhl32SdHwYkKyxuzM+JKs cmYUI0CSBL+sVPigjhXrQ4JdiAcv9OZLhfUo0cRs5Eswf1nC7JJfkZlXrBWF9BbBH7 rZDQ+oxqseId/nIhnNOfqp+COqhx/NzKmuaV5r5smcVl/ukDw2uxlaCtLTvsqvE6eP fhlibOa4agYlQ== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 01/12] dt-bindings: riscv: sifive-ccache: Add compatible for StarFive JH7100 SoC Date: Sat, 11 Feb 2023 05:18:10 +0200 Message-Id: <20230211031821.976408-2-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Document the compatible for the SiFive Composable Cache Controller found on the StarFive JH7100 SoC. This also requires extending the 'reg' property to handle distinct ranges, as specified via 'reg-names'. Signed-off-by: Cristian Ciocaltea Reviewed-by: Krzysztof Kozlowski --- .../bindings/riscv/sifive,ccache0.yaml | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index 31d20efaa6d3..2b864b2f12c9 100644 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -25,6 +25,7 @@ select: - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - starfive,jh7100-ccache required: - compatible @@ -37,6 +38,7 @@ properties: - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache + - starfive,jh7100-ccache - const: cache - items: - const: starfive,jh7110-ccache @@ -70,7 +72,13 @@ properties: - description: DirFail interrupt reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reg-names: + items: + - const: control + - const: sideband next-level-cache: true @@ -89,6 +97,7 @@ allOf: contains: enum: - sifive,fu740-c000-ccache + - starfive,jh7100-ccache - starfive,jh7110-ccache - microchip,mpfs-ccache @@ -106,12 +115,29 @@ allOf: Must contain entries for DirError, DataError and DataFail signals. maxItems: 3 + - if: + properties: + compatible: + contains: + const: starfive,jh7100-ccache + + then: + properties: + reg: + maxItems: 2 + + else: + properties: + reg: + maxItems: 1 + - if: properties: compatible: contains: enum: - sifive,fu740-c000-ccache + - starfive,jh7100-ccache - starfive,jh7110-ccache then: From patchwork Sat Feb 11 03:18:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEFDDC636D4 for ; Sat, 11 Feb 2023 03:19:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229703AbjBKDTB (ORCPT ); Fri, 10 Feb 2023 22:19:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229698AbjBKDSk (ORCPT ); Fri, 10 Feb 2023 22:18:40 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16A0323113; Fri, 10 Feb 2023 19:18:39 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 5630F6602114; Sat, 11 Feb 2023 03:18:38 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085518; bh=Qz2BvAFfeR2pDH8idXft8j3/6B8ejfNa6vswzgvImNI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GHzfI5rdTu9/UZQWhAxLUwT9InbdtWjYgD9KO+/XqXr3fY4lXHlyWhChStvUQR01m xRLs4k3bnjFo8PWBFh51vKusUx9xj/uvL1FNUKDZXF6f9TCCX2LQ3ULqnJT1TZ0Tyo Rz2D4/dDd9ddU/gHRWbfF5cH8VA38de5O2pTkRwv9EqmpIRkh9frNe8X/026R1N8V4 Tq9vVpS9hVB1I6Osa42muP8FW4Evlh11PlZ2njTaino7d+ojKQlCzS8vR7PsyWDO92 Wss6o1LNqXIDWpvrF/z0PG5pbHmgejn/aF+Ufr5DMyRRDfMUSQF2ud2JT48tfS+Qgu v1uC6CLBuhwsQ== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 02/12] dt-bindings: riscv: sifive-ccache: Add 'uncached-offset' property Date: Sat, 11 Feb 2023 05:18:11 +0200 Message-Id: <20230211031821.976408-3-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add the 'uncached-offset' property to be used for specifying the uncached memory offset required for handling non-coherent DMA transactions. Signed-off-by: Cristian Ciocaltea --- Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index 2b864b2f12c9..60cd87a2810a 100644 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -82,6 +82,11 @@ properties: next-level-cache: true + uncached-offset: + $ref: /schemas/types.yaml#/definitions/uint64 + description: | + Uncached memory offset for handling non-coherent DMA transactions. + memory-region: maxItems: 1 description: | From patchwork Sat Feb 11 03:18:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE124C64EC7 for ; Sat, 11 Feb 2023 03:19:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229727AbjBKDTD (ORCPT ); Fri, 10 Feb 2023 22:19:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229712AbjBKDTA (ORCPT ); Fri, 10 Feb 2023 22:19:00 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A5DB3C3D; Fri, 10 Feb 2023 19:18:42 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 002A06602123; Sat, 11 Feb 2023 03:18:40 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085521; bh=3V60+yUqxQRcUNuxYulirFMaKOTYIE7PaGKbZOUC0s0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mnEoqbs0VwxfMXt5qDvLiGFhb8V0gNhxaYj6rJMaOek7O/8UeoKKjk2iAFu+I6EWV MPWy3ayM5k8ZQ/I2TproZY5gdjsnltmIP9IdBHvqJopYxTJR41uSWuIyjvtfiJ14zf AH04ykzFvWuub2u7ikxOXNuQ68mQwBk6XmJsWzBAE6uHCXUuJ9hYCADWIQNcm/efHu z7cAU4mphDdxLakwH1klnEoqmgYugEdmVnjmcb61uYlWQXuq9qWeb2Bb+CS+hAfuvG Vq0HNyZSblq2UPQm2yoTgaHiq3f/zCZ1zi1R8CRdS+Gc2UkhoMnnMFsvFTuQDe246+ RH12SsTplWzLA== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 03/12] soc: sifive: ccache: Add StarFive JH7100 support Date: Sat, 11 Feb 2023 05:18:12 +0200 Message-Id: <20230211031821.976408-4-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Emil Renner Berthing This adds support for the StarFive JH7100 SoC which also feature this SiFive cache controller. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing [drop JH7110, rework Kconfig] Signed-off-by: Cristian Ciocaltea Reviewed-by: Conor Dooley --- drivers/soc/sifive/Kconfig | 1 + drivers/soc/sifive/sifive_ccache.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig index e86870be34c9..867cf16273a4 100644 --- a/drivers/soc/sifive/Kconfig +++ b/drivers/soc/sifive/Kconfig @@ -4,6 +4,7 @@ if SOC_SIFIVE || SOC_STARFIVE config SIFIVE_CCACHE bool "Sifive Composable Cache controller" + default SOC_STARFIVE help Support for the composable cache controller on SiFive platforms. diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 3684f5b40a80..676468c35859 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -106,6 +106,7 @@ static void ccache_config_read(void) static const struct of_device_id sifive_ccache_ids[] = { { .compatible = "sifive,fu540-c000-ccache" }, { .compatible = "sifive,fu740-c000-ccache" }, + { .compatible = "starfive,jh7100-ccache", .data = (void *)BIT(DATA_UNCORR) }, { .compatible = "sifive,ccache0" }, { /* end of table */ } }; @@ -210,11 +211,15 @@ static int __init sifive_ccache_init(void) struct device_node *np; struct resource res; int i, rc, intr_num; + const struct of_device_id *match; + unsigned long broken_irqs; - np = of_find_matching_node(NULL, sifive_ccache_ids); + np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match); if (!np) return -ENODEV; + broken_irqs = (uintptr_t)match->data; + if (of_address_to_resource(np, 0, &res)) { rc = -ENODEV; goto err_node_put; @@ -240,6 +245,10 @@ static int __init sifive_ccache_init(void) for (i = 0; i < intr_num; i++) { g_irq[i] = irq_of_parse_and_map(np, i); + + if (broken_irqs & BIT(i)) + continue; + rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL); if (rc) { From patchwork Sat Feb 11 03:18:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C8FEC05027 for ; Sat, 11 Feb 2023 03:19:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229789AbjBKDTI (ORCPT ); Fri, 10 Feb 2023 22:19:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229741AbjBKDTB (ORCPT ); Fri, 10 Feb 2023 22:19:01 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DC08880D6; Fri, 10 Feb 2023 19:18:45 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1719D6602112; Sat, 11 Feb 2023 03:18:44 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085524; bh=dWT0RanDNiM3R2DCgFc/XbzaC63mZATcL9ooscBLbYQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OEECfIzkegZFxQGlNbEk0xpVXMYbfsjuxNV0jzVV+mhag3vfoFisKqwcwAejSdADU c2tk68Yksshis0/Wo96/mdHLwprlFo1d7gT4NWnVZo4FhmuA3vb8qRWnxx5jPtgXWv b/pV/VG5UGPafKrQc9OH4xX5/PaK4lgE+77yMgpU1Bz0QdUXAVG4RG5L9OgAoYqk8P iQzRVEev8TgYOSWRcZ+nLYNmv7Ycrz7LIMBI0fVjR8NpLZy9o8IZDtO3Y2KKPhWK6X asyOruKtVqPgbh/86k8oWarMwscItXxCD4n4rBW0WRhCtDtEcFkJUN2o7DMhhM26VZ Q2BNo4v2uF72Q== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 04/12] soc: sifive: ccache: Add non-coherent DMA handling Date: Sat, 11 Feb 2023 05:18:13 +0200 Message-Id: <20230211031821.976408-5-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Emil Renner Berthing Add functions to flush the caches and handle non-coherent DMA. Signed-off-by: Emil Renner Berthing [replace with ] Signed-off-by: Cristian Ciocaltea --- drivers/soc/sifive/sifive_ccache.c | 60 +++++++++++++++++++++++++++++- include/soc/sifive/sifive_ccache.h | 21 +++++++++++ 2 files changed, 80 insertions(+), 1 deletion(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 676468c35859..0062635d845f 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -8,13 +8,16 @@ #define pr_fmt(fmt) "CCACHE: " fmt +#include #include #include #include #include #include #include +#include #include +#include #include #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100 @@ -39,10 +42,14 @@ #define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16) #define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24) +#define SIFIVE_CCACHE_FLUSH64 0x200 +#define SIFIVE_CCACHE_FLUSH32 0x240 + #define SIFIVE_CCACHE_WAYENABLE 0x08 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 #define SIFIVE_CCACHE_MAX_ECCINTR 4 +#define SIFIVE_CCACHE_LINE_SIZE 64 static void __iomem *ccache_base; static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; @@ -125,6 +132,47 @@ int unregister_sifive_ccache_error_notifier(struct notifier_block *nb) } EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier); +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +static phys_addr_t uncached_offset; +DEFINE_STATIC_KEY_FALSE(sifive_ccache_handle_noncoherent_key); + +void sifive_ccache_flush_range(phys_addr_t start, size_t len) +{ + phys_addr_t end = start + len; + phys_addr_t line; + + if (!len) + return; + + mb(); + for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end; + line += SIFIVE_CCACHE_LINE_SIZE) { +#ifdef CONFIG_32BIT + writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32); +#else + writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64); +#endif + mb(); + } +} +EXPORT_SYMBOL_GPL(sifive_ccache_flush_range); + +void *sifive_ccache_set_uncached(void *addr, size_t size) +{ + phys_addr_t phys_addr = __pa(addr) + uncached_offset; + void *mem_base; + + mem_base = memremap(phys_addr, size, MEMREMAP_WT); + if (!mem_base) { + pr_err("%s memremap failed for addr %p\n", __func__, addr); + return ERR_PTR(-EINVAL); + } + + return mem_base; +} +EXPORT_SYMBOL_GPL(sifive_ccache_set_uncached); +#endif /* CONFIG_RISCV_DMA_NONCOHERENT */ + static int ccache_largest_wayenabled(void) { return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; @@ -213,6 +261,7 @@ static int __init sifive_ccache_init(void) int i, rc, intr_num; const struct of_device_id *match; unsigned long broken_irqs; + u64 __maybe_unused offset; np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match); if (!np) @@ -258,6 +307,15 @@ static int __init sifive_ccache_init(void) } of_node_put(np); +#ifdef CONFIG_RISCV_DMA_NONCOHERENT + if (!of_property_read_u64(np, "uncached-offset", &offset)) { + uncached_offset = offset; + static_branch_enable(&sifive_ccache_handle_noncoherent_key); + riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE; + riscv_noncoherent_supported(); + } +#endif + ccache_config_read(); ccache_cache_ops.get_priv_group = ccache_get_priv_group; @@ -278,4 +336,4 @@ static int __init sifive_ccache_init(void) return rc; } -device_initcall(sifive_ccache_init); +arch_initcall(sifive_ccache_init); diff --git a/include/soc/sifive/sifive_ccache.h b/include/soc/sifive/sifive_ccache.h index 4d4ed49388a0..d349ccb3969b 100644 --- a/include/soc/sifive/sifive_ccache.h +++ b/include/soc/sifive/sifive_ccache.h @@ -7,10 +7,31 @@ #ifndef __SOC_SIFIVE_CCACHE_H #define __SOC_SIFIVE_CCACHE_H +#include +#include + extern int register_sifive_ccache_error_notifier(struct notifier_block *nb); extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb); #define SIFIVE_CCACHE_ERR_TYPE_CE 0 #define SIFIVE_CCACHE_ERR_TYPE_UE 1 +DECLARE_STATIC_KEY_FALSE(sifive_ccache_handle_noncoherent_key); + +static inline bool sifive_ccache_handle_noncoherent(void) +{ +#ifdef CONFIG_SIFIVE_CCACHE + return static_branch_unlikely(&sifive_ccache_handle_noncoherent_key); +#else + return false; +#endif +} + +void sifive_ccache_flush_range(phys_addr_t start, size_t len); +void *sifive_ccache_set_uncached(void *addr, size_t size); +static inline void sifive_ccache_clear_uncached(void *addr, size_t size) +{ + memunmap(addr); +} + #endif /* __SOC_SIFIVE_CCACHE_H */ From patchwork Sat Feb 11 03:18:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92B43C636D4 for ; Sat, 11 Feb 2023 03:19:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229830AbjBKDTQ (ORCPT ); Fri, 10 Feb 2023 22:19:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229762AbjBKDTC (ORCPT ); Fri, 10 Feb 2023 22:19:02 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF5A03D927; Fri, 10 Feb 2023 19:18:47 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 8B4A56602125; Sat, 11 Feb 2023 03:18:46 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085526; bh=9SuKyW5m2s3LuV67I9467kX5ZI8GexmXrVSVNnkz2OQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hMTt6dPu/18IXFr94zL95Pql9lUdJQIC8cRbs4VqMuTNSx9GF2XloISZKM+sBOr4u CsboPdGCB0WK1VYgN2LIAMbtwzKUrSMRGelHNbGahZm9MERYVOPB8944+pwz+OX5QY EBjcqKPDg+yy/WacrnF+ow+01z55aOeOlOsdd3WISdMKgdS09bvoU5aZLZej5AIrf1 NmctoUae4i0AnT+Vj5b0hIxO2usmUimXWT4H/GLzMlUr+AVnEtuV2SxrbkvvUT7Zjl U/NN9R5hqCyffo4/qvcZlfZbXKDt+Gj2/DfVtf8HPNuY0Wj2mBlmNQdJzIFbBHH9RC rhRwKeCL0yLKg== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 05/12] riscv: Implement non-coherent DMA support via SiFive cache flushing Date: Sat, 11 Feb 2023 05:18:14 +0200 Message-Id: <20230211031821.976408-6-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Emil Renner Berthing This variant is used on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing Signed-off-by: Cristian Ciocaltea --- arch/riscv/Kconfig | 6 ++++-- arch/riscv/mm/dma-noncoherent.c | 37 +++++++++++++++++++++++++++++++-- 2 files changed, 39 insertions(+), 4 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9c687da7756d..05f6c77faf6f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -232,12 +232,14 @@ config LOCKDEP_SUPPORT def_bool y config RISCV_DMA_NONCOHERENT - bool + bool "Support non-coherent DMA" + default SOC_STARFIVE select ARCH_HAS_DMA_PREP_COHERENT + select ARCH_HAS_DMA_SET_UNCACHED + select ARCH_HAS_DMA_CLEAR_UNCACHED select ARCH_HAS_SYNC_DMA_FOR_DEVICE select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SETUP_DMA_OPS - select DMA_DIRECT_REMAP config AS_HAS_INSN def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero) diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index d919efab6eba..e07e53aea537 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -9,14 +9,21 @@ #include #include #include +#include static bool noncoherent_supported; void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, enum dma_data_direction dir) { - void *vaddr = phys_to_virt(paddr); + void *vaddr; + if (sifive_ccache_handle_noncoherent()) { + sifive_ccache_flush_range(paddr, size); + return; + } + + vaddr = phys_to_virt(paddr); switch (dir) { case DMA_TO_DEVICE: ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); @@ -35,8 +42,14 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, enum dma_data_direction dir) { - void *vaddr = phys_to_virt(paddr); + void *vaddr; + + if (sifive_ccache_handle_noncoherent()) { + sifive_ccache_flush_range(paddr, size); + return; + } + vaddr = phys_to_virt(paddr); switch (dir) { case DMA_TO_DEVICE: break; @@ -49,10 +62,30 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, } } +void *arch_dma_set_uncached(void *addr, size_t size) +{ + if (sifive_ccache_handle_noncoherent()) + return sifive_ccache_set_uncached(addr, size); + + return addr; +} + +void arch_dma_clear_uncached(void *addr, size_t size) +{ + if (sifive_ccache_handle_noncoherent()) + sifive_ccache_clear_uncached(addr, size); +} + void arch_dma_prep_coherent(struct page *page, size_t size) { void *flush_addr = page_address(page); + if (sifive_ccache_handle_noncoherent()) { + memset(flush_addr, 0, size); + sifive_ccache_flush_range(__pa(flush_addr), size); + return; + } + ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); } From patchwork Sat Feb 11 03:18:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69C09C636D4 for ; Sat, 11 Feb 2023 03:19:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229874AbjBKDT0 (ORCPT ); Fri, 10 Feb 2023 22:19:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229777AbjBKDTH (ORCPT ); Fri, 10 Feb 2023 22:19:07 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCEBB84F42; Fri, 10 Feb 2023 19:18:50 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 452C46602116; Sat, 11 Feb 2023 03:18:49 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085529; bh=Ogmcu0djiCm10ycXgbUuJ7cEbzi156f9C1KsCx+q2FI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nN13tQTAM5JWAD7C8n8ylR+HsLi/Z1YQ1vwzeCV78eigKOq5MyWsW7yY4s09lgPfx smj3EctbM5vW27EAnfeFp4PcVUWKrr618YXZIgi5iocIEqAA+gwIHuBiJzN+zrLVT7 fNBAx4iTnqtPDNXBpakG4TOakUKOw7Qc3EnFjsWMYamdWu9C3ce//NUCHwomRpI4tw jDL30mNX4RuKEYHgIVtvifgpy+Y+yvFbtuYweBpM80bvbAcGdBBvK1gRqroCETAVD3 SXFs8mUcpUY/yens+0waJ0SggLIDFFABfzEax2jAnSbwdqqZH9yIF9aaqBejtM+8WS pX3cvWP3J2Xfw== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 06/12] dt-bindings: mfd: syscon: Add StarFive JH7100 sysmain compatible Date: Sat, 11 Feb 2023 05:18:15 +0200 Message-Id: <20230211031821.976408-7-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Emil Renner Berthing Document StarFive JH7100 SoC compatible for sysmain registers. Signed-off-by: Emil Renner Berthing Signed-off-by: Cristian Ciocaltea Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index c828c4f5e4a7..43f564be709f 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -67,6 +67,7 @@ properties: - rockchip,rk3568-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - starfive,jh7100-sysmain - const: syscon From patchwork Sat Feb 11 03:18:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136828 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BBEEC636D3 for ; Sat, 11 Feb 2023 03:19:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229909AbjBKDTb (ORCPT ); Fri, 10 Feb 2023 22:19:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229801AbjBKDTI (ORCPT ); Fri, 10 Feb 2023 22:19:08 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D219D880F6; Fri, 10 Feb 2023 19:18:53 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 651E6660211A; Sat, 11 Feb 2023 03:18:52 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085532; bh=0BO882sWApwI6Wscjhip8MF0KqwHYe/THm/J3y/0b0o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=S3s2oQkcRGhZ6jdQzVpXMV0mBoYa0lo/RGpLmrG3pXtSu/54qSeNOsfy66KoMutEI 3E53lyoSKP2pabRbWqY04m5Yo1cJKbP0+w5PiKuqeKJmJTIBB+vbK9uj9SvKX3KrvD dMkEpLflWHL+vEq5ylHS9BFhKkteQS8DSXmUOEFxG4Xtfo2N7aalN8+z2fS0SspDSf jf6K67v35sKNfkWTll7SJcpO1BtBFPtF8srXAmpGJOHge0+WdJWyLVXzjpeQ5vBlgI acJKoyW9JCSip1guYzv6xw7VW3zlF0q/deKqa0Kn1CXq4OVnWgzETD3dBCM5Jx4S4Z VFcUOdqcyElng== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 07/12] dt-bindings: net: Add StarFive JH7100 SoC Date: Sat, 11 Feb 2023 05:18:16 +0200 Message-Id: <20230211031821.976408-8-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add DT bindings documentation for the Synopsys DesignWare MAC found on the StarFive JH7100 SoC. Adjust 'reset' and 'reset-names' properties to allow using 'ahb' instead of the 'stmmaceth' reset signal, as required by JH7100. Signed-off-by: Cristian Ciocaltea --- .../devicetree/bindings/net/snps,dwmac.yaml | 15 ++- .../bindings/net/starfive,jh7100-dwmac.yaml | 106 ++++++++++++++++++ MAINTAINERS | 5 + 3 files changed, 122 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/starfive,jh7100-dwmac.yaml diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index e88a86623fce..71522a2cd7a4 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -89,6 +89,7 @@ properties: - snps,dwmac-5.10a - snps,dwxgmac - snps,dwxgmac-2.10 + - starfive,jh7100-dwmac reg: minItems: 1 @@ -131,12 +132,17 @@ properties: - ptp_ref resets: - maxItems: 1 - description: - MAC Reset signal. + minItems: 1 + items: + - description: MAC Reset signal + - description: AHB Reset signal reset-names: - const: stmmaceth + minItems: 1 + contains: + enum: + - stmmaceth + - ahb power-domains: maxItems: 1 @@ -578,6 +584,7 @@ allOf: - snps,dwxgmac - snps,dwxgmac-2.10 - st,spear600-gmac + - starfive,jh7100-dwmac then: properties: diff --git a/Documentation/devicetree/bindings/net/starfive,jh7100-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7100-dwmac.yaml new file mode 100644 index 000000000000..6afe30690172 --- /dev/null +++ b/Documentation/devicetree/bindings/net/starfive,jh7100-dwmac.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 StarFive Technology Co., Ltd. +# Copyright (C) 2022 Emil Renner Berthing +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/starfive,jh7100-dwmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 DWMAC Ethernet Controller + +maintainers: + - Emil Renner Berthing + +# We need a select here so we don't match all nodes with 'snps,dwmac' +select: + properties: + compatible: + contains: + const: starfive,jh7100-dwmac + required: + - compatible + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + items: + - const: starfive,jh7100-dwmac + - const: snps,dwmac + + clocks: + items: + - description: GMAC main clock + - description: GMAC AHB clock + - description: PTP clock + - description: GTX clock + - description: TX clock + + clock-names: + items: + - const: stmmaceth + - const: pclk + - const: ptp_ref + - const: gtxc + - const: tx + + resets: + description: AHB Reset signal + + reset-names: + const: ahb + + starfive,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the syscon node + + starfive,gtxclk-dlychain: + $ref: /schemas/types.yaml#/definitions/uint32 + description: GTX clock delay chain setting + +required: + - compatible + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + gmac: ethernet@10020000 { + compatible = "starfive,jh7100-dwmac", "snps,dwmac"; + reg = <0x0 0x10020000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, + <&clkgen JH7100_CLK_GMAC_AHB>, + <&clkgen JH7100_CLK_GMAC_PTP_REF>, + <&clkgen JH7100_CLK_GMAC_GTX>, + <&clkgen JH7100_CLK_GMAC_TX_INV>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "gtxc", "tx"; + resets = <&rstgen JH7100_RSTN_GMAC_AHB>; + reset-names = "ahb"; + interrupts = <6>, <7>; + interrupt-names = "macirq", "eth_wake_irq"; + max-frame-size = <9000>; + phy-mode = "rgmii-txid"; + snps,multicast-filter-bins = <32>; + snps,perfect-filter-entries = <128>; + starfive,syscon = <&sysmain>; + rx-fifo-depth = <32768>; + tx-fifo-depth = <16384>; + snps,axi-config = <&stmmac_axi_setup>; + snps,fixed-burst; + snps,force_thresh_dma_mode; + snps,no-pbl-x8; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <256 128 64 32 0 0 0>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index abed40db41f0..d48468b81b94 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19816,6 +19816,11 @@ M: Emil Renner Berthing S: Maintained F: arch/riscv/boot/dts/starfive/ +STARFIVE DWMAC GLUE LAYER +M: Emil Renner Berthing +S: Maintained +F: Documentation/devicetree/bindings/net/starfive,jh7100-dwmac.yaml + STARFIVE JH7100 CLOCK DRIVERS M: Emil Renner Berthing S: Maintained From patchwork Sat Feb 11 03:18:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136829 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87AB6C05027 for ; Sat, 11 Feb 2023 03:19:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229768AbjBKDTm (ORCPT ); Fri, 10 Feb 2023 22:19:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229845AbjBKDTY (ORCPT ); Fri, 10 Feb 2023 22:19:24 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD97F85B09; Fri, 10 Feb 2023 19:18:56 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 46C9F6602116; Sat, 11 Feb 2023 03:18:55 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085535; bh=TwwenY6La9ML4nip9B8ZX+9fLGGbM4jAo/uXYp0Qk4g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OKKkxrnUMuOi0Jh4iaoScbQdgxmTpT21oDKQCOanqE8R1krG6V9W13cJ50yrqcsVo +ucoeJ7OsadEO/0r4YYaXdoMCiUprTqbLHRIbmesNRuTkWJZcGF4WHwNEWFlMiDv7V cOX+NXcfXAB8TL+niHinGc5huEX+FnSVX89Jlvock4vuc54MDerKLyeQxlPSplwOFB N6fGJaqAHupHho1yyqlmwZqx+xRY2NkM3BM1zTh8UFFWe8KdmkWU2iYgbibZ3yPwmX om419IAXnIh0hH6Nq1tCvUHRsdq/OvvC60e6GbktI11Ny1+1hSiprEMCd0UVRLRt31 ukA0TQq82HJYw== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 08/12] net: stmmac: Add glue layer for StarFive JH7100 SoC Date: Sat, 11 Feb 2023 05:18:17 +0200 Message-Id: <20230211031821.976408-9-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Emil Renner Berthing This adds a glue layer for the Synopsys DesignWare MAC IP core on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing [drop references to JH7110, update JH7100 compatible string] Signed-off-by: Cristian Ciocaltea --- MAINTAINERS | 1 + drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-starfive.c | 155 ++++++++++++++++++ 4 files changed, 169 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS index d48468b81b94..defedaff6041 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19820,6 +19820,7 @@ STARFIVE DWMAC GLUE LAYER M: Emil Renner Berthing S: Maintained F: Documentation/devicetree/bindings/net/starfive,jh7100-dwmac.yaml +F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c STARFIVE JH7100 CLOCK DRIVERS M: Emil Renner Berthing diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index f77511fe4e87..2c81aa594291 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -165,6 +165,18 @@ config DWMAC_SOCFPGA for the stmmac device driver. This driver is used for arria5 and cyclone5 FPGA SoCs. +config DWMAC_STARFIVE + tristate "StarFive DWMAC support" + default m if SOC_STARFIVE + depends on SOC_STARFIVE || COMPILE_TEST + select MFD_SYSCON + help + Support for ethernet controller on StarFive SOCs. + + This selects StarFive SoC glue layer support for the stmmac device + driver. This driver is used for the JH71x0 series GMAC ethernet + controller. + config DWMAC_STI tristate "STi GMAC support" default ARCH_STI diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index 057e4bab5c08..8738fdbb4b2d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o +obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c new file mode 100644 index 000000000000..d4c81f1a5482 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dwmac-starfive.c - DWMAC glue layer for StarFive JH7100 SoC + * + * Copyright (C) 2021 Emil Renner Berthing + */ + +#include +#include +#include +#include +#include + +#include "stmmac.h" +#include "stmmac_platform.h" + +#define JH7100_SYSMAIN_REGISTER28 0x70 +/* The value below is not a typo, just really bad naming by StarFive ¯\_(ツ)_/¯ */ +#define JH7100_SYSMAIN_REGISTER49 0xc8 + +struct dwmac_starfive { + struct device *dev; + struct clk *gtxc; +}; + +static int dwmac_starfive_jh7100_syscon_init(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *sysmain; + u32 gtxclk_dlychain; + int ret; + + sysmain = syscon_regmap_lookup_by_phandle(np, "starfive,syscon"); + if (IS_ERR(sysmain)) + return dev_err_probe(dev, PTR_ERR(sysmain), + "error getting sysmain registers\n"); + + /* Choose RGMII interface to the phy. + * TODO: support other interfaces once we know the meaning of other + * values in the register + */ + ret = regmap_update_bits(sysmain, JH7100_SYSMAIN_REGISTER28, 0x7, 1); + if (ret) + return dev_err_probe(dev, ret, "error selecting gmac interface\n"); + + if (!of_property_read_u32(np, "starfive,gtxclk-dlychain", >xclk_dlychain)) { + ret = regmap_write(sysmain, JH7100_SYSMAIN_REGISTER49, gtxclk_dlychain); + if (ret) + return dev_err_probe(dev, ret, "error selecting gtxclk delay chain\n"); + } + + return 0; +} + +static void dwmac_starfive_fix_mac_speed(void *data, unsigned int speed) +{ + struct dwmac_starfive *dwmac = data; + unsigned long rate; + int ret; + + switch (speed) { + case SPEED_1000: + rate = 125000000; + break; + case SPEED_100: + rate = 25000000; + break; + case SPEED_10: + rate = 2500000; + break; + default: + dev_warn(dwmac->dev, "unsupported link speed %u\n", speed); + return; + } + + ret = clk_set_rate(dwmac->gtxc, rate); + if (ret) + dev_err(dwmac->dev, "error setting gtx clock rate: %d\n", ret); +} + +static int dwmac_starfive_probe(struct platform_device *pdev) +{ + struct stmmac_resources stmmac_res; + struct plat_stmmacenet_data *plat; + struct dwmac_starfive *dwmac; + struct clk *txclk; + int (*syscon_init)(struct device *dev); + int ret; + + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); + if (!dwmac) + return -ENOMEM; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + syscon_init = of_device_get_match_data(&pdev->dev); + if (syscon_init) { + ret = syscon_init(&pdev->dev); + if (ret) + return ret; + } + + dwmac->gtxc = devm_clk_get_enabled(&pdev->dev, "gtxc"); + if (IS_ERR(dwmac->gtxc)) + return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->gtxc), + "error getting/enabling gtxc clock\n"); + + txclk = devm_clk_get_enabled(&pdev->dev, "tx"); + if (IS_ERR(txclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(txclk), + "error getting/enabling tx clock\n"); + + plat = stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat)) + return dev_err_probe(&pdev->dev, PTR_ERR(plat), + "dt configuration failed\n"); + + dwmac->dev = &pdev->dev; + plat->bsp_priv = dwmac; + plat->fix_mac_speed = dwmac_starfive_fix_mac_speed; + + ret = stmmac_dvr_probe(&pdev->dev, plat, &stmmac_res); + if (ret) { + stmmac_remove_config_dt(pdev, plat); + return ret; + } + + return 0; +} + +static const struct of_device_id dwmac_starfive_match[] = { + { + .compatible = "starfive,jh7100-dwmac", + .data = dwmac_starfive_jh7100_syscon_init, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, dwmac_starfive_match); + +static struct platform_driver dwmac_starfive_driver = { + .probe = dwmac_starfive_probe, + .remove = stmmac_pltfr_remove, + .driver = { + .name = "dwmac-starfive", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = dwmac_starfive_match, + }, +}; +module_platform_driver(dwmac_starfive_driver); + +MODULE_AUTHOR("Emil Renner Berthing "); +MODULE_DESCRIPTION("StarFive DWMAC Glue Layer"); +MODULE_LICENSE("GPL"); From patchwork Sat Feb 11 03:18:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53F66C636D3 for ; Sat, 11 Feb 2023 03:19:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229777AbjBKDTy (ORCPT ); Fri, 10 Feb 2023 22:19:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229889AbjBKDT0 (ORCPT ); Fri, 10 Feb 2023 22:19:26 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4432985B1C; Fri, 10 Feb 2023 19:19:00 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id D9D2A660211D; Sat, 11 Feb 2023 03:18:58 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085539; bh=z6mSA1zFWKsbl8mcj+uQ0w8gbdjZfgd7q1ePD6gAlnc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G4XTBi0NB+o7cJELk405RK/2xN1ZA3BdMBGzuWdB8fNhFWbAhPBz6lx9nymo4UCno zmZn6Nc/fVNvbUjO/VRw3DIBUUe7UTSHYC3mwL/9/uaXjit0eaq7EKYHOHvQZ8+U4Z GMFUG5t8EaRyHxIbpkyh9cVlLy3NJKFqA7VuQcrIL3g73XrEtrl/cPjV/iXSbw2lFv iJE5SgH3ZwNXlboapW/mjHpuuMIjAugm66FtaswR76r4mD/gB8e+wcxSFp51s/vVZf 5z3JiCsVqSz/VoWnyw8HF4uXdrbfdgexT30bmSrlxWz/qj/9fDhNuPx22gFfP0J7rG L1MRolixZf+tw== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 09/12] riscv: dts: starfive: Add dma-noncoherent for JH7100 SoC Date: Sat, 11 Feb 2023 05:18:18 +0200 Message-Id: <20230211031821.976408-10-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The RISC-V architecture is by default coherent, as indicated by CONFIG_OF_DMA_DEFAULT_COHERENT, but the StarFive JH7100 is not, hence provide the dma-noncoherent property to the soc DT node. Signed-off-by: Cristian Ciocaltea --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 000447482aca..7109e70fdab8 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -114,6 +114,7 @@ soc { #address-cells = <2>; #size-cells = <2>; ranges; + dma-noncoherent; clint: clint@2000000 { compatible = "starfive,jh7100-clint", "sifive,clint0"; From patchwork Sat Feb 11 03:18:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DEC0C05027 for ; Sat, 11 Feb 2023 03:19:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229972AbjBKDTz (ORCPT ); Fri, 10 Feb 2023 22:19:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229902AbjBKDT2 (ORCPT ); Fri, 10 Feb 2023 22:19:28 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E09A885B2F; Fri, 10 Feb 2023 19:19:02 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id 80E466602127; Sat, 11 Feb 2023 03:19:01 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085541; bh=XW8rElFUTfgsJr1jtp6+bs1URQt5kqLzyalOrXtwnI0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QRSffU9SmuyvwYAm+UPE3h0oUhI+XYMgdzYG7GG38kA0e0174udJj1lzuUqTkTAW5 jJqKpWZ512dZgilIhNYQiB72no9UdbhJKRDCSU+ckWSBhW0NyvxAjkvC/8C0qyxK8e LFdZngHPm/fTyHwN8rONF8yB2RvwxPnTtwxTtIX0QoVsGCCr0dbtGF72hVIEcMJBlg 83PRBJ822Q2NEowQn1EwN4+L4YRQG/ZPxscIT5XhGFC3xtO28HnnVxnIF++/evL3/Q lh9cxBQYChoB2YQUfa+g1a6o/IwTo8CgvVaThXXaQszH7k4cp8oHKUD7aRoofocVQi egZmlE6B9+bnw== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 10/12] riscv: dts: starfive: jh7100: Add ccache DT node Date: Sat, 11 Feb 2023 05:18:19 +0200 Message-Id: <20230211031821.976408-11-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Provide a DT node for the Sifive Composable Cache controller found on the StarFive JH7100 SoC. Note this is also used to support non-coherent DMA. Signed-off-by: Cristian Ciocaltea --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 7109e70fdab8..88f91bc5753b 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -32,6 +32,7 @@ U74_0: cpu@0 { i-tlb-sets = <1>; i-tlb-size = <32>; mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; tlb-split; @@ -57,6 +58,7 @@ U74_1: cpu@1 { i-tlb-sets = <1>; i-tlb-size = <32>; mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; tlb-split; @@ -116,6 +118,20 @@ soc { ranges; dma-noncoherent; + ccache: cache-controller@2010000 { + compatible = "starfive,jh7100-ccache", "cache"; + reg = <0x0 0x2010000 0x0 0x1000>, + <0x0 0x8000000 0x0 0x2000000>; + reg-names = "control", "sideband"; + interrupts = <128>, <130>, <131>, <129>; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + uncached-offset = <0xf 0x80000000>; + }; + clint: clint@2000000 { compatible = "starfive,jh7100-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0x10000>; From patchwork Sat Feb 11 03:18:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13C8EC6379F for ; Sat, 11 Feb 2023 03:19:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229804AbjBKDT5 (ORCPT ); Fri, 10 Feb 2023 22:19:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229751AbjBKDTi (ORCPT ); Fri, 10 Feb 2023 22:19:38 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19BBDBDD8; Fri, 10 Feb 2023 19:19:06 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id B15676602112; Sat, 11 Feb 2023 03:19:04 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085544; bh=giBLXfHgd+nXmXgHpm08kBXy7O346waFR5TnsQQNUJ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c4QNRDT72f7rGgDkbpsH5cio8u1cyWic15TpkDUfoubuBgE5U6mjkH2uwqQJsEuck /zvq5XfWc3sECoa1uHGMUfMgw5BxNfXqKQVL9+J0nimoYf58szUQrILkSxUDqvtW08 B2ovKjfoji0bZP+v2SsEywo2OiyB+wXv29mrqZVM2DBeRaC/YLhDUkP+F15oQPq5fh ch5CR2oIk/P8nfnsHGCF+yyvyg+j/E1hpz/o2U5lJkRK1Mkts/8dfttRgJ1kTqVGxL yZeCyn8WW4dI2kWbdLtXmggsRq7SKHm2GLZ0HacPogzx/P3o3jfS4w7S2JwSAe/fGz NwN72WtsW7yTw== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 11/12] riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes Date: Sat, 11 Feb 2023 05:18:20 +0200 Message-Id: <20230211031821.976408-12-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Provide the sysmain and gmac DT nodes supporting the DWMAC found on the StarFive JH7100 SoC. Signed-off-by: Cristian Ciocaltea --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 88f91bc5753b..0918af7b6eb0 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -164,6 +164,44 @@ rstgen: reset-controller@11840000 { #reset-cells = <1>; }; + sysmain: syscon@11850000 { + compatible = "starfive,jh7100-sysmain", "syscon"; + reg = <0x0 0x11850000 0x0 0x10000>; + }; + + gmac: ethernet@10020000 { + compatible = "starfive,jh7100-dwmac", "snps,dwmac"; + reg = <0x0 0x10020000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>, + <&clkgen JH7100_CLK_GMAC_AHB>, + <&clkgen JH7100_CLK_GMAC_PTP_REF>, + <&clkgen JH7100_CLK_GMAC_GTX>, + <&clkgen JH7100_CLK_GMAC_TX_INV>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "gtxc", "tx"; + resets = <&rstgen JH7100_RSTN_GMAC_AHB>; + reset-names = "ahb"; + interrupts = <6>, <7>; + interrupt-names = "macirq", "eth_wake_irq"; + max-frame-size = <9000>; + phy-mode = "rgmii-txid"; + snps,multicast-filter-bins = <32>; + snps,perfect-filter-entries = <128>; + starfive,syscon = <&sysmain>; + rx-fifo-depth = <32768>; + tx-fifo-depth = <16384>; + snps,axi-config = <&stmmac_axi_setup>; + snps,fixed-burst; + snps,force_thresh_dma_mode; + snps,no-pbl-x8; + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + snps,blen = <256 128 64 32 0 0 0>; + }; + }; + i2c0: i2c@118b0000 { compatible = "snps,designware-i2c"; reg = <0x0 0x118b0000 0x0 0x10000>; From patchwork Sat Feb 11 03:18:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13136833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89D9BC636D4 for ; Sat, 11 Feb 2023 03:20:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230007AbjBKDUS (ORCPT ); Fri, 10 Feb 2023 22:20:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229942AbjBKDTm (ORCPT ); Fri, 10 Feb 2023 22:19:42 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36031BDE5; Fri, 10 Feb 2023 19:19:09 -0800 (PST) Received: from localhost (unknown [86.120.32.152]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madras.collabora.co.uk (Postfix) with ESMTPSA id ADB21660211A; Sat, 11 Feb 2023 03:19:07 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676085547; bh=FVwCMHp81rng2JtkEJwcV2RSVh1OgfTEUNvp1icmEos=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dexWFXzTRq4fY6EDM50+F7V73z2VMXWhD7QBI80JWZJcfL9WLO95pS5knaTIet4Bn LHRer0o/Sa4OYjCRDAaJxSohSsPgyPOIQ7IrQd7CRqilfOlmiSyiLDLznR97+Lvvze RdFxvm8ZhJlP6GtGQ4BuqXjan1XgBR03B9Ab0HfLNWH1MMAEC7aacNMc639Jd69SU7 cgseOHhJHk8yzf9GuiMTytsJdiK265EvK5oNkiJW3iYeiIei/h+OAD7jIZU8PWwkFh UXNcMN+O4qHGI6Xmxf7Dn1rhHru20cxjOBkWQLJ7kSF2LNPGz4VXwuaOoLipGJI79J 6oPlNU5ku7JTw== From: Cristian Ciocaltea To: Lee Jones , Rob Herring , Krzysztof Kozlowski , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 12/12] riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac Date: Sat, 11 Feb 2023 05:18:21 +0200 Message-Id: <20230211031821.976408-13-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add pinmux configuration for the DWMAC found on the JH7100 based boards and enable the gmac DT node. Signed-off-by: Cristian Ciocaltea --- .../boot/dts/starfive/jh7100-common.dtsi | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..9927e7462e9f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -41,7 +41,85 @@ led-ack { }; }; +&gmac { + starfive,gtxclk-dlychain = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins>; + status = "okay"; +}; + &gpio { + gmac_pins: gmac-0 { + gtxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <35>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + miitxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + tx-pins { + pins = , + , + , + , + , + , + , + , + ; + bias-pull-up; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + rxclk-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <6>; + }; + rxer-pins { + pins = ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + rx-pins { + pins = , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + i2c0_pins: i2c0-0 { i2c-pins { pinmux =