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[92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:11 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow , Thomas Huth Subject: [PATCH 01/12] hw/i386/pc_q35: Resolve redundant q35_host variable Date: Tue, 14 Feb 2023 14:14:30 +0100 Message-Id: <20230214131441.101760-2-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The variable is redundant to "phb" and is never used by its real type. Signed-off-by: Bernhard Beschow Reviewed-by: Thomas Huth --- hw/i386/pc_q35.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a5ffb77ed8..1ce9b16c53 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -118,8 +118,7 @@ static void pc_q35_init(MachineState *machine) PCMachineState *pcms = PC_MACHINE(machine); PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); X86MachineState *x86ms = X86_MACHINE(machine); - Q35PCIHost *q35_host; - PCIHostState *phb; + Object *phb; PCIBus *host_bus; PCIDevice *lpc; DeviceState *lpc_dev; @@ -206,10 +205,10 @@ static void pc_q35_init(MachineState *machine) } /* create pci host bus */ - q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); + phb = OBJECT(qdev_new(TYPE_Q35_HOST_DEVICE)); if (pcmc->pci_enabled) { - pci_hole64_size = object_property_get_uint(OBJECT(q35_host), + pci_hole64_size = object_property_get_uint(phb, PCI_HOST_PROP_PCI_HOLE64_SIZE, &error_abort); } @@ -217,25 +216,25 @@ static void pc_q35_init(MachineState *machine) /* allocate ram and load rom/bios */ pc_memory_init(pcms, system_memory, rom_memory, pci_hole64_size); - object_property_add_child(OBJECT(machine), "q35", OBJECT(q35_host)); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, + object_property_add_child(OBJECT(machine), "q35", phb); + object_property_set_link(phb, MCH_HOST_PROP_RAM_MEM, OBJECT(machine->ram), NULL); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SMRAM_MEM, + object_property_set_link(phb, MCH_HOST_PROP_SMRAM_MEM, OBJECT(&x86ms->smram), NULL); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM, + object_property_set_link(phb, MCH_HOST_PROP_PCI_MEM, OBJECT(pci_memory), NULL); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM, + object_property_set_link(phb, MCH_HOST_PROP_SYSTEM_MEM, OBJECT(system_memory), NULL); - object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM, + object_property_set_link(phb, MCH_HOST_PROP_IO_MEM, OBJECT(system_io), NULL); - object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE, + object_property_set_int(phb, PCI_HOST_BELOW_4G_MEM_SIZE, x86ms->below_4g_mem_size, NULL); - object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE, + object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, x86ms->above_4g_mem_size, NULL); + /* pci */ - sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal); - phb = PCI_HOST_BRIDGE(q35_host); - host_bus = phb->bus; + sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); + host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); /* create ISA bus */ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, From patchwork Tue Feb 14 13:14:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13140021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F34A6C61DA4 for ; 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[92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:12 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 02/12] hw/pci-host/q35: Fix contradicting .endianness assignment Date: Tue, 14 Feb 2023 14:14:31 +0100 Message-Id: <20230214131441.101760-3-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=shentey@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Settle on little endian which is consistent with using pci_host_conf_le_ops. Fixes: bafc90bdc594 'q35: implement TSEG' Signed-off-by: Bernhard Beschow --- hw/pci-host/q35.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 83f2a98c71..3124cad60f 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -289,7 +289,6 @@ static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, static const MemoryRegionOps blackhole_ops = { .read = blackhole_read, .write = blackhole_write, - .endianness = DEVICE_NATIVE_ENDIAN, .valid.min_access_size = 1, .valid.max_access_size = 4, .impl.min_access_size = 4, From patchwork Tue Feb 14 13:14:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13140017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2AC2C05027 for ; Tue, 14 Feb 2023 13:16:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRv9d-0007Zz-Jg; Tue, 14 Feb 2023 08:15:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRv9R-0007VD-H4 for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:21 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pRv9P-0003uP-D1 for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:16 -0500 Received: by mail-ej1-x633.google.com with SMTP id qb15so37859439ejc.1 for ; Tue, 14 Feb 2023 05:15:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AFrfKDNgDSO+JSI2nSN7vL8PgZQEIxHL9NLlLSyrouU=; b=RFXSNLxFlIPXwMZQCPMYiPJvmRkSp1P0okOrCy8lKtFXOyBkDHwNSsbC+FpetsJYPH RXXxh8jserYBMr5r3SE15y2wFWPybevuDYsKqfQzV3VBiUwZtIb9DQTsUAFJd+3qnabw mP9vXZdpAfs8yma5RXuf+AGiya+qIHHSzkWCfWm2epp07qCygwRzJAw7nRosV3LRwikw 1Tb+ot1OiBlx9iJSNXbJgePCz4li+smFt+apsdEVL7GUB7uMRXvh0lleAqCW/1lDBrsc qUvMsfHO+WRUSaq2AFWjgqi8/t+NhuXggATZ6ertF/Q6Wy9qrMkVSQ64lly/aJaTU/ub cCzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AFrfKDNgDSO+JSI2nSN7vL8PgZQEIxHL9NLlLSyrouU=; b=nrl8gj2iRFG1bVMHtwP3Mz6Okszc5zlfJyPEh0vx6UEv0XrXdVzT4yf7Rk/0ruai9Y 52lry1RcEL1x3xBxyUtVIfohx1el+CNP8NXDNYo6yHj3V2lIFo/m2FK+fqgoVCOxToEe KnSLQOZ5Wu6bYD24qn+b3hiE+adRV8jlaK4vLKwDCCBkUCHqRHZr/n9zZMl5lnfiXxyu DD6CoS7x1AFhY309bffFlaMGHHhKVuspyUbjlBfkDECsQsGjYfR7T9dK2DwstkuZKbOP rwBKmx7uMR+Brg190+EatWYLaQe++7xVIJJEpjM55A3TFhAML/bIieIwkO0NBwaQnvZM 6udQ== X-Gm-Message-State: AO0yUKWGq2z3twJbDSyLYGRtFZYE+GVzT9VIP2aHGG/Q9UzfXAecqLVp hQPDWenyXcqJM5WePyHhB9ZOlKgw6VQ= X-Google-Smtp-Source: AK7set+Pbb/tDqoLDToq3Wg3tKtR8uQf+lC1tccsV5ErP/M3JLqbqDiaCJWC8ZPJ40lA0USMWMGxhw== X-Received: by 2002:a17:907:6e0f:b0:8ae:6b88:e52d with SMTP id sd15-20020a1709076e0f00b008ae6b88e52dmr28475266ejc.7.1676380513819; Tue, 14 Feb 2023 05:15:13 -0800 (PST) Received: from localhost.localdomain (dynamic-092-224-101-237.92.224.pool.telefonica.de. [92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:13 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 03/12] hw/pci-host/q35: Use memory_region_set_address() also for tseg_blackhole Date: Tue, 14 Feb 2023 14:14:32 +0100 Message-Id: <20230214131441.101760-4-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Deleting from and adding to the parent memory region seems to be the old way of changing a memory region's address which is superseeded by memory_region_set_address(). Moreover, memory_region_set_address() is already used for tseg_window which is tseg_blackhole's counterpart in SMM space. Ammends: bafc90bdc594 'q35: implement TSEG' Signed-off-by: Bernhard Beschow --- hw/pci-host/q35.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 3124cad60f..0384ce4350 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -404,12 +404,11 @@ static void mch_update_smram(MCHPCIState *mch) } else { tseg_size = 0; } - memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); + memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); memory_region_set_size(&mch->tseg_blackhole, tseg_size); - memory_region_add_subregion_overlap(mch->system_memory, - mch->below_4g_mem_size - tseg_size, - &mch->tseg_blackhole, 1); + memory_region_set_address(&mch->tseg_blackhole, + mch->below_4g_mem_size - tseg_size); memory_region_set_enabled(&mch->tseg_window, tseg_size); memory_region_set_size(&mch->tseg_window, tseg_size); From patchwork Tue Feb 14 13:14:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13140020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0905C64EC7 for ; Tue, 14 Feb 2023 13:16:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRv9b-0007Xu-JC; Tue, 14 Feb 2023 08:15:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRv9V-0007VJ-BP for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:21 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pRv9Q-0003ua-Eh for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:18 -0500 Received: by mail-ej1-x634.google.com with SMTP id mc25so2572517ejb.13 for ; Tue, 14 Feb 2023 05:15:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5Q5vWhZ3yaheNtY1gl/eSdHz8ARO+3GshIdP1UrJAsk=; b=BRdSO84yCgruHzb+OkYt2/x283DzC6FVE9htOutr8NOJ2bGdv7kHWhpHmx79SoblEl JNUGLoZhU8nv3E3Z3t5PEOo4RCzFwMEHS12OHOrbzV4xii+jeEePSJx38pannnmSoYaw jLJBiapsMB7zbqQmyuVY3iNcyBUUDZZS4YKKrYmIq1ErpR4iMOKc6wegD4kA7xaD4Mkd ckw8T8GZhT9Rw+sIsWhhuI0HIQU6PiDk3NuX4gI4FFrqDHIBT21MY5zWku4fcXreLCp5 NAaWXvY7SOhb8cF/M/iqN2bKUsQRnC/UoOnq4sTbtIUC3nswwJCFPy0K2M0+yfyh0Yl7 FboQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5Q5vWhZ3yaheNtY1gl/eSdHz8ARO+3GshIdP1UrJAsk=; b=dl34/Jt7n8RZfrm5YdVcVoBYlYkR0ylhAKlE3VeGMrK/+guxZa0vjrrwdcaeOVY24u Vs21nvKIkCH9VV0z3FN3DzHJejdLSrTmOCdO7l0cKHvHh4Dgdbm2hup/mi4uKvXQPfCd eMtDHsE8XOZ5p2BbiMIrC7cAfNOP01iy1hp3+rb+xqRZOojo+IBY3KiDQ+qoZntNKrw7 t1Qg9yKHRz20hMLN42VjnuaoXaqR2TQrmaXe3EH9MfpMnRQjbLhCVFi7Yznz7mEoktgA UwckodwwKOtNrlp2UuhTdD5cT/QGgWUFb/h8UUm6EwajH8Ix3OioLGUz9ri/8jWK2EI/ ZB0Q== X-Gm-Message-State: AO0yUKXM7FBgKMcen8JE4OvJoujRqdqsQvy/dwFqTvXZuoW5bZV5BrP7 VPYDRt+3x1ExHEzTI0KF83uQL3frMUQ= X-Google-Smtp-Source: AK7set/iaoYuS/9RK+FLftBwRUSnIwFBmIhcOPJviAaZkinnmhLvqQ8Ii0TJRjkCELwz4RfvfkKOIA== X-Received: by 2002:a17:906:730f:b0:8ab:b03d:a34f with SMTP id di15-20020a170906730f00b008abb03da34fmr27462384ejc.12.1676380514871; Tue, 14 Feb 2023 05:15:14 -0800 (PST) Received: from localhost.localdomain (dynamic-092-224-101-237.92.224.pool.telefonica.de. [92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:14 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 04/12] hw/pci-host/q35: Initialize PCMachineState::bus in board code Date: Tue, 14 Feb 2023 14:14:33 +0100 Message-Id: <20230214131441.101760-5-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=shentey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Q35 PCI host currently sets the PC machine's PCI bus attribute through global state, thereby assuming the machine to be a PC machine. The Q35 machine code already holds on to Q35's pci bus attribute, so can easily set its own property while preserving encapsulation. Signed-off-by: Bernhard Beschow --- hw/i386/pc_q35.c | 6 ++++-- hw/pci-host/q35.c | 1 - 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 1ce9b16c53..c2dc87acee 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -231,10 +231,12 @@ static void pc_q35_init(MachineState *machine) x86ms->below_4g_mem_size, NULL); object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, x86ms->above_4g_mem_size, NULL); - - /* pci */ sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); + + /* pci */ host_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pcie.0")); + pcms->bus = host_bus; + /* create ISA bus */ lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true, diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 0384ce4350..26e9e28e0e 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -66,7 +66,6 @@ static void q35_host_realize(DeviceState *dev, Error **errp) s->mch.pci_address_space, s->mch.address_space_io, 0, TYPE_PCIE_BUS); - PC_MACHINE(qdev_get_machine())->bus = pci->bus; pci->bypass_iommu = PC_MACHINE(qdev_get_machine())->default_bus_bypass_iommu; qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); From patchwork Tue Feb 14 13:14:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13140024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4BF9C05027 for ; Tue, 14 Feb 2023 13:17:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRv9e-0007b8-8s; Tue, 14 Feb 2023 08:15:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRv9X-0007XA-Ft for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:23 -0500 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pRv9R-0003uk-SL for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:23 -0500 Received: by mail-ed1-x536.google.com with SMTP id fi26so17248114edb.7 for ; Tue, 14 Feb 2023 05:15:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aSHw5fSD+GawWcmcSXMGHhcAnPm8nrYU8mTyUZGVz+Q=; b=kMxyiP7ZJm36pRIGfE93DIaY8jxd6K+T7abPMd/4P8kLOSGYeVaHkKEFawtlH7GjLB KN+6Iu6Wl88eRC9Bg2RqeIuYkVoi1FEEUYE1klIa7wDg6yO9zDC7fY+6mtbsjMZpqHmu CXYjvWnTUjDA60iHSehzklkAccwzQNvMr3jISNi6Q5UOkd9ie5RCnqAh94lInsSTuMc7 r2zXmgu9rtEQb3b5zysijWDZa1BPHFsoIgXTABYzzER78s2/QWRRhPfW0sT41pahmCjg TV4/D/Wu2knI8vM2a1NTDGGZHxjmndkd6aV1WXhnipBCmDtSAqi4k9/HP1lypXEv6b4d d4Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aSHw5fSD+GawWcmcSXMGHhcAnPm8nrYU8mTyUZGVz+Q=; b=3lzhFnCwEIynC+P2iRnF+upACnGVwow8n4uW2WKxLf2lfxQrIVqXSiTsHa/VF8x6Zx yeI8j0s028kcTjA8KyhyU4YPqFqVCC7qaPJpJzGhNZmrmxI7CcDuFsvOmSKZUbMZfT/Z 5CKRxsse4z4SA8CobFFHs7qqggqGIXKh5gvCrpzKJOZ/MJtMU3CFsz5isNHLviV4aw7L m5k4YHQn0HvJZecv3pkpzOfDT2GkuHbTdZ+jikHfywdcxr5zk2h6FnptO25SHCt6L3WY vAjE8eQCHR/plFXyyXMkxwGAzFHnyRNt6elwdSOECRHU2QKaRiJ9aoHPAlznM5V3HApt onxQ== X-Gm-Message-State: AO0yUKXeyEMwzHbyUUDJJDz/+OeZ/kIgB9Gt6XdBrD8F2iHbOLTRsXG1 FpZOXddCP6PwLkplWrQARU0AFkl/TeU= X-Google-Smtp-Source: AK7set/oZqQ8QjiYth3Wo2rNsCmIWqUd8KuSCGKkMsDoKm5/l96/4ODU8DDefVViMnEkRJgryVQrZg== X-Received: by 2002:a50:8ad5:0:b0:4ac:be42:5c66 with SMTP id k21-20020a508ad5000000b004acbe425c66mr2768853edk.11.1676380516028; Tue, 14 Feb 2023 05:15:16 -0800 (PST) Received: from localhost.localdomain (dynamic-092-224-101-237.92.224.pool.telefonica.de. [92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:15 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 05/12] hw/pci-host/q35: Initialize "bypass-iommu" property from board code Date: Tue, 14 Feb 2023 14:14:34 +0100 Message-Id: <20230214131441.101760-6-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Q35 PCI host already has a "bypass-iommu" property. However, the host initializes this property itself by accessing global machine state, thereby assuming it to be a PC machine. Avoid this by having board code set this property. Signed-off-by: Bernhard Beschow --- hw/i386/pc_q35.c | 2 ++ hw/pci-host/q35.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index c2dc87acee..b3c55012d4 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -231,6 +231,8 @@ static void pc_q35_init(MachineState *machine) x86ms->below_4g_mem_size, NULL); object_property_set_int(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, x86ms->above_4g_mem_size, NULL); + object_property_set_bool(phb, "bypass-iommu", + pcms->default_bus_bypass_iommu, NULL); sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); /* pci */ diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 26e9e28e0e..0e198f97a7 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -66,8 +66,7 @@ static void q35_host_realize(DeviceState *dev, Error **errp) s->mch.pci_address_space, s->mch.address_space_io, 0, TYPE_PCIE_BUS); - pci->bypass_iommu = - PC_MACHINE(qdev_get_machine())->default_bus_bypass_iommu; + qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); } From patchwork Tue Feb 14 13:14:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13140018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEA98C6379F for ; Tue, 14 Feb 2023 13:16:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRv9e-0007bW-R7; Tue, 14 Feb 2023 08:15:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRv9Z-0007XM-0M for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:25 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pRv9V-0003uu-23 for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:24 -0500 Received: by mail-ej1-x631.google.com with SMTP id mc25so2572766ejb.13 for ; Tue, 14 Feb 2023 05:15:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DbrbM3p3jfrGHEMaBbnBB4lGzc6BURl9OVfHqnE3l1g=; b=ZAseUPkO/fFbUT4C8zmaiXFp1Y4Q03J0xuS/tWGeORMJ3PTZsSIBUkHNs9ZCEd3mBd KUCtoKEf6Yn/kCQbllFrNzevAG2U1jRh2iFPfLru2QF4ofxYuHTVnKhaliEhHbE9HLdR MDur00vpk/WB4UZfNUFqBqdyNopaMVZqkviJrkLc/PEY4RVUatgZD+w+qgxGCc7hkRnH KAmLFNQ1t7ESDD00M1O3f5gG99bpePpUArCb7DP8QAljogrjudAsXYYW/0wB2yFoVyzr 5jECJX2hxGD7bwY3YGCgY74qWIgtzhAAlvZo0nXYP35F240FQCwltG8x6hBgE7x9RbG9 qfsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DbrbM3p3jfrGHEMaBbnBB4lGzc6BURl9OVfHqnE3l1g=; b=oBd1RJ6KXMqXTXJMudEQ7gdUOUvLIqWcxCyQB6keERmgt1E0UI1oXtkzXCrQRgKK9J BBeIxcfM6wzNTO62d0HnBH08K611ldNU4dO594vLa0AJnx1xbMjdkSMkv47yayueUvJM djHa5Psw/Dy/gHr3Dz7BiPydpyr7nK+FYQkord1rfqf0yUEz0g6FZk18OgqypOPVLoLo 2r3D/hJpJkrf/4wLJnaHMtOEOiK4QguLDJyTwEoXzRe5UvBI3z27PVc4lSn2lCM73c2d AdE6yIwai7KI6d3gQZ1CrhASeEl4dGrp2mVoIsi19+Zq+ceIKKSfhsuIL5tT6IH+GWDT +f/g== X-Gm-Message-State: AO0yUKUfigjPJrP58J08io1oB021Ttt2Ocd5JXKzfeEmSYisCYZdPyrj 1J6Nroh3FqTQxAQK5pJggGsFilisWA4= X-Google-Smtp-Source: AK7set/9KyYfdob1xVcfJ0siERL5uCHjq5a2J+3Ag0w59HhdRTNNniZK9nb1aYmzlgjoDh5CM2wAVw== X-Received: by 2002:a17:907:379:b0:889:d156:616d with SMTP id rs25-20020a170907037900b00889d156616dmr3123143ejb.27.1676380517317; Tue, 14 Feb 2023 05:15:17 -0800 (PST) Received: from localhost.localdomain (dynamic-092-224-101-237.92.224.pool.telefonica.de. [92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:16 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 06/12] hw/pci-host/q35: Initialize properties just once Date: Tue, 14 Feb 2023 14:14:35 +0100 Message-Id: <20230214131441.101760-7-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Although not used there, the attributes for Q35's "pci-hole64-size" and "short_root_bus" properties currently reside in its child device. This causes the default values to be overwritten during the child's object_initialize() phase. Avoid this by moving both attributes into the host device. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/q35.h | 5 +++-- hw/pci-host/q35.c | 20 +++++--------------- 2 files changed, 8 insertions(+), 17 deletions(-) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index fcbe57b42d..93e41ffbee 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -54,8 +54,6 @@ struct MCHPCIState { Range pci_hole; uint64_t below_4g_mem_size; uint64_t above_4g_mem_size; - uint64_t pci_hole64_size; - uint32_t short_root_bus; uint16_t ext_tseg_mbytes; }; @@ -64,7 +62,10 @@ struct Q35PCIHost { PCIExpressHost parent_obj; /*< public >*/ + uint64_t pci_hole64_size; + uint32_t short_root_bus; bool pci_hole64_fix; + MCHPCIState mch; }; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 0e198f97a7..03aa08dae5 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -76,7 +76,7 @@ static const char *q35_host_root_bus_path(PCIHostState *host_bridge, Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); /* For backwards compat with old device paths */ - if (s->mch.short_root_bus) { + if (s->short_root_bus) { return "0000"; } return "0000:00"; @@ -161,27 +161,19 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, pci_bus_get_w64_range(h->bus, &w64); value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; - hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); + hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30); if (s->pci_hole64_fix && value < hole64_end) { value = hole64_end; } visit_type_uint64(v, name, &value, errp); } -/* - * NOTE: setting defaults for the mch.* fields in this table - * doesn't work, because mch is a separate QOM object that is - * zeroed by the object_initialize(&s->mch, ...) call inside - * q35_host_initfn(). The default values for those - * properties need to be initialized manually by - * q35_host_initfn() after the object_initialize() call. - */ static Property q35_host_props[] = { DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, - mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), - DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), + pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), + DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, short_root_bus, 0), DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, mch.below_4g_mem_size, 0), DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, @@ -218,9 +210,7 @@ static void q35_host_initfn(Object *obj) object_initialize_child(OBJECT(s), "mch", &s->mch, TYPE_MCH_PCI_DEVICE); qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); - /* mch's object_initialize resets the default value, set it again */ - qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, - Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); + object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", q35_host_get_pci_hole_start, NULL, NULL, NULL); From patchwork Tue Feb 14 13:14:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13140025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6AA0AC61DA4 for ; Tue, 14 Feb 2023 13:17:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRv9f-0007bi-8T; Tue, 14 Feb 2023 08:15:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRv9Z-0007XN-0R for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:25 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pRv9V-0003uy-2X for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:24 -0500 Received: by mail-ej1-x62f.google.com with SMTP id gn39so1617372ejc.8 for ; Tue, 14 Feb 2023 05:15:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YkQI+OmILy28+c+2zgMBpj3rebi/xKNz4e5yLjMHx+g=; b=lMjQ78Rj6wUDth17D7p3CdjXawu3REy0ubWFCODrunusV19FVnvNrpRarG1RRRJAxc Gv/tRCpdprOzC/jHRqC7b2cM0BLDd7TGfOTuehT45+EByMjPcM31P42AgptaAYPsucbf tkO/qjvsuRwwLI07iaRe6NbWDo8PRU8yu+Vdz42xlQnnrCIFehxqOuSkU01ulPLYqDT7 dBKgFFky2ZKwEjEG/+Uwb1YDjwXxIO43kwsjkRwGUXm0tYEqnLV7f7qxx22MbkkBpfBp blcJ/hBBnvn2jfBK0CDYlDMQDZ8ztnpvSpGjyNuDSy1iz4DkcJRSmlmmuDxP5lcI8dom nyUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YkQI+OmILy28+c+2zgMBpj3rebi/xKNz4e5yLjMHx+g=; b=zXjypMo1dK5wHK2VqPbvAjaPlKHkPiG+/tJnS+Gv4Z7V1oT4IJ+FzYk84F248tMysO SOs94GBkHtyoR3J1sSRIg23Of+TgQc9fW6kB9PgnG/RxWEFsVgVc8BUK3x+6ISFzBrFk LW6s8AnS+EhHwsDuTo/m3s0Y7/2az2WGiWLLxBq1pWMyQnycTaP0UC3RIGgiqA648cgk 0+6X9tMiqbar2iV1Bd9zh3b+dDQwJNxU5wlkC4aGoLW5oSV+FY8pC1r9gJYzrEeLGN7S dQJVhMMgqnLRpRtogTjhY07fLpB2293dAFwerfkhK4VGHX00cZZ3gim0igsSC4Mour97 JlbQ== X-Gm-Message-State: AO0yUKXsRwf7/muL8acMasmyAtswghhipH8osw7cbz7yDajuD54kYuu8 ZEUBFZ23MNCYsCbbvbrjt71s1dmCdps= X-Google-Smtp-Source: AK7set8M025AGNJgEjwJK0I5EabPt/5Vl8zg5UGiSHrUy5uE7uzBnVHz9dVcj/cIB8Wt+HgS8EqjnQ== X-Received: by 2002:a17:906:4710:b0:87d:9447:f7fb with SMTP id y16-20020a170906471000b0087d9447f7fbmr2371480ejq.38.1676380518425; Tue, 14 Feb 2023 05:15:18 -0800 (PST) Received: from localhost.localdomain (dynamic-092-224-101-237.92.224.pool.telefonica.de. [92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:17 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 07/12] hw/pci-host/q35: Initialize PCI hole boundaries just once Date: Tue, 14 Feb 2023 14:14:36 +0100 Message-Id: <20230214131441.101760-8-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The boundaries of the PCI hole depend on a property only which doesn't change at runtime. There is no need to reevaluate the boundaries whenever the PCI configuration space changes. While at it, move the pci_hole attribute into the host device since it is only used there. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/q35.h | 2 +- hw/pci-host/q35.c | 21 +++++++++------------ 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index 93e41ffbee..a04d5f1a17 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -51,7 +51,6 @@ struct MCHPCIState { MemoryRegion tseg_blackhole, tseg_window; MemoryRegion smbase_blackhole, smbase_window; bool has_smram_at_smbase; - Range pci_hole; uint64_t below_4g_mem_size; uint64_t above_4g_mem_size; uint16_t ext_tseg_mbytes; @@ -62,6 +61,7 @@ struct Q35PCIHost { PCIExpressHost parent_obj; /*< public >*/ + Range pci_hole; uint64_t pci_hole64_size; uint32_t short_root_bus; bool pci_hole64_fix; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 03aa08dae5..468bbfde51 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -62,6 +62,13 @@ static void q35_host_realize(DeviceState *dev, Error **errp) memory_region_set_flush_coalesced(&pci->data_mem); memory_region_add_coalescing(&pci->conf_mem, 0, 4); + /* + * pci hole goes from end-of-low-ram to io-apic. + * mmconfig will be excluded by the dsdt builder. + */ + range_set_bounds(&s->pci_hole, s->mch.below_4g_mem_size, + IO_APIC_DEFAULT_ADDRESS - 1); + pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", s->mch.pci_address_space, s->mch.address_space_io, @@ -90,8 +97,7 @@ static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, uint64_t val64; uint32_t value; - val64 = range_is_empty(&s->mch.pci_hole) - ? 0 : range_lob(&s->mch.pci_hole); + val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole); value = val64; assert(value == val64); visit_type_uint32(v, name, &value, errp); @@ -105,8 +111,7 @@ static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, uint64_t val64; uint32_t value; - val64 = range_is_empty(&s->mch.pci_hole) - ? 0 : range_upb(&s->mch.pci_hole) + 1; + val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1; value = val64; assert(value == val64); visit_type_uint32(v, name, &value, errp); @@ -498,14 +503,6 @@ static void mch_update(MCHPCIState *mch) mch_update_smram(mch); mch_update_ext_tseg_mbytes(mch); mch_update_smbase_smram(mch); - - /* - * pci hole goes from end-of-low-ram to io-apic. - * mmconfig will be excluded by the dsdt builder. - */ - range_set_bounds(&mch->pci_hole, - mch->below_4g_mem_size, - IO_APIC_DEFAULT_ADDRESS - 1); } static int mch_post_load(void *opaque, int version_id) From patchwork Tue Feb 14 13:14:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13140028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7EEBC05027 for ; Tue, 14 Feb 2023 13:17:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRv9g-0007cU-5C; Tue, 14 Feb 2023 08:15:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRv9a-0007XV-Cm for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:26 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pRv9V-0003v3-4Y for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:25 -0500 Received: by mail-ej1-x635.google.com with SMTP id ml19so40086646ejb.0 for ; Tue, 14 Feb 2023 05:15:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9J72yIOu4Uf13Rs2fXrKUf9MXOPBOsiFdWbshX8z2DI=; b=kYx3QyPhCEFjcLNjW2M51LPIcpnOGUfDKj8YSZdk2YlBsZVOIUq+2k2sMx0YnfSgyO dvaKyFiBvY/riP3OwnYQrc+uWZUauNVjxWWfYlm+GZPS5IUtJW/bPSGpP5TIuLplesO9 Bi75GbqvmUkJZ/VRYqRiMMf0X2xNg2y2Z79qjDbgNdzVBdoLgqc1OPjQZPBo9QAcPVvS R0a7wn4K/txNBbAEaXuoPKnJuaqxO0tOeYSxAa26KK8Y7nWyfXnP/KSU+MzmGWgf9FXH GbFLCKaurgjW5bIyqm3eKrQ5OVcRi6eraLq7dftw4jP0kOfVrwgjNaEIko3JWVtQQ9qT j9gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9J72yIOu4Uf13Rs2fXrKUf9MXOPBOsiFdWbshX8z2DI=; b=Cfl4TTNELNxxVxm9MNZa39fpPnDfM5uC7w44wYgQRxvsREPC2rzfNs2LHC8YLgCD1Q mIAtznSmCFFuldKdKMuy8WoYv8J9xTAoQdtThxEHKQ0u83xYqdVTZ1Uv/uYoQ67cllGe AKX1yVlguxyN+6ucGdaahAsD1qE7ErG5IX4RQ8vSw0MEdbyqRlYWV3pzdC+7AFmzSouW vRsoZMZEEJnXGyouV5lX2aRP1Z+fXnyVfZbDGN3awDyoJb4s7IV2Xjem6CVfmASal88R 0ax/pD5094TIvjUv+WOZ/mInrDju+6fn5YKj1ePs6J+M0lLjUjYya9HXiX9nSn8pZIeN o5nA== X-Gm-Message-State: AO0yUKUXP0hJ11pDzRkeDsibCEdRtw8zfqGHVH6ptNcLRgnXf40AaXkQ ISVRVxhkaei4g8+wo9krdXm8uw+s3n0= X-Google-Smtp-Source: AK7set+FQD97Kz+U7HjBntzc8A4G2aYNxSbGUeIla27N5r8bIAXOxG+35xrjidv88ner8oIhrtlffA== X-Received: by 2002:a17:906:c787:b0:84d:4e4f:1f85 with SMTP id cw7-20020a170906c78700b0084d4e4f1f85mr2633230ejb.59.1676380519480; Tue, 14 Feb 2023 05:15:19 -0800 (PST) Received: from localhost.localdomain (dynamic-092-224-101-237.92.224.pool.telefonica.de. [92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:18 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 08/12] hw/pci-host/q35: Turn PCI hole properties into class properties Date: Tue, 14 Feb 2023 14:14:37 +0100 Message-Id: <20230214131441.101760-9-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=shentey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org These properties are class properties in i440fx. No need to handle them differently in q35. Signed-off-by: Bernhard Beschow --- hw/pci-host/q35.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 468bbfde51..2fc047a9c6 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -199,6 +199,22 @@ static void q35_host_class_init(ObjectClass *klass, void *data) dc->user_creatable = false; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->fw_name = "pci"; + + object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_START, "uint32", + q35_host_get_pci_hole_start, + NULL, NULL, NULL); + + object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_END, "uint32", + q35_host_get_pci_hole_end, + NULL, NULL, NULL); + + object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", + q35_host_get_pci_hole64_start, + NULL, NULL, NULL); + + object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", + q35_host_get_pci_hole64_end, + NULL, NULL, NULL); } static void q35_host_initfn(Object *obj) @@ -216,22 +232,6 @@ static void q35_host_initfn(Object *obj) qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); - object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", - q35_host_get_pci_hole_start, - NULL, NULL, NULL); - - object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", - q35_host_get_pci_hole_end, - NULL, NULL, NULL); - - object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", - q35_host_get_pci_hole64_start, - NULL, NULL, NULL); - - object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", - q35_host_get_pci_hole64_end, - NULL, NULL, NULL); - object_property_add_uint64_ptr(obj, PCIE_HOST_MCFG_SIZE, &pehb->size, OBJ_PROP_FLAG_READ); From patchwork Tue Feb 14 13:14:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13140027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EDF85C05027 for ; Tue, 14 Feb 2023 13:17:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRv9f-0007cB-Vm; Tue, 14 Feb 2023 08:15:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRv9a-0007XX-Fe for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:26 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pRv9X-0003uP-2y for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:26 -0500 Received: by mail-ej1-x633.google.com with SMTP id qb15so37860181ejc.1 for ; Tue, 14 Feb 2023 05:15:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XOSLUYZkq7ElDzuyPaht3pB2svrDQry43zdBkhas124=; b=f8i95OsymyNFWBVlGGqR+eG+jGgAjWrNAwSBToVYOKM5rHS/K7EH7OFtNhAdJ47Rn2 Y28v53n3sr6gWHTQbS9Z9jRBpnQrEEcmv6E9EGlY9BkyvzMUQGOP8P/pdhc4cCz+vGU/ 6YQDBLrZ23UlcOLSzyILkQcna+zoeyo33soFWmqIj/TOENvkR2rNaJt6pu0uozi8g65E SL3sekAjX9/mr9QJFus17YM8bQlIkSToBQTrTZs5POoiLUAsGqA94d8CRTw+piovN65h 5ya3LvdkZ5kevyiFxKvRjS8/Ryqd75Y76riteDZBR8fWHXeTTnV8To8Tn2klzlkaOyNa 6R+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XOSLUYZkq7ElDzuyPaht3pB2svrDQry43zdBkhas124=; b=YntH5BEKgJRrbE3UONT60m+nXM2gnKTDYZN6yGZly2FXe4/3EU3PHunynVgMy29LHx GEyYSIxQyVOcqUheEQ32rNpfpi3OAkCQ3sPXmH7NwVWjE8B7LisGOiUpDvpcOUmshu6O MbqQJs8b26Lr8WhRCjKcJ1C1cLZ5p1EAmMRBcL9TsabPoEB4Pi2b++V/rAQpZ77l4K4X DoqkRVXd9djBNKK4yZNhh9zkXfuhUvxViPWJs5Sd88A4UrRqOYYrlTgO39eNeJ6xUOn1 DDLvUKhliqapRRknidGGnAGnJvZ6YySaaLF9kPkG7nZcTW3eF9nSeQSpefzaLGzhoX8A rLKQ== X-Gm-Message-State: AO0yUKUieSTvDJzlDQ9e45qBnV4NWOY8vddGKUAYvT8eiF700xqjH36s 8mOX8dkRbGE+/8rL/2DiXOCyzYgcTys= X-Google-Smtp-Source: AK7set9Jyxa1HW2VuQx2WPCagu87sGbVfB+hl3t0mM1zIqY4gYZkvXp2cUdqZTKSiG2FWkT7ngxnfQ== X-Received: by 2002:a17:906:bc9:b0:88c:3a48:715b with SMTP id y9-20020a1709060bc900b0088c3a48715bmr2778591ejg.30.1676380520650; Tue, 14 Feb 2023 05:15:20 -0800 (PST) Received: from localhost.localdomain (dynamic-092-224-101-237.92.224.pool.telefonica.de. [92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:20 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 09/12] hw/pci-host/q35: Rename local variable to more idiomatic "phb" Date: Tue, 14 Feb 2023 14:14:38 +0100 Message-Id: <20230214131441.101760-10-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Variables of type PCIHostState* are typically named "phb" in QEMU. Follow this convention here as well for consistency. Signed-off-by: Bernhard Beschow --- hw/pci-host/q35.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 2fc047a9c6..8f81debfa5 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -46,21 +46,21 @@ static void q35_host_realize(DeviceState *dev, Error **errp) { - PCIHostState *pci = PCI_HOST_BRIDGE(dev); Q35PCIHost *s = Q35_HOST_DEVICE(dev); + PCIHostState *phb = PCI_HOST_BRIDGE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); memory_region_add_subregion(s->mch.address_space_io, - MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); + MCH_HOST_BRIDGE_CONFIG_ADDR, &phb->conf_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); memory_region_add_subregion(s->mch.address_space_io, - MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); + MCH_HOST_BRIDGE_CONFIG_DATA, &phb->data_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); /* register q35 0xcf8 port as coalesced pio */ - memory_region_set_flush_coalesced(&pci->data_mem); - memory_region_add_coalescing(&pci->conf_mem, 0, 4); + memory_region_set_flush_coalesced(&phb->data_mem); + memory_region_add_coalescing(&phb->conf_mem, 0, 4); /* * pci hole goes from end-of-low-ram to io-apic. @@ -69,12 +69,12 @@ static void q35_host_realize(DeviceState *dev, Error **errp) range_set_bounds(&s->pci_hole, s->mch.below_4g_mem_size, IO_APIC_DEFAULT_ADDRESS - 1); - pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", + phb->bus = pci_root_bus_new(DEVICE(s), "pcie.0", s->mch.pci_address_space, s->mch.address_space_io, 0, TYPE_PCIE_BUS); - qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); + qdev_realize(DEVICE(&s->mch), BUS(phb->bus), &error_fatal); } static const char *q35_host_root_bus_path(PCIHostState *host_bridge, From patchwork Tue Feb 14 13:14:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13140026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACF96C05027 for ; Tue, 14 Feb 2023 13:17:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRv9f-0007bs-Dx; Tue, 14 Feb 2023 08:15:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRv9a-0007XU-BX for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:26 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pRv9X-0003ua-52 for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:25 -0500 Received: by mail-ej1-x634.google.com with SMTP id mc25so2573291ejb.13 for ; Tue, 14 Feb 2023 05:15:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tuewnRepBxWxAmnfjA8IaGCcRoQ04g+hEFXzxkgFJS4=; b=SriBttZQKBMzCwQmqNDX7yIB9WXVORGUnqWhnH3j9jTQMC4umyjWMeJ2cZVgUVOI+j ySuSKRyFo/DVKdz5OOMhsq+9PiHC2u24je/ABsAR3Ucx5S8xoFyXC7p1q2yA+d1wcv4F hoMrCIJX5kBe665pJwgBCMwKG/2tpLDTqkGeSfGbz7qX8hCNX5PfqqY1fjPj4h8UhXz1 eNa8RwHmXKZDYLpG7XtyDdNwz6MzKGyB3TyuVR41v7xiXzvfDgE2R+5RfXfns1kHjvmE m8Cj/17yGio+pQ/fUEQy1YBDwXxthTOfTDsF9Q2zjOoR5/H4OnvWM7VONsOxzT2zD0vo 9kaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tuewnRepBxWxAmnfjA8IaGCcRoQ04g+hEFXzxkgFJS4=; b=xefoHnp3jDtgZYds6z7RxWIHsVCoMEbieBdHv9o7rxkGDJmtgoEsBhIJTzdUz9Q9Ae 7e8hPSiY0uPw1Yor9qrgaUxMXhgktMOW0tJG6I3BhktZwVc2LmBkvfTRb8suw1NRGNn1 FXe05mZ2IxHIkRBBkOFsyYotVc5TE6ElvL6/badvwBQfk+/UZ9hytslTMQf9WNh+RNLk HBHbG3GmLd7WB6/Ysf5HdeU2P74DSuSzgha/mDia0pQ9KOIt5vJ5fMTKkSyejZm4H8gh xATD3FtKv+0ygaNF+0nlgLUSxrsSOeyO/GTY8TaENQF+CxBrxF/9hekGmSmLe7TlccNu 4V0A== X-Gm-Message-State: AO0yUKUTGFOtPvUZSNG4ly7SiJMnnPsgnQOZaSk3apDzKS9nUey3T+0W erUQN3AFDL95wIaLGWZ+tlDwnUQ/2VU= X-Google-Smtp-Source: AK7set9+Qp5clpot8IjBjVng8aWDesi25zng0Y0yCcYmpvdSEn56thnPWaBG2NQqxP8BWXMPxrH0eg== X-Received: by 2002:a17:906:774f:b0:8aa:c105:f0bf with SMTP id o15-20020a170906774f00b008aac105f0bfmr3551639ejn.17.1676380521981; Tue, 14 Feb 2023 05:15:21 -0800 (PST) Received: from localhost.localdomain (dynamic-092-224-101-237.92.224.pool.telefonica.de. [92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:21 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 10/12] hw/pci-host/q35: Propagate to errp rather than doing error_fatal Date: Tue, 14 Feb 2023 14:14:39 +0100 Message-Id: <20230214131441.101760-11-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=shentey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org q35_host_realize() has an errp parameter. Use that to be able to propagate the error instead of terminating abruptly. Signed-off-by: Bernhard Beschow --- hw/pci-host/q35.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 8f81debfa5..d517f5622b 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -46,6 +46,7 @@ static void q35_host_realize(DeviceState *dev, Error **errp) { + ERRP_GUARD(); Q35PCIHost *s = Q35_HOST_DEVICE(dev); PCIHostState *phb = PCI_HOST_BRIDGE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -74,7 +75,7 @@ static void q35_host_realize(DeviceState *dev, Error **errp) s->mch.address_space_io, 0, TYPE_PCIE_BUS); - qdev_realize(DEVICE(&s->mch), BUS(phb->bus), &error_fatal); + qdev_realize(DEVICE(&s->mch), BUS(phb->bus), errp); } static const char *q35_host_root_bus_path(PCIHostState *host_bridge, From patchwork Tue Feb 14 13:14:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13140029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69682C6379F for ; Tue, 14 Feb 2023 13:17:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pRv9g-0007dH-S9; Tue, 14 Feb 2023 08:15:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pRv9b-0007YR-Mp for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:27 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pRv9Z-0003xm-GV for qemu-devel@nongnu.org; Tue, 14 Feb 2023 08:15:27 -0500 Received: by mail-ed1-x529.google.com with SMTP id v13so17235717eda.11 for ; Tue, 14 Feb 2023 05:15:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZOVaZx3fH6UEahXjtANeXqEewjt57bWvCFtaZrt0zUc=; b=GM1URdy90zS8aKYTQKHhDl061Cy/zrSh/iaKTvTIoT1cHA9U4Yr17kzhSzioAetLSB CD+jabM/V17hfxkSXWqUxK3wO+XOFU8ymCfo4DGiqMhvqORF8+1Kz0TesowHpYfFwx23 Wl3bw/z1QH8Dsx4z62Ajgrp152ss2RB0tA4qOCsUO/nkNy/cPxdv4UmkemrCwDfI5Wfi qwO9/PUjjuNN3oaKs6spGMCXJ+FplMBEgw5wIvrgcfeWCPatQ+eQ8dhbYoFTo6H5LWgl cBpR3JEezWuxLpqDNcj53XzH0SZuaGturKJoWoRLuAQnCTkwcJhYxjYMcmvroCORO6wP QSTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZOVaZx3fH6UEahXjtANeXqEewjt57bWvCFtaZrt0zUc=; b=1s9XieYNI0R0kVLl5q+Rm372YTkix4zUxKPwnXjk8VqXKxC7X0VFj8D94XP/1J97nF d3hargsftmxpM1GTeY1BBkzj4EGrGzxW/JkYmtOlbQR912ZDuFNaikYsMfQxbkMSCeN+ u/BhRavxwhb8jvhLECJPFgtOvdq423WMjRxjf5EySMGO9LbxKLsiWycK5ITyAf017wd2 9kLPx9uf6pizqDcpSBZ6omKpwDJCco/GFYuqIeutbCepQ7W1H8xgq8QEePA6h3vNUD3R Kph0tIouJ8HBPz1hS39le7+WZaef7rOSdhG37zCYmjtZlaCcCiy4yXv7do7rQAw5wT+V bXrA== X-Gm-Message-State: AO0yUKUT9iW7oetMCbhcQddgwt5RXm8zUTuIEbIP/U+khPFkypXpckJC zVg+Pr/2b8bWo6Ynd7jxxLxe3/7+gBk= X-Google-Smtp-Source: AK7set92RtWQesDatv5ckixCIhqvHXtMmhxDp0FqvGIYfOnD2axTrItNkRYnLUrTNXhQVLjJTCxhGw== X-Received: by 2002:a50:9b03:0:b0:4aa:a9c7:4224 with SMTP id o3-20020a509b03000000b004aaa9c74224mr2623231edi.30.1676380523791; Tue, 14 Feb 2023 05:15:23 -0800 (PST) Received: from localhost.localdomain (dynamic-092-224-101-237.92.224.pool.telefonica.de. [92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:23 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 11/12] hw/pci-host/q35: Merge mch_realize() into q35_host_realize() Date: Tue, 14 Feb 2023 14:14:40 +0100 Message-Id: <20230214131441.101760-12-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=shentey@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch prepares movement of the MemoryRegion pointers (which are set through properties) into the host state. Moreover, it's usually the parent device which maps the memory regions of its child devices into its address space. Do the same in q35. Signed-off-by: Bernhard Beschow --- hw/pci-host/q35.c | 209 ++++++++++++++++++++++------------------------ 1 file changed, 101 insertions(+), 108 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index d517f5622b..3a7f9185a3 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -44,12 +44,40 @@ #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) +static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size) +{ + return 0xffffffff; +} + +static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, + unsigned width) +{ + /* nothing */ +} + +static const MemoryRegionOps blackhole_ops = { + .read = blackhole_read, + .write = blackhole_write, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .impl.min_access_size = 4, + .impl.max_access_size = 4, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + static void q35_host_realize(DeviceState *dev, Error **errp) { ERRP_GUARD(); Q35PCIHost *s = Q35_HOST_DEVICE(dev); PCIHostState *phb = PCI_HOST_BRIDGE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + int i; + + if (s->mch.ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { + error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, + s->mch.ext_tseg_mbytes); + return; + } memory_region_add_subregion(s->mch.address_space_io, MCH_HOST_BRIDGE_CONFIG_ADDR, &phb->conf_mem); @@ -70,6 +98,79 @@ static void q35_host_realize(DeviceState *dev, Error **errp) range_set_bounds(&s->pci_hole, s->mch.below_4g_mem_size, IO_APIC_DEFAULT_ADDRESS - 1); + /* setup pci memory mapping */ + pc_pci_as_mapping_init(s->mch.system_memory, s->mch.pci_address_space); + + /* if *disabled* show SMRAM to all CPUs */ + memory_region_init_alias(&s->mch.smram_region, OBJECT(s), "smram-region", + s->mch.pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, + MCH_HOST_BRIDGE_SMRAM_C_SIZE); + memory_region_add_subregion_overlap(s->mch.system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + &s->mch.smram_region, 1); + memory_region_set_enabled(&s->mch.smram_region, true); + + memory_region_init_alias(&s->mch.open_high_smram, OBJECT(s), "smram-open-high", + s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + MCH_HOST_BRIDGE_SMRAM_C_SIZE); + memory_region_add_subregion_overlap(s->mch.system_memory, 0xfeda0000, + &s->mch.open_high_smram, 1); + memory_region_set_enabled(&s->mch.open_high_smram, false); + + /* smram, as seen by SMM CPUs */ + memory_region_init_alias(&s->mch.low_smram, OBJECT(s), "smram-low", + s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + MCH_HOST_BRIDGE_SMRAM_C_SIZE); + memory_region_set_enabled(&s->mch.low_smram, true); + memory_region_add_subregion(s->mch.smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, + &s->mch.low_smram); + memory_region_init_alias(&s->mch.high_smram, OBJECT(s), "smram-high", + s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + MCH_HOST_BRIDGE_SMRAM_C_SIZE); + memory_region_set_enabled(&s->mch.high_smram, true); + memory_region_add_subregion(s->mch.smram, 0xfeda0000, &s->mch.high_smram); + + memory_region_init_io(&s->mch.tseg_blackhole, OBJECT(s), + &blackhole_ops, NULL, "tseg-blackhole", 0); + memory_region_set_enabled(&s->mch.tseg_blackhole, false); + memory_region_add_subregion_overlap(s->mch.system_memory, + s->mch.below_4g_mem_size, + &s->mch.tseg_blackhole, 1); + + memory_region_init_alias(&s->mch.tseg_window, OBJECT(s), "tseg-window", + s->mch.ram_memory, s->mch.below_4g_mem_size, 0); + memory_region_set_enabled(&s->mch.tseg_window, false); + memory_region_add_subregion(s->mch.smram, s->mch.below_4g_mem_size, + &s->mch.tseg_window); + + /* + * This is not what hardware does, so it's QEMU specific hack. + * See commit message for details. + */ + memory_region_init_io(&s->mch.smbase_blackhole, OBJECT(s), &blackhole_ops, + NULL, "smbase-blackhole", + MCH_HOST_BRIDGE_SMBASE_SIZE); + memory_region_set_enabled(&s->mch.smbase_blackhole, false); + memory_region_add_subregion_overlap(s->mch.system_memory, + MCH_HOST_BRIDGE_SMBASE_ADDR, + &s->mch.smbase_blackhole, 1); + + memory_region_init_alias(&s->mch.smbase_window, OBJECT(s), + "smbase-window", s->mch.ram_memory, + MCH_HOST_BRIDGE_SMBASE_ADDR, + MCH_HOST_BRIDGE_SMBASE_SIZE); + memory_region_set_enabled(&s->mch.smbase_window, false); + memory_region_add_subregion(s->mch.smram, MCH_HOST_BRIDGE_SMBASE_ADDR, + &s->mch.smbase_window); + + init_pam(&s->mch.pam_regions[0], OBJECT(s), s->mch.ram_memory, + s->mch.system_memory, s->mch.pci_address_space, + PAM_BIOS_BASE, PAM_BIOS_SIZE); + for (i = 0; i < ARRAY_SIZE(s->mch.pam_regions) - 1; ++i) { + init_pam(&s->mch.pam_regions[i + 1], OBJECT(s), s->mch.ram_memory, + s->mch.system_memory, s->mch.pci_address_space, + PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); + } + phb->bus = pci_root_bus_new(DEVICE(s), "pcie.0", s->mch.pci_address_space, s->mch.address_space_io, @@ -269,27 +370,6 @@ static const TypeInfo q35_host_info = { * MCH D0:F0 */ -static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size) -{ - return 0xffffffff; -} - -static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, - unsigned width) -{ - /* nothing */ -} - -static const MemoryRegionOps blackhole_ops = { - .read = blackhole_read, - .write = blackhole_write, - .valid.min_access_size = 1, - .valid.max_access_size = 4, - .impl.min_access_size = 4, - .impl.max_access_size = 4, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - /* PCIe MMCFG */ static void mch_update_pciexbar(MCHPCIState *mch) { @@ -552,92 +632,6 @@ static void mch_reset(DeviceState *qdev) mch_update(mch); } -static void mch_realize(PCIDevice *d, Error **errp) -{ - int i; - MCHPCIState *mch = MCH_PCI_DEVICE(d); - - if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { - error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, - mch->ext_tseg_mbytes); - return; - } - - /* setup pci memory mapping */ - pc_pci_as_mapping_init(mch->system_memory, mch->pci_address_space); - - /* if *disabled* show SMRAM to all CPUs */ - memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", - mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, - MCH_HOST_BRIDGE_SMRAM_C_SIZE); - memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, - &mch->smram_region, 1); - memory_region_set_enabled(&mch->smram_region, true); - - memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", - mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, - MCH_HOST_BRIDGE_SMRAM_C_SIZE); - memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, - &mch->open_high_smram, 1); - memory_region_set_enabled(&mch->open_high_smram, false); - - /* smram, as seen by SMM CPUs */ - memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", - mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, - MCH_HOST_BRIDGE_SMRAM_C_SIZE); - memory_region_set_enabled(&mch->low_smram, true); - memory_region_add_subregion(mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, - &mch->low_smram); - memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", - mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, - MCH_HOST_BRIDGE_SMRAM_C_SIZE); - memory_region_set_enabled(&mch->high_smram, true); - memory_region_add_subregion(mch->smram, 0xfeda0000, &mch->high_smram); - - memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), - &blackhole_ops, NULL, - "tseg-blackhole", 0); - memory_region_set_enabled(&mch->tseg_blackhole, false); - memory_region_add_subregion_overlap(mch->system_memory, - mch->below_4g_mem_size, - &mch->tseg_blackhole, 1); - - memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", - mch->ram_memory, mch->below_4g_mem_size, 0); - memory_region_set_enabled(&mch->tseg_window, false); - memory_region_add_subregion(mch->smram, mch->below_4g_mem_size, - &mch->tseg_window); - - /* - * This is not what hardware does, so it's QEMU specific hack. - * See commit message for details. - */ - memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops, - NULL, "smbase-blackhole", - MCH_HOST_BRIDGE_SMBASE_SIZE); - memory_region_set_enabled(&mch->smbase_blackhole, false); - memory_region_add_subregion_overlap(mch->system_memory, - MCH_HOST_BRIDGE_SMBASE_ADDR, - &mch->smbase_blackhole, 1); - - memory_region_init_alias(&mch->smbase_window, OBJECT(mch), - "smbase-window", mch->ram_memory, - MCH_HOST_BRIDGE_SMBASE_ADDR, - MCH_HOST_BRIDGE_SMBASE_SIZE); - memory_region_set_enabled(&mch->smbase_window, false); - memory_region_add_subregion(mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, - &mch->smbase_window); - - init_pam(&mch->pam_regions[0], OBJECT(mch), mch->ram_memory, - mch->system_memory, mch->pci_address_space, - PAM_BIOS_BASE, PAM_BIOS_SIZE); - for (i = 0; i < ARRAY_SIZE(mch->pam_regions) - 1; ++i) { - init_pam(&mch->pam_regions[i + 1], OBJECT(mch), mch->ram_memory, - mch->system_memory, mch->pci_address_space, - PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); - } -} - uint64_t mch_mcfg_base(void) { bool ambiguous; @@ -660,7 +654,6 @@ static void mch_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); - k->realize = mch_realize; k->config_write = mch_write_config; dc->reset = mch_reset; device_class_set_props(dc, mch_props); From patchwork Tue Feb 14 13:14:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13140019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03675C64ED6 for ; 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[92.224.101.237]) by smtp.gmail.com with ESMTPSA id hz17-20020a1709072cf100b008b13836801bsm220153ejc.183.2023.02.14.05.15.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 05:15:24 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 12/12] hw/pci-host/q35: Move MemoryRegion pointers to host device Date: Tue, 14 Feb 2023 14:14:41 +0100 Message-Id: <20230214131441.101760-13-shentey@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214131441.101760-1-shentey@gmail.com> References: <20230214131441.101760-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The pointers are set through the host device's properties and are only used during its realization phase. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/q35.h | 10 +++---- hw/pci-host/q35.c | 56 +++++++++++++++++++-------------------- 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index a04d5f1a17..9b9ce48ca8 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -40,11 +40,6 @@ struct MCHPCIState { PCIDevice parent_obj; /*< public >*/ - MemoryRegion *ram_memory; - MemoryRegion *pci_address_space; - MemoryRegion *system_memory; - MemoryRegion *address_space_io; - MemoryRegion *smram; PAMMemoryRegion pam_regions[PAM_REGIONS_COUNT]; MemoryRegion smram_region, open_high_smram; MemoryRegion low_smram, high_smram; @@ -61,6 +56,11 @@ struct Q35PCIHost { PCIExpressHost parent_obj; /*< public >*/ + MemoryRegion *ram_memory; + MemoryRegion *pci_address_space; + MemoryRegion *system_memory; + MemoryRegion *address_space_io; + MemoryRegion *smram; Range pci_hole; uint64_t pci_hole64_size; uint32_t short_root_bus; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 3a7f9185a3..cb8ea58c25 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -79,11 +79,11 @@ static void q35_host_realize(DeviceState *dev, Error **errp) return; } - memory_region_add_subregion(s->mch.address_space_io, + memory_region_add_subregion(s->address_space_io, MCH_HOST_BRIDGE_CONFIG_ADDR, &phb->conf_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); - memory_region_add_subregion(s->mch.address_space_io, + memory_region_add_subregion(s->address_space_io, MCH_HOST_BRIDGE_CONFIG_DATA, &phb->data_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); @@ -99,47 +99,47 @@ static void q35_host_realize(DeviceState *dev, Error **errp) IO_APIC_DEFAULT_ADDRESS - 1); /* setup pci memory mapping */ - pc_pci_as_mapping_init(s->mch.system_memory, s->mch.pci_address_space); + pc_pci_as_mapping_init(s->system_memory, s->pci_address_space); /* if *disabled* show SMRAM to all CPUs */ memory_region_init_alias(&s->mch.smram_region, OBJECT(s), "smram-region", - s->mch.pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, + s->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, MCH_HOST_BRIDGE_SMRAM_C_SIZE); - memory_region_add_subregion_overlap(s->mch.system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + memory_region_add_subregion_overlap(s->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, &s->mch.smram_region, 1); memory_region_set_enabled(&s->mch.smram_region, true); memory_region_init_alias(&s->mch.open_high_smram, OBJECT(s), "smram-open-high", - s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + s->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, MCH_HOST_BRIDGE_SMRAM_C_SIZE); - memory_region_add_subregion_overlap(s->mch.system_memory, 0xfeda0000, + memory_region_add_subregion_overlap(s->system_memory, 0xfeda0000, &s->mch.open_high_smram, 1); memory_region_set_enabled(&s->mch.open_high_smram, false); /* smram, as seen by SMM CPUs */ memory_region_init_alias(&s->mch.low_smram, OBJECT(s), "smram-low", - s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + s->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, MCH_HOST_BRIDGE_SMRAM_C_SIZE); memory_region_set_enabled(&s->mch.low_smram, true); - memory_region_add_subregion(s->mch.smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, + memory_region_add_subregion(s->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, &s->mch.low_smram); memory_region_init_alias(&s->mch.high_smram, OBJECT(s), "smram-high", - s->mch.ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, + s->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, MCH_HOST_BRIDGE_SMRAM_C_SIZE); memory_region_set_enabled(&s->mch.high_smram, true); - memory_region_add_subregion(s->mch.smram, 0xfeda0000, &s->mch.high_smram); + memory_region_add_subregion(s->smram, 0xfeda0000, &s->mch.high_smram); memory_region_init_io(&s->mch.tseg_blackhole, OBJECT(s), &blackhole_ops, NULL, "tseg-blackhole", 0); memory_region_set_enabled(&s->mch.tseg_blackhole, false); - memory_region_add_subregion_overlap(s->mch.system_memory, + memory_region_add_subregion_overlap(s->system_memory, s->mch.below_4g_mem_size, &s->mch.tseg_blackhole, 1); memory_region_init_alias(&s->mch.tseg_window, OBJECT(s), "tseg-window", - s->mch.ram_memory, s->mch.below_4g_mem_size, 0); + s->ram_memory, s->mch.below_4g_mem_size, 0); memory_region_set_enabled(&s->mch.tseg_window, false); - memory_region_add_subregion(s->mch.smram, s->mch.below_4g_mem_size, + memory_region_add_subregion(s->smram, s->mch.below_4g_mem_size, &s->mch.tseg_window); /* @@ -150,30 +150,30 @@ static void q35_host_realize(DeviceState *dev, Error **errp) NULL, "smbase-blackhole", MCH_HOST_BRIDGE_SMBASE_SIZE); memory_region_set_enabled(&s->mch.smbase_blackhole, false); - memory_region_add_subregion_overlap(s->mch.system_memory, + memory_region_add_subregion_overlap(s->system_memory, MCH_HOST_BRIDGE_SMBASE_ADDR, &s->mch.smbase_blackhole, 1); memory_region_init_alias(&s->mch.smbase_window, OBJECT(s), - "smbase-window", s->mch.ram_memory, + "smbase-window", s->ram_memory, MCH_HOST_BRIDGE_SMBASE_ADDR, MCH_HOST_BRIDGE_SMBASE_SIZE); memory_region_set_enabled(&s->mch.smbase_window, false); - memory_region_add_subregion(s->mch.smram, MCH_HOST_BRIDGE_SMBASE_ADDR, + memory_region_add_subregion(s->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, &s->mch.smbase_window); - init_pam(&s->mch.pam_regions[0], OBJECT(s), s->mch.ram_memory, - s->mch.system_memory, s->mch.pci_address_space, + init_pam(&s->mch.pam_regions[0], OBJECT(s), s->ram_memory, + s->system_memory, s->pci_address_space, PAM_BIOS_BASE, PAM_BIOS_SIZE); for (i = 0; i < ARRAY_SIZE(s->mch.pam_regions) - 1; ++i) { - init_pam(&s->mch.pam_regions[i + 1], OBJECT(s), s->mch.ram_memory, - s->mch.system_memory, s->mch.pci_address_space, + init_pam(&s->mch.pam_regions[i + 1], OBJECT(s), s->ram_memory, + s->system_memory, s->pci_address_space, PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); } phb->bus = pci_root_bus_new(DEVICE(s), "pcie.0", - s->mch.pci_address_space, - s->mch.address_space_io, + s->pci_address_space, + s->address_space_io, 0, TYPE_PCIE_BUS); qdev_realize(DEVICE(&s->mch), BUS(phb->bus), errp); @@ -338,23 +338,23 @@ static void q35_host_initfn(Object *obj) &pehb->size, OBJ_PROP_FLAG_READ); object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, - (Object **) &s->mch.ram_memory, + (Object **) &s->ram_memory, qdev_prop_allow_set_link_before_realize, 0); object_property_add_link(obj, MCH_HOST_PROP_SMRAM_MEM, TYPE_MEMORY_REGION, - (Object **) &s->mch.smram, + (Object **) &s->smram, qdev_prop_allow_set_link_before_realize, 0); object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, - (Object **) &s->mch.pci_address_space, + (Object **) &s->pci_address_space, qdev_prop_allow_set_link_before_realize, 0); object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, - (Object **) &s->mch.system_memory, + (Object **) &s->system_memory, qdev_prop_allow_set_link_before_realize, 0); object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, - (Object **) &s->mch.address_space_io, + (Object **) &s->address_space_io, qdev_prop_allow_set_link_before_realize, 0); }