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Tue, 14 Feb 2023 21:14:04 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121402epsmtip191e934de5270483bae4b5119e07abd9d~Dr9sjJ5Fi2380623806epsmtip1t; Tue, 14 Feb 2023 12:14:01 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 01/16] dt-bindings: PCI: Rename Exynos PCIe binding to Samsung PCIe Date: Tue, 14 Feb 2023 17:43:18 +0530 Message-Id: <20230214121333.1837-2-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTe1BUVRzH59y73L2oW9eFxgNOuF3HFBpg13gcSMAmcC7SNMw4jA0ztl2X G0ssu8veXRWrCQoweWvACsPDATSBBPeCQIBFaJEPqOGVmowwomIQLUJkgEPL7lL/fX6/3/d3 fo9zDolLewlPMklr5AxaVkMTG0RtV713+RpKplXyZ/NyNF7VRqC6z9So+tqACypvqwRobnlA hC4slIlRwdQEjtLzll2Q8GDUBQ11VhCov6qPQGd+/hZDmSuZIpT5wwkRunhtTIxqLi+I0Wp3 hxitmK0ilH/1E9QilOB73ZkZ4W8x8035mJg5K5gYoeEkwdwb7SaY2YEBMTM5bMaYlrpPGcts B8bUpM8RTEFrA2DmBa/YTfHJe9Qcm8AZZJxWpUtI0iaG0TEHlG8pA4PkCl9FCAqmZVo2hQuj I9+O9d2XpLGNScuOsBqTzRXL8jztH77HoDMZOZlaxxvDaE6foNEH6P14NoU3aRP9tJwxVCGX 7w60Cd9PVv9hHib030uOLZy7C9LB0MYc4EpCKgDeqc3Ac8AGUkp1AVjZl+k0ngKY+/CR05gH sOb8I7CeMlNRJ1pjKdUJ4KrF3yHKwmD2QCOxFiAoH5jxV4492526i8En8xPiNQOnbgDYM3VF vKZyo+Lg9HgpvsYiagdsbxq1+yVUCHzaU485ym2DjZd67BpXKhRmZgn2UyF1m4T3l7IIhygS rjYtOvtzg7/3tYod7AmfFGY7ORHWt5zBHayBiy11zgIRsGe4wjYPaevOGzZ3+jvcL8OSG012 CU69APOXJ51yCeyoWuftcOF5t8jBHrDqxyEXBzOwrngWONaSD2Bb8SBWBLzK/y9xFoAG4MHp +ZREjg/U79ZyR/+7N5UuRQD2x+yzvwNMjFv9egFGgl4ASZx2l7g9nFJJJQls2nHOoFMaTBqO 7wWBtgWewj1fUulsv0FrVCoCQuQBQUFBASGvBynoLZKdYddVUiqRNXLJHKfnDOt5GOnqmY65 uREHH5cUtkFL1rFb3eX8Vkttu+S3dHPai4w7StVc2T646PF55S/7Ngrer04srVjndz4n4u4f 3nGQsfic3ptNjhQfArEgPpu+rQp+sxHfguXV939ICxE1BUciqZgTpf6p4aqPZFmv9SlbN6Mv 2neRsf2EVxd7fUYZN1H7Z+93h1JxqWnTUHizPK1lqejel10xs0Pn4dHWqNIH1pGchcdfXbzw brQs7tc3yt75qXDOryk0w3vsZvRK2ddRSTKpejrCo3YuV9mqjjBbBI+onA+qD1s7rfvfezYT sbU5erTzn3Ncc/adkeDB6rzcV05+7Hcc23ZLFmi51BN/U3p5kjy1WkSLeDWr8MENPPsvGnbc clUEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRmVeSWpSXmKPExsWy7bCSnC5P9etkgxXzdSwezNvGZrGkKcNi /pFzrBazts1ltPj4+xyLxYovM9kt+l48ZLZo6PnNarHp8TVWi8u75rBZnJ13nM1ixvl9TBYt f1pYLFqOtrNYrD1yl91i0dYv7Bb/9+xgt/gz/QOLRe/hWovNm6YyO4h4vNn0nd1j56y77B4L NpV6bFrVyeZx59oeNo93586xezy5Mp3JY/OSeo+N73YweSxq+Mjm0bdlFaPH501yATxRXDYp qTmZZalF+nYJXBlvp19hKzjIW/Fl6S3GBsbL3F2MnBwSAiYSb+YsYeli5OIQEtjBKLGh8zgj REJS4vPFdUwQtrDEyn/P2SGKmpkkzh84C5ZgE9CSaPzaxQySEBF4xSRxeM8MMIdZ4AKjxK2D 3ewgVcICwRLvdj1hAbFZBFQltq+7BhbnFbCU+HRgJdQKeYnVGw4wg9icAlYSLa2bwGwhoJpZ v1YxTmDkW8DIsIpRMrWgODc9t9iwwCgvtVyvODG3uDQvXS85P3cTIzh2tLR2MO5Z9UHvECMT B+MhRgkOZiURXuGnL5KFeFMSK6tSi/Lji0pzUosPMUpzsCiJ817oOhkvJJCeWJKanZpakFoE k2Xi4JRqYCqt5p0Xe+zylHNf+mRjxFgcVGfLxEQdOVO/ZY/eU8f5b/6rpps1O702ODmbK5jl 8TrNHXv/f5hpncdU3h25bN72g/I3TuS99wg6Mafj0a0XRc9uXv5avvDQq/8H1p53runNLT53 /sH0yesEbPpU09917bp/wmtSbNuTxBlXTC/aeN2667f030Gl01VhJ9xZ6yJiApwE014VzK2y a7lzYW9s0dVf6ypNpM4Zuh75d3hTxEelFQ+k2RaavH98dsGje2mhZ4sa1b+UfS4yTTjAafIg WYhJ0tJTqlWpr4a/9GPSPD+1XWem2LksCr+wzcj1zda5VTFyVUZvJHtz2qt+HjK6XTzHMOOF tOjM6C3LNy1TYinOSDTUYi4qTgQABx/DIAwDAAA= X-CMS-MailID: 20230214121404epcas5p3bfa6af0151b7f319d418f7c0dbed7c5a X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121404epcas5p3bfa6af0151b7f319d418f7c0dbed7c5a References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The current DT bindings is being used for Exynos5433 SoC only. In order to extend this binding for all SoCs manufactured by Samsung using DWC PCIe controller, renaming this file to a more generic name. Signed-off-by: Shradha Todi --- .../pci/{samsung,exynos-pcie.yaml => samsung,pcie.yaml} | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) rename Documentation/devicetree/bindings/pci/{samsung,exynos-pcie.yaml => samsung,pcie.yaml} (93%) diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,pcie.yaml similarity index 93% rename from Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml rename to Documentation/devicetree/bindings/pci/samsung,pcie.yaml index f20ed7e709f7..6cd36d9ccba0 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,pcie.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# +$id: http://devicetree.org/schemas/pci/samsung,pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Samsung SoC series PCIe Host Controller +title: Samsung SoC series PCIe Controller maintainers: - Marek Szyprowski - Jaehoon Chung description: |+ - Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare + Samsung SoC PCIe controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. 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Tue, 14 Feb 2023 21:14:11 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121408epsmtip142a0a642b57491c7daf7930f59068986~Dr9yns0Kx1886618866epsmtip1d; Tue, 14 Feb 2023 12:14:08 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 02/16] PCI: exynos: Rename Exynos PCIe driver to Samsung PCIe Date: Tue, 14 Feb 2023 17:43:19 +0530 Message-Id: <20230214121333.1837-3-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTfVBUVRjG59x7uXexYG4LTEdCpIUsmYDd3MWDSeVEcEVHECudsoHrcttF 9uO2u1iwYy4OjImuU8wwECGhUq00WCzEgMFGiDIQUQIxLLoMTJKYtfIl4QDS7l6s/37neZ53 3vOeDxEudpChohydiTPoWI2EXEc0X9n8XIy57K5SOlyagMarm0lUe1yNPu/q90OVzWcBmlnq J5Bt/lMKnZmawJHl9JIfsv8+7IcGL1eR6OfqbhJV/OLAUNFyEYGKrp4gUH2Xi0Lnv5un0Gpb C4WWy6cJZL1yFDXay/BXgpm/7P9QTGuli2Jq7HmMve4kydwcbiMZd38/xdwaKseYxtpjTIO7 BWPOW2ZI5kxTHWDm7OHpj7+Vu13NsdmcIYLTKfXZOTpVomTXvsxXMxXxUlmMLAFtlUToWC2X KEnanR6TnKPxjCmJOMJq8jxSOms0SuJe2m7Q55m4CLXeaEqUcHy2hpfzsUZWa8zTqWJ1nGmb TCp9QeEJZuWqZ1dHcX7K9EFJdStmAZZDJcBfBGk5vP3FCFUC1onE9PcAHl9xE15DTM8C+HD1 acFYALC5fNJjiHwVi71aQW8HcHDaRgqLYgwW9tVQ3mqSjoaF90twrxFMj2LwztyErwdO9wLY MdXuSwXRadB234l5maCfgZesD/28LQLoBNh3jhf2txF+/W0H7mV/ehssKrbjgn5TBI87OIGT 4GztAilwEPyzu4kSOBTOudvXdBW82FixVquBC421mMAvw46hKt9kOL0ZfnM5TpA3wLLeS74I TgdC69KttXgAbKl+xJFwfqWNEHg9rL426CcwA1v/GAbCKVoB/Pvqux+D8Mr/O9QAUAfWc7xR q+KMCl6m497/786Ueq0d+B5y9M4W4Bqfju0EmAh0AijCJcEBQZNTSnFANptfwBn0mYY8DWfs BArP6X2Ch4Yo9Z6foDNlyuQJUnl8fLw8YUu8TPJkwLOJPUoxrWJNXC7H8ZzhUR0m8g+1YAWj BRlhW4qj6k6ZeYKn6iPjlupHMrN69tsuRuUUvxOSH+6SfsjnRm8qvVs5MNawOwSrqmEjnG8u 9yz22lzYQWvage6398o2bL3umH/D2TtzIX9fjO2osn/89Z3RTs2pwrHE0lXHD7O3w1Q3XjQ8 n3akIUXx48RirfXAQM5TD248SO52+XccSr5HONSp8qATZeKo9/oytGyS5rGusZXPLvQ4Lb9u hG2lVV86a1p+O4wtrFTVj0Te2TN09hyetWugcCImZe8xPvZeltqddvDa/j2bGP6kwh3WNJka aE7ZsaOpwixr1i5oRoJSUq+zT3z10WFzxmtmLdlXwohmuZ8CG/wLJYRRzcqicYOR/RfoUfZv UQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGLMWRmVeSWpSXmKPExsWy7bCSnK5w9etkg4bH6hYP5m1js1jSlGEx /8g5VotZ2+YyWnz8fY7FYsWXmewWfS8eMls09Pxmtdj0+BqrxeVdc9gszs47zmYx4/w+JouW Py0sFi1H21ks1h65y26xaOsXdov/e3awW/yZ/oHFovdwrcXmTVOZHUQ83mz6zu6xc9Zddo8F m0o9Nq3qZPO4c20Pm8e7c+fYPZ5cmc7ksXlJvcfGdzuYPBY1fGTz6NuyitHj8ya5AJ4oLpuU 1JzMstQifbsEroxP/28xF7woqeiat5OpgbEhqYuRg0NCwETix6ncLkYuDiGB3YwS7Te2MXUx cgLFJSU+X1wHZQtLrPz3nB3EFhJoZpKYeascxGYT0JJo/NrFDNIsIvCKSeLwnhlgDrPABUaJ Wwe7wTqEBXwlrv/rZwWxWQRUJdb1/mMF2cwrYClxZmEBxAJ5idUbDjCD2JwCVhItrZuYIZZZ Ssz6tYpxAiPfAkaGVYySqQXFuem5xYYFhnmp5XrFibnFpXnpesn5uZsYwVGjpbmDcfuqD3qH GJk4GA8xSnAwK4nwCj99kSzEm5JYWZValB9fVJqTWnyIUZqDRUmc90LXyXghgfTEktTs1NSC 1CKYLBMHp1QDk8G+4CM2+mv7VvcLb57N75O+68UCj8fTjK4ta34ofMvtY3aa1D7vkBsTP0j3 LQit1La8dPTU5miX/sYnxqfetv8uvqhS23aIjVmx8UKYy9cDE5WNY6X9+TLyUzZILk6tO798 7/+X9nmvTkZ/mVnNUXcvaMOeK3sNuHquM95beknz8dYjBUtuHBXjmWnw+F3Du08SYb3Ju0UU 7AKTUzcJ+TNd+Tvvr3xX5y8V66I9Pb/VmxfvyZivIPi/2KBSOtLi7fel958qX81cVrTD1Epw xoS3ymu4KvOOb+lwdjSXPl+nI9k0M6jtzIoPqSaWy36fq/7W7fvmZ+my1etOyRdPichRzFnL teKRvMfqbSdfL1BiKc5INNRiLipOBACp5VU4CQMAAA== X-CMS-MailID: 20230214121411epcas5p25efd5d4242c512f21165df0c2e81b8bc X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121411epcas5p25efd5d4242c512f21165df0c2e81b8bc References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The current PCIe controller driver is being used for Exynos5433 SoC only. In order to extend this driver for all SoCs manufactured by Samsung using DWC PCIe controller, rename this driver and make it Samsung specific instead of any Samsung SoC name. Signed-off-by: Shradha Todi --- MAINTAINERS | 4 +- drivers/pci/controller/dwc/Kconfig | 6 +- drivers/pci/controller/dwc/Makefile | 2 +- drivers/pci/controller/dwc/pci-samsung.c | 443 +++++++++++++++++++++++ 4 files changed, 449 insertions(+), 6 deletions(-) create mode 100644 drivers/pci/controller/dwc/pci-samsung.c diff --git a/MAINTAINERS b/MAINTAINERS index a9d38274bd4d..e61374adf193 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16084,13 +16084,13 @@ S: Maintained F: Documentation/devicetree/bindings/pci/*rcar* F: drivers/pci/controller/*rcar* -PCI DRIVER FOR SAMSUNG EXYNOS +PCI DRIVER FOR SAMSUNG M: Jingoo Han L: linux-pci@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-samsung-soc@vger.kernel.org S: Maintained -F: drivers/pci/controller/dwc/pci-exynos.c +F: drivers/pci/controller/dwc/pci-samsung.c PCI DRIVER FOR SYNOPSYS DESIGNWARE M: Jingoo Han diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 434f6a4f4041..837c7693ac6e 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -80,13 +80,13 @@ config PCIE_DW_PLAT_EP order to enable device-specific features PCI_DW_PLAT_EP must be selected. -config PCI_EXYNOS - tristate "Samsung Exynos PCIe controller" +config PCI_SAMSUNG + tristate "Samsung PCIe controller" depends on ARCH_EXYNOS || COMPILE_TEST depends on PCI_MSI select PCIE_DW_HOST help - Enables support for the PCIe controller in the Samsung Exynos SoCs + Enables support for the PCIe controller in the Samsung SoCs to work in host mode. The PCI controller is based on the DesignWare hardware and therefore the driver re-uses the DesignWare core functions to implement the driver. diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index bf5c311875a1..9daf9643342d 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o -obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o +obj-$(CONFIG_PCI_SAMSUNG) += pci-samsung.o obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c new file mode 100644 index 000000000000..cc562a8694fb --- /dev/null +++ b/drivers/pci/controller/dwc/pci-samsung.c @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Samsung SoCs + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * + * Author: Jingoo Han + * Jaehoon Chung + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_exynos_pcie(x) dev_get_drvdata((x)->dev) + +/* PCIe ELBI registers */ +#define PCIE_IRQ_PULSE 0x000 +#define IRQ_INTA_ASSERT BIT(0) +#define IRQ_INTB_ASSERT BIT(2) +#define IRQ_INTC_ASSERT BIT(4) +#define IRQ_INTD_ASSERT BIT(6) +#define PCIE_IRQ_LEVEL 0x004 +#define PCIE_IRQ_SPECIAL 0x008 +#define PCIE_IRQ_EN_PULSE 0x00c +#define PCIE_IRQ_EN_LEVEL 0x010 +#define PCIE_IRQ_EN_SPECIAL 0x014 +#define PCIE_SW_WAKE 0x018 +#define PCIE_BUS_EN BIT(1) +#define PCIE_CORE_RESET 0x01c +#define PCIE_CORE_RESET_ENABLE BIT(0) +#define PCIE_STICKY_RESET 0x020 +#define PCIE_NONSTICKY_RESET 0x024 +#define PCIE_APP_INIT_RESET 0x028 +#define PCIE_APP_LTSSM_ENABLE 0x02c +#define PCIE_ELBI_RDLH_LINKUP 0x074 +#define PCIE_ELBI_XMLH_LINKUP BIT(4) +#define PCIE_ELBI_LTSSM_ENABLE 0x1 +#define PCIE_ELBI_SLV_AWMISC 0x11c +#define PCIE_ELBI_SLV_ARMISC 0x120 +#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) + +struct exynos_pcie { + struct dw_pcie pci; + void __iomem *elbi_base; + struct clk *clk; + struct clk *bus_clk; + struct phy *phy; + struct regulator_bulk_data supplies[2]; +}; + +static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep) +{ + struct device *dev = ep->pci.dev; + int ret; + + ret = clk_prepare_enable(ep->clk); + if (ret) { + dev_err(dev, "cannot enable pcie rc clock"); + return ret; + } + + ret = clk_prepare_enable(ep->bus_clk); + if (ret) { + dev_err(dev, "cannot enable pcie bus clock"); + goto err_bus_clk; + } + + return 0; + +err_bus_clk: + clk_disable_unprepare(ep->clk); + + return ret; +} + +static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep) +{ + clk_disable_unprepare(ep->bus_clk); + clk_disable_unprepare(ep->clk); +} + +static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) +{ + writel(val, base + reg); +} + +static u32 exynos_pcie_readl(void __iomem *base, u32 reg) +{ + return readl(base + reg); +} + +static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on) +{ + u32 val; + + val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); + if (on) + val |= PCIE_ELBI_SLV_DBI_ENABLE; + else + val &= ~PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); +} + +static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on) +{ + u32 val; + + val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); + if (on) + val |= PCIE_ELBI_SLV_DBI_ENABLE; + else + val &= ~PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); +} + +static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) +{ + u32 val; + + val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); + val &= ~PCIE_CORE_RESET_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET); +} + +static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) +{ + u32 val; + + val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); + val |= PCIE_CORE_RESET_ENABLE; + + exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET); +} + +static int exynos_pcie_start_link(struct dw_pcie *pci) +{ + struct exynos_pcie *ep = to_exynos_pcie(pci); + u32 val; + + val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); + val &= ~PCIE_BUS_EN; + exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); + + /* assert LTSSM enable */ + exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE, + PCIE_APP_LTSSM_ENABLE); + return 0; +} + +static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) +{ + u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE); + + exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE); +} + +static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) +{ + struct exynos_pcie *ep = arg; + + exynos_pcie_clear_irq_pulse(ep); + return IRQ_HANDLED; +} + +static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) +{ + u32 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | + IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; + + exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE); + exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL); + exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); +} + +static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + struct exynos_pcie *ep = to_exynos_pcie(pci); + u32 val; + + exynos_pcie_sideband_dbi_r_mode(ep, true); + dw_pcie_read(base + reg, size, &val); + exynos_pcie_sideband_dbi_r_mode(ep, false); + return val; +} + +static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + struct exynos_pcie *ep = to_exynos_pcie(pci); + + exynos_pcie_sideband_dbi_w_mode(ep, true); + dw_pcie_write(base + reg, size, val); + exynos_pcie_sideband_dbi_w_mode(ep, false); +} + +static int exynos_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); + + if (PCI_SLOT(devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + + *val = dw_pcie_read_dbi(pci, where, size); + return PCIBIOS_SUCCESSFUL; +} + +static int exynos_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); + + if (PCI_SLOT(devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + + dw_pcie_write_dbi(pci, where, size, val); + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops exynos_pci_ops = { + .read = exynos_pcie_rd_own_conf, + .write = exynos_pcie_wr_own_conf, +}; + +static int exynos_pcie_link_up(struct dw_pcie *pci) +{ + struct exynos_pcie *ep = to_exynos_pcie(pci); + u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); + + return (val & PCIE_ELBI_XMLH_LINKUP); +} + +static int exynos_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct exynos_pcie *ep = to_exynos_pcie(pci); + + pp->bridge->ops = &exynos_pci_ops; + + exynos_pcie_assert_core_reset(ep); + + phy_init(ep->phy); + phy_power_on(ep->phy); + + exynos_pcie_deassert_core_reset(ep); + exynos_pcie_enable_irq_pulse(ep); + + return 0; +} + +static const struct dw_pcie_host_ops exynos_pcie_host_ops = { + .host_init = exynos_pcie_host_init, +}; + +static int exynos_add_pcie_port(struct exynos_pcie *ep, + struct platform_device *pdev) +{ + struct dw_pcie *pci = &ep->pci; + struct dw_pcie_rp *pp = &pci->pp; + struct device *dev = &pdev->dev; + int ret; + + pp->irq = platform_get_irq(pdev, 0); + if (pp->irq < 0) + return pp->irq; + + ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler, + IRQF_SHARED, "exynos-pcie", ep); + if (ret) { + dev_err(dev, "failed to request irq\n"); + return ret; + } + + pp->ops = &exynos_pcie_host_ops; + pp->msi_irq[0] = -ENODEV; + + ret = dw_pcie_host_init(pp); + if (ret) { + dev_err(dev, "failed to initialize host\n"); + return ret; + } + + return 0; +} + +static const struct dw_pcie_ops dw_pcie_ops = { + .read_dbi = exynos_pcie_read_dbi, + .write_dbi = exynos_pcie_write_dbi, + .link_up = exynos_pcie_link_up, + .start_link = exynos_pcie_start_link, +}; + +static int exynos_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct exynos_pcie *ep; + struct device_node *np = dev->of_node; + int ret; + + ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); + if (!ep) + return -ENOMEM; + + ep->pci.dev = dev; + ep->pci.ops = &dw_pcie_ops; + + ep->phy = devm_of_phy_get(dev, np, NULL); + if (IS_ERR(ep->phy)) + return PTR_ERR(ep->phy); + + /* External Local Bus interface (ELBI) registers */ + ep->elbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi"); + if (IS_ERR(ep->elbi_base)) + return PTR_ERR(ep->elbi_base); + + ep->clk = devm_clk_get(dev, "pcie"); + if (IS_ERR(ep->clk)) { + dev_err(dev, "Failed to get pcie rc clock\n"); + return PTR_ERR(ep->clk); + } + + ep->bus_clk = devm_clk_get(dev, "pcie_bus"); + if (IS_ERR(ep->bus_clk)) { + dev_err(dev, "Failed to get pcie bus clock\n"); + return PTR_ERR(ep->bus_clk); + } + + ep->supplies[0].supply = "vdd18"; + ep->supplies[1].supply = "vdd10"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies), + ep->supplies); + if (ret) + return ret; + + ret = exynos_pcie_init_clk_resources(ep); + if (ret) + return ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); + if (ret) + return ret; + + platform_set_drvdata(pdev, ep); + + ret = exynos_add_pcie_port(ep, pdev); + if (ret < 0) + goto fail_probe; + + return 0; + +fail_probe: + phy_exit(ep->phy); + exynos_pcie_deinit_clk_resources(ep); + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); + + return ret; +} + +static int __exit exynos_pcie_remove(struct platform_device *pdev) +{ + struct exynos_pcie *ep = platform_get_drvdata(pdev); + + dw_pcie_host_deinit(&ep->pci.pp); + exynos_pcie_assert_core_reset(ep); + phy_power_off(ep->phy); + phy_exit(ep->phy); + exynos_pcie_deinit_clk_resources(ep); + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); + + return 0; +} + +static int exynos_pcie_suspend_noirq(struct device *dev) +{ + struct exynos_pcie *ep = dev_get_drvdata(dev); + + exynos_pcie_assert_core_reset(ep); + phy_power_off(ep->phy); + phy_exit(ep->phy); + regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); + + return 0; +} + +static int exynos_pcie_resume_noirq(struct device *dev) +{ + struct exynos_pcie *ep = dev_get_drvdata(dev); + struct dw_pcie *pci = &ep->pci; + struct dw_pcie_rp *pp = &pci->pp; + int ret; + + ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); + if (ret) + return ret; + + /* exynos_pcie_host_init controls ep->phy */ + exynos_pcie_host_init(pp); + dw_pcie_setup_rc(pp); + exynos_pcie_start_link(pci); + return dw_pcie_wait_for_link(pci); +} + +static const struct dev_pm_ops exynos_pcie_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos_pcie_suspend_noirq, + exynos_pcie_resume_noirq) +}; + +static const struct of_device_id exynos_pcie_of_match[] = { + { .compatible = "samsung,exynos5433-pcie", }, + { }, +}; + +static struct platform_driver exynos_pcie_driver = { + .probe = exynos_pcie_probe, + .remove = __exit_p(exynos_pcie_remove), + .driver = { + .name = "exynos-pcie", + .of_match_table = exynos_pcie_of_match, + .pm = &exynos_pcie_pm_ops, + }, +}; +module_platform_driver(exynos_pcie_driver); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, exynos_pcie_of_match); From patchwork Tue Feb 14 12:13:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140276 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 413C5C6379F for ; Tue, 14 Feb 2023 14:21:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232786AbjBNOVp (ORCPT ); Tue, 14 Feb 2023 09:21:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233183AbjBNOVm (ORCPT ); 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Tue, 14 Feb 2023 21:14:16 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121412epsmtip16b2056a766c6d8bfdb919dd9855aabcb~Dr92tqndW2484124841epsmtip1M; Tue, 14 Feb 2023 12:14:12 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 03/16] PCI: samsung: Change macro names to exynos specific Date: Tue, 14 Feb 2023 17:43:20 +0530 Message-Id: <20230214121333.1837-4-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMJsWRmVeSWpSXmKPExsWy7bCmhu7Sqa+TDV48M7V4MG8bm8WSpgyL +UfOsVrM2jaX0eLj73MsFiu+zGS36HvxkNmioec3q8Wmx9dYLS7vmsNmcXbecTaLGef3MVm0 /GlhsWg52s5isfbIXXaLRVu/sFv837OD3eLP9A8sFr2Hay02b5rK7CDi8WbTd3aPnbPusnss 2FTqsWlVJ5vHnWt72DzenTvH7vHkynQmj81L6j02vtvB5LGo4SObR9+WVYwenzfJBfBEZdtk pCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam2iq5+AToumXmAL2ppFCWmFMK FApILC5W0rezKcovLUlVyMgvLrFVSi1IySkwKdArTswtLs1L18tLLbEyNDAwMgUqTMjO6H4z k63gtm3FpCmz2RsYT5h2MXJySAiYSPQ3bmbqYuTiEBLYzSgx4cEDZgjnE6PE8qknoTLfGCWa G24zw7T0zXrNCpHYyyixf/9iqJZWJolNG6exglSxCWhJNH7tAkuICNxiknj5+SE7iMMscIpR 4sCLvewgVcICXhKd9z4zgtgsAqoSD58sAYvzClhKPJ6+lg1in7zE6g0HwHZzClhJtLRuApsq IXCDQ+L0vVksEEUuEkdvTWKEsIUlXh3fwg5hS0l8frcXalC6xMrNM6CeyJH4tnkJE4RtL3Hg yhygORxA12lKrN+lDxGWlZh6ah1YCbMAn0Tv7ydQ5bwSO+bB2MoSX/7ugTpBUmLescusELaH xK5/KxghwdLLKPF72jGWCYxysxBWLGBkXMUomVpQnJueWmxaYJSXWg6PuOT83E2M4NSs5bWD 8eGDD3qHGJk4GA8xSnAwK4nwCj99kSzEm5JYWZValB9fVJqTWnyI0RQYgBOZpUST84HZIa8k 3tDE0sDEzMzMxNLYzFBJnFfd9mSykEB6YklqdmpqQWoRTB8TB6dUA9OsVfqhtsKSoWIvVy/b 4HP7y6JAplNT7N00ogXXtH5Q1fFXO7ZLNcQwIWmG8isNBcZHXw/xXv5z5lLtv5+SxowRqxQO v+79Nivn3OauwkuHZWWOxjcs/ekgf3yvoP0epwnrJacqND8+6b/V8WvG1UZm5uVuymvLLXcs /twd7rfs2EK++UsevtWaE/Cn/cmlzd3/6qvmqrc+NlGTbjAsUG+WvsSStak6cVfI+QMets3h 3GvCztyf8EnpccCD/YpR72I5T/5/7Fu2ztPoiZ5CRNhEd9Ef9udfqM5N63w07cX5vV5NZfOk GFqzjSbkntZ+vrjo2NO6lTdnTv5rW7779BehMp3YWx9Ov5Kq6shMq/yoxFKckWioxVxUnAgA zbP9MFYEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRmVeSWpSXmKPExsWy7bCSnK5E9etkgw9zxSwezNvGZrGkKcNi /pFzrBazts1ltPj4+xyLxYovM9kt+l48ZLZo6PnNarHp8TVWi8u75rBZnJ13nM1ixvl9TBYt f1pYLFqOtrNYrD1yl91i0dYv7Bb/9+xgt/gz/QOLRe/hWovNm6YyO4h4vNn0nd1j56y77B4L NpV6bFrVyeZx59oeNo93586xezy5Mp3JY/OSeo+N73YweSxq+Mjm0bdlFaPH501yATxRXDYp qTmZZalF+nYJXBndb2ayFdy2rZg0ZTZ7A+MJ0y5GTg4JAROJvlmvWbsYuTiEBHYzStyefpoJ IiEp8fniOihbWGLlv+fsEEXNTBKn1x5mBEmwCWhJNH7tYgZJiAi8YpI4vGcGmMMscIFR4tbB bnaQKmEBL4nOe5/BOlgEVCUePlkCFucVsJR4PH0tG8QKeYnVGw4wg9icAlYSLa2bwGwhoJpZ v1YxTmDkW8DIsIpRMrWgODc9t9iwwDAvtVyvODG3uDQvXS85P3cTIzh2tDR3MG5f9UHvECMT B+MhRgkOZiURXuGnL5KFeFMSK6tSi/Lji0pzUosPMUpzsCiJ817oOhkvJJCeWJKanZpakFoE k2Xi4JRqYOqYNVus/x3vzRdCm6bF3/szT++G6MmJB1+f+l+yOmTC9I6X9var2Oy6b6c4e2f3 Hd+1to4nZlGC586Fkx9tncsivr1EIylU3t/rsEXQdQ6LF+tzk79OX7Trq2pI/e+T/z9/m6Ph v5B/lYb173/xJ7s9M5YGpa7aHKt95/Kz5JeNr0udtsxZtMa6Uc3g4tYu11n/lIU4+X/27SpJ sp4ee/gN+4wSy2CLlt8KLzb2nzVZqqrOJ2O6ZS7jmSOHjHJ+WPozzvp1ec32mt8C7CGRR2+H XddeqDRT8Jfrt9vSdn++rTwWmy6da8TP8I7LsFLpaNW3GXZHVI79LKq2+Jhlnnhedm4/43+F r6t/NIl805JVYinOSDTUYi4qTgQAqey39AwDAAA= X-CMS-MailID: 20230214121416epcas5p4de066199144cba18858e68f6d0ccb1c0 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121416epcas5p4de066199144cba18858e68f6d0ccb1c0 References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Since the macros being used in samsung file are for exynos only, renaming it to be more specific. Signed-off-by: Shradha Todi Suggested-by: Pankaj Dubey Acked-by: Krzysztof Kozlowski --- drivers/pci/controller/dwc/pci-samsung.c | 116 +++++++++++------------ 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c index cc562a8694fb..cfe384aee754 100644 --- a/drivers/pci/controller/dwc/pci-samsung.c +++ b/drivers/pci/controller/dwc/pci-samsung.c @@ -26,30 +26,30 @@ #define to_exynos_pcie(x) dev_get_drvdata((x)->dev) /* PCIe ELBI registers */ -#define PCIE_IRQ_PULSE 0x000 -#define IRQ_INTA_ASSERT BIT(0) -#define IRQ_INTB_ASSERT BIT(2) -#define IRQ_INTC_ASSERT BIT(4) -#define IRQ_INTD_ASSERT BIT(6) -#define PCIE_IRQ_LEVEL 0x004 -#define PCIE_IRQ_SPECIAL 0x008 -#define PCIE_IRQ_EN_PULSE 0x00c -#define PCIE_IRQ_EN_LEVEL 0x010 -#define PCIE_IRQ_EN_SPECIAL 0x014 -#define PCIE_SW_WAKE 0x018 -#define PCIE_BUS_EN BIT(1) -#define PCIE_CORE_RESET 0x01c -#define PCIE_CORE_RESET_ENABLE BIT(0) -#define PCIE_STICKY_RESET 0x020 -#define PCIE_NONSTICKY_RESET 0x024 -#define PCIE_APP_INIT_RESET 0x028 -#define PCIE_APP_LTSSM_ENABLE 0x02c -#define PCIE_ELBI_RDLH_LINKUP 0x074 -#define PCIE_ELBI_XMLH_LINKUP BIT(4) -#define PCIE_ELBI_LTSSM_ENABLE 0x1 -#define PCIE_ELBI_SLV_AWMISC 0x11c -#define PCIE_ELBI_SLV_ARMISC 0x120 -#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21) +#define EXYNOS_PCIE_IRQ_PULSE 0x000 +#define EXYNOS_IRQ_INTA_ASSERT BIT(0) +#define EXYNOS_IRQ_INTB_ASSERT BIT(2) +#define EXYNOS_IRQ_INTC_ASSERT BIT(4) +#define EXYNOS_IRQ_INTD_ASSERT BIT(6) +#define EXYNOS_PCIE_IRQ_LEVEL 0x004 +#define EXYNOS_PCIE_IRQ_SPECIAL 0x008 +#define EXYNOS_PCIE_IRQ_EN_PULSE 0x00c +#define EXYNOS_PCIE_IRQ_EN_LEVEL 0x010 +#define EXYNOS_PCIE_IRQ_EN_SPECIAL 0x014 +#define EXYNOS_PCIE_SW_WAKE 0x018 +#define EXYNOS_PCIE_BUS_EN BIT(1) +#define EXYNOS_PCIE_CORE_RESET 0x01c +#define EXYNOS_PCIE_CORE_RESET_ENABLE BIT(0) +#define EXYNOS_PCIE_STICKY_RESET 0x020 +#define EXYNOS_PCIE_NONSTICKY_RESET 0x024 +#define EXYNOS_PCIE_APP_INIT_RESET 0x028 +#define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c +#define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074 +#define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4) +#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 +#define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c +#define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 +#define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) struct exynos_pcie { struct dw_pcie pci; @@ -105,49 +105,49 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on) { u32 val; - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); + val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_AWMISC); if (on) - val |= PCIE_ELBI_SLV_DBI_ENABLE; + val |= EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; else - val &= ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); + val &= ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_AWMISC); } static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on) { u32 val; - val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); + val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_ARMISC); if (on) - val |= PCIE_ELBI_SLV_DBI_ENABLE; + val |= EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; else - val &= ~PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); + val &= ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_ARMISC); } static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) { u32 val; - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); - val &= ~PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET); + val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val &= ~EXYNOS_PCIE_CORE_RESET_ENABLE; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_NONSTICKY_RESET); } static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) { u32 val; - val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); - val |= PCIE_CORE_RESET_ENABLE; + val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val |= EXYNOS_PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_NONSTICKY_RESET); + exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_APP_INIT_RESET); } static int exynos_pcie_start_link(struct dw_pcie *pci) @@ -155,21 +155,21 @@ static int exynos_pcie_start_link(struct dw_pcie *pci) struct exynos_pcie *ep = to_exynos_pcie(pci); u32 val; - val = exynos_pcie_readl(ep->elbi_base, PCIE_SW_WAKE); - val &= ~PCIE_BUS_EN; - exynos_pcie_writel(ep->elbi_base, val, PCIE_SW_WAKE); + val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_SW_WAKE); + val &= ~EXYNOS_PCIE_BUS_EN; + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_SW_WAKE); /* assert LTSSM enable */ - exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE, - PCIE_APP_LTSSM_ENABLE); + exynos_pcie_writel(ep->elbi_base, EXYNOS_PCIE_ELBI_LTSSM_ENABLE, + EXYNOS_PCIE_APP_LTSSM_ENABLE); return 0; } static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) { - u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE); + u32 val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_IRQ_PULSE); - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_PULSE); } static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) @@ -182,12 +182,12 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) { - u32 val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | - IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; + u32 val = EXYNOS_IRQ_INTA_ASSERT | EXYNOS_IRQ_INTB_ASSERT | + EXYNOS_IRQ_INTC_ASSERT | EXYNOS_IRQ_INTD_ASSERT; - exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_LEVEL); - exynos_pcie_writel(ep->elbi_base, 0, PCIE_IRQ_EN_SPECIAL); + exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_EN_PULSE); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); + exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); } static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, @@ -244,9 +244,9 @@ static struct pci_ops exynos_pci_ops = { static int exynos_pcie_link_up(struct dw_pcie *pci) { struct exynos_pcie *ep = to_exynos_pcie(pci); - u32 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP); + u32 val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_RDLH_LINKUP); - return (val & PCIE_ELBI_XMLH_LINKUP); + return (val & EXYNOS_PCIE_ELBI_XMLH_LINKUP); } static int exynos_pcie_host_init(struct dw_pcie_rp *pp) From patchwork Tue Feb 14 12:13:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140296 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4114BC64EC7 for ; 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Tue, 14 Feb 2023 12:14:20 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20230214121420epsmtrp13d02d0e29655688e26ac6ba69407ec66~Dr99t3azt1788717887epsmtrp11; Tue, 14 Feb 2023 12:14:20 +0000 (GMT) X-AuditID: b6c32a4b-46dfa70000011a6d-3f-63eb95c2e239 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 16.FA.17995.C1B7BE36; Tue, 14 Feb 2023 21:14:20 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121417epsmtip10da7614a02844143b442ca0c139b0737~Dr968m25i2493724937epsmtip1R; Tue, 14 Feb 2023 12:14:17 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 04/16] PCI: samsung: Use clock bulk API to get clocks Date: Tue, 14 Feb 2023 17:43:21 +0530 Message-Id: <20230214121333.1837-5-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrEJsWRmVeSWpSXmKPExsWy7bCmpu6hqa+TDVb9MLF4MG8bm8WSpgyL +UfOsVrM2jaX0eLj73MsFiu+zGS36HvxkNmioec3q8Wmx9dYLS7vmsNmcXbecTaLGef3MVm0 /GlhsWg52s5isfbIXXaLRVu/sFv837OD3eLP9A8sFr2Hay02b5rK7CDi8WbTd3aPnbPusnss 2FTqsWlVJ5vHnWt72DzenTvH7vHkynQmj81L6j02vtvB5LGo4SObR9+WVYwenzfJBfBEZdtk pCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam2iq5+AToumXmAL2ppFCWmFMK FApILC5W0rezKcovLUlVyMgvLrFVSi1IySkwKdArTswtLs1L18tLLbEyNDAwMgUqTMjO+DBl FlvBRrGKzTf2MDUwbhLqYuTkkBAwkfg34wN7FyMXh5DAbkaJnq7lzBDOJ0aJq68fskA4nxkl Nuy+ywzTMuXbOqiqXYwSd86cZ4NwWpkkGh7/YgWpYhPQkmj82gVWJSJwi0ni5eeHYFuYBU4x Shx4sZcdpEpYwFViwtqnYDaLgKrEy/MTwGxeAUuJxVemQe2Tl1i94QCYzSlgJdHSugkqfoVD 4v5HAQjbRaK/AeY+YYlXx7ewQ9hSEi/726DsdImVm2dA1eRIfNu8hAnCtpc4cGUO0KMcQMdp SqzfpQ8RlpWYemodWAmzAJ9E7+8nUOW8EjvmwdjKEl/+7mGBsCUl5h27zAphe0i8Pd3EBAmV XkaJU5seM01glJuFsGIBI+MqRsnUguLc9NRi0wLjvNRyeLwl5+duYgQnZi3vHYyPHnzQO8TI xMF4iFGCg1lJhFf46YtkId6UxMqq1KL8+KLSnNTiQ4ymwPCbyCwlmpwPzA15JfGGJpYGJmZm ZiaWxmaGSuK86rYnk4UE0hNLUrNTUwtSi2D6mDg4pRqYil2/z2JndFrdmpfpYhTjcbDnT9rt 1VkG5zZu3ZzTJF0hHT6f7QlfbqnrF4fGxH86fHcZNOO0d89i8Hsbpx3Tefu4/JyDLIJGQduU V+z+K/BgS/SXS/zxibd/HJr3bGbB7pTN/9fMm3PFNcPv9emn4rNPRMzx+Tj1U+9UsU3RK89f OhgwdyPLjjCFCWlGE1y4VLcZpr9lLTjW6sl5VedyoEM/i2KLaPdztQ01bRtr5+1dvs8kyE3l dBy7b+GJX24r/6tse7Tsb/sDvcP+qmlV9dudO+LsnKM4mIRnFfAWbPxwVTDDd9I+3r2Ht7N3 LpXXajDN3+C6ZkLZOad0uRs5EzlnyZZI7j5Xx+i1wvyIEktxRqKhFnNRcSIAedylllUEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRmVeSWpSXmKPExsWy7bCSnK5M9etkg542EYsH87axWSxpyrCY f+Qcq8WsbXMZLT7+PsdiseLLTHaLvhcPmS0aen6zWmx6fI3V4vKuOWwWZ+cdZ7OYcX4fk0XL nxYWi5aj7SwWa4/cZbdYtPULu8X/PTvYLf5M/8Bi0Xu41mLzpqnMDiIebzZ9Z/fYOesuu8eC TaUem1Z1snncubaHzePduXPsHk+uTGfy2Lyk3mPjux1MHosaPrJ59G1ZxejxeZNcAE8Ul01K ak5mWWqRvl0CV8aHKbPYCjaKVWy+sYepgXGTUBcjJ4eEgInElG/rmLsYuTiEBHYwSmy40MII kZCU+HxxHROELSyx8t9zdoiiZiaJax1/wYrYBLQkGr92gXWLCLxikji8ZwaYwyxwgVHi1sFu dpAqYQFXiQlrn4LZLAKqEi/PTwCzeQUsJRZfmcYMsUJeYvWGA2A2p4CVREvrJjBbCKhm1q9V jBMY+RYwMqxilEwtKM5Nzy02LDDKSy3XK07MLS7NS9dLzs/dxAiOHS2tHYx7Vn3QO8TIxMF4 iFGCg1lJhFf46YtkId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rwXuk7GCwmkJ5akZqemFqQWwWSZ ODilGpjaeE+9Nt/ZtZOhhVU37mza/y+1MaI6J/9YSE3l/vzep5frkS4bj9CLCKe6BhG5XDeV iOW9uaUiNavWfLcx+3Z6Y5Zn24HYG4ERbBL3n83SS05zfbaroyH72cnJ/Hxz1wpVnk19l9/C serDy20lu3J7Dsx/slvLuyfzu7A1h8PChm9Hyw66HXjz6WrOkb375k1k6sy6v+3qns4Xe75c z3bLv8g1rTbQ/P7Z/zZvKsXP/VzQvSUn/8ACF76OZXe8uxbq69lvY9n4IGnZzRs5k0x1HOQT A++s2vB4+wnW0h0LHB9d6LC8EutyMzfq/flD257dU/nn6lCpbbWVIfOUQq/HtSMbI9ZyBbye 6pqX2aGlxFKckWioxVxUnAgAgak7egwDAAA= X-CMS-MailID: 20230214121420epcas5p3a4419059969adfb45b379f7e7741968c X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121420epcas5p3a4419059969adfb45b379f7e7741968c References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Adopt to clock bulk API to handle clocks. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-samsung.c | 46 ++++++------------------ 1 file changed, 11 insertions(+), 35 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c index cfe384aee754..6c07d3f151be 100644 --- a/drivers/pci/controller/dwc/pci-samsung.c +++ b/drivers/pci/controller/dwc/pci-samsung.c @@ -54,8 +54,8 @@ struct exynos_pcie { struct dw_pcie pci; void __iomem *elbi_base; - struct clk *clk; - struct clk *bus_clk; + struct clk_bulk_data *clks; + int clk_cnt; struct phy *phy; struct regulator_bulk_data supplies[2]; }; @@ -65,30 +65,18 @@ static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep) struct device *dev = ep->pci.dev; int ret; - ret = clk_prepare_enable(ep->clk); - if (ret) { - dev_err(dev, "cannot enable pcie rc clock"); + ret = devm_clk_bulk_get_all(dev, &ep->clks); + if (ret < 0) return ret; - } - ret = clk_prepare_enable(ep->bus_clk); - if (ret) { - dev_err(dev, "cannot enable pcie bus clock"); - goto err_bus_clk; - } + ep->clk_cnt = ret; - return 0; - -err_bus_clk: - clk_disable_unprepare(ep->clk); - - return ret; + return clk_bulk_prepare_enable(ep->clk_cnt, ep->clks); } static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep) { - clk_disable_unprepare(ep->bus_clk); - clk_disable_unprepare(ep->clk); + clk_bulk_disable_unprepare(ep->clk_cnt, ep->clks); } static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) @@ -332,17 +320,9 @@ static int exynos_pcie_probe(struct platform_device *pdev) if (IS_ERR(ep->elbi_base)) return PTR_ERR(ep->elbi_base); - ep->clk = devm_clk_get(dev, "pcie"); - if (IS_ERR(ep->clk)) { - dev_err(dev, "Failed to get pcie rc clock\n"); - return PTR_ERR(ep->clk); - } - - ep->bus_clk = devm_clk_get(dev, "pcie_bus"); - if (IS_ERR(ep->bus_clk)) { - dev_err(dev, "Failed to get pcie bus clock\n"); - return PTR_ERR(ep->bus_clk); - } + ret = exynos_pcie_init_clk_resources(ep); + if (ret < 0) + return ret; ep->supplies[0].supply = "vdd18"; ep->supplies[1].supply = "vdd10"; @@ -351,10 +331,6 @@ static int exynos_pcie_probe(struct platform_device *pdev) if (ret) return ret; - ret = exynos_pcie_init_clk_resources(ep); - if (ret) - return ret; - ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); if (ret) return ret; @@ -369,8 +345,8 @@ static int exynos_pcie_probe(struct platform_device *pdev) fail_probe: phy_exit(ep->phy); - exynos_pcie_deinit_clk_resources(ep); regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); + exynos_pcie_deinit_clk_resources(ep); return ret; } From patchwork Tue Feb 14 12:13:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140298 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26B3BC6379F for ; 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Tue, 14 Feb 2023 12:14:24 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20230214121424epsmtrp114f31489629691cd65e62d91d8f2a18d~Dr_Bas2u41843918439epsmtrp1E; Tue, 14 Feb 2023 12:14:24 +0000 (GMT) X-AuditID: b6c32a49-e75fa70000012920-47-63eb95e62dff Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 98.FA.17995.02B7BE36; Tue, 14 Feb 2023 21:14:24 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121421epsmtip11cc3c41c0c08218d174e751e42f73cba~Dr9_oUh8v2436024360epsmtip1j; Tue, 14 Feb 2023 12:14:21 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 05/16] dt-bindings: PCI: Rename the term elbi to appl Date: Tue, 14 Feb 2023 17:43:22 +0530 Message-Id: <20230214121333.1837-6-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAJsWRmVeSWpSXmKPExsWy7bCmuu6zqa+TDf4cY7d4MG8bm8WSpgyL +UfOsVrM2jaX0eLj73MsFiu+zGS36HvxkNmioec3q8Wmx9dYLS7vmsNmcXbecTaLGef3MVm0 /GlhsWg52s5isfbIXXaLRVu/sFv837OD3eLP9A8sFr2Hay02b5rK7CDi8WbTd3aPnbPusnss 2FTqsWlVJ5vHnWt72DzenTvH7vHkynQmj81L6j02vtvB5LGo4SObR9+WVYwenzfJBfBEZdtk pCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam2iq5+AToumXmAL2ppFCWmFMK FApILC5W0rezKcovLUlVyMgvLrFVSi1IySkwKdArTswtLs1L18tLLbEyNDAwMgUqTMjOuNLf yFywnbNiwwK7BsZj7F2MnBwSAiYS285cZu1i5OIQEtjNKHFmxQYmCOcTo0TjtYNsEM5nRomt P6cwwbS0/J7BDpHYxShx+dEPZginlUni/6c5bCBVbAJaEo1fu8ASIgK3mCRefn4I1sIscIpR 4sCLvWDrhQVcJa7fXMEMYrMIqEqsP7EELM4rYCmxYud1qH3yEqs3HACr4RSwkmhp3cQMEb/A IbG/KRvCdpG4Pmsh1EvCEq+Ob4GypSRe9rdB2ekSKzfPgOrNkfi2eQnUfHuJA1fmsHQxcgAd pymxfpc+RFhWYuqpdWAlzAJ8Er2/n0CV80rsmAdjK0t8+buHBcKWlJh3DBSSILaHRMfHfrAa IYFeRonW96ITGOVmIWxYwMi4ilEytaA4Nz212LTAMC+1HB5ryfm5mxjBSVnLcwfj3Qcf9A4x MnEwHmKU4GBWEuEVfvoiWYg3JbGyKrUoP76oNCe1+BCjKTD4JjJLiSbnA/NCXkm8oYmlgYmZ mZmJpbGZoZI4r7rtyWQhgfTEktTs1NSC1CKYPiYOTqkGJjGTL1u1s1mf2xzfvL1h17uwU4m7 k/9WnvYUjvqf832Nnd+ka63lsxZu6H5xLu3c/Ef1bt3b4qctl/2UYDvp6bKVF3vMjr01uVSZ 8EaQa04rxxXfWTbFi1S/eeef85+rqaGds0l10+JJ2zTbfzpX5V3w0Io6u5z/ekYsw+ns+d+D uZeHOreq1Lsuf5/k8/mLiFQ3R6XXFKN+hYCJGYycsz+rL86Z9CDlyZLNlqdF97cc4A4t/iTR u7Gon+VweFnMP6MT3DwZdw2r3plN8+dMLt2ZMH0eG9ezTtXWaWeq773z2CH7zNO375PvjCvr sk+Z7f/2eMZlLavziV0hT/+X8O+5dbjHx9Rd8ePzzJUlykosxRmJhlrMRcWJABqBLptTBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsWy7bCSnK5C9etkg9mfhSwezNvGZrGkKcNi /pFzrBazts1ltPj4+xyLxYovM9kt+l48ZLZo6PnNarHp8TVWi8u75rBZnJ13nM1ixvl9TBYt f1pYLFqOtrNYrD1yl91i0dYv7Bb/9+xgt/gz/QOLRe/hWovNm6YyO4h4vNn0nd1j56y77B4L NpV6bFrVyeZx59oeNo93586xezy5Mp3JY/OSeo+N73YweSxq+Mjm0bdlFaPH501yATxRXDYp qTmZZalF+nYJXBlX+huZC7ZzVmxYYNfAeIy9i5GTQ0LARKLl9wwgm4tDSGAHo8SS1YfZIBKS Ep8vrmOCsIUlVv57DlXUzCRx+dV1FpAEm4CWROPXLmaQhIjAKyaJw3tmgDnMAhcYJW4d7Abb ISzgKnH95gpmEJtFQFVi/YklYHFeAUuJFTuvQ62Ql1i94QBYDaeAlURL6yYwWwioZtavVYwT GPkWMDKsYpRMLSjOTc8tNiwwykst1ytOzC0uzUvXS87P3cQIjhwtrR2Me1Z90DvEyMTBeIhR goNZSYRX+OmLZCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8F7pOxgsJpCeWpGanphakFsFkmTg4 pRqY6n94zPzw/Ifsr4+a5vcbnM/7cDs1feJy17x0+29d8w2JL8IVezR/NtctuCVUbyrsvW1m fqH0DLkWwfji67+X3TtVvuSB96In/LzPZVo6ZYUmXSrquNqlbyRQZLd+9flVnvef29bpfbqf b7b1sTvf7+1lHFy1t1ytsxZH9HkJHzluOHGeyL2F+p4aXypbg92WGDCwxf6Q3qI2Yz6Li/qH BeJMW9WL3gaaPLa9uOffe8Mpgn+s+JY/VNsQ9+/2Z48bT0PbqiaUMG/LiDewST7d9W5riKR0 4to7a2f2szufu27EV7PjKnPVlR7JJb1LWx7vz+jjVjn7ed3a7s33WL3jt7rK/s6OzHsbKiyw jM9ZiaU4I9FQi7moOBEAJbfJ/QsDAAA= X-CMS-MailID: 20230214121424epcas5p38e74b52a2d94a32b82a093c7e0a12499 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121424epcas5p38e74b52a2d94a32b82a093c7e0a12499 References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org DT uses the name elbi in reg-names for application logic registers which is a wrong nomenclature. This patch fixes the same. This commit shouldn't be applied without changes "arm64: dts: Rename the term elbi to appl" and "PCI: samsung: Rename the term elbi to appl" Signed-off-by: Shradha Todi --- Documentation/devicetree/bindings/pci/samsung,pcie.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/samsung,pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,pcie.yaml index 6cd36d9ccba0..9c58c4d1f6a7 100644 --- a/Documentation/devicetree/bindings/pci/samsung,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,pcie.yaml @@ -25,13 +25,13 @@ properties: reg: items: - description: Data Bus Interface (DBI) registers. - - description: External Local Bus interface (ELBI) registers. + - description: Controller's application logic registers. - description: PCIe configuration space region. reg-names: items: - const: dbi - - const: elbi + - const: appl - const: config interrupts: From patchwork Tue Feb 14 12:13:23 2023 Content-Type: text/plain; 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Tue, 14 Feb 2023 23:08:58 +0900 (KST) Received: from epsmtrp1.samsung.com (unknown [182.195.40.13]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20230214121428epcas5p3d91e877e62a78008d2b0d6066efea059~Dr_FPX-FA2572325723epcas5p3K; Tue, 14 Feb 2023 12:14:28 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20230214121428epsmtrp1c101c1be933254e023baebcdba5d17d8~Dr_FOZZP_1843918439epsmtrp1J; Tue, 14 Feb 2023 12:14:28 +0000 (GMT) X-AuditID: b6c32a4b-20fff70000011a6d-a8-63eb95fa01e7 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 17.8E.05839.42B7BE36; Tue, 14 Feb 2023 21:14:28 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121425epsmtip1837bf30f8b9641c1a91e0ec137968c60~Dr_CVAQ6I1886618866epsmtip1h; Tue, 14 Feb 2023 12:14:25 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 06/16] arm64: dts: exynos: Rename the term elbi to appl Date: Tue, 14 Feb 2023 17:43:23 +0530 Message-Id: <20230214121333.1837-7-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAJsWRmVeSWpSXmKPExsWy7bCmpu6vqa+TDfbvMLV4MG8bm8WSpgyL +UfOsVrM2jaX0eLj73MsFiu+zGS36HvxkNmioec3q8Wmx9dYLS7vmsNmcXbecTaLGef3MVm0 /GlhsWg52s5isfbIXXaLRVu/sFv837OD3eLP9A8sFr2Hay02b5rK7CDi8WbTd3aPnbPusnss 2FTqsWlVJ5vHnWt72DzenTvH7vHkynQmj81L6j02vtvB5LGo4SObR9+WVYwenzfJBfBEZdtk pCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam2iq5+AToumXmAL2ppFCWmFMK FApILC5W0rezKcovLUlVyMgvLrFVSi1IySkwKdArTswtLs1L18tLLbEyNDAwMgUqTMjO+Pb3 D3PBT/aKy2/uszUwHmXrYuTkkBAwkdhweD2QzcUhJLCbUeLSpFfsEM4nRon5n1ZAZb4xStxf /pwZpuXQ+U6oqr2MEj86F0A5rUwSq47tZwWpYhPQkmj82sUMkhARuMUk8fLzQ7AqZoFTjBIH XuwFcjg4hAXcJY4cVgJpYBFQlbjXuhdsBa+ApcTGlldQF8pLrN5wACzOKWAl0dK6CeqMGxwS H07wgIyREHCRmD3VHSIsLPHq+BZ2CFtK4mV/G5SdLrFy8wyo1hyJb5uXMEHY9hIHrsxhARnD LKApsX6XPkRYVmLqqXVgJcwCfBK9v59AlfNK7JgHYytLfPm7hwXClpSYd+wyK4TtIfFl3mZG SJj0MkpsvXKIdQKj3CyEFQsYGVcxSqYWFOempxabFhjnpZbDYy05P3cTIzgpa3nvYHz04IPe IUYmDsZDjBIczEoivMJPXyQL8aYkVlalFuXHF5XmpBYfYjQFBt9EZinR5HxgXsgriTc0sTQw MTMzM7E0NjNUEudVtz2ZLCSQnliSmp2aWpBaBNPHxMEp1cDkZOskI+CUNu9BgcOJo8eLPP6q uf3VZfzLHNUwIUOq9WYTy7qYFzWeTwu+dxXEHG+KnJWW/2+qfpPi4d9H+Nk9bigprN0qvWhF g21d5tkrO/0KvLPiJu98IHQnOHle9mWDLDWeZ6VH+xZ8nsEgu/TOwosX14bz57GVJwTtdnM1 LNgm/cQhQDjsfJMHwys+v/X+mpO/aT35el7lXvvdu/3Td1rmRnWc1m1bEi8yf/1Vu5XZR39s eczra5dTofxFRTjwoPVz07UT8w9Y/T+Z0Lhv0Qn7vr5b2y5xyiaV/9GSl2ScPrtkm3B9tnpC S8stmV0PnGZ4y0+6c+R31x3t11oPXx8xe/Mp1urLkXPXdnsosRRnJBpqMRcVJwIAMRPSAFME AAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsWy7bCSnK5K9etkg7cbpCwezNvGZrGkKcNi /pFzrBazts1ltPj4+xyLxYovM9kt+l48ZLZo6PnNarHp8TVWi8u75rBZnJ13nM1ixvl9TBYt f1pYLFqOtrNYrD1yl91i0dYv7Bb/9+xgt/gz/QOLRe/hWovNm6YyO4h4vNn0nd1j56y77B4L NpV6bFrVyeZx59oeNo93586xezy5Mp3JY/OSeo+N73YweSxq+Mjm0bdlFaPH501yATxRXDYp qTmZZalF+nYJXBnf/v5hLvjJXnH5zX22BsajbF2MnBwSAiYSh853sncxcnEICexmlFg18y4z REJS4vPFdUwQtrDEyn/PoYqamSR2ti1jB0mwCWhJNH7tYgZJiAi8YpI4vGcGmMMscIFR4tbB bqAqDg5hAXeJI4eVQBpYBFQl7rXuBdvAK2ApsbHlFdQZ8hKrNxwAi3MKWEm0tG4Cs4WAamb9 WsU4gZFvASPDKkbJ1ILi3PTcYsMCw7zUcr3ixNzi0rx0veT83E2M4MjR0tzBuH3VB71DjEwc jIcYJTiYlUR4hZ++SBbiTUmsrEotyo8vKs1JLT7EKM3BoiTOe6HrZLyQQHpiSWp2ampBahFM lomDU6qBSdeVaba53n97AYtUm+ls4vabpum/j7qfMnlZy91ZvvMnTFnyaFLaZ2eHRW9VXA/9 0tNrl1K+9GJW1WItsQ88LyTufY/RDNFT3zlXdGach/F6C77vuz037G3P5qp83nB7mYXGtA+t Wq/TeRZGp0/WcmowWvZBgFna1PpB/7/qVVKTn8Q0LzxwbfrVs+6P+m/O47Q16OOz0liY7r30 2YGjduahJjsYZS7Pj2w4l26/K6DDcs3i2lSx6B2vj+mdnlh2W/Ng/Zfr8z7UOX3LCpd549hq /c//UFXY8knnhJqaGapX3TqUW3o4ROyl+MneLTfSWh8d7f6xcMbkXXz7X2/o0Hv1O3BC0aea M6xPT7pN+q3EUpyRaKjFXFScCAAXo6RbCwMAAA== X-CMS-MailID: 20230214121428epcas5p3d91e877e62a78008d2b0d6066efea059 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121428epcas5p3d91e877e62a78008d2b0d6066efea059 References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org DT uses the name elbi in reg-names for application logic registers which is a wrong nomenclature. This patch fixes the same. This commit shouldn't be applied without changes "dt-bindings: PCI: Rename the term elbi to appl" and "PCI: samsung: Rename the term elbi to appl" Signed-off-by: Shradha Todi --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 5519a80576c5..96b216099594 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1944,7 +1944,7 @@ compatible = "samsung,exynos5433-pcie"; reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>; - reg-names = "dbi", "elbi", "config"; + reg-names = "dbi", "appl", "config"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; From patchwork Tue Feb 14 12:13:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140242 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E5F5C05027 for ; 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Tue, 14 Feb 2023 12:14:32 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20230214121432epsmtrp2aaeff2e6d8ba1fd91cf68af8eee5f102~Dr_Iy7bEK1888418884epsmtrp2h; Tue, 14 Feb 2023 12:14:32 +0000 (GMT) X-AuditID: b6c32a4b-20fff70000011a6d-fa-63eb96296114 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 4D.FA.17995.82B7BE36; Tue, 14 Feb 2023 21:14:32 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121429epsmtip1b719ca6d898005b96417aba8e73dc392~Dr_GIkwkM2553425534epsmtip1D; Tue, 14 Feb 2023 12:14:29 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 07/16] PCI: samsung: Rename the term elbi to appl Date: Tue, 14 Feb 2023 17:43:24 +0530 Message-Id: <20230214121333.1837-8-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMJsWRmVeSWpSXmKPExsWy7bCmpq7mtNfJBpPf81g8mLeNzWJJU4bF /CPnWC1mbZvLaPHx9zkWixVfZrJb9L14yGzR0POb1WLT42usFpd3zWGzODvvOJvFjPP7mCxa /rSwWLQcbWexWHvkLrvFoq1f2C3+79nBbvFn+gcWi97DtRabN01ldhDxeLPpO7vHzll32T0W bCr12LSqk83jzrU9bB7vzp1j93hyZTqTx+Yl9R4b3+1g8ljU8JHNo2/LKkaPz5vkAniism0y UhNTUosUUvOS81My89JtlbyD453jTc0MDHUNLS3MlRTyEnNTbZVcfAJ03TJzgN5UUihLzCkF CgUkFhcr6dvZFOWXlqQqZOQXl9gqpRak5BSYFOgVJ+YWl+al6+WlllgZGhgYmQIVJmRnTHq9 iLVguXXF1tlnmBoY9xp3MXJySAiYSMxZ0cHcxcjFISSwm1HibutMdgjnE6PEvllboTKfGSVO zHrGCNOyuW8qVNUuRon/DftZIJxWJoknc+ewgFSxCWhJNH7tAmsXEbjFJPHy80OwFmaBU4wS B17sZQepEhZwlNj76TwbiM0ioCox5e9+VhCbV8BSYt3ux1D75CVWbzjADGJzClhJtLRuApsq IXCHQ+La3TvMEEUuEtfev2SHsIUlXh3fAmVLSXx+t5cNwk6XWLl5BlR9jsS3zUuYIGx7iQNX QM7mALpOU2L9Ln2IsKzE1FPrwEqYBfgken8/gSrnldgxD8ZWlvjydw8LhC0pMe/YZVYI20Ni Zvd5aBj1Mkp8PfaaeQKj3CyEFQsYGVcxSqYWFOempxabFhjnpZbDIy45P3cTIzg1a3nvYHz0 4IPeIUYmDsZDjBIczEoivMJPXyQL8aYkVlalFuXHF5XmpBYfYjQFBuBEZinR5HxgdsgriTc0 sTQwMTMzM7E0NjNUEudVtz2ZLCSQnliSmp2aWpBaBNPHxMEp1cB0aM6tsshr7BxnHs3tMGCO Lar32/CLr/rh27/f1s2ZMm+FUZVl6JJzy0xas1uO3D3zIHlrQdoVj6jlnEVbqtj3G4lMsMjj cHsRdCCA4013pOv0212JEX///FxWmhHtLuJz8ORWHhOrf6fi+603d1ZHLvig6LQ3uqt86aZd qq4SOeWc6S1TRJV0Ine1pataSfUoVV6om3mh5vA1PxeOj5k57zlTX3x4fCBP6GtzGUOfcsKf Fpsr3x502002kpOcY50ldiE68nkhs/bZu/+5tp7dnPb+zpM1PIqSoZu6rz/5uIP7Q5sZb42C ueSj3b92ei624t1mImPhZalltmdmlZxvjzu/xywH676QY009m5RYijMSDbWYi4oTARGVKHxW BAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsWy7bCSnK5G9etkg9NTBS0ezNvGZrGkKcNi /pFzrBazts1ltPj4+xyLxYovM9kt+l48ZLZo6PnNarHp8TVWi8u75rBZnJ13nM1ixvl9TBYt f1pYLFqOtrNYrD1yl91i0dYv7Bb/9+xgt/gz/QOLRe/hWovNm6YyO4h4vNn0nd1j56y77B4L NpV6bFrVyeZx59oeNo93586xezy5Mp3JY/OSeo+N73YweSxq+Mjm0bdlFaPH501yATxRXDYp qTmZZalF+nYJXBmTXi9iLVhuXbF19hmmBsa9xl2MnBwSAiYSm/umsncxcnEICexglJjYcIYV IiEp8fniOiYIW1hi5b/n7CC2kEAzk8SyM7UgNpuAlkTj1y5mkGYRgVdMEof3zABzmAUuMErc OtgN1iEs4Cix99N5NhCbRUBVYsrf/WAbeAUsJdbtfswIsUFeYvWGA8wgNqeAlURL6yZmiG2W ErN+rWKcwMi3gJFhFaNkakFxbnpusWGBUV5quV5xYm5xaV66XnJ+7iZGcORoae1g3LPqg94h RiYOxkOMEhzMSiK8wk9fJAvxpiRWVqUW5ccXleakFh9ilOZgURLnvdB1Ml5IID2xJDU7NbUg tQgmy8TBKdXAxHht/wWJ1fuuKN98u/bG7rrqyr2/vr340nB9/oGm/1fit9SlLgpXU2CZ66l2 cueE8CCt9Sy6ks9YqkRZdmf0frV7MyHz7+7YdqePEx0Dbu428d33YeWdByf2Cs2ebG0Wb+g/ WUrM+GaXSOeTQun0494XWcze/Q1cGD31lubTxwcVM7e+OT/1plWN+PqzP25v0W45+HDJqc3n 77vFXTz+aaWI7DHJ26e03f6GHJtV1RJbJSszS+iE2/93bofnP7vy9MilnVzNHFXpB7WXix/s q78XKv8tPP3xMaGGPHuO9ryJymvk3n8XvhYTkrexJPPcT50PJjrSTAavru6NqT98wY29/fuH sGmdH1e03C5zOmGpxFKckWioxVxUnAgAhP21vAsDAAA= X-CMS-MailID: 20230214121432epcas5p27248b4dafdec64b0172c69f7909d7a64 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121432epcas5p27248b4dafdec64b0172c69f7909d7a64 References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The driver uses the name elbi for application logic registers which is a wrong nomenclature. This patch fixes the same. This commit shouldn't be applied without changes "arm64: dts: exynos: Rename the term elbi to appl" and "dt-bindings: PCI: Rename the term elbi to appl" Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-samsung.c | 80 ++++++++++++------------ 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c index 6c07d3f151be..d5adf1017a05 100644 --- a/drivers/pci/controller/dwc/pci-samsung.c +++ b/drivers/pci/controller/dwc/pci-samsung.c @@ -25,7 +25,7 @@ #define to_exynos_pcie(x) dev_get_drvdata((x)->dev) -/* PCIe ELBI registers */ +/* PCIe APPL registers */ #define EXYNOS_PCIE_IRQ_PULSE 0x000 #define EXYNOS_IRQ_INTA_ASSERT BIT(0) #define EXYNOS_IRQ_INTB_ASSERT BIT(2) @@ -44,16 +44,16 @@ #define EXYNOS_PCIE_NONSTICKY_RESET 0x024 #define EXYNOS_PCIE_APP_INIT_RESET 0x028 #define EXYNOS_PCIE_APP_LTSSM_ENABLE 0x02c -#define EXYNOS_PCIE_ELBI_RDLH_LINKUP 0x074 -#define EXYNOS_PCIE_ELBI_XMLH_LINKUP BIT(4) -#define EXYNOS_PCIE_ELBI_LTSSM_ENABLE 0x1 -#define EXYNOS_PCIE_ELBI_SLV_AWMISC 0x11c -#define EXYNOS_PCIE_ELBI_SLV_ARMISC 0x120 -#define EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE BIT(21) +#define EXYNOS_PCIE_APPL_RDLH_LINKUP 0x074 +#define EXYNOS_PCIE_APPL_XMLH_LINKUP BIT(4) +#define EXYNOS_PCIE_APPL_LTSSM_ENABLE 0x1 +#define EXYNOS_PCIE_APPL_SLV_AWMISC 0x11c +#define EXYNOS_PCIE_APPL_SLV_ARMISC 0x120 +#define EXYNOS_PCIE_APPL_SLV_DBI_ENABLE BIT(21) struct exynos_pcie { struct dw_pcie pci; - void __iomem *elbi_base; + void __iomem *appl_base; struct clk_bulk_data *clks; int clk_cnt; struct phy *phy; @@ -93,49 +93,49 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on) { u32 val; - val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_AWMISC); + val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_APPL_SLV_AWMISC); if (on) - val |= EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + val |= EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; else - val &= ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_AWMISC); + val &= ~EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_APPL_SLV_AWMISC); } static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on) { u32 val; - val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_SLV_ARMISC); + val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_APPL_SLV_ARMISC); if (on) - val |= EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; + val |= EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; else - val &= ~EXYNOS_PCIE_ELBI_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_ELBI_SLV_ARMISC); + val &= ~EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; + exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_APPL_SLV_ARMISC); } static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) { u32 val; - val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_CORE_RESET); val &= ~EXYNOS_PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_NONSTICKY_RESET); + exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_NONSTICKY_RESET); } static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) { u32 val; - val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_CORE_RESET); + val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_CORE_RESET); val |= EXYNOS_PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_CORE_RESET); - exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_STICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_NONSTICKY_RESET); - exynos_pcie_writel(ep->elbi_base, 1, EXYNOS_PCIE_APP_INIT_RESET); - exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(ep->appl_base, 1, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(ep->appl_base, 1, EXYNOS_PCIE_NONSTICKY_RESET); + exynos_pcie_writel(ep->appl_base, 1, EXYNOS_PCIE_APP_INIT_RESET); + exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_APP_INIT_RESET); } static int exynos_pcie_start_link(struct dw_pcie *pci) @@ -143,21 +143,21 @@ static int exynos_pcie_start_link(struct dw_pcie *pci) struct exynos_pcie *ep = to_exynos_pcie(pci); u32 val; - val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_SW_WAKE); + val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_SW_WAKE); val &= ~EXYNOS_PCIE_BUS_EN; - exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_SW_WAKE); + exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_SW_WAKE); /* assert LTSSM enable */ - exynos_pcie_writel(ep->elbi_base, EXYNOS_PCIE_ELBI_LTSSM_ENABLE, + exynos_pcie_writel(ep->appl_base, EXYNOS_PCIE_APPL_LTSSM_ENABLE, EXYNOS_PCIE_APP_LTSSM_ENABLE); return 0; } static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) { - u32 val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_IRQ_PULSE); + u32 val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_IRQ_PULSE); - exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_PULSE); + exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_IRQ_PULSE); } static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) @@ -173,9 +173,9 @@ static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) u32 val = EXYNOS_IRQ_INTA_ASSERT | EXYNOS_IRQ_INTB_ASSERT | EXYNOS_IRQ_INTC_ASSERT | EXYNOS_IRQ_INTD_ASSERT; - exynos_pcie_writel(ep->elbi_base, val, EXYNOS_PCIE_IRQ_EN_PULSE); - exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); - exynos_pcie_writel(ep->elbi_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); + exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_IRQ_EN_PULSE); + exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); + exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); } static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, @@ -232,9 +232,9 @@ static struct pci_ops exynos_pci_ops = { static int exynos_pcie_link_up(struct dw_pcie *pci) { struct exynos_pcie *ep = to_exynos_pcie(pci); - u32 val = exynos_pcie_readl(ep->elbi_base, EXYNOS_PCIE_ELBI_RDLH_LINKUP); + u32 val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_APPL_RDLH_LINKUP); - return (val & EXYNOS_PCIE_ELBI_XMLH_LINKUP); + return (val & EXYNOS_PCIE_APPL_XMLH_LINKUP); } static int exynos_pcie_host_init(struct dw_pcie_rp *pp) @@ -315,10 +315,10 @@ static int exynos_pcie_probe(struct platform_device *pdev) if (IS_ERR(ep->phy)) return PTR_ERR(ep->phy); - /* External Local Bus interface (ELBI) registers */ - ep->elbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi"); - if (IS_ERR(ep->elbi_base)) - return PTR_ERR(ep->elbi_base); + /* Application logic registers */ + ep->appl_base = devm_platform_ioremap_resource_byname(pdev, "appl"); + if (IS_ERR(ep->appl_base)) + return PTR_ERR(ep->appl_base); ret = exynos_pcie_init_clk_resources(ep); if (ret < 0) From patchwork Tue Feb 14 12:13:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140275 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7520BC05027 for ; Tue, 14 Feb 2023 14:21:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229564AbjBNOVb (ORCPT ); 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Tue, 14 Feb 2023 12:14:36 +0000 (GMT) X-AuditID: b6c32a4b-46dfa70000011a6d-4d-63eb964f1ee7 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 5A.8E.05839.C2B7BE36; Tue, 14 Feb 2023 21:14:36 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121433epsmtip1a3fddefe573546349aa6f900e47fff4f~Dr_Jq6lkH2436024360epsmtip1m; Tue, 14 Feb 2023 12:14:33 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 08/16] PCI: samsung: Rename exynos_pcie to samsung_pcie Date: Tue, 14 Feb 2023 17:43:25 +0530 Message-Id: <20230214121333.1837-9-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VTfUxTVxTf7evHQ4G9AcYLyZC8ZU6aAK223aUDWTLiXgbbSDQuMxv1pX0D QmlrW3RuEAurMsmo+IkwqIQ1m7AhUDpE5KOCWMeEuYE4P3B8yVAIou0gWIQVWrb/fud3fuf+ zjn3XhwLsnPD8AyVntGqaCXJXcdu6orcEvXhmSm5IM8uQcPmJi6y5Kejc1f7OKisqQKgp+4+ NjrvKuUh0+QIhgzfuDnIOjbIQf0t5VzUa3Zw0dnf2lnIuGhkI2N3ARvVXh3ioaqfXTy03NrM Q4sls2xU1JWLGq2nsbdDqGnrPI+6VDbEoyqt2ZS15iiXuj/YyqVm+vp41PhACYtqtByiGmaa WVSV4SmXMtlqAOW0hqf478mMS2doBaONYFRytSJDlRZPJu2UvSMTSwTCKGEsepOMUNFZTDyZ mJwStSND6RmTjNhPK7M9VAqt05Ex2+O06mw9E5Gu1unjSUajUGpEmmgdnaXLVqVFqxi9VCgQ bBV7hHsz0wsu8zX5qs8dPQoDGP20EPjhkBBBm62FVwjW4UHEZQAvWixcb/AMQOu3JzjeYA5A 04051lpJfd0g25toA7Due7ev5DALdtyo462ouAQf5v1TiK0kQoi7LPjIObLqghE9ANon21ZV wcS78Ot6O2cFs4nX4cm8Xg+P4wFELDxuUXrtNsEf6+3YCvYjpNB42Lp6KCQGcOhwFfG8okR4 9PE8x4uD4WOHzceHwUfHjvhwGqxuPIt5sRLONVp88yRA+0A5e8UXIyJhXUuMl34Vnu65sCrB iEBY5B73yQNgs3kNvwZdL1rZXhwKzdf6fS1QcOHOHeDdShGA5qFedjEIL/vfohKAGhDKaHRZ aYxOrNmmYg78d2tydZYVrD5lflIzGB2eje4ELBx0AohjZEhA8MNJeVCAgj74BaNVy7TZSkbX CcSe/R3HwjbI1Z6/oNLLhKJYgUgikYhit0mE5MaAN+J/kQcRabSeyWQYDaNdq2PhfmEGFrdq +Pz77zEHzvyQJN1oqEW7t1SeanApRxTtL2o3AeNNjDW79In5ks5/FzlvLP4jdPmK7S16STRy K1IquF9+qME54ZzMR8dSd128ltuKby9zSHMPJvjrTXtHp45ML37l5iM/k5q348vul3IW/rQU yJKef/f8r3sfdD1L/lskdsrqQlPHE/y33qyOw3/avGdC5hZWapbtbdIhJ/nx9Xv221Ef5Twp urL86+8D7WMlgdP96n3zO5MnInpfSQ27ndtXbQt8uKE/8eWBjowc1W6zGD4pvZVT6oiSZXw2 lTS0Hm9ZGovprji3z8V/sHy32HRi/Sn9A1uHoeL6Qu2F8PjNIfu1MyRbl04L+ZhWR/8Lh3s+ jlMEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKLMWRmVeSWpSXmKPExsWy7bCSnK5O9etkg++fWSwezNvGZrGkKcNi /pFzrBazts1ltPj4+xyLxYovM9kt+l48ZLZo6PnNarHp8TVWi8u75rBZnJ13nM1ixvl9TBYt f1pYLFqOtrNYrD1yl91i0dYv7Bb/9+xgt/gz/QOLRe/hWovNm6YyO4h4vNn0nd1j56y77B4L NpV6bFrVyeZx59oeNo93586xezy5Mp3JY/OSeo+N73YweSxq+Mjm0bdlFaPH501yATxRXDYp qTmZZalF+nYJXBntu7UKmvIqjp9KaWB8FNvFyMkhIWAisWH9NZYuRi4OIYHdjBK3bh5hhEhI Sny+uI4JwhaWWPnvOTuILSTQzCRx+KEuiM0moCXR+LWLGaRZROAVUHzPDDCHWeAC0KSD3WAd wgLuEh0bDrCC2CwCqhKTG88CxTk4eAUsJSYuyYFYIC+xesMBZhCbU8BKoqV1EzPEMkuJWb9W MU5g5FvAyLCKUTK1oDg3PbfYsMAwL7Vcrzgxt7g0L10vOT93EyM4ZrQ0dzBuX/VB7xAjEwfj IUYJDmYlEV7hpy+ShXhTEiurUovy44tKc1KLDzFKc7AoifNe6DoZLySQnliSmp2aWpBaBJNl 4uCUamAq1jPdqbN0yrOnfO86nazZu6dm7WKMNw4SWjPLnn/GiTO87/liPXN/3JxrvWLBhkW2 C3Z+27mx/d/e1xNizZ8u92yfmLL5ScvteY1qD42XmzfvEw5w/XMpLtnUyG3PdfFT8y+JHD74 +4vdlDq+nbzXjp3zMHq3dZVpRtR/n9ylnx455ax4N+XP/6rbGk6Bb7892NmpwCfz/+AE30km odVfGg6VBBX15OslGx9YZ/t7yYen1q/OijxL8b6ULbGjU/fyGYnOFQcPKVpsjvNY29gdzpS1 SPJmwL/YZfcOnPmz2tpey1/XYLn7Hy5W1atXbjJwflvx/FSUtdqj7v4t4retWDc6Wpo4CF04 VxfN4XJHTomlOCPRUIu5qDgRAHhZzFAIAwAA X-CMS-MailID: 20230214121436epcas5p1641de02220bea5edb23bc875b6311270 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121436epcas5p1641de02220bea5edb23bc875b6311270 References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The platform specific structure being used is named exynos_pcie. Changing it to samsung_pcie for making it generic. Suggested-by: Pankaj Dubey Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-samsung.c | 190 +++++++++++------------ 1 file changed, 95 insertions(+), 95 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c index d5adf1017a05..be0177fcd763 100644 --- a/drivers/pci/controller/dwc/pci-samsung.c +++ b/drivers/pci/controller/dwc/pci-samsung.c @@ -23,7 +23,7 @@ #include "pcie-designware.h" -#define to_exynos_pcie(x) dev_get_drvdata((x)->dev) +#define to_samsung_pcie(x) dev_get_drvdata((x)->dev) /* PCIe APPL registers */ #define EXYNOS_PCIE_IRQ_PULSE 0x000 @@ -51,7 +51,7 @@ #define EXYNOS_PCIE_APPL_SLV_ARMISC 0x120 #define EXYNOS_PCIE_APPL_SLV_DBI_ENABLE BIT(21) -struct exynos_pcie { +struct samsung_pcie { struct dw_pcie pci; void __iomem *appl_base; struct clk_bulk_data *clks; @@ -60,23 +60,23 @@ struct exynos_pcie { struct regulator_bulk_data supplies[2]; }; -static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep) +static int exynos_pcie_init_clk_resources(struct samsung_pcie *sp) { - struct device *dev = ep->pci.dev; + struct device *dev = sp->pci.dev; int ret; - ret = devm_clk_bulk_get_all(dev, &ep->clks); + ret = devm_clk_bulk_get_all(dev, &sp->clks); if (ret < 0) return ret; - ep->clk_cnt = ret; + sp->clk_cnt = ret; - return clk_bulk_prepare_enable(ep->clk_cnt, ep->clks); + return clk_bulk_prepare_enable(sp->clk_cnt, sp->clks); } -static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep) +static void exynos_pcie_deinit_clk_resources(struct samsung_pcie *sp) { - clk_bulk_disable_unprepare(ep->clk_cnt, ep->clks); + clk_bulk_disable_unprepare(sp->clk_cnt, sp->clks); } static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) @@ -89,115 +89,115 @@ static u32 exynos_pcie_readl(void __iomem *base, u32 reg) return readl(base + reg); } -static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on) +static void exynos_pcie_sideband_dbi_w_mode(struct samsung_pcie *sp, bool on) { u32 val; - val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_APPL_SLV_AWMISC); + val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_SLV_AWMISC); if (on) val |= EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; else val &= ~EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_APPL_SLV_AWMISC); + exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_APPL_SLV_AWMISC); } -static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on) +static void exynos_pcie_sideband_dbi_r_mode(struct samsung_pcie *sp, bool on) { u32 val; - val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_APPL_SLV_ARMISC); + val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_SLV_ARMISC); if (on) val |= EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; else val &= ~EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; - exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_APPL_SLV_ARMISC); + exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_APPL_SLV_ARMISC); } -static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep) +static void exynos_pcie_assert_core_reset(struct samsung_pcie *sp) { u32 val; - val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_CORE_RESET); + val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_CORE_RESET); val &= ~EXYNOS_PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_CORE_RESET); - exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_STICKY_RESET); - exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_NONSTICKY_RESET); + exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_NONSTICKY_RESET); } -static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep) +static void exynos_pcie_deassert_core_reset(struct samsung_pcie *sp) { u32 val; - val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_CORE_RESET); + val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_CORE_RESET); val |= EXYNOS_PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_CORE_RESET); - exynos_pcie_writel(ep->appl_base, 1, EXYNOS_PCIE_STICKY_RESET); - exynos_pcie_writel(ep->appl_base, 1, EXYNOS_PCIE_NONSTICKY_RESET); - exynos_pcie_writel(ep->appl_base, 1, EXYNOS_PCIE_APP_INIT_RESET); - exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_APP_INIT_RESET); + exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_CORE_RESET); + exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_STICKY_RESET); + exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_NONSTICKY_RESET); + exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_APP_INIT_RESET); + exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_APP_INIT_RESET); } static int exynos_pcie_start_link(struct dw_pcie *pci) { - struct exynos_pcie *ep = to_exynos_pcie(pci); + struct samsung_pcie *sp = to_samsung_pcie(pci); u32 val; - val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_SW_WAKE); + val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_SW_WAKE); val &= ~EXYNOS_PCIE_BUS_EN; - exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_SW_WAKE); + exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_SW_WAKE); /* assert LTSSM enable */ - exynos_pcie_writel(ep->appl_base, EXYNOS_PCIE_APPL_LTSSM_ENABLE, + exynos_pcie_writel(sp->appl_base, EXYNOS_PCIE_APPL_LTSSM_ENABLE, EXYNOS_PCIE_APP_LTSSM_ENABLE); return 0; } -static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep) +static void exynos_pcie_clear_irq_pulse(struct samsung_pcie *sp) { - u32 val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_IRQ_PULSE); + u32 val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_IRQ_PULSE); - exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_IRQ_PULSE); + exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_IRQ_PULSE); } static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) { - struct exynos_pcie *ep = arg; + struct samsung_pcie *sp = arg; - exynos_pcie_clear_irq_pulse(ep); + exynos_pcie_clear_irq_pulse(sp); return IRQ_HANDLED; } -static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep) +static void exynos_pcie_enable_irq_pulse(struct samsung_pcie *sp) { u32 val = EXYNOS_IRQ_INTA_ASSERT | EXYNOS_IRQ_INTB_ASSERT | EXYNOS_IRQ_INTC_ASSERT | EXYNOS_IRQ_INTD_ASSERT; - exynos_pcie_writel(ep->appl_base, val, EXYNOS_PCIE_IRQ_EN_PULSE); - exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); - exynos_pcie_writel(ep->appl_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); + exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_IRQ_EN_PULSE); + exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); + exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); } static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size) { - struct exynos_pcie *ep = to_exynos_pcie(pci); + struct samsung_pcie *sp = to_samsung_pcie(pci); u32 val; - exynos_pcie_sideband_dbi_r_mode(ep, true); + exynos_pcie_sideband_dbi_r_mode(sp, true); dw_pcie_read(base + reg, size, &val); - exynos_pcie_sideband_dbi_r_mode(ep, false); + exynos_pcie_sideband_dbi_r_mode(sp, false); return val; } static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size, u32 val) { - struct exynos_pcie *ep = to_exynos_pcie(pci); + struct samsung_pcie *sp = to_samsung_pcie(pci); - exynos_pcie_sideband_dbi_w_mode(ep, true); + exynos_pcie_sideband_dbi_w_mode(sp, true); dw_pcie_write(base + reg, size, val); - exynos_pcie_sideband_dbi_w_mode(ep, false); + exynos_pcie_sideband_dbi_w_mode(sp, false); } static int exynos_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, @@ -231,8 +231,8 @@ static struct pci_ops exynos_pci_ops = { static int exynos_pcie_link_up(struct dw_pcie *pci) { - struct exynos_pcie *ep = to_exynos_pcie(pci); - u32 val = exynos_pcie_readl(ep->appl_base, EXYNOS_PCIE_APPL_RDLH_LINKUP); + struct samsung_pcie *sp = to_samsung_pcie(pci); + u32 val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_RDLH_LINKUP); return (val & EXYNOS_PCIE_APPL_XMLH_LINKUP); } @@ -240,17 +240,17 @@ static int exynos_pcie_link_up(struct dw_pcie *pci) static int exynos_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct exynos_pcie *ep = to_exynos_pcie(pci); + struct samsung_pcie *sp = to_samsung_pcie(pci); pp->bridge->ops = &exynos_pci_ops; - exynos_pcie_assert_core_reset(ep); + exynos_pcie_assert_core_reset(sp); - phy_init(ep->phy); - phy_power_on(ep->phy); + phy_init(sp->phy); + phy_power_on(sp->phy); - exynos_pcie_deassert_core_reset(ep); - exynos_pcie_enable_irq_pulse(ep); + exynos_pcie_deassert_core_reset(sp); + exynos_pcie_enable_irq_pulse(sp); return 0; } @@ -259,10 +259,10 @@ static const struct dw_pcie_host_ops exynos_pcie_host_ops = { .host_init = exynos_pcie_host_init, }; -static int exynos_add_pcie_port(struct exynos_pcie *ep, +static int exynos_add_pcie_port(struct samsung_pcie *sp, struct platform_device *pdev) { - struct dw_pcie *pci = &ep->pci; + struct dw_pcie *pci = &sp->pci; struct dw_pcie_rp *pp = &pci->pp; struct device *dev = &pdev->dev; int ret; @@ -272,7 +272,7 @@ static int exynos_add_pcie_port(struct exynos_pcie *ep, return pp->irq; ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler, - IRQF_SHARED, "exynos-pcie", ep); + IRQF_SHARED, "exynos-pcie", sp); if (ret) { dev_err(dev, "failed to request irq\n"); return ret; @@ -300,95 +300,95 @@ static const struct dw_pcie_ops dw_pcie_ops = { static int exynos_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct exynos_pcie *ep; + struct samsung_pcie *sp; struct device_node *np = dev->of_node; int ret; - ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); - if (!ep) + sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); + if (!sp) return -ENOMEM; - ep->pci.dev = dev; - ep->pci.ops = &dw_pcie_ops; + sp->pci.dev = dev; + sp->pci.ops = &dw_pcie_ops; - ep->phy = devm_of_phy_get(dev, np, NULL); - if (IS_ERR(ep->phy)) - return PTR_ERR(ep->phy); + sp->phy = devm_of_phy_get(dev, np, NULL); + if (IS_ERR(sp->phy)) + return PTR_ERR(sp->phy); /* Application logic registers */ - ep->appl_base = devm_platform_ioremap_resource_byname(pdev, "appl"); - if (IS_ERR(ep->appl_base)) - return PTR_ERR(ep->appl_base); + sp->appl_base = devm_platform_ioremap_resource_byname(pdev, "appl"); + if (IS_ERR(sp->appl_base)) + return PTR_ERR(sp->appl_base); - ret = exynos_pcie_init_clk_resources(ep); + ret = exynos_pcie_init_clk_resources(sp); if (ret < 0) return ret; - ep->supplies[0].supply = "vdd18"; - ep->supplies[1].supply = "vdd10"; - ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ep->supplies), - ep->supplies); + sp->supplies[0].supply = "vdd18"; + sp->supplies[1].supply = "vdd10"; + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(sp->supplies), + sp->supplies); if (ret) return ret; - ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); + ret = regulator_bulk_enable(ARRAY_SIZE(sp->supplies), sp->supplies); if (ret) return ret; - platform_set_drvdata(pdev, ep); + platform_set_drvdata(pdev, sp); - ret = exynos_add_pcie_port(ep, pdev); + ret = exynos_add_pcie_port(sp, pdev); if (ret < 0) goto fail_probe; return 0; fail_probe: - phy_exit(ep->phy); - regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); - exynos_pcie_deinit_clk_resources(ep); + phy_exit(sp->phy); + regulator_bulk_disable(ARRAY_SIZE(sp->supplies), sp->supplies); + exynos_pcie_deinit_clk_resources(sp); return ret; } static int __exit exynos_pcie_remove(struct platform_device *pdev) { - struct exynos_pcie *ep = platform_get_drvdata(pdev); + struct samsung_pcie *sp = platform_get_drvdata(pdev); - dw_pcie_host_deinit(&ep->pci.pp); - exynos_pcie_assert_core_reset(ep); - phy_power_off(ep->phy); - phy_exit(ep->phy); - exynos_pcie_deinit_clk_resources(ep); - regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); + dw_pcie_host_deinit(&sp->pci.pp); + exynos_pcie_assert_core_reset(sp); + phy_power_off(sp->phy); + phy_exit(sp->phy); + exynos_pcie_deinit_clk_resources(sp); + regulator_bulk_disable(ARRAY_SIZE(sp->supplies), sp->supplies); return 0; } static int exynos_pcie_suspend_noirq(struct device *dev) { - struct exynos_pcie *ep = dev_get_drvdata(dev); + struct samsung_pcie *sp = dev_get_drvdata(dev); - exynos_pcie_assert_core_reset(ep); - phy_power_off(ep->phy); - phy_exit(ep->phy); - regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies); + exynos_pcie_assert_core_reset(sp); + phy_power_off(sp->phy); + phy_exit(sp->phy); + regulator_bulk_disable(ARRAY_SIZE(sp->supplies), sp->supplies); return 0; } static int exynos_pcie_resume_noirq(struct device *dev) { - struct exynos_pcie *ep = dev_get_drvdata(dev); - struct dw_pcie *pci = &ep->pci; + struct samsung_pcie *sp = dev_get_drvdata(dev); + struct dw_pcie *pci = &sp->pci; struct dw_pcie_rp *pp = &pci->pp; int ret; - ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); + ret = regulator_bulk_enable(ARRAY_SIZE(sp->supplies), sp->supplies); if (ret) return ret; - /* exynos_pcie_host_init controls ep->phy */ + /* exynos_pcie_host_init controls sp->phy */ exynos_pcie_host_init(pp); dw_pcie_setup_rc(pp); exynos_pcie_start_link(pci); From patchwork Tue Feb 14 12:13:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140297 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 049F3C64ED6 for ; Tue, 14 Feb 2023 14:26:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232810AbjBNO0m (ORCPT ); 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Tue, 14 Feb 2023 12:14:40 +0000 (GMT) X-AuditID: b6c32a4b-46dfa70000011a6d-61-63eb96596475 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 10.0B.17995.F2B7BE36; Tue, 14 Feb 2023 21:14:39 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121437epsmtip1f825737ce144318188ec9e3afb312c2b~Dr_NKqQiS2493824938epsmtip1S; Tue, 14 Feb 2023 12:14:36 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 09/16] PCI: samsung: Make common appl readl/writel functions Date: Tue, 14 Feb 2023 17:43:26 +0530 Message-Id: <20230214121333.1837-10-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAJsWRmVeSWpSXmKPExsWy7bCmhm7ktNfJBiduqVg8mLeNzWJJU4bF /CPnWC1mbZvLaPHx9zkWixVfZrJb9L14yGzR0POb1WLT42usFpd3zWGzODvvOJvFjPP7mCxa /rSwWLQcbWexWHvkLrvFoq1f2C3+79nBbvFn+gcWi97DtRabN01ldhDxeLPpO7vHzll32T0W bCr12LSqk83jzrU9bB7vzp1j93hyZTqTx+Yl9R4b3+1g8ljU8JHNo2/LKkaPz5vkAniism0y UhNTUosUUvOS81My89JtlbyD453jTc0MDHUNLS3MlRTyEnNTbZVcfAJ03TJzgN5UUihLzCkF CgUkFhcr6dvZFOWXlqQqZOQXl9gqpRak5BSYFOgVJ+YWl+al6+WlllgZGhgYmQIVJmRnTFvR wFLwUrfiwoGIBsZv6l2MnBwSAiYSv35NYu9i5OIQEtjNKLHu0iFWkISQwCdGialf5SESnxkl 7q/8w9LFyAHW8eRdBkR8F1B82wdmCKeVSaJl/S1GkG42AS2Jxq9dYAkRgVtMEi8/PwTbwSxw ilHiwIu97CBVwgI+Ej+fXADrYBFQlei+sZkZxOYVsJLY0/OQGeJAeYnVGw6A2ZxA8ZbWTWBT JQRucEgcnrSEBaLIRaLnyFwoW1ji1fEt7BC2lMTL/jYoO11i5eYZUENzJL5tXsIEYdtLHLgy B+w3ZgFNifW79CHCshJTT60DK2EW4JPo/f0EqpxXYsc8GFtZ4svfPVBrJSXmHbvMCmF7SFz6 v4UREiy9jBITuv4wT2CUm4WwYgEj4ypGydSC4tz01GLTAuO81HJ4rCXn525iBCdlLe8djI8e fNA7xMjEwXiIUYKDWUmEV/jpi2Qh3pTEyqrUovz4otKc1OJDjKbAAJzILCWanA/MC3kl8YYm lgYmZmZmJpbGZoZK4rzqtieThQTSE0tSs1NTC1KLYPqYODilGpgm9KsEeZ/d+eVJ50/zzH6H c79jX/w1Ko86Z9IgaR/VxP3E+ZVL/Lzn1+IU/+m7G2RMZ2B588Gw75hzxBNVe8vPcuLb1l0z sw+Lzzh6NnbPtaNZpVM2eP2SU1prb/nnQEPWlGMZa780z3q497+x88qqt6v8vvTycP4PT73K 22kS+OVKSdmrVWwyjk+dJka5aonEb/3hKDdhVUDA79dLzitJ54mf8TEJ/vHEe58b61KFYgOV ywl33v+4EXX9dJnOo802ipKiMtcONE18xS+d9/f9R27/qbfbw3t7V9TGfc/3eqXBsnZxfCaH sL9y+bGid7JTqsXuzxZ91mhvPfmb+r/fi2aHut++eEhdMsH5fJ0SS3FGoqEWc1FxIgBX67SJ UwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOLMWRmVeSWpSXmKPExsWy7bCSnK5+9etkg5d/bCwezNvGZrGkKcNi /pFzrBazts1ltPj4+xyLxYovM9kt+l48ZLZo6PnNarHp8TVWi8u75rBZnJ13nM1ixvl9TBYt f1pYLFqOtrNYrD1yl91i0dYv7Bb/9+xgt/gz/QOLRe/hWovNm6YyO4h4vNn0nd1j56y77B4L NpV6bFrVyeZx59oeNo93586xezy5Mp3JY/OSeo+N73YweSxq+Mjm0bdlFaPH501yATxRXDYp qTmZZalF+nYJXBnTVjSwFLzUrbhwIKKB8Zt6FyMHh4SAicSTdxldjFwcQgI7GCW+vr7A2MXI CRSXlPh8cR0ThC0ssfLfc3aIomYmib5T91hBEmwCWhKNX7uYQRIiAq+YJA7vmQHmMAtcYJS4 dbCbHaRKWMBH4ucTiLEsAqoS3Tc2M4PYvAJWEnt6HjJDrJCXWL3hAJjNCRRvad0EZgsJWErM +rWKcQIj3wJGhlWMkqkFxbnpucWGBUZ5qeV6xYm5xaV56XrJ+bmbGMFxo6W1g3HPqg96hxiZ OBgPMUpwMCuJ8Ao/fZEsxJuSWFmVWpQfX1Sak1p8iFGag0VJnPdC18l4IYH0xJLU7NTUgtQi mCwTB6dUA5OJtb7Ysjm/zzTo+u8Xed9g++L+z4nbi3buKT/4Ibts+/tAtiKGf6zb9yqE/H0l HKNjsMGH9abR3CW8VwW/dl0pnJbsuvzpp4XRHIWrtuueXCTdtGTyovNrWdnqY3VVTzO5blR7 tOq1fnFFvEJcMGcP18XNfgfs00/KWGTXNbMcijzbdXDLz+P6N3/0HdIuiYn8fZPlVXtM6eTy 6+mi9Yt+5K2q/VizrUNnrqUoY8amhby3LH30Jp6SeCXTyPm/28z4cvnFcuPjG+/dfmeel1zQ yeXHHmjGUM3qvP/p3TyRHcuCfnHYhYkGPfWYpcF0+o3y7jUyht7/HyZPzUiYcnb2m8f5SR2T Dpkqfk3Xl1ViKc5INNRiLipOBACL4r2/CgMAAA== X-CMS-MailID: 20230214121440epcas5p46db82a141c3e2664cff4b290b49c3938 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121440epcas5p46db82a141c3e2664cff4b290b49c3938 References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Common application logic register read and write functions used for better readability. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-samsung.c | 54 ++++++++++++------------ 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c index be0177fcd763..e6e2a8ab4403 100644 --- a/drivers/pci/controller/dwc/pci-samsung.c +++ b/drivers/pci/controller/dwc/pci-samsung.c @@ -79,63 +79,63 @@ static void exynos_pcie_deinit_clk_resources(struct samsung_pcie *sp) clk_bulk_disable_unprepare(sp->clk_cnt, sp->clks); } -static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) +static void samsung_pcie_appl_writel(struct samsung_pcie *sp, u32 val, u32 reg) { - writel(val, base + reg); + writel(val, sp->appl_base + reg); } -static u32 exynos_pcie_readl(void __iomem *base, u32 reg) +static unsigned int samsung_pcie_appl_readl(struct samsung_pcie *sp, u32 reg) { - return readl(base + reg); + return readl(sp->appl_base + reg); } static void exynos_pcie_sideband_dbi_w_mode(struct samsung_pcie *sp, bool on) { u32 val; - val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_SLV_AWMISC); + val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_APPL_SLV_AWMISC); if (on) val |= EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; else val &= ~EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_APPL_SLV_AWMISC); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_APPL_SLV_AWMISC); } static void exynos_pcie_sideband_dbi_r_mode(struct samsung_pcie *sp, bool on) { u32 val; - val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_SLV_ARMISC); + val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_APPL_SLV_ARMISC); if (on) val |= EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; else val &= ~EXYNOS_PCIE_APPL_SLV_DBI_ENABLE; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_APPL_SLV_ARMISC); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_APPL_SLV_ARMISC); } static void exynos_pcie_assert_core_reset(struct samsung_pcie *sp) { u32 val; - val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_CORE_RESET); + val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_CORE_RESET); val &= ~EXYNOS_PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_CORE_RESET); - exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_STICKY_RESET); - exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_NONSTICKY_RESET); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_CORE_RESET); + samsung_pcie_appl_writel(sp, 0, EXYNOS_PCIE_STICKY_RESET); + samsung_pcie_appl_writel(sp, 0, EXYNOS_PCIE_NONSTICKY_RESET); } static void exynos_pcie_deassert_core_reset(struct samsung_pcie *sp) { u32 val; - val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_CORE_RESET); + val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_CORE_RESET); val |= EXYNOS_PCIE_CORE_RESET_ENABLE; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_CORE_RESET); - exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_STICKY_RESET); - exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_NONSTICKY_RESET); - exynos_pcie_writel(sp->appl_base, 1, EXYNOS_PCIE_APP_INIT_RESET); - exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_APP_INIT_RESET); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_CORE_RESET); + samsung_pcie_appl_writel(sp, 1, EXYNOS_PCIE_STICKY_RESET); + samsung_pcie_appl_writel(sp, 1, EXYNOS_PCIE_NONSTICKY_RESET); + samsung_pcie_appl_writel(sp, 1, EXYNOS_PCIE_APP_INIT_RESET); + samsung_pcie_appl_writel(sp, 0, EXYNOS_PCIE_APP_INIT_RESET); } static int exynos_pcie_start_link(struct dw_pcie *pci) @@ -143,21 +143,21 @@ static int exynos_pcie_start_link(struct dw_pcie *pci) struct samsung_pcie *sp = to_samsung_pcie(pci); u32 val; - val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_SW_WAKE); + val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_SW_WAKE); val &= ~EXYNOS_PCIE_BUS_EN; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_SW_WAKE); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_SW_WAKE); /* assert LTSSM enable */ - exynos_pcie_writel(sp->appl_base, EXYNOS_PCIE_APPL_LTSSM_ENABLE, + samsung_pcie_appl_writel(sp, EXYNOS_PCIE_APPL_LTSSM_ENABLE, EXYNOS_PCIE_APP_LTSSM_ENABLE); return 0; } static void exynos_pcie_clear_irq_pulse(struct samsung_pcie *sp) { - u32 val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_IRQ_PULSE); + u32 val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_IRQ_PULSE); - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_IRQ_PULSE); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_IRQ_PULSE); } static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) @@ -173,9 +173,9 @@ static void exynos_pcie_enable_irq_pulse(struct samsung_pcie *sp) u32 val = EXYNOS_IRQ_INTA_ASSERT | EXYNOS_IRQ_INTB_ASSERT | EXYNOS_IRQ_INTC_ASSERT | EXYNOS_IRQ_INTD_ASSERT; - exynos_pcie_writel(sp->appl_base, val, EXYNOS_PCIE_IRQ_EN_PULSE); - exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); - exynos_pcie_writel(sp->appl_base, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); + samsung_pcie_appl_writel(sp, val, EXYNOS_PCIE_IRQ_EN_PULSE); + samsung_pcie_appl_writel(sp, 0, EXYNOS_PCIE_IRQ_EN_LEVEL); + samsung_pcie_appl_writel(sp, 0, EXYNOS_PCIE_IRQ_EN_SPECIAL); } static u32 exynos_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, @@ -232,7 +232,7 @@ static struct pci_ops exynos_pci_ops = { static int exynos_pcie_link_up(struct dw_pcie *pci) { struct samsung_pcie *sp = to_samsung_pcie(pci); - u32 val = exynos_pcie_readl(sp->appl_base, EXYNOS_PCIE_APPL_RDLH_LINKUP); + u32 val = samsung_pcie_appl_readl(sp, EXYNOS_PCIE_APPL_RDLH_LINKUP); return (val & EXYNOS_PCIE_APPL_XMLH_LINKUP); } From patchwork Tue Feb 14 12:13:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140278 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F348BC6379F for ; Tue, 14 Feb 2023 14:22:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233371AbjBNOW2 (ORCPT ); Tue, 14 Feb 2023 09:22:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233412AbjBNOWS (ORCPT ); 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Tue, 14 Feb 2023 21:14:44 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121441epsmtip16a4cfe37f004dab5520b727e5563a714~Dr_Q3t0xU2493824938epsmtip1T; Tue, 14 Feb 2023 12:14:40 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 10/16] dt-bindings: PCI: Add phy-names as required property Date: Tue, 14 Feb 2023 17:43:27 +0530 Message-Id: <20230214121333.1837-11-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VTa0xbZRj26ynnHHCwY4HwrW6F1CkbGdBubT0Qihtu7OwWUSMxxARP2pO2 o7f0ArploTNlaqUgsgnUjSEXdZCpazcsCKMBxrIpsAVCEMeEUQ1sE0FuysVZ2qL/nvd9n+e9 fh+OcLpQLq7SmhiDllbz0TB2c9fOHYnyTx/JBGW/88ix6maUrH9PSV7s7gshHc0XADm70scm v5qvwsiSyXGEtBSvhJDOiaEQcqD1PEr2Vt9Eycr+6yzSumplk9Yb77PJy92jGFl7bR4jn7S5 MXK1YoZN2rtOkS7nOWRvFPXYuYRRLY5RjKpxmiln44codW+oDaWm+/owyjtYwaJc9YXUlWk3 i6q1zKJUydVGQM05eVmbcvLSlAwtZwxxjFamk6u0Cin/yOu5L+eKJQJhojCFfJEfp6U1jJS/ /2hWYqZK7RuTH5dPq80+VxZtNPKT09MMOrOJiVPqjCYpn9HL1XqRPslIa4xmrSJJy5hShQLB brGP+HaessZ7H9MvY++UDVuABVxBbSAUh4QIuhxrmA2E4RziewAr3DYQMP4E0PakPRhZBLBl cSFkQzJ890c0EGgH8M7fTayAUcSCxRN2sM5CiQR4esGGrAeiiBEWnJob9+dCiNsAeibXE4fi kcQRuFxa5VewiefhhNXrbyucSIXXZqxYoF4sbPrWg6zjUJ/fWuT0Z4XEMA4H3T8jAdJ+2N3Z wQ7gSPjw5tWgmAvnptuDsyrgJVdlkK+Gi656VgC/BD2D531a3NfdTvhNa3LAvQ2eu/21n4IQ EdC+4g3Sw6G7egM/B+fX2oJlt8DqnoHgjijoWb0c3KQdQMfSGvIx4Dn+L1EDQCPYwuiNGgVj FOuFWqbgv8PJdBon8L/mhENuMDo2k9QJWDjoBBBH+FHhkb9OyjjhcvrdE4xBl2swqxljJxD7 FliGcKNlOt930JpyhaIUgUgikYhS9kiE/JjweOktGYdQ0CYmj2H0jGFDx8JDuRZW1d58h6T4 H2r7Baw8+hh7lrMtb3SsjieOO9jjkA8MYnN7cjIEq9OqzLdafjgY+oa09CwtKf+tJVpycsmg Of7FmWftHQ3zGcIzbdnyke96Y8o+T5B+6dn89HCMyxS/fA+vUDWkaDI3534UW2qeeu263cZb O/a47lbyRFiJNzW97KmLpwtOPjA92Lp8wI61p68M5f9StVtclMPpqO+J2vXwj7QdMcJ9KXeT txPd/dytsT+JRtUNdQXLr+y7JJLcz1itsUsrG57JfrU8+5PjIy9k3Ug8DEfOcmlGmRHxGRHx F9off7Q1/s6mhZrC3qLCzsJaS8YHB7yqR+Mn6k/1JOl5b+6aauKzjUpamIAYjPS/q5E0TlYE AAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRmVeSWpSXmKPExsWy7bCSnK5J9etkgzVNHBYP5m1js1jSlGEx /8g5VotZ2+YyWnz8fY7FYsWXmewWfS8eMls09Pxmtdj0+BqrxeVdc9gszs47zmYx4/w+JouW Py0sFi1H21ks1h65y26xaOsXdov/e3awW/yZ/oHFovdwrcXmTVOZHUQ83mz6zu6xc9Zddo8F m0o9Nq3qZPO4c20Pm8e7c+fYPZ5cmc7ksXlJvcfGdzuYPBY1fGTz6NuyitHj8ya5AJ4oLpuU 1JzMstQifbsErowFT+6xF/xir5h4o4GxgXEjWxcjJ4eEgInEjYtngGwuDiGB3YwSl+c0skAk JCU+X1zHBGELS6z895wdoqiZSaLt+ztmkASbgJZE49cuZpCEiMArJonDe2aAOcwCFxglbh3s ZgepEhbwlvjVP5MRxGYRUJV43PIEbDevgJXE1g8t7BAr5CVWbzgANpUTKN7SugnMFhKwlJj1 axXjBEa+BYwMqxglUwuKc9Nziw0LDPNSy/WKE3OLS/PS9ZLzczcxgmNHS3MH4/ZVH/QOMTJx MB5ilOBgVhLhFX76IlmINyWxsiq1KD++qDQntfgQozQHi5I474Wuk/FCAumJJanZqakFqUUw WSYOTqkGpmpHsYBHnEs28qwr/dwvLTRzrtsLMYUixoup3vGTrk9gvx0is/Nq4dNe2b8Tq6zM XRWXKsoeSTN7e+vykoDz4tY3GreI5m1rXPhmjfaC3vYDVzmueDhyTD8hfvlMr5SP12rW0h0W VV/MdeU+5vnmzJvn+U7mwtei7r3d2uGl9ttlOz2q5XZtv+fcpbnw/gPGL3Ov+R/24I6xFXV9 OP+yvszapf+YUrbc/SRacudewy3FhVM2sFY6Jr32bnF4orx/zgo1f+MlKx/zmsT8vzZd4vHd aT889sg67J11vpOPv6bI8PP290+nuz3L5IvjnXDVvu/ho+J75z+lLj6ze3fA9zn8Tt75Au/f fZ4Qw1e+REqJpTgj0VCLuag4EQA/2ovQDAMAAA== X-CMS-MailID: 20230214121444epcas5p16c5f7665fc9dee78cd427d976114e4f1 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121444epcas5p16c5f7665fc9dee78cd427d976114e4f1 References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org To replace devm_of_phy_get with devm_phy_get to get the PHY pointer using non DT version, we need to add phy-names property in DT and make it a required property with const value. Signed-off-by: Shradha Todi --- Documentation/devicetree/bindings/pci/samsung,pcie.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/samsung,pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,pcie.yaml index 9c58c4d1f6a7..11feff9d6526 100644 --- a/Documentation/devicetree/bindings/pci/samsung,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,pcie.yaml @@ -50,6 +50,10 @@ properties: phys: maxItems: 1 + phy-names: + items: + - const: pcie_phy + vdd10-supply: description: Phandle to a regulator that provides 1.0V power to the PCIe block. @@ -81,6 +85,7 @@ required: - clocks - clock-names - phys + - phy-names - vdd10-supply - vdd18-supply From patchwork Tue Feb 14 12:13:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140272 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D36AFC05027 for ; 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Signed-off-by: Shradha Todi --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 96b216099594..f50167923fd8 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1957,6 +1957,7 @@ num-viewport = <3>; bus-range = <0x00 0xff>; phys = <&pcie_phy>; + phy-names = "pcie_phy"; ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; status = "disabled"; From patchwork Tue Feb 14 12:13:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140277 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F441C61DA4 for ; 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Tue, 14 Feb 2023 12:14:51 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20230214121451epsmtrp1c9dcc1ace98f1c0abbdda39d4d22fc5c~Dr_a6oYg01843918439epsmtrp1Y; Tue, 14 Feb 2023 12:14:51 +0000 (GMT) X-AuditID: b6c32a49-e75fa70000012920-71-63eb969239f3 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 42.9E.05839.B3B7BE36; Tue, 14 Feb 2023 21:14:51 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121448epsmtip1e40e9843a96cbd637c69ac1b6b33fb8a~Dr_YP1vvE2380623806epsmtip1y; Tue, 14 Feb 2023 12:14:48 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 12/16] PCI: samsung: Get PHY using non-DT version Date: Tue, 14 Feb 2023 17:43:29 +0530 Message-Id: <20230214121333.1837-13-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrEJsWRmVeSWpSXmKPExsWy7bCmlu6kaa+TDWa94Ld4MG8bm8WSpgyL +UfOsVrM2jaX0eLj73MsFiu+zGS36HvxkNmioec3q8Wmx9dYLS7vmsNmcXbecTaLGef3MVm0 /GlhsWg52s5isfbIXXaLRVu/sFv837OD3eLP9A8sFr2Hay02b5rK7CDi8WbTd3aPnbPusnss 2FTqsWlVJ5vHnWt72DzenTvH7vHkynQmj81L6j02vtvB5LGo4SObR9+WVYwenzfJBfBEZdtk pCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam2iq5+AToumXmAL2ppFCWmFMK FApILC5W0rezKcovLUlVyMgvLrFVSi1IySkwKdArTswtLs1L18tLLbEyNDAwMgUqTMjO2PP9 J3PBL/aK89M/MDUw3mTrYuTkkBAwkdg76yZTFyMXh5DAbkaJ97Pes0E4nxgl+r48gXK+MUrM bT7ACNNy+cE0qMReRok5rz+wQjitTBJru8+BVbEJaEk0fu1iBkmICNxiknj5+SE7iMMscIpR 4sCLvewgVcICjhKPuq8ygdgsAqoS92bMAOvmFbCSePFnBTvEPnmJ1RsOMIPYnEDxltZNYFMl BK5wSKz6uYIVoshF4vOGbmYIW1ji1fEtUM1SEi/726DsdImVm2dA1eRIfNu8hAnCtpc4cGUO SxcjB9B1mhLrd+lDhGUlpp5aB1bCLMAn0fv7CVQ5r8SOeTC2ssSXv3tYIGxJiXnHLkOd4yHR vvs52C9CAr2MEv0z6yYwys1C2LCAkXEVo2RqQXFuemqxaYFhXmo5PN6S83M3MYITs5bnDsa7 Dz7oHWJk4mA8xCjBwawkwiv89EWyEG9KYmVValF+fFFpTmrxIUZTYPhNZJYSTc4H5oa8knhD E0sDEzMzMxNLYzNDJXFedduTyUIC6YklqdmpqQWpRTB9TBycUg1MORUp03gaf91rPHauJ0z+ W4rgRYGlTe02jbndm6KqDYL8fvRcZLnDvZtlim3M5Z2PWBN+XtIXkTCpSj/c1u6rPOWKxPOl 3FNmsr0umlCkYiynEDt7t+TK/RG+vmGHglfdiuOS6F3+zKWD7fe3Hwpy0sriwifXZCbO4Nwq IWGuvXftqrj3bkatU5SjYh+/VjvDd3XbnywnAU7rr6EP2aKX9ultE785L00pUe3V5K9Wmf53 3njxea7YlcRiL+tokLDqo+tKrpNH70dmHr2dFnezf+ucHdPTRfmM+lmM1r430P8UqaHyZ2fw ztD7T7ZtyHbbX2LnI/vB6unls+G/s+LnyPx51rjUtJwrkts9ZpUSS3FGoqEWc1FxIgDG2C4y VQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRmVeSWpSXmKPExsWy7bCSnK519etkgx1TtCwezNvGZrGkKcNi /pFzrBazts1ltPj4+xyLxYovM9kt+l48ZLZo6PnNarHp8TVWi8u75rBZnJ13nM1ixvl9TBYt f1pYLFqOtrNYrD1yl91i0dYv7Bb/9+xgt/gz/QOLRe/hWovNm6YyO4h4vNn0nd1j56y77B4L NpV6bFrVyeZx59oeNo93586xezy5Mp3JY/OSeo+N73YweSxq+Mjm0bdlFaPH501yATxRXDYp qTmZZalF+nYJXBl7vv9kLvjFXnF++gemBsabbF2MnBwSAiYSlx9MA7K5OIQEdjNKfJt8kAUi ISnx+eI6JghbWGLlv+fsEEXNTBKbn+9gBEmwCWhJNH7tYgZJiAi8YpI4vGcGmMMscIFR4tbB bnaQKmEBR4lH3VfBRrEIqErcmzEDrJtXwErixZ8V7BAr5CVWbzjADGJzAsVbWjeB2UIClhKz fq1inMDIt4CRYRWjZGpBcW56brFhgWFearlecWJucWleul5yfu4mRnDsaGnuYNy+6oPeIUYm DsZDjBIczEoivMJPXyQL8aYkVlalFuXHF5XmpBYfYpTmYFES573QdTJeSCA9sSQ1OzW1ILUI JsvEwSnVwNQpsXmt1c8bRct+ZZs6GjuyrHT57WlY/GnW6dfVF1+/rqyckZXH9WZnn5ipr9wl uUNXv3Rc8jMP/a372WZNSq6Yz9yUnkMBvM67fvb9sT8RaFAbUTpv22LdK40L954TNb/Glqcr fqufVWrfQqHjczVOVHnumf8vSv7kxifF9/nyLdhfnrLU2r7SpnT2wuAg6ZJQeW22fYayX9Ln TtWIm2b0W/xB+PWvG05uyaopPMDfyxP1fbLm1vqAeRr9kxL9H7XOqvbwzFp6UMSP0XmXQSwb 50JB5ZPy/t47DH3Z+d1Epi7c8Uih5YV95T7LRUpp/uz3k23tOrUbnY50nytglbC6fU9dUOCZ 2cGM2mYBJZbijERDLeai4kQAjgOM/AwDAAA= X-CMS-MailID: 20230214121451epcas5p148118502c76299b2a6f389881fa296cc X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121451epcas5p148118502c76299b2a6f389881fa296cc References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Replace devm_of_phy_get with devm_phy_get to get the PHY pointer. Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-samsung.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c index e6e2a8ab4403..719d284e1552 100644 --- a/drivers/pci/controller/dwc/pci-samsung.c +++ b/drivers/pci/controller/dwc/pci-samsung.c @@ -301,7 +301,6 @@ static int exynos_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct samsung_pcie *sp; - struct device_node *np = dev->of_node; int ret; sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL); @@ -311,7 +310,7 @@ static int exynos_pcie_probe(struct platform_device *pdev) sp->pci.dev = dev; sp->pci.ops = &dw_pcie_ops; - sp->phy = devm_of_phy_get(dev, np, NULL); + sp->phy = devm_phy_get(dev, "pcie_phy"); if (IS_ERR(sp->phy)) return PTR_ERR(sp->phy); From patchwork Tue Feb 14 12:13:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140257 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5599CC05027 for ; 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Tue, 14 Feb 2023 12:14:56 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20230214121456epsmtrp1fda2db0719d5e8d922c54d556495a537~Dr_e04eqs1788717887epsmtrp1Q; Tue, 14 Feb 2023 12:14:56 +0000 (GMT) X-AuditID: b6c32a4b-46dfa70000011a6d-f5-63eb96b4cc3b Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id E6.0B.17995.F3B7BE36; Tue, 14 Feb 2023 21:14:55 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121452epsmtip16085c3c7717daffba84e84cb8bf1ee37~Dr_bm37Mg2436024360epsmtip1q; Tue, 14 Feb 2023 12:14:52 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 13/16] PCI: samsung: Rename common functions to samsung Date: Tue, 14 Feb 2023 17:43:30 +0530 Message-Id: <20230214121333.1837-14-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VTbUxTVxje6b3tLcyyO8DtQCKD65CAAi2WcjDiZzeuccmaEPcDSdhduaGV 0ja97YYm22ABmXWgiyIfQlUkU1kEKVA7YICAoCxUExgkBBJRdMUtfJXh5COutGX79zzP+7wf 5z3nCLHAXkGoUK01sgYto6EE/ritNzoqtuXSn0rx+nwEemKxCVDddyp0pc/BR1W2GoAWVh04 urlUSaBS5xSG8n9Y5SPrs1E+Gm6rFqAhy4AAVTzq5KHCtUIcFd4vxtHtvkkC1bYuEehNh51A a+XzOCrp/Ro1W8uwA8H0X9ZXBP1L1SRBX7WaaGv9GQE9MdohoGcdDoKeHinn0c1139JNs3Ye XZu/IKBLW+oB7bKGKbak5+xVsUwWawhntUpdllqbnUIdTcs8nJkoE0tiJckoiQrXMrlsCiX/ RBH7sVrjPiYV/iWjMbklBcNxVPy+vQadyciGq3ScMYVi9VkavVQfxzG5nEmbHadljXskYnFC otv4eY7K9ngA07+m8vInS0A+mN5mBn5CSEphUbMLNwN/YSDZDmCX4zrmJYsAVk61+ogLwLN3 G8FmSp/tNd8baAPwWv8cz0uKeHB1zCzYcAnIGFjwt9mTHkyO8+CMa4rYIBg5CGC381diwxVE psKJ36yeujgZCa8POrENLCL3wMXx0zxvvw/gz3e6PbqfWy8ssnqqQnJECNsb5vlekxy+eDhP eHEQfDnQ4sOhcObcaR/OhreaKzAv1sDl5jpfg/2we6TavQOhe7po2NgW75W3wbLBBo8FIwNg yeq0zy6Cdssm3g6X1jtwLw6Blv5h3zg0bFwpILxrKQFwYeAecR6EVf3f4ioA9SCE1XO52SyX qN+tZb/67+KUulwr8LzmmKN28PTJfFwP4AlBD4BCjAoWBT13KgNFWczJU6xBl2kwaViuByS6 F/gjFrpVqXN/B60xUyJNFktlMpk0ebdMQr0vikp5qAwksxkjm8OyetawmccT+oXm87qqI3vU Ud1Nl+9e4V7eCI0eH8sgB6dvzpzImDsoquq03Hj7C1FZ0Cku4ZuPGsxdQ8sZkYro/sX2f05s DwmQHM+SG7Q10Xjq7Kv2x0StZvqPCwGHMna44o+tNRXfSkvfP7lz+P6Wd3b2K6Ic8SsKwLLl 4u/Ti7caHxz49Hj8EXuq7dkF2UTnGVPBQdGYfu5e2PNjBYnik/67iFHd5UXJ+YiEfbfPPvVz 7hCR3JAlr9h2eN28rFZePPLZhysSlV2u7nDyqYjhJFKqKql47y2b4nfXwrmEcmahaFfSu/LK pbyf7pgyiNaL15L5BW8OPWi1XMJlkS+CSv2SYmbgcs2jACaNwjkVI4nBDBzzL0QRPRZWBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJLMWRmVeSWpSXmKPExsWy7bCSnK599etkg2UvzS0ezNvGZrGkKcNi /pFzrBazts1ltPj4+xyLxYovM9kt+l48ZLZo6PnNarHp8TVWi8u75rBZnJ13nM1ixvl9TBYt f1pYLFqOtrNYrD1yl91i0dYv7Bb/9+xgt/gz/QOLRe/hWovNm6YyO4h4vNn0nd1j56y77B4L NpV6bFrVyeZx59oeNo93586xezy5Mp3JY/OSeo+N73YweSxq+Mjm0bdlFaPH501yATxRXDYp qTmZZalF+nYJXBnbLhxnLvipVNFwt5exgfGJbBcjJ4eEgInEkW0/WbsYuTiEBHYwSizYv4EN IiEp8fniOiYIW1hi5b/n7BBFzUwS5/+fAUuwCWhJNH7tYgZJiAi8YpI4vGcGmMMscIFR4tbB bnaQKmEBd4k7pzcxgtgsAqoSi0+9YAaxeQWsJD7daoNaIS+xesMBsDgnULyldROYLSRgKTHr 1yrGCYx8CxgZVjFKphYU56bnFhsWGOWllusVJ+YWl+al6yXn525iBMeOltYOxj2rPugdYmTi YDzEKMHBrCTCK/z0RbIQb0piZVVqUX58UWlOavEhRmkOFiVx3gtdJ+OFBNITS1KzU1MLUotg skwcnFINTOmxGU7e+vvvh0mZf8jQORV7S2zzqjz9LWq5UyfpcPprbVFcFnGdP+PLLpuadQkh LZMCrT+9nH4mc8213Ir7Zd33Zk3a3JO/+/Kd9pmb1vvUyf/gOTmJi6vVkis5VPfYTvufAfMO np2ceMyY98Ff2TnfhNla37EdYfi1spupU+VxmUFmfe+21kc35v480pRyaFOb8nI9cd5De4qP PnGQ+vJzvsPakLcHlRN1rvxWLcl0Xbfhvn31mosnzVX0T75t2H0rzGe6l4TBrbaQjVqyFdfr JsoKllzYErZDp8fyRuYtYYHzTVpKXI01WmG7Xtx7qyN68rGhmPqNCUz7W9nbHtUnaExcpb3q 7Aqu+SJP05RYijMSDbWYi4oTAcxvLLcMAwAA X-CMS-MailID: 20230214121456epcas5p36603c8d717588699d1b5575229d19114 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121456epcas5p36603c8d717588699d1b5575229d19114 References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use samsung instead of exynos for all common functions like probe/remove/suspend/resume. Suggested-by: Pankaj Dubey Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-samsung.c | 42 ++++++++++++------------ 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c index 719d284e1552..dc8ec0b546fd 100644 --- a/drivers/pci/controller/dwc/pci-samsung.c +++ b/drivers/pci/controller/dwc/pci-samsung.c @@ -60,7 +60,7 @@ struct samsung_pcie { struct regulator_bulk_data supplies[2]; }; -static int exynos_pcie_init_clk_resources(struct samsung_pcie *sp) +static int samsung_pcie_init_clk_resources(struct samsung_pcie *sp) { struct device *dev = sp->pci.dev; int ret; @@ -74,7 +74,7 @@ static int exynos_pcie_init_clk_resources(struct samsung_pcie *sp) return clk_bulk_prepare_enable(sp->clk_cnt, sp->clks); } -static void exynos_pcie_deinit_clk_resources(struct samsung_pcie *sp) +static void samsung_pcie_deinit_clk_resources(struct samsung_pcie *sp) { clk_bulk_disable_unprepare(sp->clk_cnt, sp->clks); } @@ -297,7 +297,7 @@ static const struct dw_pcie_ops dw_pcie_ops = { .start_link = exynos_pcie_start_link, }; -static int exynos_pcie_probe(struct platform_device *pdev) +static int samsung_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct samsung_pcie *sp; @@ -319,7 +319,7 @@ static int exynos_pcie_probe(struct platform_device *pdev) if (IS_ERR(sp->appl_base)) return PTR_ERR(sp->appl_base); - ret = exynos_pcie_init_clk_resources(sp); + ret = samsung_pcie_init_clk_resources(sp); if (ret < 0) return ret; @@ -345,12 +345,12 @@ static int exynos_pcie_probe(struct platform_device *pdev) fail_probe: phy_exit(sp->phy); regulator_bulk_disable(ARRAY_SIZE(sp->supplies), sp->supplies); - exynos_pcie_deinit_clk_resources(sp); + samsung_pcie_deinit_clk_resources(sp); return ret; } -static int __exit exynos_pcie_remove(struct platform_device *pdev) +static int __exit samsung_pcie_remove(struct platform_device *pdev) { struct samsung_pcie *sp = platform_get_drvdata(pdev); @@ -358,13 +358,13 @@ static int __exit exynos_pcie_remove(struct platform_device *pdev) exynos_pcie_assert_core_reset(sp); phy_power_off(sp->phy); phy_exit(sp->phy); - exynos_pcie_deinit_clk_resources(sp); + samsung_pcie_deinit_clk_resources(sp); regulator_bulk_disable(ARRAY_SIZE(sp->supplies), sp->supplies); return 0; } -static int exynos_pcie_suspend_noirq(struct device *dev) +static int samsung_pcie_suspend_noirq(struct device *dev) { struct samsung_pcie *sp = dev_get_drvdata(dev); @@ -376,7 +376,7 @@ static int exynos_pcie_suspend_noirq(struct device *dev) return 0; } -static int exynos_pcie_resume_noirq(struct device *dev) +static int samsung_pcie_resume_noirq(struct device *dev) { struct samsung_pcie *sp = dev_get_drvdata(dev); struct dw_pcie *pci = &sp->pci; @@ -394,25 +394,25 @@ static int exynos_pcie_resume_noirq(struct device *dev) return dw_pcie_wait_for_link(pci); } -static const struct dev_pm_ops exynos_pcie_pm_ops = { - NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos_pcie_suspend_noirq, - exynos_pcie_resume_noirq) +static const struct dev_pm_ops samsung_pcie_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(samsung_pcie_suspend_noirq, + samsung_pcie_resume_noirq) }; -static const struct of_device_id exynos_pcie_of_match[] = { +static const struct of_device_id samsung_pcie_of_match[] = { { .compatible = "samsung,exynos5433-pcie", }, { }, }; -static struct platform_driver exynos_pcie_driver = { - .probe = exynos_pcie_probe, - .remove = __exit_p(exynos_pcie_remove), +static struct platform_driver samsung_pcie_driver = { + .probe = samsung_pcie_probe, + .remove = __exit_p(samsung_pcie_remove), .driver = { - .name = "exynos-pcie", - .of_match_table = exynos_pcie_of_match, - .pm = &exynos_pcie_pm_ops, + .name = "samsung-pcie", + .of_match_table = samsung_pcie_of_match, + .pm = &samsung_pcie_pm_ops, }, }; -module_platform_driver(exynos_pcie_driver); +module_platform_driver(samsung_pcie_driver); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, exynos_pcie_of_match); +MODULE_DEVICE_TABLE(of, samsung_pcie_of_match); From patchwork Tue Feb 14 12:13:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140273 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DA89C64ED6 for ; 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Tue, 14 Feb 2023 12:15:03 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20230214121503epsmtrp2bfc29dd6e661af95921a823f554c978e~Dr_l-CZxx1888418884epsmtrp26; Tue, 14 Feb 2023 12:15:03 +0000 (GMT) X-AuditID: b6c32a49-e75fa70000012920-2d-63eb96f8983e Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 78.9E.05839.74B7BE36; Tue, 14 Feb 2023 21:15:03 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121500epsmtip106e59f353fd89b085fd5fb3806a8e2a2~Dr_jSVJzv2481024810epsmtip1a; Tue, 14 Feb 2023 12:15:00 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 15/16] PCI: samsung: Add structure to hold resource operations Date: Tue, 14 Feb 2023 17:43:32 +0530 Message-Id: <20230214121333.1837-16-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAJsWRmVeSWpSXmKPExsWy7bCmpu6Paa+TDXZM5rB4MG8bm8WSpgyL +UfOsVrM2jaX0eLj73MsFiu+zGS36HvxkNmioec3q8Wmx9dYLS7vmsNmcXbecTaLGef3MVm0 /GlhsWg52s5isfbIXXaLRVu/sFv837OD3eLP9A8sFr2Hay02b5rK7CDi8WbTd3aPnbPusnss 2FTqsWlVJ5vHnWt72DzenTvH7vHkynQmj81L6j02vtvB5LGo4SObR9+WVYwenzfJBfBEZdtk pCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam2iq5+AToumXmAL2ppFCWmFMK FApILC5W0rezKcovLUlVyMgvLrFVSi1IySkwKdArTswtLs1L18tLLbEyNDAwMgUqTMjOODBz KlPBF/GK2yv1GxgvCncxcnJICJhIPHiynrWLkYtDSGA3o8TshQ1MEM4nRom1e18zQjjfGCXu zG5khWlZd/80VNVeRolNV3YwQzitTBJv2iaAVbEJaEk0fu0CS4gI3GKSePn5ITuIwyxwilHi wIu97CBVwgIBEjP2TWABsVkEVCWen7/LBGLzClhJ7L63jh1in7zE6g0HmEFsTqB4S+smsKkS Alc4JO68ugLkcAA5LhLbDytC1AtLvDq+BapXSuLzu71sEHa6xMrNM5gh7ByJb5uXMEHY9hIH rsxhARnDLKApsX6XPkRYVmLqqXVgJcwCfBK9v59AlfNK7JgHYytLfPm7hwXClpSYd+wyK8Q1 HhILtulAAqWXUWL7sWesExjlZiFsWMDIuIpRMrWgODc9tdi0wDAvtRwea8n5uZsYwUlZy3MH 490HH/QOMTJxMB5ilOBgVhLhFX76IlmINyWxsiq1KD++qDQntfgQoykw+CYyS4km5wPzQl5J vKGJpYGJmZmZiaWxmaGSOK+67clkIYH0xJLU7NTUgtQimD4mDk6pBqbFC/exZZ+6/lDwU9wX zh2a7vOuH3vRpcvsbHdRQ+Aph94jr9IQx0Pz/aWMOAxZLnm+OPOkeKZKW0n6+c1XZ8s9zSr7 vtHnf3mK+NSkmXZqK+7cniEak5yQ+uNGQPMsfqXMuVOS3yyoOTmTU/VuxaIZ8wTV2VtUVxcX tUiI2vysOrtmzaLCVZfZTlQqbrlpvsI6uVE7bgWvzxsZntv+jyXP6Wa5u7fVHSptMvR6rXix 6HGZTbaS43muE6s+Bqxy+qRm+obnU1HPyp+9Tcqp70+oagY9TYpZum/GlNWCiRtr3Ofe+xB7 bMN8rqirJxbVS7y58Nho4mRdLWeuK7cXzuk82MVw8WSk3pX76zeef+OqxFKckWioxVxUnAgA YU0rXFMEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOLMWRmVeSWpSXmKPExsWy7bCSnK579etkg9XdihYP5m1js1jSlGEx /8g5VotZ2+YyWnz8fY7FYsWXmewWfS8eMls09Pxmtdj0+BqrxeVdc9gszs47zmYx4/w+JouW Py0sFi1H21ks1h65y26xaOsXdov/e3awW/yZ/oHFovdwrcXmTVOZHUQ83mz6zu6xc9Zddo8F m0o9Nq3qZPO4c20Pm8e7c+fYPZ5cmc7ksXlJvcfGdzuYPBY1fGTz6NuyitHj8ya5AJ4oLpuU 1JzMstQifbsErowDM6cyFXwRr7i9Ur+B8aJwFyMnh4SAicS6+6eZuhi5OIQEdjNKrD99mB0i ISnx+eI6JghbWGLlv+fsEEXNTBKvNi1mBEmwCWhJNH7tYgZJiAi8YpI4vGcGmMMscIFR4tbB bqAWDg5hAT+JF090QRpYBFQlnp+/CzaVV8BKYve9dVDb5CVWbzjADGJzAsVbWjeB2UIClhKz fq1inMDIt4CRYRWjZGpBcW56brFhgWFearlecWJucWleul5yfu4mRnDcaGnuYNy+6oPeIUYm DsZDjBIczEoivMJPXyQL8aYkVlalFuXHF5XmpBYfYpTmYFES573QdTJeSCA9sSQ1OzW1ILUI JsvEwSnVwMTwwiuVpUZRcf3yZ+JN87NCSkzWzeR7uPjn00/rHrhccdIotllW/1Sx5JvOjLaE //n6nsGcD+2vqSl5qgTe3bOx4Xh43a6F8w7VHmrefPSKbEHb6cbJFqbmK9svGn4VTa/2Lj2U 9kr6uJzk7hUJ09gz6zqanfOrt71n0zH81peQKn2wUYNZRZG7OcBhvvGUzAOv8oPum1d+lMzz jpry6I65RZF8391CgfSyKWpnN0eW2MrOduZft3PRvayS1Mk8i3pvvZfZMEv3yvzsgOs/fgpN eVp2+lcX4xN2DWGhnx9+frjK8UDolPQaXfunLbOmOP9dcS3TumfOvSt51ZJXMldHZFbc4Yur bdCZ4naWXYmlOCPRUIu5qDgRAOawcDAKAwAA X-CMS-MailID: 20230214121503epcas5p291dce2b37ec4cdabcfecbf8fbdfcca51 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121503epcas5p291dce2b37ec4cdabcfecbf8fbdfcca51 References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some resources might differ based on platforms and we need platform specific functions to initialize or alter them. For better code reusibility, making a separate res_ops which will hold all such function pointers or other resource specific data. This patch includes adding function pointer for IRQ initialization which will help to move common operations for host init into the probe sequence. Suggested-by: Pankaj Dubey Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-samsung.c | 26 ++++++++++++++++-------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c index 47ca2a6a545d..01882f2d06c7 100644 --- a/drivers/pci/controller/dwc/pci-samsung.c +++ b/drivers/pci/controller/dwc/pci-samsung.c @@ -55,6 +55,7 @@ struct samsung_pcie_pdata { struct pci_ops *pci_ops; const struct dw_pcie_ops *dwc_ops; const struct dw_pcie_host_ops *host_ops; + const struct samsung_res_ops *res_ops; }; /* @@ -77,6 +78,10 @@ struct samsung_pcie { struct regulator_bulk_data supplies[2]; }; +struct samsung_res_ops { + int (*irq_init)(struct samsung_pcie *sp, struct platform_device *pdev); +}; + static int samsung_pcie_init_clk_resources(struct samsung_pcie *sp) { struct device *dev = sp->pci.dev; @@ -276,7 +281,7 @@ static const struct dw_pcie_host_ops exynos_pcie_host_ops = { .host_init = exynos_pcie_host_init, }; -static int exynos_add_pcie_port(struct samsung_pcie *sp, +static int exynos_irq_init(struct samsung_pcie *sp, struct platform_device *pdev) { struct dw_pcie *pci = &sp->pci; @@ -295,15 +300,8 @@ static int exynos_add_pcie_port(struct samsung_pcie *sp, return ret; } - pp->ops = &exynos_pcie_host_ops; pp->msi_irq[0] = -ENODEV; - ret = dw_pcie_host_init(pp); - if (ret) { - dev_err(dev, "failed to initialize host\n"); - return ret; - } - return 0; } @@ -314,6 +312,10 @@ static const struct dw_pcie_ops exynos_dw_pcie_ops = { .start_link = exynos_pcie_start_link, }; +static const struct samsung_res_ops exynos_res_ops_data = { + .irq_init = exynos_irq_init, +}; + static int samsung_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -357,7 +359,12 @@ static int samsung_pcie_probe(struct platform_device *pdev) platform_set_drvdata(pdev, sp); - ret = exynos_add_pcie_port(sp, pdev); + if (pdata->res_ops->irq_init) + pdata->res_ops->irq_init(sp, pdev); + + sp->pci.pp.ops = pdata->host_ops; + + ret = dw_pcie_host_init(&sp->pci.pp); if (ret < 0) goto fail_probe; @@ -428,6 +435,7 @@ static const struct samsung_pcie_pdata exynos_5433_pcie_rc_pdata = { .dwc_ops = &exynos_dw_pcie_ops, .pci_ops = &exynos_pci_ops, .host_ops = &exynos_pcie_host_ops, + .res_ops = &exynos_res_ops_data, }; static const struct of_device_id samsung_pcie_of_match[] = { From patchwork Tue Feb 14 12:13:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shradha Todi X-Patchwork-Id: 13140279 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6387EC05027 for ; Tue, 14 Feb 2023 14:22:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231143AbjBNOWr (ORCPT ); Tue, 14 Feb 2023 09:22:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232771AbjBNOWY (ORCPT ); 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Tue, 14 Feb 2023 21:15:07 +0900 (KST) Received: from cheetah.sa.corp.samsungelectronics.net (unknown [107.109.115.53]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20230214121504epsmtip1bb62400f5fae28e9e805f82dd632a8ef~Dr_mvjZl72484124841epsmtip1V; Tue, 14 Feb 2023 12:15:04 +0000 (GMT) From: Shradha Todi To: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org, alim.akhtar@samsung.com, jingoohan1@gmail.com, Sergey.Semin@baikalelectronics.ru, lukas.bulwahn@gmail.com, hongxing.zhu@nxp.com, tglx@linutronix.de, m.szyprowski@samsung.com, jh80.chung@samsung.co, pankaj.dubey@samsung.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Shradha Todi Subject: [PATCH 16/16] PCI: samsung: Make handling of regulators generic Date: Tue, 14 Feb 2023 17:43:33 +0530 Message-Id: <20230214121333.1837-17-shradha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230214121333.1837-1-shradha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTf0wTZxjH896114OsywW67QUGNqcbQgK0QOvBYE7nzG3zD5I595PBpZyU UK61105cooIrIzBAWUb4IWOIzSgs/LBlhCIgAhVHZvkDx48NFaZmgBuxFCURZSs92P77Ps/z ed7nx/u+OBo0jIXiOZyJNXKMjsQCRd3DUbtjQPUDjcLdGkHNNXRjlPWMlvp+xC2m6rq/A5Rn 3S2ibKu1EqpiYR6lCsrWxZT97qSYmuitx6gbDaMYVTM+gFCWpxYRZXEVi6i2kVsSqumnVQn1 T1+PhHpa/VBElQ+fpBz2KvQNGf2XfU1CO+tuSehGu5m2t5Zg9OxkH0Yvu90S+t7NaoR2WE/T l5Z7ELqpwIPRFV2tgPbaI9Ke+zg3RcsyWaxRznIafVYOl51KvvtexpsZKrVCGaNMovaQco7J Y1PJA4fSYg7m6HxjkvLPGZ3Z50pjeJ6Mez3FqDebWLlWz5tSSdaQpTMkGmJ5Jo83c9mxHGtK VioU8SofmJmrXXz0LWLoi8y3jQ+hBeCqvBQE4JBIhFNXasSlIBAPIi4D6J0p3TJWADzfVYUI xmMAp6+fQbZTVi43i4RAP4DtHUsSwShC4MSGBWxSGBENCx+VopsBGfEbAhe9834KJcYAHFzo l2xSwQQN/3QW+jNExCvw178voptaSiTDot9HRUK9HfDHzkG/P8DntxTZ/adCYhqHzvUpIEAH YFPjGiroYLg02iURdCj0Lvdjgs6GLY6aLUYHHzusWwPthYM3633FcF93UbCjN05wh8OqsXY/ ghLPw/L1e1u4FPY0bOudcPVZ31afIbDh2oRY0DT0VJWgwlrKAVybuwbOgYi6/0s0AtAKQlgD n5fN8ipDPMce/+/iNPo8O/C/5uh3esD83MPYIYDgYAhAHCVl0uD7C5ogaRZz4gvWqM8wmnUs PwRUvgVWoqEvaPS+78CZMpSJSYpEtVqdmJSgVpIvSSNTf9YEEdmMic1lWQNr3M5D8IDQAoT8 NOCOFW1fTb6zPzdzp1XRVlER3rJyQnz0gIkPXC7OlwVaE2pk9PxibebYPufUjZHP4NGwFtY2 mdz8jW1X1bHK3pYxd+EwN3E27KMOc+DV20caap+EiXY/m83PW3+S3rpwNtXF5s8knHMXvZZs CLvgOnzofnNU84Zn/ynxUkj88dvSF2Vzr/7yVrEqIOZK5ctaUwq+UejkLuwKMv4xvvd85MXO 8KRO1ycpZcUfGlSUOt1RT5yeOXLpYNiefR9cD/EOeE3pypE2U/P7rsMlCZayFWfkg5P5Eeld A6eaIgbxWduKDRDyu19N4xlfH9vh6Xa9/YMDIys9zJfEZH3coCGeFPFaRhmNGnnmXyz/hfFW BAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsWy7bCSnK539etkg5+fBCwezNvGZrGkKcNi /pFzrBazts1ltPj4+xyLxYovM9kt+l48ZLZo6PnNarHp8TVWi8u75rBZnJ13nM1ixvl9TBYt f1pYLFqOtrNYrD1yl91i0dYv7Bb/9+xgt/gz/QOLRe/hWovNm6YyO4h4vNn0nd1j56y77B4L NpV6bFrVyeZx59oeNo93586xezy5Mp3JY/OSeo+N73YweSxq+Mjm0bdlFaPH501yATxRXDYp qTmZZalF+nYJXBkvv05hKtijXrHi/CHmBsaDCl2MnBwSAiYSn3YvZ+li5OIQEtjNKLFlw042 iISkxOeL65ggbGGJlf+es4PYQgLNTBLHrluB2GwCWhKNX7uYQZpFBF4xSRzeMwPMYRa4wChx 62A3WIewgIfE852NjCA2i4CqxNW3i5lBbF4BK4nW28dZIDbIS6zecAAszgkUb2ndxAyxzVJi 1q9VjBMY+RYwMqxilEwtKM5Nzy02LDDMSy3XK07MLS7NS9dLzs/dxAiOHC3NHYzbV33QO8TI xMF4iFGCg1lJhFf46YtkId6UxMqq1KL8+KLSnNTiQ4zSHCxK4rwXuk7GCwmkJ5akZqemFqQW wWSZODilGpiY9YRf268QehjiveeSz+udJ+V7TRcxbLRdtoZtX3/0ugP77vCXHs87xigg6/32 nj7LBO07gkbfCmXmslkev/VNxfXoDC/nHq87ehn6N2YKbtS4oBkeufTejYef7F3W+fy9w/0v dOKyZ0zSyV3KC8/bSG7Jnn2j9/1GVzN75oYnLP3XOCat4T186aHJ7Y+T3j3nCuQvvNAe2/fg d8+EE2GrY5m49CVjJmeE+U536uP4oXPRacXnFWsZAyJ4PSvPenPIv93IzThl4rfbLkdt1Eol fSecMvbcZ3C8+Hfh1FmXbrpHTbfif756Rmus+HMvN4VHfPtkXpvVF1+ccer4beNCwdiWX+pf ouJ+LI73mrlSiaU4I9FQi7moOBEAjZev5QsDAAA= X-CMS-MailID: 20230214121507epcas5p1590024fc32dfcf562efce93cf5f07221 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20230214121507epcas5p1590024fc32dfcf562efce93cf5f07221 References: <20230214121333.1837-1-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use pointers instead of fixed size array to store regulator related information. Add common regulator initialization and de-initialization functions. For platform specific init, add a res_ops function pointer. Suggested-by: Pankaj Dubey Signed-off-by: Shradha Todi --- drivers/pci/controller/dwc/pci-samsung.c | 79 +++++++++++++++++++----- 1 file changed, 64 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-samsung.c b/drivers/pci/controller/dwc/pci-samsung.c index 01882f2d06c7..bf18020c14da 100644 --- a/drivers/pci/controller/dwc/pci-samsung.c +++ b/drivers/pci/controller/dwc/pci-samsung.c @@ -66,7 +66,8 @@ struct samsung_pcie_pdata { * @clks: list of clocks required for the controller * @clk_cnt: count of clocks required for the controller * @phy: PHY device associated with the controller - * @supplies: array of regulators required for the controller + * @supplies: list of regulators required for the controller + * @supplies_cnt: count of regulators required for the controller */ struct samsung_pcie { struct dw_pcie pci; @@ -75,10 +76,12 @@ struct samsung_pcie { struct clk_bulk_data *clks; int clk_cnt; struct phy *phy; - struct regulator_bulk_data supplies[2]; + struct regulator_bulk_data *supplies; + int supplies_cnt; }; struct samsung_res_ops { + int (*init_regulator)(struct samsung_pcie *sp); int (*irq_init)(struct samsung_pcie *sp, struct platform_device *pdev); }; @@ -111,6 +114,34 @@ static unsigned int samsung_pcie_appl_readl(struct samsung_pcie *sp, u32 reg) return readl(sp->appl_base + reg); } +static int samsung_regulator_enable(struct samsung_pcie *sp) +{ + struct device *dev = sp->pci.dev; + int ret; + + if (sp->supplies_cnt == 0) + return 0; + + ret = devm_regulator_bulk_get(dev, sp->supplies_cnt, + sp->supplies); + if (ret) + return ret; + + ret = regulator_bulk_enable(sp->supplies_cnt, sp->supplies); + if (ret) + return ret; + + return 0; +} + +static void samsung_regulator_disable(struct samsung_pcie *sp) +{ + if (sp->supplies_cnt == 0) + return; + + regulator_bulk_disable(sp->supplies_cnt, sp->supplies); +} + static void exynos_pcie_sideband_dbi_w_mode(struct samsung_pcie *sp, bool on) { u32 val; @@ -281,6 +312,24 @@ static const struct dw_pcie_host_ops exynos_pcie_host_ops = { .host_init = exynos_pcie_host_init, }; +static int exynos_init_regulator(struct samsung_pcie *sp) +{ + struct device *dev = sp->pci.dev; + + sp->supplies_cnt = 2; + + sp->supplies = devm_kcalloc(dev, sp->supplies_cnt, + sizeof(*sp->supplies), + GFP_KERNEL); + if (!sp->supplies) + return -ENOMEM; + + sp->supplies[0].supply = "vdd18"; + sp->supplies[1].supply = "vdd10"; + + return 0; +} + static int exynos_irq_init(struct samsung_pcie *sp, struct platform_device *pdev) { @@ -313,6 +362,7 @@ static const struct dw_pcie_ops exynos_dw_pcie_ops = { }; static const struct samsung_res_ops exynos_res_ops_data = { + .init_regulator = exynos_init_regulator, .irq_init = exynos_irq_init, }; @@ -346,16 +396,15 @@ static int samsung_pcie_probe(struct platform_device *pdev) if (ret < 0) return ret; - sp->supplies[0].supply = "vdd18"; - sp->supplies[1].supply = "vdd10"; - ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(sp->supplies), - sp->supplies); - if (ret) - return ret; + if (pdata->res_ops && pdata->res_ops->init_regulator) { + ret = sp->pdata->res_ops->init_regulator(sp); + if (ret) + goto fail_regulator; + } - ret = regulator_bulk_enable(ARRAY_SIZE(sp->supplies), sp->supplies); + ret = samsung_regulator_enable(sp); if (ret) - return ret; + goto fail_regulator; platform_set_drvdata(pdev, sp); @@ -372,7 +421,8 @@ static int samsung_pcie_probe(struct platform_device *pdev) fail_probe: phy_exit(sp->phy); - regulator_bulk_disable(ARRAY_SIZE(sp->supplies), sp->supplies); + samsung_regulator_disable(sp); +fail_regulator: samsung_pcie_deinit_clk_resources(sp); return ret; @@ -387,8 +437,7 @@ static int __exit samsung_pcie_remove(struct platform_device *pdev) phy_power_off(sp->phy); phy_exit(sp->phy); samsung_pcie_deinit_clk_resources(sp); - regulator_bulk_disable(ARRAY_SIZE(sp->supplies), sp->supplies); - + samsung_regulator_disable(sp); return 0; } @@ -399,7 +448,7 @@ static int samsung_pcie_suspend_noirq(struct device *dev) exynos_pcie_assert_core_reset(sp); phy_power_off(sp->phy); phy_exit(sp->phy); - regulator_bulk_disable(ARRAY_SIZE(sp->supplies), sp->supplies); + samsung_regulator_disable(sp); return 0; } @@ -411,7 +460,7 @@ static int samsung_pcie_resume_noirq(struct device *dev) struct dw_pcie_rp *pp = &pci->pp; int ret; - ret = regulator_bulk_enable(ARRAY_SIZE(sp->supplies), sp->supplies); + ret = samsung_regulator_enable(sp); if (ret) return ret;