From patchwork Tue Feb 14 14:08:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 13140233 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64124C6379F for ; Tue, 14 Feb 2023 14:10:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233241AbjBNOKo (ORCPT ); Tue, 14 Feb 2023 09:10:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233305AbjBNOKg (ORCPT ); Tue, 14 Feb 2023 09:10:36 -0500 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0816029419; Tue, 14 Feb 2023 06:10:06 -0800 (PST) Received: by mail-ej1-x629.google.com with SMTP id gn39so2067047ejc.8; Tue, 14 Feb 2023 06:10:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8MA+FezG4F1FhZiXu5UiMUXpedUBh3Xy0N9KRcXckUI=; b=G1xR6IRfr7vwGp2wPLVa+Hb9A6hDLa6n7jzOZ9CARQAEfa7Oehy+rqcuwgKFYZvwsd hrAnqnVf9/4zX180IH9eCkyH1TEDePKk7EEptuasz5scZzxI7dj5QOiJLsiSKZGVS89h cMu7fkuBSPbt9PeNyrW8koTVe7Qp6+IhP6ZNzENlgayGEIG8o4FNAvdEggiyD2N8UEiO 7qZeuP1+qCLmlhtxpD3nJtHoutgioxlvtoxuGBoutZsBz7rFpX3RIV81iQ2O/EcGYi2W gJZMfSWa9DWW8YB5YwEScCqyZRRKsHSaTkuyhh7PsxZlGiNpv9s56Uo48KH6sv8+aOkT lGBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8MA+FezG4F1FhZiXu5UiMUXpedUBh3Xy0N9KRcXckUI=; b=q23iqyViDtWi2hN6mI+UXpKrYnwsnU42pJT8qVx9YR0FGLDPQhtQBjz1bP8yc27DHA W06QGz2iK7EtwYzB1kB5BntuhXmXbDNh4zLPKgW6WFRdQhGPH2IHedNarKgAwfBvHjr+ HoPr343MDEgfY8yomRldc/UQEMKdciTkuMpGPCHr+zpKrwXqNi5WmOM5mQqcrOk3CSNT +uDaehYLo7mw03iN4u8BB3nh4fjELrU/oPyCB8p/3X/MkVEGHrVdB+EqLJ595uXKF4Yt nv0KGZnArrQ5jihMLevgmt9hmoialRLh9LN5Y/y2Ctcrkg6Ykz1l0RqWesYxOme0l2JN NzSQ== X-Gm-Message-State: AO0yUKXhiYBASd6Y5XNfWgTU7FsUrNmcvODAqcwfgfBRPLPsY9UmTkSs NJvKtXdFU9VHWRfKCrSyj5o= X-Google-Smtp-Source: AK7set+gsBO80IHS6L6K/JrkjsdLQmNzyKDwSGga+oFAqSy+DEnpXAKyJueMu6hB9+W/2qWlDCpZTQ== X-Received: by 2002:a17:906:13d2:b0:8b1:238b:80ac with SMTP id g18-20020a17090613d200b008b1238b80acmr2756454ejc.67.1676383794181; Tue, 14 Feb 2023 06:09:54 -0800 (PST) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id n11-20020a1709065e0b00b008b13814f804sm332241eju.186.2023.02.14.06.09.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 06:09:53 -0800 (PST) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rick Wertenbroek , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Jani Nikula , Greg Kroah-Hartman , Rodrigo Vivi , Mikko Kovanen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 1/9] PCI: rockchip: Remove writes to unused registers Date: Tue, 14 Feb 2023 15:08:49 +0100 Message-Id: <20230214140858.1133292-2-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> References: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Remove write accesses to registers that are marked "unused" (and therefore read-only) in the technical reference manual (TRM) (see RK3399 TRM 17.6.8.1) Signed-off-by: Rick Wertenbroek --- drivers/pci/controller/pcie-rockchip-ep.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index d1a200b93..d5c477020 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -61,10 +61,6 @@ static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip, ROCKCHIP_PCIE_AT_OB_REGION_DESC0(region)); rockchip_pcie_write(rockchip, 0, ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region)); - rockchip_pcie_write(rockchip, 0, - ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(region)); - rockchip_pcie_write(rockchip, 0, - ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(region)); } static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, @@ -114,12 +110,6 @@ static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); addr1 = upper_32_bits(cpu_addr); } - - /* CPU bus address region */ - rockchip_pcie_write(rockchip, addr0, - ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r)); - rockchip_pcie_write(rockchip, addr1, - ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r)); } static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, From patchwork Tue Feb 14 14:08:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 13140234 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1000C6379F for ; Tue, 14 Feb 2023 14:10:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233312AbjBNOKr (ORCPT ); Tue, 14 Feb 2023 09:10:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233290AbjBNOKo (ORCPT ); Tue, 14 Feb 2023 09:10:44 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEA1829E14; Tue, 14 Feb 2023 06:10:12 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id ml19so40537589ejb.0; Tue, 14 Feb 2023 06:10:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oJTwPyCQKw5xBpJ8wEGHmbNEVhauYC4jLoYSRftpEKg=; b=kkFxkofTxxdGhjgj3REYIMX9GeLMAeendKxgveM/SC4TYLmR+K165wntSVZkcT61W4 h6B6VVvZZFu8+tLVlu7t7atlSqNdbPm8OskYI1ZFZ7TJvgEFqyZcXpM3lghFOty+18e6 vuLSNm6c4lEJ4xuPF3HOZ8n84/CVGect/6JMku3YXYtOdC0JXl2GvRqNdDzbaVN9oeUR V8emS1cvyF5+pvlZlmvYD3QIlNVe7JqrO60fsOkjHTQvBatJogE9FB3U/EpsvX4gxNqY 1brOKk5Pv6t4Z+oRztT9NU6zThbDpdShToPEiL0DsRtUfRs8P4OTNUwrbx+SCdYcEmBi w0ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oJTwPyCQKw5xBpJ8wEGHmbNEVhauYC4jLoYSRftpEKg=; b=6tIWUhJiOrzo5Ma1ZIRrT12RHER3t4mTWJL9U1VFIe20d7IAyOJ52mb7901PM4YQEP Y+rSqezAgOuWR0YhLr0PHPScCoD/OPUl/Df0L3cG13tOjtFex7GGKBYRCt2SGRIHWs63 iYPMl0u5VwjjDRIXVzpBGUGABt38ubK91OfEF7W5fv9wkDqZERISngiaTRsDhNKx428k K2Zv4DCF/nyiAIOqn133IwasP5l7UD+d1ZT5DCPtdr8iVmPXXGlhE/Mnrk8J40vN9FYz 4twYWqKbsJl9LpGQfdA5GSzM9ESGqTU4xuth1Qu66YAJwG8NlxmxQvW8Tv/U8LQVPwSr F/fw== X-Gm-Message-State: AO0yUKVrLIY48IA/zUUKTA2Lu1gJJi87XtBfbEZJ9xRUYXUXCjDvsvFl XTfoR+7crYXdbELpkLUaOKI= X-Google-Smtp-Source: AK7set/c5lGyAwr4OVJk7RpIJxVAqoq2U13GK1o+yKE8UmSYOwLhqX6RvdpoS/x46llDlPwkZ1J+AQ== X-Received: by 2002:a17:907:7d8a:b0:8aa:b526:36b3 with SMTP id oz10-20020a1709077d8a00b008aab52636b3mr4107755ejc.14.1676383797839; Tue, 14 Feb 2023 06:09:57 -0800 (PST) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id n11-20020a1709065e0b00b008b13814f804sm332241eju.186.2023.02.14.06.09.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 06:09:57 -0800 (PST) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rick Wertenbroek , stable@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Jani Nikula , Mikko Kovanen , Rodrigo Vivi , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 2/9] PCI: rockchip: Write PCI Device ID to correct register Date: Tue, 14 Feb 2023 15:08:50 +0100 Message-Id: <20230214140858.1133292-3-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> References: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Write PCI Device ID (DID) to the correct register. The Device ID was not updated through the correct register. Device ID was written to a read-only register and therefore did not work. The Device ID is now set through the correct register. This is documented in the RK3399 TRM section 17.6.6.1.1 Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Cc: stable@vger.kernel.org Signed-off-by: Rick Wertenbroek Reviewed-by: Damien Le Moal Tested-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 6 ++++-- drivers/pci/controller/pcie-rockchip.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index d5c477020..9b835377b 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -115,6 +115,7 @@ static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_header *hdr) { + u32 reg; struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; @@ -127,8 +128,9 @@ static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, PCIE_CORE_CONFIG_VENDOR); } - rockchip_pcie_write(rockchip, hdr->deviceid << 16, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); + reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID); + reg = (reg & 0xFFFF) | (hdr->deviceid << 16); + rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID); rockchip_pcie_write(rockchip, hdr->revid | diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 32c3a859c..51a123e5c 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -133,6 +133,8 @@ #define PCIE_RC_RP_ATS_BASE 0x400000 #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 #define PCIE_RC_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 From patchwork Tue Feb 14 14:08:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 13140235 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF0B7C64ED6 for ; Tue, 14 Feb 2023 14:10:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233430AbjBNOK5 (ORCPT ); Tue, 14 Feb 2023 09:10:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233301AbjBNOKq (ORCPT ); Tue, 14 Feb 2023 09:10:46 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C90DE2A141; Tue, 14 Feb 2023 06:10:13 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id mc25so3023031ejb.13; Tue, 14 Feb 2023 06:10:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CTWPMQ5IkIsp33gvRTV303Woi805qt5LWeJY1A4m9uw=; b=iRlk5JA6Owj1tpws1EfuazhlcuU+rLUsxc4gTBtwVUs4Q9lo9qvpvsYcNZJlbZ/JpE oK21vzja6sMUmUzIodoZTYUYtdFan5EAlpeMGzSl9AcMHptN4c4s7+PViEkF29SMzUv7 3GFX025yHPRed6vxvk84JBOK3WfyWoCaZSaG41y9VTxvCV4ani39VSJDzoa3zUjnuC8h RIanKdM7Z61smgWoUAhAo9bk8kFPc0zpqgH/ThekupRHUpCa8p2/Mp2LqcoLr3n+RbC5 jQaGBc2bQEBMq61ascyWWDBrPVkdCATbE+MY6luviuG2Dkx3fvMqKiOHxaI4ubCB/eV7 qvXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CTWPMQ5IkIsp33gvRTV303Woi805qt5LWeJY1A4m9uw=; b=wUOZ1/HyJunzvX7b2JSyEaS17tFNEdR+IZKqohdMyW9VRysp+uDcGizM/itjpsydLa 4dT7UJAgtXNFVBmvKJCIhAF4dcLDA39I4JagaoETxhOI49bPURF6Rem32RNqEy8v6t8D Ka8ltw+2U0K9FQMv7w/477UnchU2Oxk6CLSbXLj0rm99tFBJUrJs2YqXGmGcciF5aTIp LxfyYU2ZOEPDzeq5GpI/x0wyT1vXGHULGbXw/fpbnImE6wONo7ride6b5vk986a4A2dv J0Asxq6eIxWRCqkT33Ja8o4d8VB+9h9owyH+trQ6ll7CrepNRFfAd0GfufRp2x0IM2V1 Jy9g== X-Gm-Message-State: AO0yUKXThJ5dkTEXAGy/5YmZsP5XwYxFWnw1YVr81v3Iiz94zvQIqyfq mEa3NCCWh0Lgkhs8IFX8mY8= X-Google-Smtp-Source: AK7set9KhVRcL1vkjLJPVGMyilsn5eE+TJWdC9vdzFon7EJF13hwGE1UA2zzRaRP2jZ55wjDvdPiXQ== X-Received: by 2002:a17:906:2214:b0:8b1:304e:58a7 with SMTP id s20-20020a170906221400b008b1304e58a7mr2092828ejs.56.1676383800712; Tue, 14 Feb 2023 06:10:00 -0800 (PST) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id n11-20020a1709065e0b00b008b13814f804sm332241eju.186.2023.02.14.06.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 06:10:00 -0800 (PST) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rick Wertenbroek , stable@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Jani Nikula , Mikko Kovanen , Greg Kroah-Hartman , Rodrigo Vivi , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 3/9] PCI: rockchip: Assert PCI Configuration Enable bit after probe Date: Tue, 14 Feb 2023 15:08:51 +0100 Message-Id: <20230214140858.1133292-4-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> References: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Assert PCI Configuration Enable bit after probe. When this bit is left to 0 in the endpoint mode, the RK3399 PCIe endpoint core will generate configuration request retry status (CRS) messages back to the root complex. Assert this bit after probe to allow the RK3399 PCIe endpoint core to reply to configuration requests from the root complex. This is documented in section 17.5.8.1.2 of the RK3399 TRM. Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Cc: stable@vger.kernel.org Signed-off-by: Rick Wertenbroek Reviewed-by: Damien Le Moal Tested-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 9b835377b..4c84e403e 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -623,6 +623,8 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; + rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, PCIE_CLIENT_CONFIG); + return 0; err_epc_mem_exit: pci_epc_mem_exit(epc); From patchwork Tue Feb 14 14:08:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 13140237 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21EDAC64ED9 for ; Tue, 14 Feb 2023 14:11:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233310AbjBNOK7 (ORCPT ); Tue, 14 Feb 2023 09:10:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233311AbjBNOKq (ORCPT ); Tue, 14 Feb 2023 09:10:46 -0500 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 053452A154; Tue, 14 Feb 2023 06:10:15 -0800 (PST) Received: by mail-ej1-x62b.google.com with SMTP id k16so8836516ejv.10; Tue, 14 Feb 2023 06:10:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wlhNVngokcMAaPIU9YsiNMvp+CICZXJFUIQaHO3ObSo=; b=HS6vt8v8FJ4bXQy/YZe5flTG49HKxTKB1pLjucGq+lUFeWZcdClLvjWzIVJvSplQVI 7PA2I2gzFZ4I0F6hJT27YGypLzagHMBp6I7feTyiKmoeUhRjWEL4VRBZeKUce/SwMUle 4D7qF0ZesQzsGxkkgbZQ1ta1kNx2nrkHfDwy7I9+F0ofKMaqK16t+3LoUNBrde/NjyQs az5U6ZZE8zHE8HizqQGScI2J+SMjKIiZTGtRITqAPDzyv3N7ZtU5S0+MLaHQpDz8FZYZ LF4qHa6oV1SUR/cJmfSs6pQergQrwvDGFJ4hT4mzztx43dwNnHH25Piw+wMcBWyYpzez wxow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wlhNVngokcMAaPIU9YsiNMvp+CICZXJFUIQaHO3ObSo=; b=si3WTI3S0YLluzbVdDJoqeWZjGnUo1dAFhczgCZLdaRh3Qzgb75T+9gXHCKjfL36qU 49WvXgLlbeJw8UWdohnY1ntqRjcG9Yb/DzvukcBEAT0eQxwLxBf/MLdI43MSSwwVcw3u TdhpYWWW3K7KB3WOdNvHE/kS58CoUBWLDu6/lEThcIuTwlEq+LP2cbPX1ypKyuV1HBPW A4LQwcjCTu2yZ+cNg7bWshLCK2xA1U6zxhtYKtayVS3zsPPaBzig2UW0Xo2JWpY0sUxa OwBQNaHnbaj0tGaYQfOZSrCI+cq3C65mXge/Gm9dt1I+7TdMWDQiLWVkbluDsfh+6Q2t VTzA== X-Gm-Message-State: AO0yUKVCbJ2AbZWmG1YxptJjZPPZFwza7DJBzZjb1FmllFggHB1XZrGk 7ZBhxU3w9JXpftakqQyRiKUxc49AZ66p8Q== X-Google-Smtp-Source: AK7set8O61hFgKTFZuDfgH32RN6jBC0eEFWlPfzOZWQPCNksB1GIDJF//jlppO0Izpan8+U5ZnXmQw== X-Received: by 2002:a17:906:5512:b0:8aa:c0d6:2dc6 with SMTP id r18-20020a170906551200b008aac0d62dc6mr3098791ejp.29.1676383803683; Tue, 14 Feb 2023 06:10:03 -0800 (PST) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id n11-20020a1709065e0b00b008b13814f804sm332241eju.186.2023.02.14.06.10.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 06:10:03 -0800 (PST) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rick Wertenbroek , stable@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Jani Nikula , Greg Kroah-Hartman , Rodrigo Vivi , Mikko Kovanen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 4/9] PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked Date: Tue, 14 Feb 2023 15:08:52 +0100 Message-Id: <20230214140858.1133292-5-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> References: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The RK3399 PCIe controller should wait until the PHY PLLs are locked. Add poll and timeout to wait for PHY PLLs to be locked. If they cannot be locked generate error message and jump to error handler. Accessing registers in the PHY clock domain when PLLs are not locked causes hang The PHY PLLs status is checked through a side channel register. This is documented in the TRM section 17.5.8.1 "PCIe Initialization Sequence". Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Cc: stable@vger.kernel.org Signed-off-by: Rick Wertenbroek Reviewed-by: Damien Le Moal Tested-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip.c | 16 ++++++++++++++++ drivers/pci/controller/pcie-rockchip.h | 2 ++ 2 files changed, 18 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index 990a00e08..5f2e2dd5d 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -153,6 +154,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) } EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt); +#define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr) +/* 100 ms max wait time for PHY PLLs to lock */ +#define RK_PHY_PLL_LOCK_TIMEOUT_US 100000 +/* Sleep should be less than 20ms */ +#define RK_PHY_PLL_LOCK_SLEEP_US 1000 + int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->dev; @@ -254,6 +261,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) } } + err = readx_poll_timeout(rockchip_pcie_read_addr, PCIE_CLIENT_SIDE_BAND_STATUS, + regs, !(regs & PCIE_CLIENT_PHY_ST), RK_PHY_PLL_LOCK_SLEEP_US, + RK_PHY_PLL_LOCK_TIMEOUT_US); + + if (err) { + dev_err(dev, "PHY PLLs could not lock, %d\n", err); + goto err_power_off_phy; + } + /* * Please don't reorder the deassert sequence of the following * four reset pins. diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 51a123e5c..f3a5ff1cf 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -38,6 +38,8 @@ #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) +#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) +#define PCIE_CLIENT_PHY_ST BIT(12) #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) #define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0) #define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18 From patchwork Tue Feb 14 14:08:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 13140236 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D4E2C61DA4 for ; Tue, 14 Feb 2023 14:11:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233442AbjBNOK6 (ORCPT ); Tue, 14 Feb 2023 09:10:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233343AbjBNOKt (ORCPT ); Tue, 14 Feb 2023 09:10:49 -0500 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 293C22A145; Tue, 14 Feb 2023 06:10:17 -0800 (PST) Received: by mail-ej1-x62f.google.com with SMTP id lf10so8514247ejc.5; Tue, 14 Feb 2023 06:10:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZyRxgGKgBmZ7vlz9B0DPHOS/vRaGIdO6oxSW3aBTwD0=; b=DHncKPYs87waR3yJGxtEcKoh3OyMcA7zdF3rOXm3j38m6CDX/iQqffz0+04g2A3+bf GffdS4BULOVh9kWWLEh+LXl/+mJ+a7Yf3ZD9CBZjCpZhYzlggO3VwSBmaLjwzja2RdM+ gxwVHpFgOFkY3b53Xeh42awaCb4Drw0n2jtMHW+uflM4ToEFt25BrIOlPHfXCCtiZJ3K fJg5HIcSYpEXucDMsRiqCNeT22ekeN8gi94IbFbiN1VwItRwUoutXOn3UbniynDjb/1q S7ct7A0a0AnO2Lbl0LnFqsAO3+LBOkQQTuO6L3AoWQBKrlynHKDcIk/cW/BdVu/Qk9bW g7hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZyRxgGKgBmZ7vlz9B0DPHOS/vRaGIdO6oxSW3aBTwD0=; b=AKPdcURQ2jR53KnPTtvnYHMPSxEPFsJKihoKtyDB2wLAavmkaxfOpb2xDbfcAhQZX9 yJFOdBc7HpBF2wtsKGIciBCIpR2BuZBt1ysd0PPwg868B+HxVsUw06MiZ6ZDIj65DkrS MRNFTmX0VZJikQNV6o0TEfPoDb2f/Q4CuiWeSuWGHb+d3pJQqdGzhVBlH2RHAzyfidOn uc75VMJ9U74eEhblFKTK/9nJInYeobTSTs2/CciVRYFraIIAfys/uVJZ3AlDuN+ifDJj V++yUq1tVIyS1rPnRHIKTv4qr8NfPZAKdAwcSEM1WZh/2wdYIhuUqDX0mmZc0MH777pC BYug== X-Gm-Message-State: AO0yUKWx5xadOplZ0YzjWvJ8ypiyIOZ2mnYKhLkr9NBvlSLA57DL/LdQ N3WI2pINAegLMNdDAj6nOGY= X-Google-Smtp-Source: AK7set8457lF/1ct6QNmD+ni295zwiDN6/EivlGIF+JpLzVOpzazEgBBkLErUzQwRm93A7rAOTYAOg== X-Received: by 2002:a17:906:2f06:b0:878:714b:5e16 with SMTP id v6-20020a1709062f0600b00878714b5e16mr3011287eji.28.1676383806487; Tue, 14 Feb 2023 06:10:06 -0800 (PST) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id n11-20020a1709065e0b00b008b13814f804sm332241eju.186.2023.02.14.06.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 06:10:06 -0800 (PST) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rick Wertenbroek , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Jani Nikula , Rodrigo Vivi , Greg Kroah-Hartman , Mikko Kovanen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 5/9] arm64: dts: rockchip: Add dtsi entry for RK3399 PCIe endpoint core Date: Tue, 14 Feb 2023 15:08:53 +0100 Message-Id: <20230214140858.1133292-6-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> References: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add dtsi entry for RK3399 PCIe endpoint core in the device tree. The status is "disabled" by default, so it will not be loaded unless explicitly chosen to. The RK3399 PCIe endpoit core should be enabled with the RK3399 PCIe root complex disabled because the RK3399 PCIe controller can only work one mode at the time, either in "root complex" mode or in "endpoint" mode. Signed-off-by: Rick Wertenbroek --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 9d5b0e8c9..8cc5a1ee2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -265,6 +265,29 @@ pcie0_intc: interrupt-controller { }; }; + pcie0_ep: pcie-ep@f8000000 { + compatible = "rockchip,rk3399-pcie-ep"; + rockchip,max-outbound-regions = <32>; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + max-functions = /bits/ 8 <8>; + num-lanes = <4>; + reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>; + reg-names = "apb-base", "mem-base"; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> , + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; + phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + status = "disabled"; + }; + gmac: ethernet@fe300000 { compatible = "rockchip,rk3399-gmac"; reg = <0x0 0xfe300000 0x0 0x10000>; From patchwork Tue Feb 14 14:08:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 13140238 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD776C05027 for ; Tue, 14 Feb 2023 14:11:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233374AbjBNOLE (ORCPT ); Tue, 14 Feb 2023 09:11:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233384AbjBNOKw (ORCPT ); Tue, 14 Feb 2023 09:10:52 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1360A2A16C; Tue, 14 Feb 2023 06:10:20 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id rp23so40363534ejb.7; Tue, 14 Feb 2023 06:10:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hjzsS5Cb3Aw1I5GcqBzV0WBKikDqzXmefD2Bm8OuvxM=; b=TW+n04PyhZk2A7qMZOtaGUnU3B3I/ewsSZU1E4HNZXo2OM/E3pLd5mAyzb4vHCXQA8 C34WFgJ4wNhbUg3WTuLCXIpc0QRvnyI1x4em74GJTetCRGvRXnJzBWYyLt5uAE+hE5uq tED0t1BSVuaJkCfl1Jyn3LuoY3XqhIXVkylpeqnMHP3ACluIrQrsUCMdBFf0DyU5/Uhm mSFp2adQrw5WLyvl9NUgeLHRb+ns3RWl32GGV905m/+TaUmN6Zm9hA2pwU524P5SR1/+ KIccgYbwBN1qk1lN4RZUnXF8xWJHoykb2YTJUjOck/iSo4EXupwW1YiOpSEQ3ZMITpcX aCaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hjzsS5Cb3Aw1I5GcqBzV0WBKikDqzXmefD2Bm8OuvxM=; b=B//U5uXEF2jejZLR4wyi4Hz2ym84w39c7CVjOuHJMVOSdhBtD585TYEu4SbKdjQNol ZClk2f8uDFWmc/JFEbVYPTF8X+nJ+jCa/wm0sxoAo8aDqHu48nMoA7RXKcvZbngtgdVy jqGwfz8LrOtSIMEHwZb1Olp5odYao/Bt/JR95RLmgIuhMDfK8t957JwQcjLJGvs8tBPZ dP1NObk1yHTdaMVFB8xDTRHLsUsvRTJLjTLp4iWb5UklBbJoT6Fqv9LbQ/4VoYN+7bnn Hl1qsgI5aqR3mPQbT/pViWzEb9WkD23F6o0Qc15+ufxp1bWYajj1TOckCum3MwY6aXAg SueQ== X-Gm-Message-State: AO0yUKXYRjHdLREGuCD8XrrCk4Ey+TIAPegqMP62wiRYH9g4Onk1elBE NLS/pzv8yeRSFkdM+ZTur4E= X-Google-Smtp-Source: AK7set9FmvjNi/k83LIGFAjALI7EXsDAnckd9rJPiHM4xoRE4Nerp+mvPS/iS0sbP7aABjidZ1iVrw== X-Received: by 2002:a17:906:a951:b0:8af:2cf7:dd2b with SMTP id hh17-20020a170906a95100b008af2cf7dd2bmr3422183ejb.13.1676383809326; Tue, 14 Feb 2023 06:10:09 -0800 (PST) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id n11-20020a1709065e0b00b008b13814f804sm332241eju.186.2023.02.14.06.10.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 06:10:08 -0800 (PST) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rick Wertenbroek , stable@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Jani Nikula , Rodrigo Vivi , Mikko Kovanen , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 6/9] PCI: rockchip: Fix window mapping and address translation for endpoint Date: Tue, 14 Feb 2023 15:08:54 +0100 Message-Id: <20230214140858.1133292-7-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> References: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The RK3399 PCI endpoint core has 33 windows for PCIe space, now in the driver up to 32 fixed size (1M) windows are used and pages are allocated and mapped accordingly. The driver first used a single window and allocated space inside which caused translation issues (between CPU space and PCI space) because a window can only have a single translation at a given time, which if multiple pages are allocated inside will cause conflicts. Now each window is a single region of 1M which will always guarantee that the translation is not in conflict. Set the translation register addresses for physical function. As documented in the technical reference manual (TRM) section 17.5.5 "PCIe Address Translation" and section 17.6.8 "Address Translation Registers Description" Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Cc: stable@vger.kernel.org Signed-off-by: Rick Wertenbroek --- drivers/pci/controller/pcie-rockchip-ep.c | 67 ++++++++++++----------- drivers/pci/controller/pcie-rockchip.h | 25 +++++---- 2 files changed, 49 insertions(+), 43 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 4c84e403e..cbc281a6a 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -76,11 +76,17 @@ static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, if (num_pass_bits < 8) num_pass_bits = 8; - cpu_addr -= rockchip->mem_res->start; - addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) & - PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | - (lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); - addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr); + if (is_nor_msg) { + dev_warn(rockchip->dev, "NOR MSG\n"); + cpu_addr -= rockchip->mem_res->start; + addr0 = (0x10 & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | + (lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); + addr1 = upper_32_bits(cpu_addr); + } else { + addr0 = (num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | + (lower_32_bits(pci_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); + addr1 = upper_32_bits(pci_addr); + } desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type; desc1 = 0; @@ -103,12 +109,6 @@ static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r)); rockchip_pcie_write(rockchip, desc1, ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r)); - - addr0 = - ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | - (lower_32_bits(cpu_addr) & - PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); - addr1 = upper_32_bits(cpu_addr); } } @@ -256,15 +256,7 @@ static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, struct rockchip_pcie *pcie = &ep->rockchip; u32 r; - r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG); - /* - * Region 0 is reserved for configuration space and shouldn't - * be used elsewhere per TRM, so leave it out. - */ - if (r >= ep->max_regions - 1) { - dev_err(&epc->dev, "no free outbound region\n"); - return -EINVAL; - } + r = (addr >> ilog2(SZ_1M)) & 0x1f; rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr, pci_addr, size); @@ -282,15 +274,11 @@ static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn, struct rockchip_pcie *rockchip = &ep->rockchip; u32 r; - for (r = 0; r < ep->max_regions - 1; r++) + for (r = 0; r < ep->max_regions; r++) if (ep->ob_addr[r] == addr) break; - /* - * Region 0 is reserved for configuration space and shouldn't - * be used elsewhere per TRM, so leave it out. - */ - if (r == ep->max_regions - 1) + if (r == ep->max_regions) return; rockchip_pcie_clear_ep_ob_atu(rockchip, r); @@ -411,6 +399,7 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, u16 flags, mme, data, data_mask; u8 msi_count; u64 pci_addr, pci_addr_mask = 0xff; + u32 r; /* Check MSI enable bit */ flags = rockchip_pcie_read(&ep->rockchip, @@ -444,12 +433,12 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + ROCKCHIP_PCIE_EP_MSI_CTRL_REG + PCI_MSI_ADDRESS_LO); - pci_addr &= GENMASK_ULL(63, 2); /* Set the outbound region if needed. */ if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) || ep->irq_pci_fn != fn)) { - rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1, + r = (ep->irq_phys_addr >> ilog2(SZ_1M)) & 0x1f; + rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r, AXI_WRAPPER_MEM_WRITE, ep->irq_phys_addr, pci_addr & ~pci_addr_mask, @@ -539,6 +528,8 @@ static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip, if (err < 0 || ep->max_regions > MAX_REGION_LIMIT) ep->max_regions = MAX_REGION_LIMIT; + ep->ob_region_map = 0; + err = of_property_read_u8(dev->of_node, "max-functions", &ep->epc->max_functions); if (err < 0) @@ -559,7 +550,10 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) struct rockchip_pcie *rockchip; struct pci_epc *epc; size_t max_regions; + struct pci_epc_mem_window *windows = NULL; int err; + u32 cfg; + int i; ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); if (!ep) @@ -606,15 +600,26 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) /* Only enable function 0 by default */ rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); - err = pci_epc_mem_init(epc, rockchip->mem_res->start, - resource_size(rockchip->mem_res), PAGE_SIZE); + windows = devm_kcalloc(dev, ep->max_regions, sizeof(struct pci_epc_mem_window), GFP_KERNEL); + if (!windows) { + err = -ENOMEM; + goto err_uninit_port; + } + for (i = 0; i < ep->max_regions; i++) { + windows[i].phys_base = rockchip->mem_res->start + (SZ_1M * i); + windows[i].size = SZ_1M; + windows[i].page_size = SZ_1M; + } + err = pci_epc_multi_mem_init(epc, windows, ep->max_regions); + devm_kfree(dev, windows); + if (err < 0) { dev_err(dev, "failed to initialize the memory space\n"); goto err_uninit_port; } ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, - SZ_128K); + SZ_1M); if (!ep->irq_cpu_addr) { dev_err(dev, "failed to reserve memory space for MSI\n"); err = -ENOMEM; diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index f3a5ff1cf..72e427a0f 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -134,6 +134,7 @@ #define PCIE_RC_RP_ATS_BASE 0x400000 #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 +#define PCIE_EP_PF_CONFIG_REGS_BASE 0x800000 #define PCIE_RC_CONFIG_BASE 0xa00000 #define PCIE_EP_CONFIG_BASE 0xa00000 #define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) @@ -228,13 +229,14 @@ #define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24) #define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1 #define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3 -#define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) +#define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) \ + (PCIE_EP_PF_CONFIG_REGS_BASE + (((fn) << 12) & GENMASK(19, 12))) +#define ROCKCHIP_PCIE_EP_VIRT_FUNC_BASE(fn) \ + (PCIE_EP_PF_CONFIG_REGS_BASE + 0x10000 + (((fn) << 12) & GENMASK(19, 12))) #define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ - (PCIE_RC_RP_ATS_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) + (PCIE_CORE_AXI_CONF_BASE + 0x0828 + (fn) * 0x0040 + (bar) * 0x0008) #define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ - (PCIE_RC_RP_ATS_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) -#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ - (PCIE_RC_RP_ATS_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) + (PCIE_CORE_AXI_CONF_BASE + 0x082c + (fn) * 0x0040 + (bar) * 0x0008) #define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) #define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ (((devfn) << 12) & \ @@ -242,20 +244,19 @@ #define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) #define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ (((bus) << 20) & ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) +#define PCIE_RC_EP_ATR_OB_REGIONS_1_32 (PCIE_CORE_AXI_CONF_BASE + 0x0020) +#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ + (PCIE_RC_EP_ATR_OB_REGIONS_1_32 + 0x0000 + ((r) & 0x1f) * 0x0020) #define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ - (PCIE_RC_RP_ATS_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) + (PCIE_RC_EP_ATR_OB_REGIONS_1_32 + 0x0004 + ((r) & 0x1f) * 0x0020) #define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) #define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) #define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ (((devfn) << 24) & ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) #define ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r) \ - (PCIE_RC_RP_ATS_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) + (PCIE_RC_EP_ATR_OB_REGIONS_1_32 + 0x0008 + ((r) & 0x1f) * 0x0020) #define ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r) \ - (PCIE_RC_RP_ATS_BASE + 0x000c + ((r) & 0x1f) * 0x0020) -#define ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ - (PCIE_RC_RP_ATS_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) -#define ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ - (PCIE_RC_RP_ATS_BASE + 0x001c + ((r) & 0x1f) * 0x0020) + (PCIE_RC_EP_ATR_OB_REGIONS_1_32 + 0x000c + ((r) & 0x1f) * 0x0020) #define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn) \ (PCIE_CORE_CTRL_MGMT_BASE + 0x0240 + (fn) * 0x0008) From patchwork Tue Feb 14 14:08:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 13140239 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 053A0C64EC7 for ; Tue, 14 Feb 2023 14:11:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233309AbjBNOLP (ORCPT ); Tue, 14 Feb 2023 09:11:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233385AbjBNOKw (ORCPT ); Tue, 14 Feb 2023 09:10:52 -0500 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E004076AD; Tue, 14 Feb 2023 06:10:21 -0800 (PST) Received: by mail-ej1-x62b.google.com with SMTP id qw12so40431245ejc.2; Tue, 14 Feb 2023 06:10:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G4b0gzVsxfEDBk+JDTdDvkxVPx/flrfnXIUXp8EED98=; b=nxK2vZfJXOqwBGbbppTW8iDiFJSXqmQ5KmohCvhBk0pjaSYsqYIoB4TI4NRG7P0IkW 7d1QUkfthIZN1ya1+OMz3yiVYsupijkwSRdTDvZtWpdqKoFywte3fNHQNFs5jnoxUg5t 5O7Vc5L75Fg2Vs/gVnmtr1U/usiZ1xPuaAk2SErDZi1Jks3kCTJcEUyBeZrhtfw9np1H 0SYt8QFz6840QrA0K8YZiGVnBNhebtlcqRwZ0Bu7wywZvz/empEeN/tbNVsL8zNJLrH7 12U5um6OMZqb2jKJ+UrtiGggWUouIEZFPeYsrZRRt05z9MvWwlFWbRUupJAAbHrKwA4i 1KiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G4b0gzVsxfEDBk+JDTdDvkxVPx/flrfnXIUXp8EED98=; b=sIabrMAW+tuc4HvOEAc4U7nBSHI6AJo+4qpexRt6Aj4yeBQqffaOo1waZzBc0WVjDE n/rAEG0a/cgBBtNGq4IU6LT5PbJS+Tl1lf2fykZYaELpf3t0OTG8UATS7lMSwlyf66Bp aFpK+oaSI521Xx9lWup+AaED+mYoS0l4nqUMiNtK8rbO9Luyqqk1VITwOPY5mBys7YKq fB1ieX9/otrXOE7V1B7nsfhQtLWf0jt4fyKTSspEoeo2QSwU+NM3BaNuf6XGCrvYZyh6 lUGkwtaWJcEt88w275QUYjATF1kBSkxlfoAh+rSyG+TVHnkVBAdDwpAyigIzFgoAaImZ m6dg== X-Gm-Message-State: AO0yUKWFlGcUptMPxkOqvjAd1LaefR6NfCkadmjBMWPzgKR/a7iWNHgv 7JItIwAV1xr2oSyH16NNVuw= X-Google-Smtp-Source: AK7set+P3I5w7NnN9v0I+op7ljbZo1mpuW8lMzNNdJQ1kPpeO7OxY8oGIb+Y6liq++qmYYEvZIT26w== X-Received: by 2002:a17:906:b886:b0:8aa:be1a:c4bf with SMTP id hb6-20020a170906b88600b008aabe1ac4bfmr4165664ejb.16.1676383811928; Tue, 14 Feb 2023 06:10:11 -0800 (PST) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id n11-20020a1709065e0b00b008b13814f804sm332241eju.186.2023.02.14.06.10.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 06:10:11 -0800 (PST) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rick Wertenbroek , stable@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Jani Nikula , Mikko Kovanen , Rodrigo Vivi , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 7/9] PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core Date: Tue, 14 Feb 2023 15:08:55 +0100 Message-Id: <20230214140858.1133292-8-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> References: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Fix legacy IRQ generation for RK3399 PCIe endpoint core according to the technical reference manual (TRM). Assert and deassert legacy interrupt (INTx) through the legacy interrupt control register ("PCIE_CLIENT_LEGACY_INT_CTRL") instead of manually generating a PCIe message. The generation of the legacy interrupt was tested and validated with the PCIe endpoint test driver. Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Cc: stable@vger.kernel.org Signed-off-by: Rick Wertenbroek --- drivers/pci/controller/pcie-rockchip-ep.c | 38 +++++------------------ drivers/pci/controller/pcie-rockchip.h | 6 ++++ 2 files changed, 14 insertions(+), 30 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index cbc281a6a..ca5b363ba 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -328,45 +328,23 @@ static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn, u8 intx, bool is_asserted) { struct rockchip_pcie *rockchip = &ep->rockchip; - u32 r = ep->max_regions - 1; - u32 offset; - u32 status; - u8 msg_code; - - if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR || - ep->irq_pci_fn != fn)) { - rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r, - AXI_WRAPPER_NOR_MSG, - ep->irq_phys_addr, 0, 0); - ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR; - ep->irq_pci_fn = fn; - } intx &= 3; if (is_asserted) { ep->irq_pending |= BIT(intx); - msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx; } else { ep->irq_pending &= ~BIT(intx); - msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx; } - status = rockchip_pcie_read(rockchip, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + - ROCKCHIP_PCIE_EP_CMD_STATUS); - status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; - - if ((status != 0) ^ (ep->irq_pending != 0)) { - status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; - rockchip_pcie_write(rockchip, status, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + - ROCKCHIP_PCIE_EP_CMD_STATUS); + if (is_asserted) { + rockchip_pcie_write(rockchip, + PCIE_CLIENT_INT_IN_ASSERT | PCIE_CLIENT_INT_PEND_ST_PEND, + PCIE_CLIENT_LEGACY_INT_CTRL); + } else { + rockchip_pcie_write(rockchip, + PCIE_CLIENT_INT_IN_DEASSERT | PCIE_CLIENT_INT_PEND_ST_NORMAL, + PCIE_CLIENT_LEGACY_INT_CTRL); } - - offset = - ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) | - ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA; - writel(0, ep->irq_cpu_addr + offset); } static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn, diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 72e427a0f..e90c2a2b8 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -39,6 +39,12 @@ #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) #define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) +#define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c) +#define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002) +#define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0) +#define PCIE_CLIENT_INT_PEND_ST_PEND HIWORD_UPDATE_BIT(0x0001) +#define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0) +#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) #define PCIE_CLIENT_PHY_ST BIT(12) #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) #define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0) From patchwork Tue Feb 14 14:08:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 13140241 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1639C678D4 for ; Tue, 14 Feb 2023 14:11:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233480AbjBNOLS (ORCPT ); Tue, 14 Feb 2023 09:11:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233410AbjBNOKy (ORCPT ); Tue, 14 Feb 2023 09:10:54 -0500 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 748802A14E; Tue, 14 Feb 2023 06:10:25 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id s11so9817360edd.10; Tue, 14 Feb 2023 06:10:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=leNS6hmyIgQxbPlXUve4JFJD/yn1aM7eCJEzZy46jcA=; b=GxhRaKhlcHs299NEKAX+wtIe80PW+/cCcVAN85uszD6SL/ZLUlVBRK/zZy6eTtxirj LFnv1ol9ft1keCp8bdOfrT/daz2JpshsLZ7+Kf3h+Iit6De2lNuJOMhG+3i+geaugKje DQcUtcvnOt7nsySzShkD7elKEwj8Shxiyfucv8pGlvA58Bj8dxLgH1WLcdYa35Dik8JI pGOgGpZGfNf7MQ+uVbijgCiYn1rPiTfPIojD5Z5zGtqAQiXJirGtAGKUuNhgEeETTtuR gA/v4Yj4CB4+rRZwPqtWQmt3ksLC+hqZMHMHY6QAV+IfUd/n2GnHofVZKFIEDWA+qf1e YQEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=leNS6hmyIgQxbPlXUve4JFJD/yn1aM7eCJEzZy46jcA=; b=TZZYWEdMz6nMzgXMFECL+D4dt6U4rc/x/UObOi6Txv+7f4dQzrDMg9IceqLCVmZEsk 3f8VFmykTh0S+49DTl0S/0SjnOUMzhmJ+jKe6gCESJGxed2jgPDkfziJdC8nsuEugCKG jZp7J2ezOSVD/h2wELOwWWEze8uAZfmT4QVF86qIQwxF+clPiDslSR+7WPEczI+WT/3f qpAl8ngQLWAqjqKrMmN/Bt+Skp3ApB8Egt1Mgmz93As5VwDt/UOSpVhUvfbilwpwKRP4 NJQZfmMdCpVQe7T+KDq4vTKODN7mdXbJnUuhy3lKh9aABV3et7jh2W33ZIkt740o4NBE a8Ag== X-Gm-Message-State: AO0yUKVZ4WB293Jzwx9vERWGN31ufywiSei2f1nCf54gTiUXJljMWB8k pnHlUf/KMqgsj4g5FhiQN/Y= X-Google-Smtp-Source: AK7set9N9N3VH6ABv4tYrC+s4HqH1z0Kb6sgQzquJYWLZEM44/gK2FHTXsNm0Mn9sTpMk7RJnouLTw== X-Received: by 2002:a50:d7dc:0:b0:4aa:c77d:fa0a with SMTP id m28-20020a50d7dc000000b004aac77dfa0amr2388921edj.22.1676383814714; Tue, 14 Feb 2023 06:10:14 -0800 (PST) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id n11-20020a1709065e0b00b008b13814f804sm332241eju.186.2023.02.14.06.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 06:10:14 -0800 (PST) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rick Wertenbroek , stable@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Jani Nikula , Rodrigo Vivi , Mikko Kovanen , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 8/9] PCI: rockchip: Use u32 variable to access 32-bit registers Date: Tue, 14 Feb 2023 15:08:56 +0100 Message-Id: <20230214140858.1133292-9-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> References: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Previously u16 variables were used to access 32-bit registers, this resulted in not all of the data being read from the registers. Also the left shift of more than 16-bits would result in moving data out of the variable. Use u32 variables to access 32-bit registers Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Cc: stable@vger.kernel.org Signed-off-by: Rick Wertenbroek --- drivers/pci/controller/pcie-rockchip-ep.c | 10 +++++----- drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index ca5b363ba..b7865a94e 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -292,15 +292,15 @@ static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, { struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags; + u32 flags; flags = rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK; flags |= - ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | - PCI_MSI_FLAGS_64BIT; + (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | + (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET); flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP; rockchip_pcie_write(rockchip, flags, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -312,7 +312,7 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) { struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags; + u32 flags; flags = rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -374,7 +374,7 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, u8 interrupt_num) { struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags, mme, data, data_mask; + u32 flags, mme, data, data_mask; u8 msi_count; u64 pci_addr, pci_addr_mask = 0xff; u32 r; diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index e90c2a2b8..11dbf53cd 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -227,6 +227,7 @@ #define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4 #define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19) #define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90 +#define ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET 16 #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17 #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17) #define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20 From patchwork Tue Feb 14 14:08:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rick Wertenbroek X-Patchwork-Id: 13140240 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E014DC64ED9 for ; Tue, 14 Feb 2023 14:11:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233403AbjBNOLT (ORCPT ); Tue, 14 Feb 2023 09:11:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233418AbjBNOK4 (ORCPT ); Tue, 14 Feb 2023 09:10:56 -0500 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10CD32A6D2; Tue, 14 Feb 2023 06:10:31 -0800 (PST) Received: by mail-ej1-x62e.google.com with SMTP id k16so8838406ejv.10; Tue, 14 Feb 2023 06:10:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YFaCpSoOh56OQteewfZTVMaeWIQyKb2eWSuRe9wY0g4=; b=oawyfDtd4HUlixv3sc8fZB+y6sxxiksKZ4eU55nrdO/SmBP4kNGX255/isXuDEWjfI dMoeLo58pSfJRjFoOestBhkzoTulA8PDB7E3VaOp/7VSW4xhQ4lP2TdTAwT52+wxeMR5 7AFChbur3VIZtBmRFkA1EqF9YZMwmJm0T9px+ooQXbvAKoCmtywskBQc010vH45IV4uk l1zM+ampBJPpo8R8JS8MGlYI+8x5dWLdrvLfiAGGsdGn/9RsIk2NnjYmXyBzHs5s5lhx o/XH626hiiJ2s7VjSOtc/zhNlNb/nzDqXA5JzQuea+/P5KCLxRAVfo4hkceeXdmLjpuH v1rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YFaCpSoOh56OQteewfZTVMaeWIQyKb2eWSuRe9wY0g4=; b=waFnDYYTZKq1sLopqW59IwitdX1GkxOwQWy0woolpLAZR6Cqx817d0tLpFkrCqf+LA hv3BAUBFL9c+5NGHyZysTL4zvfVDJh44TaAFboquohoMh0Vj4D7sDAO2poiEk7hNfAAh RZ8t5+j0wUn1IgXdjJ1ADNRyaxpdosU5vBHucUjAwiP8rcRvBcOVXIjsqmKHSb3mhOJg K9uWx18ywtjJAfUt75xbioBl7J310xFricoUhwWCg4BA/p0kKGLqySiyNUvoDnkElBKQ m/yzVnYnRtDsaofMzwaKhTThiDEXC37qSiBgeup+7uxqGj5xpEq09QLEIzOE90hXLyKa nJJA== X-Gm-Message-State: AO0yUKVFZDHUIdqkaLSAE18aWLgM09KvdRpt9hihwsTwq28OWsExt8+m 8Mn7b9n3Zh4bbdtGKabpbhk= X-Google-Smtp-Source: AK7set9qx8i6ewx1KKF13ke9e6N7GALFeNK0DAgAP0ZyuOYAr/7qo2cNVkJA5U73LXL7dOkPQFdgNg== X-Received: by 2002:a17:906:7c07:b0:888:7d50:33b4 with SMTP id t7-20020a1709067c0700b008887d5033b4mr3040433ejo.34.1676383817601; Tue, 14 Feb 2023 06:10:17 -0800 (PST) Received: from A13PC04R.einet.ad.eivd.ch ([193.134.219.72]) by smtp.googlemail.com with ESMTPSA id n11-20020a1709065e0b00b008b13814f804sm332241eju.186.2023.02.14.06.10.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 06:10:17 -0800 (PST) From: Rick Wertenbroek To: alberto.dassatti@heig-vd.ch Cc: xxm@rock-chips.com, rick.wertenbroek@heig-vd.ch, Rick Wertenbroek , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Jani Nikula , Greg Kroah-Hartman , Rodrigo Vivi , Mikko Kovanen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v2 9/9] PCI: rockchip: Add parameter check for RK3399 PCIe endpoint core set_msi() Date: Tue, 14 Feb 2023 15:08:57 +0100 Message-Id: <20230214140858.1133292-10-rick.wertenbroek@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> References: <20230214140858.1133292-1-rick.wertenbroek@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The RK3399 PCIe endpoint core supports only a single PCIe physcial function (function number 0), therefore return -EINVAL if set_msi() is called with a function number greater than 0. The PCIe standard only allows the multi message capability (MMC) value to be up to 0x5 (32 messages), therefore return -EINVAL if set_msi() is called with a MMC value of over 0x5. Signed-off-by: Rick Wertenbroek --- drivers/pci/controller/pcie-rockchip-ep.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index b7865a94e..80634b690 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -294,6 +294,16 @@ static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, struct rockchip_pcie *rockchip = &ep->rockchip; u32 flags; + if (fn) { + dev_err(&epc->dev, "This endpoint controller only supports a single physical function\n"); + return -EINVAL; + } + + if (mmc > 0x5) { + dev_err(&epc->dev, "Number of MSI IRQs cannot be more than 32\n"); + return -EINVAL; + } + flags = rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + ROCKCHIP_PCIE_EP_MSI_CTRL_REG);