From patchwork Tue Feb 14 19:23:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13140763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5795CC6379F for ; Tue, 14 Feb 2023 19:25:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pS0uQ-0005R6-Ql; Tue, 14 Feb 2023 14:24:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pS0uP-0005Q6-B9 for qemu-devel@nongnu.org; Tue, 14 Feb 2023 14:24:09 -0500 Received: from mail-oi1-x22c.google.com ([2607:f8b0:4864:20::22c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pS0uN-00056i-Qw for qemu-devel@nongnu.org; Tue, 14 Feb 2023 14:24:09 -0500 Received: by mail-oi1-x22c.google.com with SMTP id dt8so13903089oib.0 for ; Tue, 14 Feb 2023 11:24:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LC73mPmFrGq5o3KC93WRhQ0uBlIIBFIRs5CA6y4B+Tk=; b=Cq+dQTQfJWoTeDleX+T/9EyfaDIoxDB5Crv4RuI4umGJ8e7vY02x+eAc9k6q6o94vN qNkXXhpm99pHedCDyhGoWFL44lZvUOAbadkS4mmK3XcaLGY6NOAuvcHsaGNz31D48GPR /+5bXHcxDTinOy/rbxoIggmU+npjNVotnds9t83PlqPwarQ1JrZmdvmQeFODImZvsvst 9NYcSp4Bv8BY6d/Di2cF/kFpP6hJaWzPBV0AB8FedjyZt64pJvU7NMSMLVlAqtz5ZdsU nTCimhRImyKuBLO9w0AXqn5FA6oIEbxpqEAV0bzSkhjpbjYG35epvcDFho8lG24nO4fn 9xew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LC73mPmFrGq5o3KC93WRhQ0uBlIIBFIRs5CA6y4B+Tk=; b=uynu/rIcp95Hg1ghGNEQhY3lnGhCOKhsGdh6kRaOIv3wYs1KAT0q9O2d1ejI0+0qF0 2xN54nzlzOb/9OFqbOmOQvrFgObopApzyaAuppYJmVhWC+dsfL7fZ8Uqovd6B2PvoXtO aXjbY3n+fCSzrNAEcyBSytFkkWGfHegDNiD5ceL3yIIrzIgXdRlifjsZTsdm0ryN00vM nTyOFO7rs+9HBtdNwCqwr8qlaHLAME4R3e9yEzvAaZ+1p31Krn/0aXkr4FPk3bEa91aI +cNgC5ihtR4J65a3YCnnkqYss5tQJ71yI1oJo3XxuD+atbUwoqzXEkXAkJq9MyIIzl2p GAWQ== X-Gm-Message-State: AO0yUKUlGjTlI3cfHftBy6jDw8W401/0puya3FKAkx7dZ/CCCzGd1v/a FwYy2zSr/4nD00woCzbmHuY1GIpKvrzmAzZj X-Google-Smtp-Source: AK7set9o9cke3UPKcHIFJs9PcVy/va3CuNO4lnfcAi+thzvWk+lAZvLf1Uw9j2J6RKtRoPI1N9i9kw== X-Received: by 2002:aca:2211:0:b0:378:81f8:bb2a with SMTP id b17-20020aca2211000000b0037881f8bb2amr1545048oic.33.1676402646194; Tue, 14 Feb 2023 11:24:06 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.19.40.109]) by smtp.gmail.com with ESMTPSA id g5-20020a9d6185000000b006865223e532sm6653752otk.51.2023.02.14.11.24.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 11:24:05 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH v2 01/11] target/riscv: do not mask unsupported QEMU extensions in write_misa() Date: Tue, 14 Feb 2023 16:23:46 -0300 Message-Id: <20230214192356.319991-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214192356.319991-1-dbarboza@ventanamicro.com> References: <20230214192356.319991-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The masking done using env->misa_ext_mask already filters any extension that QEMU doesn't support. If the hart supports the extension then QEMU supports it as well. If the masking done by env->misa_ext_mask is somehow letting unsupported QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead. Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- target/riscv/csr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1b0a0c1693..e149b453da 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1356,9 +1356,6 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, /* Mask extensions that are not supported by this hart */ val &= env->misa_ext_mask; - /* Mask extensions that are not supported by QEMU */ - val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); - /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ if ((val & RVD) && !(val & RVF)) { val &= ~RVD; From patchwork Tue Feb 14 19:23:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13140766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A95FC05027 for ; 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Tue, 14 Feb 2023 11:24:09 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.19.40.109]) by smtp.gmail.com with ESMTPSA id g5-20020a9d6185000000b006865223e532sm6653752otk.51.2023.02.14.11.24.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 11:24:08 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH v2 02/11] target/riscv: introduce riscv_cpu_cfg() Date: Tue, 14 Feb 2023 16:23:47 -0300 Message-Id: <20230214192356.319991-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214192356.319991-1-dbarboza@ventanamicro.com> References: <20230214192356.319991-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We're going to do changes that requires accessing the RISCVCPUConfig struct from the RISCVCPU, having access only to a CPURISCVState 'env' pointer. Add a helper to make the code easier to read. Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- target/riscv/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7128438d8e..5e4d056772 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -654,6 +654,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) #endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) +static inline RISCVCPUConfig riscv_cpu_cfg(CPURISCVState *env) +{ + return env_archcpu(env)->cfg; +} + #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) #else From patchwork Tue Feb 14 19:23:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13140760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0113C05027 for ; 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Tue, 14 Feb 2023 11:24:11 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.19.40.109]) by smtp.gmail.com with ESMTPSA id g5-20020a9d6185000000b006865223e532sm6653752otk.51.2023.02.14.11.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 11:24:11 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH v2 03/11] target/riscv: allow users to actually write the MISA CSR Date: Tue, 14 Feb 2023 16:23:48 -0300 Message-Id: <20230214192356.319991-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214192356.319991-1-dbarboza@ventanamicro.com> References: <20230214192356.319991-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, has always been a no-op as well because write_misa() will always exit earlier. This seems to be benign in the majority of cases. Booting an Ubuntu 'virt' guest and logging all the calls to 'write_misa' shows that no writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling RISC-V extensions after the machine is powered on, seems to be a niche use. There is a good chance that the code in write_misa() hasn't been properly tested. Allowing users to write MISA can open the floodgates of new breeds of bugs. We could instead remove most (if not all) of write_misa() since it's never used. Well, as a hardware emulator, dealing with crashes because a register write went wrong is what we're here for. Create a 'misa-w' CPU property to allow users to choose whether writes to MISA should be allowed. The default is set to 'false' for all RISC-V machines to keep compatibility with what we´ve been doing so far. Read cpu->cfg.misa_w directly in write_misa(), instead of executing riscv_set_feature(RISCV_FEATURE_MISA) in riscv_cpu_realize(), that would simply reflect the cpu->cfg.misa_w bool value in 'env->features' and require a riscv_feature() call to read it back. Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/csr.c | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 93b52b826c..69fb9e123f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1197,6 +1197,7 @@ static void register_cpu_props(DeviceState *dev) static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + DEFINE_PROP_BOOL("misa-w", RISCVCPU, cfg.misa_w, false), DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5e4d056772..fe572b83e9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -498,6 +498,7 @@ struct RISCVCPUConfig { bool pmp; bool epmp; bool debug; + bool misa_w; bool short_isa_string; }; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e149b453da..e949e6248a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1329,7 +1329,7 @@ static RISCVException read_misa(CPURISCVState *env, int csrno, static RISCVException write_misa(CPURISCVState *env, int csrno, target_ulong val) { - if (!riscv_feature(env, RISCV_FEATURE_MISA)) { + if (!riscv_cpu_cfg(env).misa_w) { /* drop write to misa */ return RISCV_EXCP_NONE; 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Tue, 14 Feb 2023 11:24:14 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH v2 04/11] target/riscv: remove RISCV_FEATURE_MISA Date: Tue, 14 Feb 2023 16:23:49 -0300 Message-Id: <20230214192356.319991-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214192356.319991-1-dbarboza@ventanamicro.com> References: <20230214192356.319991-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This enum is no longer used after write_misa() started reading the value from cpu->cfg.misa_w. Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fe572b83e9..00a464c9c4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -89,7 +89,6 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, - RISCV_FEATURE_MISA, RISCV_FEATURE_DEBUG }; From patchwork Tue Feb 14 19:23:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13140756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED735C64EC7 for ; Tue, 14 Feb 2023 19:25:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pS0ub-0005XN-4V; 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Tue, 14 Feb 2023 11:24:17 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH v2 05/11] target/riscv: remove RISCV_FEATURE_DEBUG Date: Tue, 14 Feb 2023 16:23:50 -0300 Message-Id: <20230214192356.319991-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214192356.319991-1-dbarboza@ventanamicro.com> References: <20230214192356.319991-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead. Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- target/riscv/cpu.c | 6 +----- target/riscv/cpu.h | 1 - target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 2 +- target/riscv/machine.c | 3 +-- 5 files changed, 4 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 69fb9e123f..272cf1a8bf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); #ifndef CONFIG_USER_ONLY - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + if (cpu->cfg.debug) { riscv_trigger_init(env); } @@ -935,10 +935,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (cpu->cfg.debug) { - riscv_set_feature(env, RISCV_FEATURE_DEBUG); - } - #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sstc) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 00a464c9c4..46de6f2f7f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -89,7 +89,6 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, - RISCV_FEATURE_DEBUG }; /* Privileged specification version */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ad8d82662c..4cdd247c6c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, get_field(env->mstatus_hs, MSTATUS_VS)); } - if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) { + if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e949e6248a..120a0541bb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno) static RISCVException debug(CPURISCVState *env, int csrno) { - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + if (riscv_cpu_cfg(env).debug) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c6ce318cce..4634968898 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = { static bool debug_needed(void *opaque) { RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; - return riscv_feature(env, RISCV_FEATURE_DEBUG); + return cpu->cfg.debug; } static int debug_post_load(void *opaque, int version_id) From patchwork Tue Feb 14 19:23:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13140755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F15DFC64ED8 for ; Tue, 14 Feb 2023 19:25:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pS0uf-0005fH-A2; Tue, 14 Feb 2023 14:24:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pS0ud-0005dV-4v for qemu-devel@nongnu.org; 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Tue, 14 Feb 2023 11:24:19 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH v2 06/11] target/riscv/cpu.c: error out if EPMP is enabled without PMP Date: Tue, 14 Feb 2023 16:23:51 -0300 Message-Id: <20230214192356.319991-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214192356.319991-1-dbarboza@ventanamicro.com> References: <20230214192356.319991-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of silently ignoring the EPMP setting if there is no PMP available, error out informing the user that EPMP depends on PMP support: $ ./qemu-system-riscv64 -cpu rv64,pmp=false,x-epmp=true qemu-system-riscv64: Invalid configuration: EPMP requires PMP support This will force users to pick saner options in the QEMU command line. Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- target/riscv/cpu.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 272cf1a8bf..1e67e72f90 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -925,13 +925,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.pmp) { riscv_set_feature(env, RISCV_FEATURE_PMP); + } + + if (cpu->cfg.epmp) { + riscv_set_feature(env, RISCV_FEATURE_EPMP); /* * Enhanced PMP should only be available * on harts with PMP support */ - if (cpu->cfg.epmp) { - riscv_set_feature(env, RISCV_FEATURE_EPMP); + if (!cpu->cfg.pmp) { + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); + return; } } From patchwork Tue Feb 14 19:23:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13140761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63075C64EC7 for ; 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Tue, 14 Feb 2023 11:24:23 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.19.40.109]) by smtp.gmail.com with ESMTPSA id g5-20020a9d6185000000b006865223e532sm6653752otk.51.2023.02.14.11.24.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 11:24:22 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH v2 07/11] target/riscv: remove RISCV_FEATURE_EPMP Date: Tue, 14 Feb 2023 16:23:52 -0300 Message-Id: <20230214192356.319991-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214192356.319991-1-dbarboza@ventanamicro.com> References: <20230214192356.319991-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp flag. Use the flag directly. Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- target/riscv/cpu.c | 10 +++------- target/riscv/cpu.h | 1 - target/riscv/csr.c | 2 +- target/riscv/pmp.c | 4 ++-- 4 files changed, 6 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e67e72f90..430b6adccb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -927,17 +927,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_set_feature(env, RISCV_FEATURE_PMP); } - if (cpu->cfg.epmp) { - riscv_set_feature(env, RISCV_FEATURE_EPMP); - + if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available * on harts with PMP support */ - if (!cpu->cfg.pmp) { - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); - return; - } + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); + return; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 46de6f2f7f..d0de11fd41 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -88,7 +88,6 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, - RISCV_FEATURE_EPMP, }; /* Privileged specification version */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 120a0541bb..223162af5e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -428,7 +428,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno) static RISCVException epmp(CPURISCVState *env, int csrno) { - if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (env->priv == PRV_M && riscv_cpu_cfg(env).epmp) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 4bc4113531..bb54899635 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) if (pmp_index < MAX_RISCV_PMPS) { bool locked = true; - if (riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (riscv_cpu_cfg(env).epmp) { /* mseccfg.RLB is set */ if (MSECCFG_RLB_ISSET(env)) { locked = false; @@ -239,7 +239,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, { bool ret; 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Tue, 14 Feb 2023 11:24:25 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH v2 08/11] target/riscv: remove RISCV_FEATURE_PMP Date: Tue, 14 Feb 2023 16:23:53 -0300 Message-Id: <20230214192356.319991-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214192356.319991-1-dbarboza@ventanamicro.com> References: <20230214192356.319991-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead. Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- target/riscv/cpu.c | 4 ---- target/riscv/cpu.h | 1 - target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 2 +- target/riscv/machine.c | 3 +-- target/riscv/op_helper.c | 2 +- target/riscv/pmp.c | 2 +- 7 files changed, 5 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 430b6adccb..a803395ed1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -923,10 +923,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_set_feature(env, RISCV_FEATURE_MMU); } - if (cpu->cfg.pmp) { - riscv_set_feature(env, RISCV_FEATURE_PMP); - } - if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0de11fd41..62919cd5cc 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -87,7 +87,6 @@ so a cpu features bitfield is required, likewise for optional PMP support */ enum { RISCV_FEATURE_MMU, - RISCV_FEATURE_PMP, }; /* Privileged specification version */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4cdd247c6c..15d9542691 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -706,7 +706,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, pmp_priv_t pmp_priv; int pmp_index = -1; - if (!riscv_feature(env, RISCV_FEATURE_PMP)) { + if (!riscv_cpu_cfg(env).pmp) { *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TRANSLATE_SUCCESS; } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 223162af5e..356cf3c04f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -419,7 +419,7 @@ static int aia_hmode32(CPURISCVState *env, int csrno) static RISCVException pmp(CPURISCVState *env, int csrno) { - if (riscv_feature(env, RISCV_FEATURE_PMP)) { + if (riscv_cpu_cfg(env).pmp) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 4634968898..67e9e56853 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -27,9 +27,8 @@ static bool pmp_needed(void *opaque) { RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; - return riscv_feature(env, RISCV_FEATURE_PMP); + return cpu->cfg.pmp; } static int pmp_post_load(void *opaque, int version_id) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 48f918b71b..f34701b443 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -195,7 +195,7 @@ target_ulong helper_mret(CPURISCVState *env) uint64_t mstatus = env->mstatus; target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); - if (riscv_feature(env, RISCV_FEATURE_PMP) && + if (riscv_cpu_cfg(env).pmp && !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index bb54899635..1e7903dffa 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -265,7 +265,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, } } - if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) { + if (!riscv_cpu_cfg(env).pmp || (mode == PRV_M)) { /* * Privileged spec v1.10 states if HW doesn't implement any PMP entry * or no PMP entry matches an M-Mode access, the access succeeds. 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As a bonus, use cpu_ptr in riscv_isa_string(). Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- hw/riscv/virt.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 86c4adc0c9..49f2c157f7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -232,20 +232,21 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, bool is_32_bit = riscv_is_32bit(&s->soc[0]); for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { + RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; + cpu_phandle = (*phandle)++; cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(ms->fdt, cpu_name); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_MMU)) { + if (cpu_ptr->cfg.mmu) { qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); } else { qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", "riscv,none"); } - name = riscv_isa_string(&s->soc[socket].harts[cpu]); + name = riscv_isa_string(cpu_ptr); qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); g_free(name); qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); From patchwork Tue Feb 14 19:23:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13140765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E923C05027 for ; Tue, 14 Feb 2023 19:26:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pS0up-0005v8-DF; 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Tue, 14 Feb 2023 11:24:31 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, Daniel Henrique Barboza Subject: [PATCH v2 10/11] target/riscv: remove RISCV_FEATURE_MMU Date: Tue, 14 Feb 2023 16:23:55 -0300 Message-Id: <20230214192356.319991-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230214192356.319991-1-dbarboza@ventanamicro.com> References: <20230214192356.319991-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use the flag directly instead. With this change the enum is also removed. It is worth noticing that this enum, and all the RISCV_FEATURES_* that were contained in it, predates the existence of the cpu->cfg object. Today, using cpu->cfg is an easier way to retrieve all the features and extensions enabled in the hart. Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- target/riscv/cpu.c | 4 ---- target/riscv/cpu.h | 7 ------- target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 4 ++-- target/riscv/monitor.c | 2 +- target/riscv/pmp.c | 2 +- 6 files changed, 5 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a803395ed1..2859ebc3e6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -919,10 +919,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (cpu->cfg.mmu) { - riscv_set_feature(env, RISCV_FEATURE_MMU); - } - if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 62919cd5cc..83a9fa38d9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,13 +81,6 @@ #define RVH RV('H') #define RVJ RV('J') -/* S extension denotes that Supervisor mode exists, however it is possible - to have a core that support S mode but does not have an MMU and there - is currently no bit in misa to indicate whether an MMU exists or not - so a cpu features bitfield is required, likewise for optional PMP support */ -enum { - RISCV_FEATURE_MMU, -}; /* Privileged specification version */ enum { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 15d9542691..e76b206191 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -796,7 +796,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, mode = PRV_U; } - if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { + if (mode == PRV_M || !riscv_cpu_cfg(env).mmu) { *physical = addr; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TRANSLATE_SUCCESS; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 356cf3c04f..54bcdbc4dc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2621,7 +2621,7 @@ static RISCVException rmw_siph(CPURISCVState *env, int csrno, static RISCVException read_satp(CPURISCVState *env, int csrno, target_ulong *val) { - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + if (!riscv_cpu_cfg(env).mmu) { *val = 0; return RISCV_EXCP_NONE; } @@ -2640,7 +2640,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno, { target_ulong vm, mask; - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + if (!riscv_cpu_cfg(env).mmu) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 236f93b9f5..b7b8d0614f 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -218,7 +218,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + if (!riscv_cpu_cfg(env).mmu) { monitor_printf(mon, "S-mode MMU unavailable\n"); return; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 1e7903dffa..c67de36942 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -315,7 +315,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, } if (size == 0) { - if (riscv_feature(env, RISCV_FEATURE_MMU)) { + if (riscv_cpu_cfg(env).mmu) { /* * If size is unknown (0), assume that all bytes * from addr to the end of the page will be accessed. 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Remove env->feature, riscv_feature() and riscv_set_feature(). We also need to bump vmstate_riscv_cpu version_id and minimal_version_id since 'features' is no longer being migrated. Reviewed-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng --- target/riscv/cpu.h | 12 ------------ target/riscv/machine.c | 5 ++--- 2 files changed, 2 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 83a9fa38d9..6290c6d357 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -173,8 +173,6 @@ struct CPUArchState { /* 128-bit helpers upper part return value */ target_ulong retxh; - uint32_t features; - #ifdef CONFIG_USER_ONLY uint32_t elf_flags; #endif @@ -525,16 +523,6 @@ static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) return (env->misa_ext & ext) != 0; } -static inline bool riscv_feature(CPURISCVState *env, int feature) -{ - return env->features & (1ULL << feature); -} - -static inline void riscv_set_feature(CPURISCVState *env, int feature) -{ - env->features |= (1ULL << feature); -} - #include "cpu_user.h" extern const char * const riscv_int_regnames[]; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 67e9e56853..9c455931d8 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -331,8 +331,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = { const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", - .version_id = 6, - .minimum_version_id = 6, + .version_id = 7, + .minimum_version_id = 7, .post_load = riscv_cpu_post_load, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -351,7 +351,6 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINT32(env.misa_ext, RISCVCPU), VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), - VMSTATE_UINT32(env.features, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_UINTTL(env.virt, RISCVCPU), VMSTATE_UINT64(env.resetvec, RISCVCPU),