From patchwork Mon Jan 28 11:53:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 10783631 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 538C813BF for ; Mon, 28 Jan 2019 11:56:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 462A3289D7 for ; Mon, 28 Jan 2019 11:56:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3A0902926D; Mon, 28 Jan 2019 11:56:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA6A7289D7 for ; Mon, 28 Jan 2019 11:56:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726714AbfA1L4L (ORCPT ); Mon, 28 Jan 2019 06:56:11 -0500 Received: from mail.kernel.org ([198.145.29.99]:34210 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726611AbfA1L4K (ORCPT ); Mon, 28 Jan 2019 06:56:10 -0500 Received: from localhost.localdomain (unknown [106.200.228.251]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5E7BE2086C; Mon, 28 Jan 2019 11:56:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548676569; bh=559CPLfcG5St/5z9rJpZ8EVehSIrsJuSZjAHbs7bDY0=; h=From:To:Cc:Subject:Date:From; b=FlW51fWdpwmWeOkpHsDAmIJLbYWPa1GmefF70qwvSc8bWa5n6Joi2B68D+I9PzupT SZQI09SNjhbL1ml4xf7VDZmeLMWTOVpNYwEkM2UZ8kBJBvXPnrjKu9qULnUEud2IOo 9TuRz+vX0FA0feL4A5ULgm7XnQjL800MwfRool9w= From: Vinod Koul To: Michael Turquette , Stephen Boyd Cc: Khasim Syed Mohammed , Bjorn Andersson , Taniya Das , Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Anu Ramanathan , Shawn Guo , Vinod Koul Subject: [PATCH 1/2] clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs Date: Mon, 28 Jan 2019 17:23:58 +0530 Message-Id: <20190128115359.30039-1-vkoul@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Taniya Das The RCG CFG/M/N/D register base could be at a different offset than the CMD register, so introduce a cfg_offset to identify the offset with respect to the CMD register. Signed-off-by: Taniya Das Signed-off-by: Anu Ramanathan Signed-off-by: Shawn Guo Signed-off-by: Vinod Koul --- drivers/clk/qcom/clk-rcg.h | 2 ++ drivers/clk/qcom/clk-rcg2.c | 30 +++++++++++++++++++----------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index e5eca8a1abe4..f06783c20688 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -140,6 +140,7 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @parent_map: map from software's parent index to hardware's src_sel field * @freq_tbl: frequency table * @clkr: regmap clock handle + * @cfg_off: defines the cfg register offset from the CMD_RCGR * */ struct clk_rcg2 { @@ -150,6 +151,7 @@ struct clk_rcg2 { const struct parent_map *parent_map; const struct freq_tbl *freq_tbl; struct clk_regmap clkr; + u8 cfg_off; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 6e3bd195d012..106848e3313f 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -74,7 +74,8 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw) u32 cfg; int i, ret; - ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); + ret = regmap_read(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, &cfg); if (ret) goto err; @@ -123,7 +124,8 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) int ret; u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, + ret = regmap_update_bits(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, CFG_SRC_SEL_MASK, cfg); if (ret) return ret; @@ -162,13 +164,16 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) struct clk_rcg2 *rcg = to_clk_rcg2(hw); u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask; - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); + regmap_read(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, &cfg); if (rcg->mnd_width) { mask = BIT(rcg->mnd_width) - 1; - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m); + regmap_read(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + M_REG, &m); m &= mask; - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n); + regmap_read(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + N_REG, &n); n = ~n; n &= mask; n += m; @@ -263,17 +268,20 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) if (rcg->mnd_width && f->n) { mask = BIT(rcg->mnd_width) - 1; ret = regmap_update_bits(rcg->clkr.regmap, - rcg->cmd_rcgr + M_REG, mask, f->m); + rcg->cmd_rcgr + rcg->cfg_off + M_REG, + mask, f->m); if (ret) return ret; ret = regmap_update_bits(rcg->clkr.regmap, - rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m)); + rcg->cmd_rcgr + rcg->cfg_off + N_REG, + mask, ~(f->n - f->m)); if (ret) return ret; ret = regmap_update_bits(rcg->clkr.regmap, - rcg->cmd_rcgr + D_REG, mask, ~f->n); + rcg->cmd_rcgr + rcg->cfg_off + D_REG, + mask, ~f->n); if (ret) return ret; } @@ -284,9 +292,9 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; if (rcg->mnd_width && f->n && (f->m != f->n)) cfg |= CFG_MODE_DUAL_EDGE; - - return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, - mask, cfg); + return regmap_update_bits(rcg->clkr.regmap, + rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, + mask, cfg); } static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) From patchwork Mon Jan 28 11:53:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 10783633 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A1010922 for ; Mon, 28 Jan 2019 11:56:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8F8D328569 for ; Mon, 28 Jan 2019 11:56:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 835EB28EB6; Mon, 28 Jan 2019 11:56:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1D36428569 for ; Mon, 28 Jan 2019 11:56:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726877AbfA1L4O (ORCPT ); Mon, 28 Jan 2019 06:56:14 -0500 Received: from mail.kernel.org ([198.145.29.99]:34250 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726784AbfA1L4O (ORCPT ); Mon, 28 Jan 2019 06:56:14 -0500 Received: from localhost.localdomain (unknown [106.200.228.251]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6A23B21738; Mon, 28 Jan 2019 11:56:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1548676573; bh=f3lxgKhF5Et41sfz+Bweyn0o307QENkvpp62lR482mE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=phE01TLNGPIl7vvyPKyB+ZNrL+FuPEpohMrRjK56EOMlyjGRzIY4NK+LaYRYv4uV0 z5tD0QMSqmV+dJvNVUcCk4Ss3JpQ59j0InOUopDtMprO3s6tLfiNpC5Cdm8HIlUYdB fiY1gZlVtj915/LNvCPyMn51UESyZVZTYKaypHpo= From: Vinod Koul To: Michael Turquette , Stephen Boyd Cc: Khasim Syed Mohammed , Bjorn Andersson , Taniya Das , Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Anu Ramanathan , Shawn Guo , Vinod Koul Subject: [PATCH 2/2] clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock Date: Mon, 28 Jan 2019 17:23:59 +0530 Message-Id: <20190128115359.30039-2-vkoul@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190128115359.30039-1-vkoul@kernel.org> References: <20190128115359.30039-1-vkoul@kernel.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Taniya Das The CFG/M/N/D registers are at an offset of 0x20 from the CMD register for blsp1_uart3 clock, so add it. Signed-off-by: Taniya Das Signed-off-by: Anu Ramanathan Signed-off-by: Shawn Guo Signed-off-by: Vinod Koul --- drivers/clk/qcom/gcc-qcs404.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 64da032bb9ed..493e055299b4 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -678,6 +678,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .cmd_rcgr = 0x4014, .mnd_width = 16, .hid_width = 5, + .cfg_off = 0x20, .parent_map = gcc_parent_map_0, .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){