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Miller" , Florian Fainelli , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v1 net-next 1/7] phy: phy-ocelot-serdes: add ability to be used in a non-syscon configuration Date: Wed, 15 Feb 2023 23:53:15 -0800 Message-Id: <20230216075321.2898003-2-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216075321.2898003-1-colin.foster@in-advantage.com> References: <20230216075321.2898003-1-colin.foster@in-advantage.com> X-ClientProxiedBy: BY3PR05CA0019.namprd05.prod.outlook.com (2603:10b6:a03:254::24) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWHPR1001MB2351:EE_|IA1PR10MB5993:EE_ X-MS-Office365-Filtering-Correlation-Id: a02f608d-293c-419f-a121-08db0ff2e87a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YpTsvfcufPCGXmqdLdNRbKpAECrbva50ThN74at7lEdR7nK59aRmTNcj0wpF4pEbDtjsooqhwMMiQEDEwWpg14VHlf63OEbh+EhG7tqWbGy1zt8WeUz4LxykNPmEWQuK9dUeJAu91mWpxnDTp9eWtdK0T3hAiFnRa44mKJy0zfFX2GWyEUeRISQBT1kkISgOoo2rd4CX1c2+OgudSL+F3NuurNKqEvkhGCLc26/Yjm9rgzSnFbyeSXjRWpCoV1jNOb76nbxQy7z4rbVDLsDUJxu62nAzX+a0JCT6T4E8ZdmV8drImy5ESXrx/ulSDLynfFXLf7+/KJZ1HC0r1BXexsuGFE/yOaCci+5QdszNHb+fgvWhO0w4IGGms0reH4kGwWW2OPKLdEUpuKbNqaBnryo00afdNo0vujL07SdsIW5CyQzz1CTVgTi1HI6xW18Ye80AbvOe2Db1trLZYca5A4pEdiYdWQCMcBKG2GeyI/7UeOnhE8niVZxUeX9AiO7tKaZ+BS3uBFQfOepsl2Re0+Y5oebjznmF32xhC/vNk7tzEGjS8DOPZONW59Omrl1cOq6Z5BBwZvzTiX0fVaUd6896ntK2tnro1ItcnU9Wc44yhweJb2sAmJfMhzVcHgYu7elutrLfSuenKukILLpVLXUiGNxA7ITTPpOM12hn1rxHbc8HtevJFEyMi+aDAzLO8vZsuFR/cCbM1Q4atasuHA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(136003)(39830400003)(396003)(366004)(346002)(376002)(451199018)(5660300002)(38350700002)(41300700001)(2906002)(8936002)(38100700002)(2616005)(6506007)(26005)(6512007)(186003)(6666004)(478600001)(52116002)(6486002)(44832011)(1076003)(86362001)(316002)(66476007)(66946007)(54906003)(4326008)(8676002)(66556008)(7416002)(36756003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YlfRWrYo+cTsf5sNMc+Pb0+tq60+jm384Hewe0vVmSwh2KjvRe0J8UaoF+QBoWl6VGz8/CFsvOua60zOufprnUBSSE3AVDv/5OGtuQJkCuvwoc1FmKe+f7SVKys/3npDAGw/BdH4j3lqqPI6Td1X5QUZ89kOdIDMrAYEm+vSNthOmfgVaDMEK5uHNpxr3E9iS9MOpF9mXNYPkl34cdQpnFI/j4BmbWkzV5jaPWd8FWGX/RuFn2jWJHS5YbJ7HIDo6GpK3jOoENozeVUIJa3BlnBTrC52H4HtDr+OKZ/ZOxsl543KrKUv/Xx1PZJkixEpTlsVJ//Z4EHYDmSdG/BiRCPEsQw+/377WgqPOVh5ig370sZwSfrvwsSJoBPSP45iPFeQu/dyCUI/Zuw6xY87+ZKESoqXuTji+XgeCqvM9+JLmpjR7IxCwjIgBjkUpQR1+kQBuwBKMvVEwGcnrfF8+8uEPTXq/LcDx+f18LqdOJjoPFvjpuLOfWdHcuPtf3AVxGS+OeQ8s1FuVyPtPE0I9nsPBfPgVIjSTvnnWQLpITMbHDNK6ZKaXzVtiIHpdz8Mvemxek6AyuOUrMgdFgqIuRzL2Dv2K223EFj8wnpIRJHXnj8CtaflbCES5BVEO8llAcsR+MuCHfHPKIgNk0HUk4oloivuA19951YOtxhux5DNqlAEEO+uJaBQOBNpOF+NXkVPULmfIdG+e2E+hzOuexxV8rEMYI/XoU8DoJtW3ZSMxey63HkejJgeb7gkb/etruAdz/WvrWxq24yLWTKvoZJ7CgS4qWq82wx3Do3gd4o0Pdn2tnE1T6Liu8wdPCmdx7FCpPRva/xutBf5y9TeVJNEFC8EYku5xwAdHnvwdofP+uAalpVAMhIlVZW8yEDqsWrOe2hxipwU40U9IOdh6f1GwolS9PqFKnMBo+SLiewgl2r23VOHysQsSDxG5miaKBnexWFiIUadBNXNpTegsduJM7GBXX2lxmX0XQjslaZlZaP8diL+utBw73KkODqSQhexLkNuqjfR5E0SXPIkvF/kyOa1jjqQpNOK9wXTyaJ+yFKwH8K2NCpUS9KPxi+KnGiUXIahhzTFBlyiGJxu/SQRlM/W5S5U3ZVTj20AoXHynYbOKXP9CMugWUtumqfj1HoxxosJwWDdlwsKJpzKQ+mnIv3QR7oiNTpwB6/8H4vCu/rnv7lz1M4qscVmUfRccjrb9spb4961Yahl4dWq9eQi+ZGmnJ44nE3KjDZCNOUkRBsM76YbksTmqt4ePJ01R1q0WLEZrot4xxcurITH7cZig/dGUQgq9CMvzsUbdVZ6afoWPAI8yT5o9iTs8xifrRFZCSqLc+NZS11pYUfMsHqX8uwk39KjwsJnt+AfBa4q6B5uGb5NAk5/AB5sn7Ao0HD8L51ksBhzdr9JbGG9v518QaOX9+VyFv80q2Qm8sBg0jTAD1Zt8xLPdQVA2v25ppZB1a8biPipzZBINIGzxH2ueigP/y5FCiKjdx3qvINNNl6+AGmoOhvYf0wM8cO4PRaKg4Wr5NiTYmTYp53E17U0ijZ67qwtRStO/6Yge8VB11wGn3NSeJd7W1CEPky5pH9yOQ4z5I96k08ceNq3C6Wy73s1kJnRSCLjyJV/DGc= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: a02f608d-293c-419f-a121-08db0ff2e87a X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2023 07:53:36.3191 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: p3ICbx8N8LzoE+VrlWO44Tkq1Lxkls+mzXXShz0mxNH2O1q889nRrjYesV+A7JmTiw33VuNqIfVO7oCH9VOYVherlJVAErv/iR+pcknY6xU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR10MB5993 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230215_235339_775545_3163DDF7 X-CRM114-Status: GOOD ( 12.36 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The phy-ocelot-serdes module has exclusively been used in a syscon setup, from an internal CPU. The addition of external control of ocelot switches via an existing MFD implementation means that syscon is no longer the only interface that phy-ocelot-serdes will see. In the MFD configuration, an IORESOURCE_REG resource will exist for the device. Utilize this resource to be able to function in both syscon and non-syscon configurations. Signed-off-by: Colin Foster --- drivers/phy/mscc/phy-ocelot-serdes.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/mscc/phy-ocelot-serdes.c b/drivers/phy/mscc/phy-ocelot-serdes.c index 76f596365176..d9443e865a78 100644 --- a/drivers/phy/mscc/phy-ocelot-serdes.c +++ b/drivers/phy/mscc/phy-ocelot-serdes.c @@ -494,6 +494,7 @@ static int serdes_probe(struct platform_device *pdev) { struct phy_provider *provider; struct serdes_ctrl *ctrl; + struct resource *res; unsigned int i; int ret; @@ -503,6 +504,14 @@ static int serdes_probe(struct platform_device *pdev) ctrl->dev = &pdev->dev; ctrl->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(ctrl->regs)) { + /* Fall back to using IORESOURCE_REG, if possible */ + res = platform_get_resource(pdev, IORESOURCE_REG, 0); + if (res) + ctrl->regs = dev_get_regmap(ctrl->dev->parent, + res->name); + } + if (IS_ERR(ctrl->regs)) return PTR_ERR(ctrl->regs); From patchwork Thu Feb 16 07:53:16 2023 Content-Type: text/plain; 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Signed-off-by: Colin Foster --- drivers/mfd/ocelot-core.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c index b0ff05c1759f..c2224f8a16c0 100644 --- a/drivers/mfd/ocelot-core.c +++ b/drivers/mfd/ocelot-core.c @@ -45,6 +45,9 @@ #define VSC7512_SIO_CTRL_RES_START 0x710700f8 #define VSC7512_SIO_CTRL_RES_SIZE 0x00000100 +#define VSC7512_HSIO_RES_START 0x710d0000 +#define VSC7512_HSIO_RES_SIZE 0x00000128 + #define VSC7512_ANA_RES_START 0x71880000 #define VSC7512_ANA_RES_SIZE 0x00010000 @@ -129,8 +132,13 @@ static const struct resource vsc7512_sgpio_resources[] = { DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"), }; +static const struct resource vsc7512_serdes_resources[] = { + DEFINE_RES_REG_NAMED(VSC7512_HSIO_RES_START, VSC7512_HSIO_RES_SIZE, "hsio"), +}; + static const struct resource vsc7512_switch_resources[] = { DEFINE_RES_REG_NAMED(VSC7512_ANA_RES_START, VSC7512_ANA_RES_SIZE, "ana"), + DEFINE_RES_REG_NAMED(VSC7512_HSIO_RES_START, VSC7512_HSIO_RES_SIZE, "hsio"), DEFINE_RES_REG_NAMED(VSC7512_QS_RES_START, VSC7512_QS_RES_SIZE, "qs"), DEFINE_RES_REG_NAMED(VSC7512_QSYS_RES_START, VSC7512_QSYS_RES_SIZE, "qsys"), DEFINE_RES_REG_NAMED(VSC7512_REW_RES_START, VSC7512_REW_RES_SIZE, "rew"), @@ -176,6 +184,11 @@ static const struct mfd_cell vsc7512_devs[] = { .use_of_reg = true, .num_resources = ARRAY_SIZE(vsc7512_miim1_resources), .resources = vsc7512_miim1_resources, + }, { + .name = "ocelot-serdes", + .of_compatible = "mscc,vsc7514-serdes", + .num_resources = ARRAY_SIZE(vsc7512_serdes_resources), + .resources = vsc7512_serdes_resources, }, { .name = "ocelot-switch", .of_compatible = "mscc,vsc7512-switch", From patchwork Thu Feb 16 07:53:17 2023 Content-Type: text/plain; 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Miller" , Florian Fainelli , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v1 net-next 3/7] net: mscc: ocelot: expose ocelot_pll5_init routine Date: Wed, 15 Feb 2023 23:53:17 -0800 Message-Id: <20230216075321.2898003-4-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216075321.2898003-1-colin.foster@in-advantage.com> References: <20230216075321.2898003-1-colin.foster@in-advantage.com> X-ClientProxiedBy: BY3PR05CA0019.namprd05.prod.outlook.com (2603:10b6:a03:254::24) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWHPR1001MB2351:EE_|IA1PR10MB5993:EE_ X-MS-Office365-Filtering-Correlation-Id: 88e1b277-ffd3-4b79-99e6-08db0ff2ea20 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OHMAkuAuUFmRZ5IOSNlGlZqidXCpIJ7SpvQEUP9emxW0PMyfAXuVaPYcJvh2ptjPWIqMTNYZgFjobRMeo8nUxwAq368YcveJbJaryrddX3uNPtT8u2xVKCsevXt5USXZ8wS8Sg5Sp4tRc1Ha7QGYFC0j5Yqb3GaAvmfdDJCcM89ENNOYN0IGJH/NOCKoviwfM7cxC73emjQRzqH4gYKGhoWv25PGUy9Dg/OcKiDxY4nmU8BEoEKHZtAcrr+TKVzjP6Jn0CI3123H7reqfrJifU6woYh7pfFRBPn2+TGuhD+6jEji4LEWhjFVElFvz1SRbkoHJTCffkpVOV1qtSWqDGHlt8bB0grb7QE4VOS63uU4MluX9Hwn/sQ3QlKsdC2X++13H5fC0lW8PkVpx/clMfnCaiR+H4CadrNW81UmYrz2fKe2CEzX2ldjmFUkR/CyU808CL2vIzPVncVeUrxrIzSBZjCjlZ/R+49WqhvoyCZasfBGEXvPzuvikKB6FPjTx0Nc4BcYb0y2Lc1dcG56a4OTYSVXkm6yLrxJAk38Zjc459lecb+kHc5vNhB7fPLI7kZcMllk5LpYZemEc54y6RolnNQcBu30KxVlQlRJHnkFCDFLZsW4PGx9w5usU97qQlpkhWcwDSIu7FsHhA+2jrx0rY6pDSV6nRmZ38Qki/gwzYi4K9YsDw4hqUnyC8hKrkOYUdyGYTaiFtrO5WI/vQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(136003)(39830400003)(396003)(366004)(346002)(376002)(451199018)(83380400001)(5660300002)(38350700002)(41300700001)(2906002)(8936002)(38100700002)(2616005)(6506007)(26005)(6512007)(186003)(6666004)(478600001)(52116002)(6486002)(44832011)(1076003)(86362001)(316002)(66476007)(66946007)(54906003)(4326008)(8676002)(66556008)(7416002)(36756003);DIR:OUT;SFP:1102; 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Expose the init routine, so it can be used by other drivers. Signed-off-by: Colin Foster --- drivers/net/ethernet/mscc/ocelot.c | 31 ++++++++++++++++++++++ drivers/net/ethernet/mscc/ocelot_vsc7514.c | 30 --------------------- include/soc/mscc/ocelot.h | 2 ++ 3 files changed, 33 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index 08acb7b89086..9b8403e29445 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "ocelot.h" #include "ocelot_vcap.h" @@ -211,6 +212,36 @@ static void ocelot_mact_init(struct ocelot *ocelot) ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); } +void ocelot_pll5_init(struct ocelot *ocelot) +{ + /* Configure PLL5. This will need a proper CCF driver + * The values are coming from the VTSS API for Ocelot + */ + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, + HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | + HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, + HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | + HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | + HSIO_PLL5G_CFG0_ENA_BIAS | + HSIO_PLL5G_CFG0_ENA_VCO_BUF | + HSIO_PLL5G_CFG0_ENA_CP1 | + HSIO_PLL5G_CFG0_SELCPI(2) | + HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | + HSIO_PLL5G_CFG0_SELBGV820(4) | + HSIO_PLL5G_CFG0_DIV4 | + HSIO_PLL5G_CFG0_ENA_CLKTREE | + HSIO_PLL5G_CFG0_ENA_LANE); + regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, + HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | + HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | + HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | + HSIO_PLL5G_CFG2_ENA_AMPCTRL | + HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | + HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); +} +EXPORT_SYMBOL(ocelot_pll5_init); + static void ocelot_vcap_enable(struct ocelot *ocelot, int port) { ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c index 7388c3b0535c..97e90e2869d4 100644 --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c @@ -18,7 +18,6 @@ #include #include -#include #include #include "ocelot_fdma.h" #include "ocelot.h" @@ -26,35 +25,6 @@ #define VSC7514_VCAP_POLICER_BASE 128 #define VSC7514_VCAP_POLICER_MAX 191 -static void ocelot_pll5_init(struct ocelot *ocelot) -{ - /* Configure PLL5. This will need a proper CCF driver - * The values are coming from the VTSS API for Ocelot - */ - regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG4, - HSIO_PLL5G_CFG4_IB_CTRL(0x7600) | - HSIO_PLL5G_CFG4_IB_BIAS_CTRL(0x8)); - regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG0, - HSIO_PLL5G_CFG0_CORE_CLK_DIV(0x11) | - HSIO_PLL5G_CFG0_CPU_CLK_DIV(2) | - HSIO_PLL5G_CFG0_ENA_BIAS | - HSIO_PLL5G_CFG0_ENA_VCO_BUF | - HSIO_PLL5G_CFG0_ENA_CP1 | - HSIO_PLL5G_CFG0_SELCPI(2) | - HSIO_PLL5G_CFG0_LOOP_BW_RES(0xe) | - HSIO_PLL5G_CFG0_SELBGV820(4) | - HSIO_PLL5G_CFG0_DIV4 | - HSIO_PLL5G_CFG0_ENA_CLKTREE | - HSIO_PLL5G_CFG0_ENA_LANE); - regmap_write(ocelot->targets[HSIO], HSIO_PLL5G_CFG2, - HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET | - HSIO_PLL5G_CFG2_EN_RESET_OVERRUN | - HSIO_PLL5G_CFG2_GAIN_TEST(0x8) | - HSIO_PLL5G_CFG2_ENA_AMPCTRL | - HSIO_PLL5G_CFG2_PWD_AMPCTRL_N | - HSIO_PLL5G_CFG2_AMPC_SEL(0x10)); -} - static int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops) { int ret; diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 2080879e4134..751d9b250615 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -1183,4 +1183,6 @@ ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port, } #endif +void ocelot_pll5_init(struct ocelot *ocelot); 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Miller" , Florian Fainelli , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v1 net-next 4/7] net: mscc: ocelot: expose generic phylink_mac_config routine Date: Wed, 15 Feb 2023 23:53:18 -0800 Message-Id: <20230216075321.2898003-5-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216075321.2898003-1-colin.foster@in-advantage.com> References: <20230216075321.2898003-1-colin.foster@in-advantage.com> X-ClientProxiedBy: BY3PR05CA0019.namprd05.prod.outlook.com (2603:10b6:a03:254::24) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWHPR1001MB2351:EE_|IA1PR10MB5993:EE_ X-MS-Office365-Filtering-Correlation-Id: 822d5cd9-a75e-4919-a082-08db0ff2eaed X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 13jp7GOR7xHp8nQtC2KuNz7p4fKOGlFjGCXcm62/6z38Wme7+fNX+Sjn5L0zbkMoHyuwl4ZFlHGg9wvo2vZ1wBajFkW7jXC8hhtzOXtBCwRTq6vcOsDtjgSYPCTPi5nWPdPtZ3xfkik1CF2Xq+zE7HdDQQ7u7BChKZED6Llk8oCcgPZsZnphCEYdbsAqQgpxK60hjmU+bsU5rec3ewH8UOWG94+LTyHEmVhbKqY8We49mgo/Z1mM3KsaBOzaQVhfaYMcmTVcbPgvUflTb5aOG1quA2Md20BMIGjCbqbIbTkMFUaEGFYc0qpta4IlzsnreAqRGiqDXyzZd2B6a2MWmLTCQ09qHDROucG5Ltf2MrB2geR9CK/c3R9iqzy4BWsp1gzXxlxNbUkxMH0jC0Axh9W6pSEcl1igDd3P86b/dEHABbKsbAop4A6B5Z4w7dVH8Zt7eK9apHb0sNhV0D0+RoHTwkAV2wXJ6QnauiuNgH/LE/j0MWCE8cSGnO2UrIlM+uaC2WvCW+kE70U8Y9IjY2Zp4/KFF9E4Av+vTIBJPYDF+AjIBO+mZ9lsEIhwU9od1I8lz08tD8Bns2i26W7lpMJ6soF5e1OMtkVmnkb7VGsT1nlTVEmrYtwNNKL3v+Yaeg319HVpmUOvTXib0aqM6Q5vTpb7C0K71C1aaeew7Hwzhw3wrqceLTFBp0lF39OU90pGWsO3JxHGyfSs7bcg7XYuuNqXT5OzqT2Qoi+Zetk= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(136003)(39830400003)(396003)(366004)(346002)(376002)(451199018)(83380400001)(5660300002)(38350700002)(41300700001)(2906002)(8936002)(38100700002)(2616005)(6506007)(26005)(6512007)(186003)(6666004)(478600001)(52116002)(6486002)(44832011)(1076003)(86362001)(316002)(66476007)(66946007)(54906003)(4326008)(8676002)(66556008)(7416002)(36756003)(41533002);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: j0AeEHXSSGkFjUvM6ZIaiaY+LEiXvIlQ2ImPI5ZBwfS8tjr5fKKoU804g+9Tpfk5lZNIa+eRwD1521x0vzAoTsmsO9nTQ2IRXadg+qvxph57ZK8GNTprNCg4+nwCh347p5+EGHwOC0iEcfu5r0x89Eeu4A/7TH53/RwgAqfu7FESN93GimgEW8MMdEYgz3nB177eaoOiqIvfA5WARh125VW1iZXiVe1NEPyjVOhkpfksyMQewkHzXlHWuK9+W8923GQZOBSO7onF+mLBW8HbtrBs7hrClfmrnMoMPh1AvLox2HxyLhlC2JnW0YnK0FU0v26RSsYoeaMszl3pqsThFylkIQ8x6Wu1/AGn//aF5dnipuu6dkpNKq4ZpIdnJKgUifO6oiOv2dMjFjjYGWKwH2xEFRO27KgHnFshXgxWFwrnz9va1wQWrhemF0JWyjN/Y8DyikUBXIDmG2rfBYjwM7PZqLHFBej9HnQzNM53FwDOWOo1THZeEHpoLdl8c+XkaO5oFI216lBHZc4J3iNhYKaZQN2kG98R0xyzEnb88T28zAEvneruNRAMZcMA8F7N5pivTNFdfkmbiIqHIdiio96iKCJurOWP2No7ay62fnwMGuvCS2i5rvjMqbV+zN10rH+GRu9fNfT3/hnjoBtmCxu7Z+kUhe8rFFT/Tj351+QPfVWANB/vpoitcPaw4Unh8xDcSBjPBaneKkXF0mqy5wkUB2lLWajn4No9E+UH+rkO9TP7CU2Pd9GZ/Q3tN2yQVW6mYPyI4IFIKKWSVvWdy+oZWCnVEc2yniM/1xpegGR6t2Sdiy3x54GAPZi+7iol9cWJpTB3S8llbEdZQbqt1NnVkLfWnWNVas+UVCwEarqpdqdedcRmZk91uSjQzbKiHoYWYJQDP25e6xzx49CniS8aiTpNvIasIWmLE+BwcZQZCdJT1U8moKKCkWUpdTVL7I6mFGspowhB37KRGigWNKm5bDsiQe/eMxBoAkKo9cSohr+wtRFM+jR1DQLpFbNCt+H5sGBhK4ouHyb8E92+IqouEm3mdSzCFtPJKRGqJm2vfCXv73KyVg4f89ZaM4cAcvUVSqv3syLwedEicMiFdI9GVrf89+fDkhpBUAZt507VvNvJZihXoidyXqzI0Nk3z8tyd8jOYc8JcEqdQCmvfbSL5OTyFkiQJIbGFIuKUU985PqExBKnAnzPpDrmYXuzsHeuBRB/qpR3ckZYF2LtmK2OoM/XAszQj5P0EByMZMR2i+Z0Mke4fRiWC9a42zSZIp4TUvwz/tduuObL4+TeatalvfCu6tT3cYue0RYENyhiPmEsexE44yTbXN8d/E3E93dAuxjQK4xjRhAGHye6vha3BsYEXHUEN8sg75yxuYZhmDm8blufzFi6eoM01WINQ0hqY9uJHt9ZyTmFZ0kGTrYzuGfCKW+KOZlmBngmK0BUuddSj8YKLh9gBVPmFAo/kTIFiKOdAMqpIcfOpD0rsuvqOUMInpIq3fissi5Ny7d+Sz/H/72JXJE0cYg2zdgx518Z6DltQUJ387whrcqi+JG986DTpfAmcJCvfhXBprv3jHOnn1hoQG2B6zUUork9lHLBnzjoo3K7XqaP8LwA4j6etvGJSMGs/H2hJdO/v4g= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 822d5cd9-a75e-4919-a082-08db0ff2eaed X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2023 07:53:40.2875 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FUgX7t9nlFBRqAHuzIfpAzgN0PVR+IELHXv45PnZP1wWw8WWpYMuKRc3Hn5O7vBTxoyOp1JeMN5XhtEmNiRQM6f3sQVLoEbjnsaO/1vxjDo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR10MB5993 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230215_235346_314842_455BF39D X-CRM114-Status: GOOD ( 12.67 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The ocelot-switch driver can utilize the phylink_mac_config routine. Move this to the ocelot library location and export the symbol to make this possible. Signed-off-by: Colin Foster --- drivers/net/ethernet/mscc/ocelot.c | 26 ++++++++++++++++++++++++++ drivers/net/ethernet/mscc/ocelot_net.c | 21 +++------------------ include/soc/mscc/ocelot.h | 3 +++ 3 files changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index 9b8403e29445..8292e93a3782 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -809,6 +809,32 @@ static int ocelot_port_flush(struct ocelot *ocelot, int port) return err; } +void ocelot_phylink_mac_config(struct ocelot *ocelot, int port, + unsigned int link_an_mode, + const struct phylink_link_state *state) +{ + struct ocelot_port *ocelot_port = ocelot->ports[port]; + + /* Disable HDX fast control */ + ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, + DEV_PORT_MISC); + + /* SGMII only for now */ + ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, + PCS1G_MODE_CFG); + ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); + + /* Enable PCS */ + ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); + + /* No aneg on SGMII */ + ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); + + /* No loopback */ + ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); +} +EXPORT_SYMBOL_GPL(ocelot_phylink_mac_config); + void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, unsigned int link_an_mode, phy_interface_t interface, diff --git a/drivers/net/ethernet/mscc/ocelot_net.c b/drivers/net/ethernet/mscc/ocelot_net.c index ca4bde861397..590a2b2816ad 100644 --- a/drivers/net/ethernet/mscc/ocelot_net.c +++ b/drivers/net/ethernet/mscc/ocelot_net.c @@ -1675,25 +1675,10 @@ static void vsc7514_phylink_mac_config(struct phylink_config *config, { struct net_device *ndev = to_net_dev(config->dev); struct ocelot_port_private *priv = netdev_priv(ndev); - struct ocelot_port *ocelot_port = &priv->port; - - /* Disable HDX fast control */ - ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, - DEV_PORT_MISC); - - /* SGMII only for now */ - ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, - PCS1G_MODE_CFG); - ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); - - /* Enable PCS */ - ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); - - /* No aneg on SGMII */ - ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); + struct ocelot *ocelot = priv->port.ocelot; + int port = priv->port.index; - /* No loopback */ - ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); + ocelot_phylink_mac_config(ocelot, port, link_an_mode, state); } static void vsc7514_phylink_mac_link_down(struct phylink_config *config, diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index 751d9b250615..87ade87d3540 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -1111,6 +1111,9 @@ int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port, enum devlink_sb_pool_type pool_type, u32 *p_cur, u32 *p_max); +void ocelot_phylink_mac_config(struct ocelot *ocelot, int port, + unsigned int link_an_mode, + const struct phylink_link_state *state); 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Initialize these high speed I/O (HSIO) PLLs when they exist, so that dependent peripherals like QSGMII can function. Signed-off-by: Colin Foster --- drivers/net/dsa/ocelot/felix.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c index d4cc9e60f369..21dcb9cadc12 100644 --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c @@ -1555,6 +1555,9 @@ static int felix_setup(struct dsa_switch *ds) if (err) return err; + if (ocelot->targets[HSIO]) + ocelot_pll5_init(ocelot); + err = ocelot_init(ocelot); if (err) goto out_mdiobus_free; From patchwork Thu Feb 16 07:53:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 13142696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DD5CC6379F for ; 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This is done in the felix_init_structs() function. After this is done, a separate loop will invoke ocelot_init_port() on each port. This causes problems if a user of the felix driver needs to retain some information from the device tree during port initialization. A driver might, for example, need to create call phylink_create() during ocelot_init_port(), which requires a reference to the fwnode_handle. Add a hook from felix into the sub-drivers, where they can optionally grab references to the device_node when needed. Signed-off-by: Colin Foster --- drivers/net/dsa/ocelot/felix.c | 54 +++++++++++++++++++++++++--------- drivers/net/dsa/ocelot/felix.h | 5 ++++ 2 files changed, 45 insertions(+), 14 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c index 21dcb9cadc12..b6e3a88addb8 100644 --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c @@ -1245,7 +1245,8 @@ static int felix_parse_ports_node(struct felix *felix, struct device_node *ports_node, phy_interface_t *port_phy_modes) { - struct device *dev = felix->ocelot.dev; + struct ocelot *ocelot = &felix->ocelot; + struct device *dev = ocelot->dev; struct device_node *child; for_each_available_child_of_node(ports_node, child) { @@ -1285,6 +1286,19 @@ static int felix_parse_ports_node(struct felix *felix, } port_phy_modes[port] = phy_mode; + + if (dsa_is_cpu_port(felix->ds, port) || + !felix->info->parse_port_node) + continue; + + err = felix->info->parse_port_node(ocelot, child, phy_mode, + port); + if (err < 0) { + dev_err(dev, "Unable to create etherdev for port %d\n", + port); + of_node_put(child); + return err; + } } return 0; @@ -1396,8 +1410,7 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports) err = felix_parse_dt(felix, port_phy_modes); if (err) { - kfree(port_phy_modes); - return err; + goto free_port_modes; } for (i = 0; i < TARGET_MAX; i++) { @@ -1406,8 +1419,8 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports) dev_err(ocelot->dev, "Failed to map device memory space: %pe\n", target); - kfree(port_phy_modes); - return PTR_ERR(target); + err = PTR_ERR(target); + goto free_port_modes; } ocelot->targets[i] = target; @@ -1416,8 +1429,7 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports) err = ocelot_regfields_init(ocelot, felix->info->regfields); if (err) { dev_err(ocelot->dev, "failed to init reg fields map\n"); - kfree(port_phy_modes); - return err; + goto free_port_modes; } for (port = 0; port < num_phys_ports; port++) { @@ -1429,8 +1441,8 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports) if (!ocelot_port) { dev_err(ocelot->dev, "failed to allocate port memory\n"); - kfree(port_phy_modes); - return -ENOMEM; + err = -ENOMEM; + goto free_port_modes; } target = felix_request_port_regmap(felix, port); @@ -1438,8 +1450,8 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports) dev_err(ocelot->dev, "Failed to map memory space for port %d: %pe\n", port, target); - kfree(port_phy_modes); - return PTR_ERR(target); + err = PTR_ERR(target); + goto free_port_modes; } ocelot_port->phy_mode = port_phy_modes[port]; @@ -1449,15 +1461,21 @@ static int felix_init_structs(struct felix *felix, int num_phys_ports) ocelot->ports[port] = ocelot_port; } - kfree(port_phy_modes); - if (felix->info->mdio_bus_alloc) { err = felix->info->mdio_bus_alloc(ocelot); if (err < 0) - return err; + goto free_port_modes; } + kfree(port_phy_modes); + return 0; + +free_port_modes: + if (felix->info->phylink_of_cleanup) + felix->info->phylink_of_cleanup(ocelot); + kfree(port_phy_modes); + return err; } static void ocelot_port_purge_txtstamp_skb(struct ocelot *ocelot, int port, @@ -1574,12 +1592,18 @@ static int felix_setup(struct dsa_switch *ds) dsa_switch_for_each_available_port(dp, ds) { ocelot_init_port(ocelot, dp->index); + if (felix->info->phylink_create) + felix->info->phylink_create(ocelot, dp->index); + /* Set the default QoS Classification based on PCP and DEI * bits of vlan tag. */ felix_port_qos_map_init(ocelot, dp->index); } + if (felix->info->phylink_of_cleanup) + felix->info->phylink_of_cleanup(ocelot); + err = ocelot_devlink_sb_register(ocelot); if (err) goto out_deinit_ports; @@ -1604,6 +1628,8 @@ static int felix_setup(struct dsa_switch *ds) ocelot_deinit(ocelot); out_mdiobus_free: + if (felix->info->phylink_of_cleanup) + felix->info->phylink_of_cleanup(ocelot); if (felix->info->mdio_bus_free) felix->info->mdio_bus_free(ocelot); diff --git a/drivers/net/dsa/ocelot/felix.h b/drivers/net/dsa/ocelot/felix.h index d5d0b30c0b75..ffb60bcf1817 100644 --- a/drivers/net/dsa/ocelot/felix.h +++ b/drivers/net/dsa/ocelot/felix.h @@ -58,6 +58,11 @@ struct felix_info { void (*tas_guard_bands_update)(struct ocelot *ocelot, int port); void (*port_sched_speed_set)(struct ocelot *ocelot, int port, u32 speed); + int (*parse_port_node)(struct ocelot *ocelot, + struct device_node *ports_node, + phy_interface_t phy_mode, int port); + int (*phylink_create)(struct ocelot *ocelot, int port); + void (*phylink_of_cleanup)(struct ocelot *ocelot); }; /* Methods for initializing the hardware resources specific to a tagging From patchwork Thu Feb 16 07:53:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 13142697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76602C636CC for ; Thu, 16 Feb 2023 07:53:55 +0000 (UTC) DKIM-Signature: v=1; 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Thu, 16 Feb 2023 07:53:44 +0000 From: Colin Foster To: linux-phy@lists.infradead.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Russell King , Kishon Vijay Abraham I , Vinod Koul , Paolo Abeni , Jakub Kicinski , Eric Dumazet , "David S. Miller" , Florian Fainelli , Andrew Lunn , UNGLinuxDriver@microchip.com, Alexandre Belloni , Claudiu Manoil , Vladimir Oltean , Lee Jones Subject: [RFC v1 net-next 7/7] net: dsa: ocelot_ext: add support for external phys Date: Wed, 15 Feb 2023 23:53:21 -0800 Message-Id: <20230216075321.2898003-8-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230216075321.2898003-1-colin.foster@in-advantage.com> References: <20230216075321.2898003-1-colin.foster@in-advantage.com> X-ClientProxiedBy: BY3PR05CA0019.namprd05.prod.outlook.com (2603:10b6:a03:254::24) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWHPR1001MB2351:EE_|IA1PR10MB5993:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c0e3ce2-439e-49f9-3f9b-08db0ff2ed3f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LuU3L6a5G4gpMJJa5gIrBAc+npbeGvNAd/qfW9cxMGEo+gNgpfnem4QbD2Mo02iiCMEzimDnuLzoSuf02brgonUFy+gQKOeR9LUn/wqaM/FDHXHj2q2adp5WuzUdt8CZOpXWi47h2eXO/RetgpVCOtAAhVFa5qEUo29zp4t2w8iPBuZYE7YTZjjowDVOdkFlo/bhnCs5B2tTpo+YDePgJOkNm3mjRuFbvf+zjGVa7Naswxyi+xDnkXEEyaarGs2VkMAkURgNT7thcWx8fsGqtvmnQrl5GfKKoVfpD9p4A79s1oQEw13GzK44rEXpQhZIvLGgSOjawtoNTWu42wVuFEzxOcQ+LwactXm2BsNBFr/L7t/YHNL0ixnLe/2IhVSYvLUWekJoXTfnPU6LFAhocnOwI/5W8KAPXwu3qeHEOMdRuEUGDGfg+Y0Ge71HP6cl8IRiyCWxXV/tqRCk9pRLkTWLOiBxpId8v2FQWKJAu9v/zDXBSnMMb+rq50y34VOt5+nrWmmHLQMMkhpjf+csmr93sRsptd7FflcCs+E3PdcZbxx9/7xmjO9jwcpKBmMUANr2Ixxb8XgrLfB1vAxQIlmmJinlAbjLIGOI9F0UyZmR3xJEPZhaEzt5BFzB3rGbBZV5bXquCdIRt0AyM9f06tK2xX+sDh9cSuJHz5GNTvAjD+p0D6at4Uy/Y9DE03q6iovirY4eTx0kSIXFRlwP9g== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MWHPR1001MB2351.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(136003)(39830400003)(396003)(366004)(346002)(376002)(451199018)(83380400001)(5660300002)(38350700002)(41300700001)(2906002)(8936002)(38100700002)(2616005)(6506007)(26005)(6512007)(186003)(6666004)(478600001)(66899018)(52116002)(6486002)(30864003)(44832011)(1076003)(86362001)(316002)(66476007)(66946007)(54906003)(4326008)(8676002)(66556008)(7416002)(36756003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ctaF2cFn8buXG/8kHSPVZsZKp4sBgeS36pGUCmoCT9MhYnTZBw3mfXLTgGKwrKOWzuK5s1pIEWebavoP+jVjXvGL0u9GpUQaYVaxDubUbkNYYGILEjTVlqaKecJXd/98LBHtB8oOXHbOTHGaBOOv5cg6VbmPYLjCSIwZ69R33RtsCJmjuvzmWHIJ1e38qncJLjVwSiosvmIS9fTf+0uluia2ktKjApPtcgBfXyekdAZNu3G9RU410GAyQj7wcm6OWY9xw4KH2sXZrZBqBCLsgSV78cdVCucalOqoOqRUOHuGnvqICdhLLl1yR8uRYn0DYT3XhL9GqgufURkG3jfJBofaKexVhVY9G6Nfl00wIkZ/+bCedcMLB0vLQMi5mBND36+IbbsDwUtAJX9hmFpqFZ9R4I/oQkv/Ox6Ap3HEW9WjmEKoHomBkcHnlL7m/W9Y3Ru3E3X0ZRcV5ZrvZgCua8EpxXrcLSlJP6wVEKthk3gCPfsxMWYtnHkZTHU0I+9g6NzjhMwVR0K4oub5eR8i9EjRLdaCnJMfjYvyIyZYZeoHVNBQMtVPJ215XXxe3BWUHyXJ04WC0JoJnfvaZM0E6OqYuMJamaEJ2IHEFiszNb5Mpp+aBR8tbL5WflyFYFYDD/Fij40Edz6c6M+EJdx7BQUYsNYsrpAh3BXSGcpkiDbmd0szvfAu/i1AMqZIbQRuH6ZdCKmdeRWiE8JbV7fvBhKZCVDrDQ39Hck7nRT9oUHI0sSK8e5LikNr21Z+hhcbayCOj5DE4M+wtZ9BnWFtUPiflRXhB+XB7WoeGHyWABpkMpsdTyjGX11InYCIpyaDwxlNLFZRAUnIa+i+2iHeoSpGOvi4mnkUOtNj8aCsoQ6f1+7iFQvkOQa9DwcInh9P1pHqTNvBAkf0IvnOYkf0u4z2+ghcgKoL43955EdX/WHW+oJjgYHIAulxRnPnNXLMEP0weIa8lKnhsxUCAiXmshtLfMUth0XaIfGo+s4nytgrBWpuC8TvUHbDBs00Vh/jfRwH9beM+BNOxkKRFwnwaK4jTWgfBw9vmFxG2OwRxBAHA37vZlJOhGQJ77IsQcgS72bMcVxCwBjtAieUJt+dUakRpgRrKrCee3R91XAH84WVCZoD2Mo+F+9a1H74wePQQ7jDaM71/AlBoZZNgJbc9oydJUOcqncsF2/EYYrMYBNW1abUgMMWmi9caFvVqkifp5nrYbw2imxyAV1XxBSwa4SCBOVjGA2S6RlBx02EUZ5bXb6Q0C8V7zULPretmeSF3sgyZAxhsZjhlkeiGruCseIITTy37d2+5B8HgNd+7uERV/QShAtQm3iTirHB1TXi186fQ2bsgXQf5gSdP3MCvoosJZ9WcQK/2tdSkAggenh07z2CbSXhdgjV+LLmBjygkw4il4C5lBl+hEt1T6GEBKCpVn46cX12TvgcXbY60Fnv8QvkTN/ABkovR6anrMnG26LvfmRzyOlUfYIvs22yw7RFB0pElWH8TS/7m2JqQ+eO2fR+q4dMqDMYg6BnEl9JNAJElCriN5c46REgnnxe7Je+vYe6G3DAFLNjg7bT8pzgUWMVhrwlPY0EXC3TPa88AU6sJLju6TjxfFHB20HIxGwxO4n/yM2ahi28RUJDyGo= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2c0e3ce2-439e-49f9-3f9b-08db0ff2ed3f X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2023 07:53:44.3341 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kyKsNffDssYjTln8wjgxVSZ+4cvNGj8H7H8brpUZRNYxL5f0MMNwB0JGd3m1r71jM5LO/OWWtbDtFZ4hh4XcxhyOm3lOg45tZN1BgVElgMU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR10MB5993 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230215_235351_126012_74EA8ECA X-CRM114-Status: GOOD ( 18.97 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org The VSC7512 has four internal copper ports, and can be configured to work in various configurations with up to six additional ports. Support for the initial four ports was added in commit 3d7316ac81ac ("net: dsa: ocelot: add external ocelot switch control"). This patch adds support for the additional ports. The specific hardware configuration for this development uses a QSGMII link between a VSC7512 and a VSC8514. The VSC8514 offers connection to four RJ45 ports, all of which are verified functional. Signed-off-by: Colin Foster --- drivers/net/dsa/ocelot/felix.h | 1 + drivers/net/dsa/ocelot/ocelot_ext.c | 319 ++++++++++++++++++++++++++-- 2 files changed, 305 insertions(+), 15 deletions(-) diff --git a/drivers/net/dsa/ocelot/felix.h b/drivers/net/dsa/ocelot/felix.h index ffb60bcf1817..fdd402305925 100644 --- a/drivers/net/dsa/ocelot/felix.h +++ b/drivers/net/dsa/ocelot/felix.h @@ -6,6 +6,7 @@ #define ocelot_to_felix(o) container_of((o), struct felix, ocelot) #define FELIX_MAC_QUIRKS OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION +#define OCELOT_EXT_MAC_QUIRKS OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP #define OCELOT_PORT_MODE_NONE 0 #define OCELOT_PORT_MODE_INTERNAL BIT(0) diff --git a/drivers/net/dsa/ocelot/ocelot_ext.c b/drivers/net/dsa/ocelot/ocelot_ext.c index 14efa6387bd7..f10271b973b2 100644 --- a/drivers/net/dsa/ocelot/ocelot_ext.c +++ b/drivers/net/dsa/ocelot/ocelot_ext.c @@ -4,10 +4,13 @@ */ #include +#include +#include #include #include #include #include +#include #include #include "felix.h" @@ -16,20 +19,283 @@ #define OCELOT_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ OCELOT_PORT_MODE_QSGMII) +#define phylink_config_to_ocelot_port(config) \ + container_of(config, struct ocelot_ext_port_priv, phylink_config) +#define phylink_pcs_to_ocelot_port(pl_pcs) \ + container_of(pl_pcs, struct ocelot_ext_port_priv, pcs) + +struct ocelot_ext_port_priv { + struct device_node *node; + struct phylink_config phylink_config; + struct phylink *phylink; + struct ocelot *ocelot; + int chip_port; + struct phylink_pcs pcs; +}; + +struct ocelot_ext_priv { + struct felix felix; + struct ocelot_ext_port_priv *port_priv[VSC7514_NUM_PORTS]; +}; + +static struct ocelot_ext_priv *felix_to_ocelot_ext_priv(struct felix *felix) +{ + return container_of(felix, struct ocelot_ext_priv, felix); +} + static const u32 vsc7512_port_modes[VSC7514_NUM_PORTS] = { OCELOT_PORT_MODE_INTERNAL, OCELOT_PORT_MODE_INTERNAL, OCELOT_PORT_MODE_INTERNAL, OCELOT_PORT_MODE_INTERNAL, - OCELOT_PORT_MODE_NONE, - OCELOT_PORT_MODE_NONE, - OCELOT_PORT_MODE_NONE, - OCELOT_PORT_MODE_NONE, - OCELOT_PORT_MODE_NONE, - OCELOT_PORT_MODE_NONE, - OCELOT_PORT_MODE_NONE, + OCELOT_PORT_MODE_SERDES, + OCELOT_PORT_MODE_SERDES, + OCELOT_PORT_MODE_SERDES, + OCELOT_PORT_MODE_SERDES, + OCELOT_PORT_MODE_SERDES, + OCELOT_PORT_MODE_SGMII, + OCELOT_PORT_MODE_SERDES, +}; + +static void ocelot_ext_phylink_of_cleanup(struct ocelot *ocelot) +{ + struct felix *felix = ocelot_to_felix(ocelot); + struct ocelot_ext_priv *ocelot_ext_priv; + int i; + + ocelot_ext_priv = felix_to_ocelot_ext_priv(felix); + for (i = 0; i < VSC7514_NUM_PORTS; i++) { + struct ocelot_ext_port_priv *port_priv; + + port_priv = ocelot_ext_priv->port_priv[i]; + if (port_priv && port_priv->node) + of_node_put(port_priv->node); + } +} + +static void ocelot_ext_phylink_mac_config(struct phylink_config *config, + unsigned int link_an_mode, + const struct phylink_link_state *state) +{ + struct ocelot_ext_port_priv *priv = + phylink_config_to_ocelot_port(config); + struct ocelot *ocelot = priv->ocelot; + int port = priv->chip_port; + + ocelot_phylink_mac_config(ocelot, port, link_an_mode, state); +} + +static void ocelot_ext_phylink_mac_link_down(struct phylink_config *config, + unsigned int link_an_mode, + phy_interface_t interface) +{ + struct ocelot_ext_port_priv *priv = + phylink_config_to_ocelot_port(config); + struct ocelot *ocelot = priv->ocelot; + struct felix *felix = ocelot_to_felix(ocelot); + int port = priv->chip_port; + + ocelot_phylink_mac_link_down(ocelot, port, link_an_mode, interface, + felix->info->quirks); +} + +static void ocelot_ext_phylink_mac_link_up(struct phylink_config *config, + struct phy_device *phydev, + unsigned int link_an_mode, + phy_interface_t interface, + int speed, int duplex, + bool tx_pause, bool rx_pause) +{ + struct ocelot_ext_port_priv *priv = + phylink_config_to_ocelot_port(config); + struct ocelot *ocelot = priv->ocelot; + struct felix *felix = ocelot_to_felix(ocelot); + int port = priv->chip_port; + + ocelot_phylink_mac_link_up(ocelot, port, phydev, link_an_mode, + interface, speed, duplex, tx_pause, rx_pause, + felix->info->quirks); +} + +static const struct phylink_mac_ops ocelot_ext_phylink_ops = { + .validate = phylink_generic_validate, + .mac_config = ocelot_ext_phylink_mac_config, + .mac_link_down = ocelot_ext_phylink_mac_link_down, + .mac_link_up = ocelot_ext_phylink_mac_link_up, +}; + +static void ocelot_ext_pcs_get_state(struct phylink_pcs *pcs, + struct phylink_link_state *state) +{ + struct ocelot_ext_port_priv *port_priv = + phylink_pcs_to_ocelot_port(pcs); + + /* TODO: Determine state from hardware? */ +} + +static int ocelot_ext_pcs_config(struct phylink_pcs *pcs, unsigned int mode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac) +{ + struct ocelot_ext_port_priv *port_priv = + phylink_pcs_to_ocelot_port(pcs); + + switch (interface) { + case PHY_INTERFACE_MODE_QSGMII: + ocelot_ext_phylink_mac_config(&port_priv->phylink_config, mode, + NULL); + break; + default: + break; + } + + return 0; +} + +static void ocelot_ext_pcs_an_restart(struct phylink_pcs *pcs) +{ + /* TODO: Restart autonegotiaion process */ +} + +static void ocelot_ext_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, + phy_interface_t interface, int speed, + int duplex) +{ + struct ocelot_ext_port_priv *port_priv = + phylink_pcs_to_ocelot_port(pcs); + + ocelot_ext_phylink_mac_link_up(&port_priv->phylink_config, NULL, mode, + interface, speed, duplex, false, false); +} + +static const struct phylink_pcs_ops ocelot_ext_pcs_ops = { + .pcs_get_state = ocelot_ext_pcs_get_state, + .pcs_config = ocelot_ext_pcs_config, + .pcs_an_restart = ocelot_ext_pcs_an_restart, + .pcs_link_up = ocelot_ext_pcs_link_up, }; +static int ocelot_ext_parse_port_node(struct ocelot *ocelot, + struct device_node *ports_node, + phy_interface_t phy_mode, int port) +{ + struct ocelot_ext_port_priv *ocelot_ext_port_priv; + struct felix *felix = ocelot_to_felix(ocelot); + struct ocelot_ext_priv *ocelot_ext_priv; + + ocelot_ext_priv = felix_to_ocelot_ext_priv(felix); + + ocelot_ext_port_priv = devm_kzalloc(ocelot->dev, + sizeof(*ocelot_ext_port_priv), + GFP_KERNEL); + if (!ocelot_ext_port_priv) + return -ENOMEM; + + ocelot_ext_port_priv->ocelot = ocelot; + ocelot_ext_port_priv->chip_port = port; + ocelot_ext_port_priv->pcs.ops = &ocelot_ext_pcs_ops; + + if (!felix->pcs) + felix->pcs = devm_kcalloc(ocelot->dev, felix->info->num_ports, + sizeof(struct phylink_pcs *), + GFP_KERNEL); + + if (!felix->pcs) + return -ENOMEM; + + felix->pcs[port] = &ocelot_ext_port_priv->pcs; + + ocelot_ext_priv->port_priv[port] = ocelot_ext_port_priv; + + ocelot_ext_port_priv->node = of_node_get(ports_node); + + return 0; +} + +static int ocelot_ext_phylink_create(struct ocelot *ocelot, int port) +{ + struct ocelot_ext_port_priv *ocelot_ext_port_priv; + struct felix *felix = ocelot_to_felix(ocelot); + struct ocelot_ext_priv *ocelot_ext_priv; + struct device *dev = ocelot->dev; + struct ocelot_port *ocelot_port; + struct device_node *portnp; + phy_interface_t phy_mode; + struct phylink *phylink; + int err; + + ocelot_ext_priv = felix_to_ocelot_ext_priv(felix); + ocelot_port = ocelot->ports[port]; + ocelot_ext_port_priv = ocelot_ext_priv->port_priv[port]; + + if (!ocelot_ext_port_priv) + return 0; + + portnp = ocelot_ext_port_priv->node; + phy_mode = ocelot_port->phy_mode; + + /* Break out early if we're internal...? */ + if (phy_mode == PHY_INTERFACE_MODE_INTERNAL) + return 0; + + if (phy_mode == PHY_INTERFACE_MODE_QSGMII) + ocelot_port_rmwl(ocelot_port, 0, + DEV_CLOCK_CFG_MAC_TX_RST | + DEV_CLOCK_CFG_MAC_RX_RST, + DEV_CLOCK_CFG); + + if (phy_mode != PHY_INTERFACE_MODE_INTERNAL) { + struct phy *serdes = of_phy_get(portnp, NULL); + + if (IS_ERR(serdes)) { + err = PTR_ERR(serdes); + dev_err_probe(dev, err, + "missing SerDes phys for port %d\n", + port); + return err; + } + + err = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET, phy_mode); + of_phy_put(serdes); + if (err) { + dev_err(dev, + "Could not set SerDes mode on port %d: %pe\n", + port, ERR_PTR(err)); + return err; + } + } + + ocelot_ext_port_priv->phylink_config.dev = dev; + ocelot_ext_port_priv->phylink_config.type = PHYLINK_DEV; + ocelot_ext_port_priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | + MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD; + + __set_bit(ocelot_port->phy_mode, + ocelot_ext_port_priv->phylink_config.supported_interfaces); + + phylink = phylink_create(&ocelot_ext_port_priv->phylink_config, + of_fwnode_handle(portnp), + phy_mode, &ocelot_ext_phylink_ops); + if (IS_ERR(phylink)) { + err = PTR_ERR(phylink); + dev_err(dev, "Could not create phylink (%pe)\n", phylink); + return err; + } + + ocelot_ext_port_priv->phylink = phylink; + + err = phylink_of_phy_connect(phylink, portnp, 0); + if (err) { + dev_err(dev, "Could not connect to PHY: %pe\n", ERR_PTR(err)); + phylink_destroy(phylink); + ocelot_ext_port_priv->phylink = NULL; + return err; + } + + return 0; +} + static const struct ocelot_ops ocelot_ext_ops = { .reset = ocelot_reset, .wm_enc = ocelot_wm_enc, @@ -48,6 +314,7 @@ static const char * const vsc7512_resource_names[TARGET_MAX] = { [QS] = "qs", [QSYS] = "qsys", [ANA] = "ana", + [HSIO] = "hsio", }; static const struct felix_info vsc7512_info = { @@ -56,25 +323,32 @@ static const struct felix_info vsc7512_info = { .map = vsc7514_regmap, .ops = &ocelot_ext_ops, .vcap = vsc7514_vcap_props, + .quirks = OCELOT_EXT_MAC_QUIRKS, .num_mact_rows = 1024, .num_ports = VSC7514_NUM_PORTS, .num_tx_queues = OCELOT_NUM_TC, .port_modes = vsc7512_port_modes, + .parse_port_node = ocelot_ext_parse_port_node, + .phylink_create = ocelot_ext_phylink_create, + .phylink_of_cleanup = ocelot_ext_phylink_of_cleanup, }; static int ocelot_ext_probe(struct platform_device *pdev) { + struct ocelot_ext_priv *ocelot_ext_priv; struct device *dev = &pdev->dev; struct dsa_switch *ds; struct ocelot *ocelot; struct felix *felix; int err; - felix = kzalloc(sizeof(*felix), GFP_KERNEL); - if (!felix) + ocelot_ext_priv = kzalloc(sizeof(*ocelot_ext_priv), GFP_KERNEL); + if (!ocelot_ext_priv) return -ENOMEM; - dev_set_drvdata(dev, felix); + dev_set_drvdata(dev, ocelot_ext_priv); + + felix = &ocelot_ext_priv->felix; ocelot = &felix->ocelot; ocelot->dev = dev; @@ -116,28 +390,43 @@ static int ocelot_ext_probe(struct platform_device *pdev) static int ocelot_ext_remove(struct platform_device *pdev) { - struct felix *felix = dev_get_drvdata(&pdev->dev); + struct ocelot_ext_priv *ocelot_ext_priv = dev_get_drvdata(&pdev->dev); + struct felix *felix; - if (!felix) + if (!ocelot_ext_priv) return 0; + felix = &ocelot_ext_priv->felix; + dsa_unregister_switch(felix->ds); kfree(felix->ds); - kfree(felix); + kfree(ocelot_ext_priv); return 0; } static void ocelot_ext_shutdown(struct platform_device *pdev) { - struct felix *felix = dev_get_drvdata(&pdev->dev); + struct ocelot_ext_priv *ocelot_ext_priv = dev_get_drvdata(&pdev->dev); + struct ocelot_ext_port_priv *port_priv; + struct felix *felix; + int i; - if (!felix) + if (!ocelot_ext_priv) return; + felix = &ocelot_ext_priv->felix; + dsa_switch_shutdown(felix->ds); + for (i = 0; i < felix->info->num_ports; i++) { + port_priv = ocelot_ext_priv->port_priv[i]; + + if (port_priv && port_priv->phylink) + phylink_destroy(port_priv->phylink); + } + dev_set_drvdata(&pdev->dev, NULL); }