From patchwork Thu Feb 16 18:21:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13143659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F189C61DA4 for ; Thu, 16 Feb 2023 18:23:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DT86XPhAZDbJg83H3lXJNVoCItBz2gQpk1qtnvbRrVs=; b=ISK5Cxd9QBZ9RR dElURITH2e3E1XeUo2XJ/cxZx+yPxVm1xLmyz2eWlGpTBCH22GbWTPMqeTaBPtncD4DCGVe5wpRLT SvOZiirVgGyNmrh5YJBAptOSFe9ed6aMy8cHR/d1eHEudq4BPMzP1/sxwTh/2luzkCdezZlrOvzaE Nu1yPnatO5FDVLX8YfFR6EXoe087s0w1ptXf+s34EmnxRSQR9XLmGP5NZB+6S2MBVC3y5fOAbOcea d8umlcGfIbb2c7Zx2PRVQlk0wywYiCXy+Zai2NAxKVdcAKYZ85URdASjgbhaI8C/AWHMzUNfRXdnQ ew+GKhiCSZke4l9X8diA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pSiuJ-00BUok-VX; Thu, 16 Feb 2023 18:23:00 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pSitn-00BURr-Nt for linux-arm-kernel@lists.infradead.org; Thu, 16 Feb 2023 18:22:30 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 421F91042; Thu, 16 Feb 2023 10:23:08 -0800 (PST) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 563FB3F663; Thu, 16 Feb 2023 10:22:24 -0800 (PST) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , Marc Zyngier , Oliver Upton , James Morse Subject: [RFC PATCH 1/3] firmware: smccc: Add support for erratum discovery API Date: Thu, 16 Feb 2023 18:21:59 +0000 Message-Id: <20230216182201.1705406-2-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230216182201.1705406-1-james.morse@arm.com> References: <20230216182201.1705406-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230216_102227_916914_6849571D X-CRM114-Status: GOOD ( 21.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org It is not always possible for the OS to determine if a CPU is affected by a particular erratum. For example, it may depend on an integration choice the chip designer made, or whether firmware has enabled some particular feature. Add support for the SMCCC 'Errata Management Firmware Interface' that lets the OS query firmware for this information. Link: https://developer.arm.com/documentation/den0100/1-0/?lang=en Signed-off-by: James Morse --- arch/arm64/kernel/cpufeature.c | 6 +++ drivers/firmware/smccc/Kconfig | 8 ++++ drivers/firmware/smccc/Makefile | 1 + drivers/firmware/smccc/em.c | 78 +++++++++++++++++++++++++++++++++ include/linux/arm-smccc.h | 28 ++++++++++++ 5 files changed, 121 insertions(+) create mode 100644 drivers/firmware/smccc/em.c diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index a77315b338e6..2eb4d38e491a 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -62,6 +62,7 @@ #define pr_fmt(fmt) "CPU features: " fmt +#include #include #include #include @@ -1036,6 +1037,11 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) */ init_cpu_hwcaps_indirect_list(); + /* + * Early erratum workaround may need to be discovered from firmware. + */ + arm_smccc_em_init(); + /* * Detect and enable early CPU capabilities based on the boot CPU, * after we have initialised the CPU feature infrastructure. diff --git a/drivers/firmware/smccc/Kconfig b/drivers/firmware/smccc/Kconfig index 15e7466179a6..a10a150d49bb 100644 --- a/drivers/firmware/smccc/Kconfig +++ b/drivers/firmware/smccc/Kconfig @@ -23,3 +23,11 @@ config ARM_SMCCC_SOC_ID help Include support for the SoC bus on the ARM SMCCC firmware based platforms providing some sysfs information about the SoC variant. + +config ARM_SMCCC_EM + bool "Errata discovery by ARM SMCCC" + depends on HAVE_ARM_SMCCC_DISCOVERY + default y + help + Include support for querying firmware via SMCCC to determine whether + the CPU is affected by a specific erratum. diff --git a/drivers/firmware/smccc/Makefile b/drivers/firmware/smccc/Makefile index 40d19144a860..39ed128b59b5 100644 --- a/drivers/firmware/smccc/Makefile +++ b/drivers/firmware/smccc/Makefile @@ -2,3 +2,4 @@ # obj-$(CONFIG_HAVE_ARM_SMCCC_DISCOVERY) += smccc.o kvm_guest.o obj-$(CONFIG_ARM_SMCCC_SOC_ID) += soc_id.o +obj-$(CONFIG_ARM_SMCCC_EM) += em.o diff --git a/drivers/firmware/smccc/em.c b/drivers/firmware/smccc/em.c new file mode 100644 index 000000000000..2c66240d8707 --- /dev/null +++ b/drivers/firmware/smccc/em.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Arm Errata Management firmware interface. + * + * This firmware interface advertises support for firmware mitigations for CPU + * errata. It can also be used to discover erratum where the 'configurations + * affected' depends on the integration. + * + * Copyright (C) 2022 ARM Limited + */ + +#define pr_fmt(fmt) "arm_smccc_em: " fmt + +#include +#include +#include +#include + +#include + +#include + +static u32 supported; + +int arm_smccc_em_cpu_features(u32 erratum_id) +{ + struct arm_smccc_res res; + + if (!READ_ONCE(supported)) + return -EOPNOTSUPP; + + arm_smccc_1_1_invoke(ARM_SMCCC_EM_CPU_ERRATUM_FEATURES, erratum_id, 0, &res); + switch (res.a0) { + case SMCCC_RET_NOT_SUPPORTED: + return -EOPNOTSUPP; + case SMCCC_EM_RET_INVALID_PARAMTER: + return -EINVAL; + case SMCCC_EM_RET_UNKNOWN: + return -ENOENT; + case SMCCC_EM_RET_HIGHER_EL_MITIGATION: + case SMCCC_EM_RET_NOT_AFFECTED: + case SMCCC_EM_RET_AFFECTED: + return res.a0; + }; + + return -EIO; +} + +int __init arm_smccc_em_init(void) +{ + u32 major_ver, minor_ver; + struct arm_smccc_res res; + enum arm_smccc_conduit conduit = arm_smccc_1_1_get_conduit(); + + if (conduit == SMCCC_CONDUIT_NONE) + return -EOPNOTSUPP; + + arm_smccc_1_1_invoke(ARM_SMCCC_EM_VERSION, &res); + if (res.a0 == SMCCC_RET_NOT_SUPPORTED) + return -EOPNOTSUPP; + + major_ver = PSCI_VERSION_MAJOR(res.a0); + minor_ver = PSCI_VERSION_MINOR(res.a0); + if (major_ver != 1) + return -EIO; + + arm_smccc_1_1_invoke(ARM_SMCCC_EM_FEATURES, + ARM_SMCCC_EM_CPU_ERRATUM_FEATURES, &res); + if (res.a0 == SMCCC_RET_NOT_SUPPORTED) + return -EOPNOTSUPP; + + pr_info("SMCCC Errata Management Interface v%d.%d\n", + major_ver, minor_ver); + + WRITE_ONCE(supported, 1); + + return 0; +} diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 220c8c60e021..cc2e38ce8707 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -182,6 +182,25 @@ ARM_SMCCC_OWNER_STANDARD, \ 0x53) +/* Errata Management calls (defined by ARM DEN0100) */ +#define ARM_SMCCC_EM_VERSION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0xF0) + +#define ARM_SMCCC_EM_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0xF1) + +#define ARM_SMCCC_EM_CPU_ERRATUM_FEATURES \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_STANDARD, \ + 0xF2) + /* * Return codes defined in ARM DEN 0070A * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C @@ -191,6 +210,15 @@ #define SMCCC_RET_NOT_REQUIRED -2 #define SMCCC_RET_INVALID_PARAMETER -3 +/* + * Return codes defined in ARM DEN 0100 + */ +#define SMCCC_EM_RET_HIGHER_EL_MITIGATION 3 +#define SMCCC_EM_RET_NOT_AFFECTED 2 +#define SMCCC_EM_RET_AFFECTED 1 +#define SMCCC_EM_RET_INVALID_PARAMTER -2 +#define SMCCC_EM_RET_UNKNOWN -3 + #ifndef __ASSEMBLY__ #include From patchwork Thu Feb 16 18:22:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13143660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD2C2C636CC for ; Thu, 16 Feb 2023 18:24:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9ZRneN6v3sshk35ZEx6i9ovpMWR66K995eJWANHUzWI=; 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Thu, 16 Feb 2023 10:22:26 -0800 (PST) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , Marc Zyngier , Oliver Upton , James Morse Subject: [RFC PATCH 2/3] arm64: cputype: Add new part numbers for Cortex-X3, and Neoverse-V2 Date: Thu, 16 Feb 2023 18:22:00 +0000 Message-Id: <20230216182201.1705406-3-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230216182201.1705406-1-james.morse@arm.com> References: <20230216182201.1705406-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230216_102231_129165_132C0AB3 X-CRM114-Status: UNSURE ( 7.80 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org New CPUs have new errata. Add the new partnumbers. Signed-off-by: James Morse --- Cortex-X3: https://developer.arm.com/documentation/101593/0102/?lang=en Neoverse-V2: https://developer.arm.com/documentation/102375/0002/?lang=en --- arch/arm64/include/asm/cputype.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 683ca3af4084..1a2c55e172e8 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -84,6 +84,8 @@ #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B +#define ARM_CPU_PART_CORTEX_X3 0xD4E +#define ARM_CPU_PART_NEOVERSE_V2 0xD4F #define APM_CPU_PART_POTENZA 0x000 @@ -149,6 +151,8 @@ #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) +#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3) +#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) From patchwork Thu Feb 16 18:22:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Morse X-Patchwork-Id: 13143661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42483C61DA4 for ; Thu, 16 Feb 2023 18:24:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=QN47W+lBPpJU1iLbUwuReJZKzSAZ8/X1l5iqC9rpPJw=; b=cXfz4UcbwhBI4I yviRsaZrYvh1UtUCyVfEFoe1X8d9V38XkLPntzi0+BAWxeYchBg+v8AOYYn/oMv4w7Ctb8E8796/T Com2xjf3Yps5YbGsDmKHRERa/nqj6JiTKVv1aaxe8eJQMvrzctTM81POky6iUtMMOS762iVwPCOqJ 48IoakgFYaA2jKKRe0Tkwb0b9RwJmi4Lh1pM/ZqXBJjFBmFPV1MVTbRQr4LRkp8gA3bg0ecHKeaIo B0yJDeBlNC5a3hFEptGLK6WaJWag9YcRMPLGU9/sqR02Nq85E3DWH3KZNdGXlg5aVtalhjnAUPM9K yjnIQjlANGLOP+lNXEeQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pSivB-00BVSW-TA; Thu, 16 Feb 2023 18:23:54 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pSits-00BUVj-7V for linux-arm-kernel@lists.infradead.org; Thu, 16 Feb 2023 18:22:34 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C5E7A16A3; Thu, 16 Feb 2023 10:23:12 -0800 (PST) Received: from eglon.cambridge.arm.com (eglon.cambridge.arm.com [10.1.196.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BFC5B3F663; Thu, 16 Feb 2023 10:22:28 -0800 (PST) From: James Morse To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , Marc Zyngier , Oliver Upton , James Morse Subject: [RFC PATCH 3/3] arm64: errata: Disable FWB on parts with non-ARM interconnects Date: Thu, 16 Feb 2023 18:22:01 +0000 Message-Id: <20230216182201.1705406-4-james.morse@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230216182201.1705406-1-james.morse@arm.com> References: <20230216182201.1705406-1-james.morse@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230216_102232_396087_2AAF469D X-CRM114-Status: GOOD ( 26.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Force Write Back (FWB) allows the hypervisor to force non-cacheable accesses made by a guest to be cacheable. This saves the hypervisor from doing cache maintenance on all pages the guest can access, to ensure the guest doesn't see stale (and possibly sensitive) data when making a non-cacheable access. When stage1 translation is disabled, the SCTRL_E1.I bit controls the attributes used for instruction fetch, one of the options results in a non-cacheable access. A whole host of CPUs missed the FWB override in this case, meaning a KVM guest could fetch stale/junk data instead of instructions. The workaround is to always do the cache maintenance. These parts don't have fine-grained-traps, so it isn't feasible to detect the guest disabling the MMU. Instead, disable FWB on the host. While the CPUs are affected, this erratum doesn't occur on parts using Arm's CMN interconnects. Use the Errata Management API to discover whether this CPU is affected. Because guest execution is compromised, the workaround is enabled by default. If the Errata Management API isn't implemented by firmware, the workaround will be enabled. If a target platform is not affected, and it isn't possible to add support for the Errata Management API, the erratum can be disabled in Kconfig. Signed-off-by: James Morse --- Documentation/arm64/silicon-errata.rst | 18 +++++++ arch/arm64/Kconfig | 27 ++++++++++ arch/arm64/kernel/cpufeature.c | 71 +++++++++++++++++++++++++- 3 files changed, 115 insertions(+), 1 deletion(-) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index ec5f889d7681..d6ca86ebc7af 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -106,6 +106,10 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A78 | #2712571 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A78C | #2712575,2712572| ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 | @@ -120,12 +124,20 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A710 | #2701952 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X1 | #2712571 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X2 | #2701952 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X3 | #2701951 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1349291 | N/A | @@ -138,6 +150,12 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-N2 | #2728475 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-V1 | #2701953 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-V2 | #2719103 | ARM64_ERRATUM_2701951 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #841119,826419 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c5ccca26a408..adc46e82cee6 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -986,6 +986,33 @@ config ARM64_ERRATUM_2645198 If unsure, say Y. +config ARM64_ERRATUM_2701951 + bool "ARM CPUs: 2701951: disable FWB on affected parts" + select ARM_SMCCC_EM + default y + help + This option adds the workaround for multiple ARM errata titled + "The core might fetch stale instruction from memory when both Stage 1 + Translation and Instruction Cache are Disabled with Stage 2 forced + Write-Back". + This affects Cortex cores: A78, A78C, A710, X1, X2, X3, and Neoverse + cores: V1, V2 and N2. + + Affected cores fail to apply the FWB override to instruction fetch + when stage1 translation is disabled, and SCTLR_EL1.I is clear. This + results in stale data being fetched and executed. Only CPUs that are + connected to a non-Arm interconnect will exhibit symptoms due to this + errata. + + Work around this problem in the driver by disabling FWB on affected + parts. The SMCCC Errata Management API is used to query firmware to + learn if the part is affected. + + If the SMCCC Errata Management API is not implemented on a platform + with an affected core, the workaround will be applied. + + If unsure, say Y. + config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 2eb4d38e491a..1d7156e75468 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1574,6 +1574,75 @@ static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, return ctr & BIT(CTR_EL0_DIC_SHIFT); } +static bool has_stage2_fwb(const struct arm64_cpu_capabilities *entry, + int scope) +{ + bool has_feature = has_cpuid_feature(entry, scope); + + /* List of CPUs which may have broken FWB support. */ + static const struct midr_range cpus[] = { +#ifdef CONFIG_ARM64_ERRATUM_2701951 + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), + MIDR_RANGE(MIDR_CORTEX_X3, 0, 0, 1, 1), + MIDR_RANGE(MIDR_NEOVERSE_V1, 0, 0, 1, 1), + MIDR_RANGE(MIDR_NEOVERSE_V2, 0, 0, 0, 1), + MIDR_RANGE(MIDR_NEOVERSE_N2, 0, 0, 0, 2), +#endif + { /* sentinel */ }, + }; + + if (!has_feature) + return false; + + if (is_midr_in_range_list(read_cpuid_id(), cpus)) { + int i; + bool fwb_broken = true; + + /* + * List of erratum numbers for these CPUs. + * It isn't possible to match these to their CPUs, as A78C has + * two erratum numbers. The errata management API will return + * 'UNKNOWN' for an erratum it doesn't recognise. + */ + static const u32 erratum_nums[] = { + 2701951, + 2701952, + 2701953, + 2712571, + 2712572, + 2712575, + 2719103, + 2728475, + }; + + /* + * The CPU is affected, but what about this configuration? + * Only firmware has the answer. Assume the part is affected, + * and query firmware for the set of erratum numbers. If one + * returns not-affected, the workaround isn't needed. + */ + for (i = 0; i < ARRAY_SIZE(erratum_nums); i++) { + int state = arm_smccc_em_cpu_features(erratum_nums[i]); + + if (state == SMCCC_EM_RET_NOT_AFFECTED) { + fwb_broken = false; + break; + } + } + + if (fwb_broken) { + pr_info_once("%s disabled due to erratum #2701951\n", entry->desc); + return false; + } + } + + return has_feature; +} + static bool __maybe_unused has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) { @@ -2365,7 +2434,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .field_pos = ID_AA64MMFR2_EL1_FWB_SHIFT, .field_width = 4, .min_field_value = 1, - .matches = has_cpuid_feature, + .matches = has_stage2_fwb, }, { .desc = "ARMv8.4 Translation Table Level",