From patchwork Fri Feb 17 21:26:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Asmaa Mnebhi X-Patchwork-Id: 13145278 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A187C05027 for ; Fri, 17 Feb 2023 21:27:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229847AbjBQV1C (ORCPT ); Fri, 17 Feb 2023 16:27:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229664AbjBQV1B (ORCPT ); Fri, 17 Feb 2023 16:27:01 -0500 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2088.outbound.protection.outlook.com [40.107.96.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33DFB5BD8B; Fri, 17 Feb 2023 13:27:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lGoxpVJUgVC6dgFNsT+wVGw8x+EvRGLdr51zrJqOM3dbyss2+pyGuH2ZvfQyAKhXsX/9NAZPEB5YlV7jqskEItybCuOGwWZoz3ZQp0zrVH4gXOmJqOaKwNIwPe09C9W7VYKpRih35qy6Ev3yw+xH52Vm4pF2L4rNIr8dRTNHPxoMrY28ikHOM3YRVBEnrW5CNYlQkwqS5X/sAoWZKH3WruR7mZsfj9Fa3UmhonsQY0sVGlMiVXZpYgRAuqQorrFCcqFCzrCmmJG4UTILLfTqHYfq5ipKrjJ0YGZaxdGUyfUdkrVEIqfLt96cjA2quQyvw16EdNYkXV5hNx+R7j2+0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=y8jmPLxoASWvpITD03Bk9a6gqoWc5V0f3A2QgRe1kyo=; b=NvKeZKCIQ6SJyr7/tfW+2Ybs+jO+dwNYjIqfZ+fuGeds8mEiQUc/wuTvSkMkzOfp/SYC7KzUZ3RxFF77gc9VMgjKU6xy3ZqJAEXAOK0qsAok5wNKeT3iZO525CpoZiVPrAy3h7QQBanhenhCNodPjonCPwiCg18bJL4VxhN0xjtV34327uRVbZlopzGGCFgf/96y8ke4X6D8dskT75yD9Vezxh5agfnRpzh846wEYoneHZSE6q2qDRtuld9rfi36UawXPzwi9DzWv9XFi6O1xgjZixRQc2w0b+a9XPJIY7MuoYhXqJRj3TIvnos0ZViNX/TyTcisrC8xvBI7+ZoUDA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=y8jmPLxoASWvpITD03Bk9a6gqoWc5V0f3A2QgRe1kyo=; b=FuX/y+FK3Qihdawdms7vUP5cUnJC1WDZ4NoIzpULaKNsTfLKfgg/pO3T/QGvNQXM+uH70HD13ajmSFxvkRvCSJAyHbmtFSS46QF+tfROZxShWXg/qLx/cqh6QpEonCmSjQGYklWEHW5tR9Spsno2jSS3FU42rKKGRUkn+yRuEyU2xYARhUrNoZRU9/me9/r0MVQuR6kXip/cToIJQg+ZhrGcHPo0L3J0zcgG/zSXjCAOLq3l/ks6n4nl7ztq0PWDMRdxN91ti8PEeUvFsBcfoc6X7KZZYxdypwZVCZQSVy8B2qEXKFzSrSSuPYzxNvM+2LAmq0iDduCoRV4ucyBN3Q== Received: from DM6PR08CA0018.namprd08.prod.outlook.com (2603:10b6:5:80::31) by CH2PR12MB4924.namprd12.prod.outlook.com (2603:10b6:610:6b::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6111.15; Fri, 17 Feb 2023 21:26:58 +0000 Received: from DM6NAM11FT044.eop-nam11.prod.protection.outlook.com (2603:10b6:5:80:cafe::6c) by DM6PR08CA0018.outlook.office365.com (2603:10b6:5:80::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6111.15 via Frontend Transport; Fri, 17 Feb 2023 21:26:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by DM6NAM11FT044.mail.protection.outlook.com (10.13.173.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.22 via Frontend Transport; Fri, 17 Feb 2023 21:26:57 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 17 Feb 2023 13:26:57 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 17 Feb 2023 13:26:56 -0800 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Fri, 17 Feb 2023 13:26:56 -0800 From: Asmaa Mnebhi To: , , , , , CC: Asmaa Mnebhi Subject: [PATCH v4 1/2] gpio: gpio-mlxbf3: Add gpio driver support Date: Fri, 17 Feb 2023 16:26:50 -0500 Message-ID: <28f0d670407c127614b64d9c382b11c795f5077d.1676668853.git.asmaa@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT044:EE_|CH2PR12MB4924:EE_ X-MS-Office365-Filtering-Correlation-Id: 4cb1f5f2-c2ac-478e-14f7-08db112db31b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4kAfgZ8UTeCAX/8Ol9bYXrkb+ShECD3/6G3PgAYmmO2GPx5G57KrtA38zJ28jLNj8sgpE4sYB2D/9nNnnoJ54Gu/4pbMbql4ytIT/BNvPrrc+xA6r2HMArdTluXl3z+Ve+z/uMYZS9Qi90KWyumo6pjA4rjMa+0SwTeekvpFLhtoaGn/+NMRcNaQ99SX9lYzpudRBZO0o2/eLNmsUcaiwMBv6g4PYqJhjwUd3wbUgQ8Yr93itQoDozBZQtdDpn1cqOJTGIUohV7UT6XRhtbLPT8XqoxEXPjXa6BjFgagJH+61RUbmNqkGeM4Unkd7bjh7FshmDCOkhNdrUKcfrTa39wC7Fzbj0IPjjCyui60pnw81zGIYCRn6quWVUR1vOq90cGztcwlzbW4i0wpTKs2VfXY8HXILOxK8oPpfghCO1xJs/0uJzzsAEczgQkMN4gCHpGGYWNyU4cfUKQIxtQl1j4MkB7jhp85kSAMTF1q8wOC3VwK4cO6jz9F7JC4cz3tKSWqwPByEuwutNQHlRNtSfrETi/hnDdqtEXmhbxsCcVBs5CB+eTg+B5qLo8MTpdNbkLoC8dtY0w2y9CEtjf1ueWhSAymKb5oHSJybkurTMZ321x1KuCmzSws1r+0wErfuEcBoYAsLQ4phT58+Lk2kKBKUukFEYBN75SuXa6WqWUuRREZsYvio148hwkfnFUByRJ7NvCoQZEkiNcylq6zxQ== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(346002)(136003)(376002)(396003)(39860400002)(451199018)(40470700004)(36840700001)(46966006)(7636003)(47076005)(2616005)(83380400001)(4326008)(86362001)(426003)(5660300002)(336012)(41300700001)(36860700001)(8676002)(40480700001)(7696005)(36756003)(70206006)(70586007)(82310400005)(110136005)(316002)(40460700003)(478600001)(8936002)(107886003)(2906002)(26005)(186003)(356005)(82740400003)(6666004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Feb 2023 21:26:57.7904 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cb1f5f2-c2ac-478e-14f7-08db112db31b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4924 Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Add support for the BlueField-3 SoC GPIO driver. This driver configures and handles GPIO interrupts. It also enables a user to manipulate certain GPIO pins via libgpiod tools or other kernel drivers. The usables pins are defined via the gpio-reserved-ranges property. Signed-off-by: Asmaa Mnebhi --- drivers/gpio/Kconfig | 12 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-mlxbf3.c | 230 +++++++++++++++++++++++++++++++++++++ 3 files changed, 243 insertions(+) create mode 100644 drivers/gpio/gpio-mlxbf3.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ec7cfd4f52b1..5cddcb56353d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1534,6 +1534,18 @@ config GPIO_MLXBF2 help Say Y here if you want GPIO support on Mellanox BlueField 2 SoC. +config GPIO_MLXBF3 + tristate "Mellanox BlueField 3 SoC GPIO" + depends on (MELLANOX_PLATFORM && ARM64 && ACPI) || (64BIT && COMPILE_TEST) + select GPIO_GENERIC + help + Say Y if you want GPIO support on Mellanox BlueField 3 SoC. + This GPIO controller supports interrupt handling and enables the + manipulation of certain GPIO pins. + This controller should be used in parallel with pinctrl-mlxbf to + control the desired gpios. + This driver can also be built as a module called mlxbf3-gpio. + config GPIO_ML_IOH tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support" depends on X86 || COMPILE_TEST diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 010587025fc8..76545ca31457 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_GPIO_MERRIFIELD) += gpio-merrifield.o obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o obj-$(CONFIG_GPIO_MLXBF) += gpio-mlxbf.o obj-$(CONFIG_GPIO_MLXBF2) += gpio-mlxbf2.o +obj-$(CONFIG_GPIO_MLXBF3) += gpio-mlxbf3.o obj-$(CONFIG_GPIO_MM_LANTIQ) += gpio-mm-lantiq.o obj-$(CONFIG_GPIO_MOCKUP) += gpio-mockup.o obj-$(CONFIG_GPIO_MOXTET) += gpio-moxtet.o diff --git a/drivers/gpio/gpio-mlxbf3.c b/drivers/gpio/gpio-mlxbf3.c new file mode 100644 index 000000000000..cdc93c8e77ff --- /dev/null +++ b/drivers/gpio/gpio-mlxbf3.c @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause +/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * There are 2 YU GPIO blocks: + * gpio[0]: HOST_GPIO0->HOST_GPIO31 + * gpio[1]: HOST_GPIO32->HOST_GPIO55 + */ +#define MLXBF3_GPIO_MAX_PINS_PER_BLOCK 32 + +/* + * fw_gpio[x] block registers and their offset + */ +#define MLXBF_GPIO_FW_OUTPUT_ENABLE_SET 0x04 +#define MLXBF_GPIO_FW_DATA_OUT_SET 0x08 +#define MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR 0x18 +#define MLXBF_GPIO_FW_DATA_OUT_CLEAR 0x1c +#define MLXBF_GPIO_CAUSE_RISE_EN 0x28 +#define MLXBF_GPIO_CAUSE_FALL_EN 0x2c +#define MLXBF_GPIO_READ_DATA_IN 0x30 + +#define MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x00 +#define MLXBF_GPIO_CAUSE_OR_EVTEN0 0x14 +#define MLXBF_GPIO_CAUSE_OR_CLRCAUSE 0x18 + +struct mlxbf3_gpio_context { + struct gpio_chip gc; + + /* YU GPIO block address */ + void __iomem *gpio_io; + + /* YU GPIO cause block address */ + void __iomem *gpio_cause_io; +}; + +static void mlxbf3_gpio_irq_enable(struct irq_data *irqd) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(irqd); + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); + + val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + val |= BIT(offset); + writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); +} + +static void mlxbf3_gpio_irq_disable(struct irq_data *irqd) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(irqd); + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + val &= ~BIT(offset); + writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); +} + +static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr) +{ + struct mlxbf3_gpio_context *gs = ptr; + struct gpio_chip *gc = &gs->gc; + unsigned long pending; + u32 level; + + pending = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0); + writel(pending, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); + + for_each_set_bit(level, &pending, gc->ngpio) + generic_handle_domain_irq(gc->irq.domain, level); + + return IRQ_RETVAL(pending); +} + +static int +mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); + int offset = irqd_to_hwirq(irqd); + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags); + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_BOTH: + val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + val |= BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + val |= BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + break; + case IRQ_TYPE_EDGE_RISING: + val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + val |= BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + break; + case IRQ_TYPE_EDGE_FALLING: + val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + val |= BIT(offset); + writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + break; + default: + return -EINVAL; + } + + raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); + + irq_set_handler_locked(irqd, handle_simple_irq); + + return 0; +} + +static const struct irq_chip gpio_mlxbf3_irqchip = { + .name = "MLNXBF33", + .irq_set_type = mlxbf3_gpio_irq_set_type, + .irq_enable = mlxbf3_gpio_irq_enable, + .irq_disable = mlxbf3_gpio_irq_disable, +}; + +static int +mlxbf3_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mlxbf3_gpio_context *gs; + struct gpio_irq_chip *girq; + struct gpio_chip *gc; + unsigned int npins; + int ret, irq; + + gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL); + if (!gs) + return -ENOMEM; + + gs->gpio_io = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(gs->gpio_io)) + return PTR_ERR(gs->gpio_io); + + gs->gpio_cause_io = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(gs->gpio_cause_io)) + return PTR_ERR(gs->gpio_cause_io); + + npins = MLXBF3_GPIO_MAX_PINS_PER_BLOCK; + device_property_read_u32(dev, "npins", &npins); + + gc = &gs->gc; + + ret = bgpio_init(gc, dev, 4, + gs->gpio_io + MLXBF_GPIO_READ_DATA_IN, + gs->gpio_io + MLXBF_GPIO_FW_DATA_OUT_SET, + gs->gpio_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR, + gs->gpio_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET, + gs->gpio_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0); + + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + + gc->ngpio = npins; + gc->owner = THIS_MODULE; + + irq = platform_get_irq(pdev, 0); + if (irq >= 0) { + girq = &gs->gc.irq; + gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip); + girq->default_type = IRQ_TYPE_NONE; + /* This will let us handle the parent IRQ in the driver */ + girq->num_parents = 0; + girq->parents = NULL; + girq->parent_handler = NULL; + + /* + * Directly request the irq here instead of passing + * a flow-handler because the irq is shared. + */ + ret = devm_request_irq(dev, irq, mlxbf3_gpio_irq_handler, + IRQF_SHARED, dev_name(dev), gs); + if (ret) + return dev_err_probe(dev, ret, "failed to request IRQ"); + } + + platform_set_drvdata(pdev, gs); + + ret = devm_gpiochip_add_data(dev, &gs->gc, gs); + if (ret) + dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n"); + + return 0; +} + +static const struct acpi_device_id __maybe_unused mlxbf3_gpio_acpi_match[] = { + { "MLNXBF33", 0 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, mlxbf3_gpio_acpi_match); + +static struct platform_driver mlxbf3_gpio_driver = { + .driver = { + .name = "mlxbf3_gpio", + .acpi_match_table = mlxbf3_gpio_acpi_match, + }, + .probe = mlxbf3_gpio_probe, +}; +module_platform_driver(mlxbf3_gpio_driver); + +MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver"); +MODULE_AUTHOR("Asmaa Mnebhi "); +MODULE_LICENSE("Dual BSD/GPL"); From patchwork Fri Feb 17 21:26:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Asmaa Mnebhi X-Patchwork-Id: 13145280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DB39C636D7 for ; Fri, 17 Feb 2023 21:27:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229903AbjBQV1T (ORCPT ); Fri, 17 Feb 2023 16:27:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229922AbjBQV1P (ORCPT ); Fri, 17 Feb 2023 16:27:15 -0500 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2058.outbound.protection.outlook.com [40.107.223.58]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37D956568A; Fri, 17 Feb 2023 13:27:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=POQmsL9Djgv7IYnxqlQTKFktawfISxF+6aXx2n/umy3zmGLyN+lKVBncN78pAaAzUzE2u7hfQK9uiZOMV+81Xqm9o8xlX07uzhrJKxBEleCAPsG1tnky/7o8DNcQR7YhDCqxZVAhYWy/F1d+DERhjvZqRu5K0NGj6+LdhkyAbGdKjxeVO4DnMm/dz5JZoPnzOAXOmwZY9uoR6ocevrYhKpTt/4zb/vKVSKsWowCiY5mg0D3dnjugKRqE6AqwPeJ3M2Hb9mziygjg7DX7WF69O2FwnF5/Wb0QT3+z7Lh11uXMuN6wo1l5WMjejbg+ZQxAoTeRiXqL0jEj1GX1sDMBhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MllLApfvmXP1g5oiy+++fkI/8ru63KVX1M4F6wYBq1U=; b=f/2iADYI1C2yKwNirIIiFVz1tAjSlRVjUm+Sh23ulY10t1/j1GVi4OUYJCOmJNa0cQUMCjUY3g52UTObKxilXtHten9CUCqbbKy+9P3pkfBepNfD6eQNkxqPzsfYhwcFjgTyG8E+hBrif10eXjJrWXbcd5bIuOTYsh+JYTfjXfw1PsspyOUX83XVP+0yMmocKNSOACTo7YQdCFCBR4UN7iQLoxttYXBTGuDvHLULSgn6e2G9dnlzH9vgtttlzdIaPZxlRk4kSUMq4Dimk7TQixG/JRiLcHR3ptOkY4YCgAgYrb1DIjpR188VczmEhdRAxG2meeaH05IQfDQrnGVI9Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MllLApfvmXP1g5oiy+++fkI/8ru63KVX1M4F6wYBq1U=; b=H/9noGeKytlddDSmlh29H/tM4Zz+Oe3YSEJraHKMQ2Tm4UiapZAD2D62EmjJ22G+OyKbSif3w0wCjGQeRVlykLRpWHk9f11aqBorLAUXeAGdibuRe4WlIusTjQi4thVzC579Q7WToc3xAW6ucFH9T8W/Lroj8AYYlqkMinotOzDMeVLCcu3SU05PPlEoGFXd/x6GLJ1lf32TTW1Snmw9qFZEdQ1QcKNsW3xaCR5uTbXfiVx7H0qgxbRLa4Dir8X+5v86dU4Zck+g1JlI3cM9voIhOC6ffRx+rBBmA++FwjvJ/EfA0FziaKxzw5P0Sj/k9VxtwiZmoaymrZ/l4rcroQ== Received: from BN0PR04CA0209.namprd04.prod.outlook.com (2603:10b6:408:e9::34) by BL0PR12MB4851.namprd12.prod.outlook.com (2603:10b6:208:1c1::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6111.13; Fri, 17 Feb 2023 21:27:07 +0000 Received: from BN8NAM11FT078.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e9:cafe::a5) by BN0PR04CA0209.outlook.office365.com (2603:10b6:408:e9::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6111.15 via Frontend Transport; Fri, 17 Feb 2023 21:27:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BN8NAM11FT078.mail.protection.outlook.com (10.13.176.251) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6111.17 via Frontend Transport; Fri, 17 Feb 2023 21:27:06 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 17 Feb 2023 13:26:59 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 17 Feb 2023 13:26:59 -0800 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Fri, 17 Feb 2023 13:26:58 -0800 From: Asmaa Mnebhi To: , , , , , , CC: Asmaa Mnebhi Subject: [PATCH v4 2/2] pinctrl: pinctrl-mlxbf: Add pinctrl driver support Date: Fri, 17 Feb 2023 16:26:51 -0500 Message-ID: <4cda8cfc37fb15a0c3b180ab4c34a6f6f859fe3c.1676668853.git.asmaa@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT078:EE_|BL0PR12MB4851:EE_ X-MS-Office365-Filtering-Correlation-Id: 14398248-0b1f-4bac-6599-08db112db87f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WtZWgXaHX5ILFFfZfNsVZdhm/IcX7NBCEOU2CTDbZ2R7nFQuNGdLA/wqe6xtJx3eZDNbekYjFCWJhFOEwknp7gPpKemiqwfp4l7jYvTtkdvqVYzgjkXz95rpfcHXLTMhrbuVUSfp0jzr7jp6QBY6mHidNSnBoQ0pWPgRs37WJh45MWGWpsrgiJFItDFfKFX2VOdtIX2ScsseVcEjyoAZRsHgDQuICze7Jdrnx44FNcydhRfudoVBocgYHMm+mHk/MTKj17/69l3Lw7MhcvU+C8tWbzKwWUe63DrxSEoipI9qQ0bID7LD/C9rYsyfsb9R9Gvl5DXLKPxkq1TET/P4XEDsn3Rkqmv0xNE0zdCpVIdo88DCgrdOaO12WDoNG9w6eJ9qmwoW/nIYYbu3W95mQaXzHbZn+qzfAFuymyYD7i1sI9Xb4/81VGOyDTNqsQEOWzwGDccxtp+N/Q+DFG/Kyuz7gwxZSDQOgL+WL1Omwb7ch/VHHdh3YheSYqa/Dcx9G6KNmwfhqGkTH+CGKzReroAKBNfNi6IYRcqRzc9pFSSDLI4q7JjL1Xk/nM+nLCnZn33ubSzXOuX/22Vg2DRPtaIXDspSV69b+8jcR8quxTFaf89/8Plc+T0sg/7jMsv/vUnqA2NAI8Qgk5fYIn6IGtBK4KTVqVbuA2qBvmBFLIE= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(396003)(39860400002)(346002)(376002)(136003)(451199018)(36840700001)(46966006)(40480700001)(83380400001)(2616005)(86362001)(2906002)(336012)(82310400005)(36756003)(186003)(7696005)(107886003)(6666004)(26005)(478600001)(36860700001)(356005)(47076005)(7636003)(426003)(82740400003)(4326008)(41300700001)(5660300002)(8936002)(30864003)(70206006)(70586007)(8676002)(110136005)(316002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Feb 2023 21:27:06.7583 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14398248-0b1f-4bac-6599-08db112db87f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT078.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4851 Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org NVIDIA BlueField-3 SoC has a few pins that can be used as GPIOs or take the default hardware functionality. Add a driver for the pinmuxing. Signed-off-by: Asmaa Mnebhi --- drivers/pinctrl/Kconfig | 14 ++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-mlxbf.c | 338 ++++++++++++++++++++++++++++++++ 3 files changed, 353 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-mlxbf.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7d5f5458c72e..900fa17635c9 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -523,6 +523,20 @@ config PINCTRL_ZYNQMP This driver can also be built as a module. If so, the module will be called pinctrl-zynqmp. +config PINCTRL_MLXBF + tristate "NVIDIA BlueField-3 SoC Pinctrl driver" + depends on (MELLANOX_PLATFORM && ARM64) || (64BIT && COMPILE_TEST) + select PINMUX + select GPIOLIB + select GPIOLIB_IRQCHIP + select GPIO_MLXBF3 + help + Say Y to select the pinctrl driver for BlueField-3 SoCs. + This pin controller works hand in hand with the gpio-mlxbf3 + driver and allows selecting the mux function for each + pin. This driver can also be built as a module called + pinctrl-mlxbf. + source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d5939840bb2a..67252469e76b 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o obj-$(CONFIG_PINCTRL_MCP23S08_SPI) += pinctrl-mcp23s08_spi.o obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o +obj-$(CONFIG_PINCTRL_MLXBF) += pinctrl-mlxbf.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o diff --git a/drivers/pinctrl/pinctrl-mlxbf.c b/drivers/pinctrl/pinctrl-mlxbf.c new file mode 100644 index 000000000000..95fc5b8f2dc7 --- /dev/null +++ b/drivers/pinctrl/pinctrl-mlxbf.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause +/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#define MLXBF_GPIO0_FW_CONTROL_SET 0 +#define MLXBF_GPIO0_FW_CONTROL_CLEAR 0x14 +#define MLXBF_GPIO1_FW_CONTROL_SET 0x80 +#define MLXBF_GPIO1_FW_CONTROL_CLEAR 0x94 + +#define MLXBF_NGPIOS_GPIO0 32 + +enum { + MLXBF_GPIO_HW_MODE, + MLXBF_GPIO_SW_MODE +}; + +struct mlxbf_pinctrl { + void __iomem *base; + struct device *dev; + struct pinctrl_dev *pctl; + struct pinctrl_gpio_range gpio_range; +}; + +#define MLXBF_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \ + { \ + .name = "mlxbf_gpio_range", \ + .id = _id, \ + .base = _gpiobase, \ + .pin_base = _pinbase, \ + .npins = _npins, \ + } + +static struct pinctrl_gpio_range mlxbf_pinctrl_gpio_ranges[] = { + MLXBF_GPIO_RANGE(0, 0, 480, 32), + MLXBF_GPIO_RANGE(1, 32, 456, 24), +}; + +static const struct pinctrl_pin_desc mlxbf_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), + PINCTRL_PIN(32, "gpio32"), + PINCTRL_PIN(33, "gpio33"), + PINCTRL_PIN(34, "gpio34"), + PINCTRL_PIN(35, "gpio35"), + PINCTRL_PIN(36, "gpio36"), + PINCTRL_PIN(37, "gpio37"), + PINCTRL_PIN(38, "gpio38"), + PINCTRL_PIN(39, "gpio39"), + PINCTRL_PIN(40, "gpio40"), + PINCTRL_PIN(41, "gpio41"), + PINCTRL_PIN(42, "gpio42"), + PINCTRL_PIN(43, "gpio43"), + PINCTRL_PIN(44, "gpio44"), + PINCTRL_PIN(45, "gpio45"), + PINCTRL_PIN(46, "gpio46"), + PINCTRL_PIN(47, "gpio47"), + PINCTRL_PIN(48, "gpio48"), + PINCTRL_PIN(49, "gpio49"), + PINCTRL_PIN(50, "gpio50"), + PINCTRL_PIN(51, "gpio51"), + PINCTRL_PIN(52, "gpio52"), + PINCTRL_PIN(53, "gpio53"), + PINCTRL_PIN(54, "gpio54"), + PINCTRL_PIN(55, "gpio55"), +}; + +/* + * All single-pin functions can be mapped to any GPIO, however pinmux applies + * functions to pin groups and only those groups declared as supporting that + * function. To make this work we must put each pin in its own dummy group so + * that the functions can be described as applying to all pins. + * We use the same name as in the datasheet. + */ +static const char * const mlxbf_pinctrl_single_group_names[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", + "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", + "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", + "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", + "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", + "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55" +}; + +/* Set of pin numbers for single-pin groups */ +static const unsigned int mlxbf_pinctrl_single_group_pins[] = { + 0, 1, 2, 3, 4, 5, 6, + 7, 8, 9, 10, 11, 12, 13, + 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, + 28, 29, 30, 31, 32, 33, 34, + 35, 36, 37, 38, 39, 40, 41, + 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51, 52, 53, 54, 55, +}; + +static int mlxbf_get_groups_count(struct pinctrl_dev *pctldev) +{ + /* Number single-pin groups */ + return ARRAY_SIZE(mlxbf_pinctrl_single_group_pins); +} + +static const char *mlxbf_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return mlxbf_pinctrl_single_group_names[selector]; +} + +static int mlxbf_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + /* return the dummy group for a single pin */ + *pins = &mlxbf_pinctrl_single_group_pins[selector]; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops mlxbf_pinctrl_group_ops = { + .get_groups_count = mlxbf_get_groups_count, + .get_group_name = mlxbf_get_group_name, + .get_group_pins = mlxbf_get_group_pins, +}; + +static const char * const mlxbf_gpiofunc_group_names[] = { "swctrl" }; +static const char * const mlxbf_hwfunc_group_names[] = { "hwctrl" }; + +/* + * Only 2 functions are supported and they apply to all pins: + * 1) Default hardware functionality + * 2) Software controlled GPIO + */ +static const struct { + const char *name; + const char * const *group_names; +} mlxbf_pmx_funcs[] = { + { + .name = "hwfunc", + .group_names = mlxbf_hwfunc_group_names + }, + { + .name = "gpiofunc", + .group_names = mlxbf_gpiofunc_group_names + }, +}; + +static int mlxbf_pmx_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(mlxbf_pmx_funcs); +} + +static const char *mlxbf_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return mlxbf_pmx_funcs[selector].name; +} + +static int mlxbf_pmx_get_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + *groups = mlxbf_pmx_funcs[selector].group_names; + *num_groups = ARRAY_SIZE(mlxbf_pinctrl_single_group_pins); + + return 0; +} + +static int mlxbf_pmx_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned int group) +{ + struct mlxbf_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + if (selector == MLXBF_GPIO_HW_MODE) { + if (group < MLXBF_NGPIOS_GPIO0) + writel(BIT(group), priv->base + MLXBF_GPIO0_FW_CONTROL_CLEAR); + else + writel(BIT(group % MLXBF_NGPIOS_GPIO0), priv->base + MLXBF_GPIO1_FW_CONTROL_CLEAR); + } + + if (selector == MLXBF_GPIO_SW_MODE) { + if (group < MLXBF_NGPIOS_GPIO0) + writel(BIT(group), priv->base + MLXBF_GPIO0_FW_CONTROL_SET); + else + writel(BIT(group % MLXBF_NGPIOS_GPIO0), priv->base + MLXBF_GPIO1_FW_CONTROL_SET); + } + + return 0; +} + +static int mlxbf_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct mlxbf_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + if (offset < MLXBF_NGPIOS_GPIO0) + writel(BIT(offset), priv->base + MLXBF_GPIO0_FW_CONTROL_SET); + else + writel(BIT(offset % MLXBF_NGPIOS_GPIO0), priv->base + MLXBF_GPIO1_FW_CONTROL_SET); + + return 0; +} + +static void mlxbf_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct mlxbf_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + /* disable GPIO functionality by giving control back to hardware */ + if (offset < MLXBF_NGPIOS_GPIO0) + writel(BIT(offset), priv->base + MLXBF_GPIO0_FW_CONTROL_CLEAR); + else + writel(BIT(offset % MLXBF_NGPIOS_GPIO0), priv->base + MLXBF_GPIO1_FW_CONTROL_CLEAR); + +} + +static const struct pinmux_ops mlxbf_pmx_ops = { + .get_functions_count = mlxbf_pmx_get_funcs_count, + .get_function_name = mlxbf_pmx_get_func_name, + .get_function_groups = mlxbf_pmx_get_groups, + .set_mux = mlxbf_pmx_set, + .gpio_request_enable = mlxbf_gpio_request_enable, + .gpio_disable_free = mlxbf_gpio_disable_free, +}; + +static struct pinctrl_desc mlxbf_pin_desc = { + .name = "pinctrl-mlxbf", + .pins = mlxbf_pins, + .npins = ARRAY_SIZE(mlxbf_pins), + .pctlops = &mlxbf_pinctrl_group_ops, + .pmxops = &mlxbf_pmx_ops, + .owner = THIS_MODULE, +}; + +static_assert(ARRAY_SIZE(mlxbf_pinctrl_single_group_names) == + ARRAY_SIZE(mlxbf_pinctrl_single_group_pins)); + +static int mlxbf_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mlxbf_pinctrl *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + + /* This resource is shared so use devm_ioremap */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + priv->base = devm_ioremap(dev, res->start, resource_size(res)); + if (!priv->base) + return -ENOMEM; + + ret = devm_pinctrl_register_and_init(priv->dev, + &mlxbf_pin_desc, + priv, + &priv->pctl); + if (ret) + return dev_err_probe(dev, ret, "Failed to register pinctrl\n"); + + ret = pinctrl_enable(priv->pctl); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable pinctrl\n"); + + pinctrl_add_gpio_range(priv->pctl, &mlxbf_pinctrl_gpio_ranges[0]); + pinctrl_add_gpio_range(priv->pctl, &mlxbf_pinctrl_gpio_ranges[1]); + + return 0; +} + +static const struct acpi_device_id mlxbf_pinctrl_acpi_ids[] = { + { "MLNXBF34", 0 }, + {} +}; +MODULE_DEVICE_TABLE(acpi, mlxbf_pinctrl_acpi_ids); + +static struct platform_driver mlxbf_pinctrl_driver = { + .driver = { + .name = "pinctrl-mlxbf", + .acpi_match_table = mlxbf_pinctrl_acpi_ids, + }, + .probe = mlxbf_pinctrl_probe, +}; +module_platform_driver(mlxbf_pinctrl_driver); + +MODULE_DESCRIPTION("NVIDIA pinctrl driver"); +MODULE_AUTHOR("Asmaa Mnebhi "); +MODULE_LICENSE("Dual BSD/GPL");