From patchwork Mon Feb 20 08:12:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: qianfan X-Patchwork-Id: 13146145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC83AC05027 for ; Mon, 20 Feb 2023 08:14:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pU1Ix-0002zn-GG; Mon, 20 Feb 2023 03:13:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pU1It-0002py-Ly; Mon, 20 Feb 2023 03:13:43 -0500 Received: from m12.mail.163.com ([220.181.12.199]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pU1Ir-0001QY-0M; Mon, 20 Feb 2023 03:13:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=Loe6a ZHMrzE9iFa8rDoWH/ayBVuYxe1lFz57yi2qNNw=; b=YWFCMWjBySzmf4lXutwkY DEuGfDKuS2w25Q10VZ79Q6SeUwW9f2nNnqxyMwLxfAPX6FeJHFH28TrfL/F1URFY nWamcKs5TIyoNsXeTp4B5D7lZ90Td4ypS1UdEJMyd1xrenrDe1nwzSgWLyA2qEhg p44YnusIiW6VbYvg2fp3Vs= Received: from DESKTOP-B1R4FVG.localdomain (unknown [218.201.129.20]) by zwqz-smtp-mta-g2-4 (Coremail) with SMTP id _____wCnPYyDK_NjSU3yAQ--.59158S2; Mon, 20 Feb 2023 16:12:52 +0800 (CST) From: qianfanguijin@163.com To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Strahinja Jankovic , Peter Maydell , Beniamino Galvani , qianfan Zhao Subject: [PATCH v2 1/3] hw: allwinner-i2c: Make the trace message more readable Date: Mon, 20 Feb 2023 16:12:50 +0800 Message-Id: <20230220081252.25348-1-qianfanguijin@163.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: _____wCnPYyDK_NjSU3yAQ--.59158S2 X-Coremail-Antispam: 1Uf129KBjvJXoW3Jr4kuw4kKw4UCryfCr43GFg_yoW7Kr17pr Z0krsIgr15Kas8Zr1fKF1DJF1rJFyqyr1Iyws7W347uF1xCw13ZrykGF45A390k34Utr45 GFZ8Za42qFWYya7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0piS_M7UUUUU= X-Originating-IP: [218.201.129.20] X-CM-SenderInfo: htld0w5dqj3xxmlqqiywtou0bp/1tbiGgYc7VaEEUbKJwAAsF Received-SPF: pass client-ip=220.181.12.199; envelope-from=qianfanguijin@163.com; helo=m12.mail.163.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: qianfan Zhao Next is an example when read/write trace enabled: allwinner_i2c_write write XADDR(0x04): 0x00 allwinner_i2c_write write CNTR(0x0c): 0x50 M_STP BUS_EN allwinner_i2c_write write CNTR(0x0c): 0xe4 A_ACK M_STA BUS_EN INT_EN allwinner_i2c_read read CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN allwinner_i2c_read read STAT(0x10): 0x08 STAT_M_STA_TX Signed-off-by: qianfan Zhao --- hw/i2c/allwinner-i2c.c | 110 ++++++++++++++++++++++++++++++++++++++++- hw/i2c/trace-events | 5 +- 2 files changed, 110 insertions(+), 5 deletions(-) diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c index a435965836..fa650e7e02 100644 --- a/hw/i2c/allwinner-i2c.c +++ b/hw/i2c/allwinner-i2c.c @@ -129,6 +129,39 @@ enum { STAT_IDLE = 0x1f } TWI_STAT_STA; +#define TWI_STAT_STA_DESC(sta) [sta] = #sta +static const char *twi_stat_sta_descriptors[] = { + TWI_STAT_STA_DESC(STAT_BUS_ERROR), + TWI_STAT_STA_DESC(STAT_M_STA_TX), + TWI_STAT_STA_DESC(STAT_M_RSTA_TX), + TWI_STAT_STA_DESC(STAT_M_ADDR_WR_ACK), + TWI_STAT_STA_DESC(STAT_M_ADDR_WR_NACK), + TWI_STAT_STA_DESC(STAT_M_DATA_TX_ACK), + TWI_STAT_STA_DESC(STAT_M_DATA_TX_NACK), + TWI_STAT_STA_DESC(STAT_M_ARB_LOST), + TWI_STAT_STA_DESC(STAT_M_ADDR_RD_ACK), + TWI_STAT_STA_DESC(STAT_M_ADDR_RD_NACK), + TWI_STAT_STA_DESC(STAT_M_DATA_RX_ACK), + TWI_STAT_STA_DESC(STAT_M_DATA_RX_NACK), + TWI_STAT_STA_DESC(STAT_S_ADDR_WR_ACK), + TWI_STAT_STA_DESC(STAT_S_ARB_LOST_AW_ACK), + TWI_STAT_STA_DESC(STAT_S_GCA_ACK), + TWI_STAT_STA_DESC(STAT_S_ARB_LOST_GCA_ACK), + TWI_STAT_STA_DESC(STAT_S_DATA_RX_SA_ACK), + TWI_STAT_STA_DESC(STAT_S_DATA_RX_SA_NACK), + TWI_STAT_STA_DESC(STAT_S_DATA_RX_GCA_ACK), + TWI_STAT_STA_DESC(STAT_S_DATA_RX_GCA_NACK), + TWI_STAT_STA_DESC(STAT_S_STP_RSTA), + TWI_STAT_STA_DESC(STAT_S_ADDR_RD_ACK), + TWI_STAT_STA_DESC(STAT_S_ARB_LOST_AR_ACK), + TWI_STAT_STA_DESC(STAT_S_DATA_TX_ACK), + TWI_STAT_STA_DESC(STAT_S_DATA_TX_NACK), + TWI_STAT_STA_DESC(STAT_S_LB_TX_ACK), + TWI_STAT_STA_DESC(STAT_M_2ND_ADDR_WR_ACK), + TWI_STAT_STA_DESC(STAT_M_2ND_ADDR_WR_NACK), + TWI_STAT_STA_DESC(STAT_IDLE), +}; + static const char *allwinner_i2c_get_regname(unsigned offset) { switch (offset) { @@ -155,6 +188,79 @@ static const char *allwinner_i2c_get_regname(unsigned offset) } } +static const char *twi_cntr_reg_bits[] = { + [2] = "A_ACK", + [3] = "INT_FLAG", + [4] = "M_STP", + [5] = "M_STA", + [6] = "BUS_EN", + [7] = "INT_EN", +}; + +static const char *twi_line_ctrl_reg_bits[] = { + [5] = "SCL_STATE", + [4] = "SDA_STATE", + [3] = "SCL_CTL", + [2] = "SCL_CTL_EN", + [1] = "SDA_CTL", + [0] = "SDA_CTL_EN", +}; + +static void make_reg_value_bit_descriptors(char *s, size_t sz, uint8_t value, + const char **desc_arrays, + size_t array_size) +{ + unsigned i = 0; + + for (; i < array_size; i++) { + if ((value & (1 << i)) && desc_arrays[i]) { + strncat(s, desc_arrays[i], sz - 1); + strncat(s, " ", sz - 1); + } + } +} + +static void make_reg_value_descriptors(char *s, size_t sz, uint8_t addr, + uint8_t value) +{ + switch (addr) { + case TWI_CNTR_REG: + make_reg_value_bit_descriptors(s, sz, value, twi_cntr_reg_bits, + ARRAY_SIZE(twi_cntr_reg_bits)); + break; + case TWI_LCR_REG: + make_reg_value_bit_descriptors(s, sz, value, twi_line_ctrl_reg_bits, + ARRAY_SIZE(twi_line_ctrl_reg_bits)); + break; + case TWI_STAT_REG: + if (STAT_TO_STA(value) <= STAT_IDLE) + strncat(s, twi_stat_sta_descriptors[STAT_TO_STA(value)], sz - 1); + break; + } +} + +static void allwinner_i2c_trace_read(uint8_t addr, uint8_t value) +{ + char desc[256] = { 0 }; + + if (trace_event_get_state_backends(TRACE_ALLWINNER_I2C_READ)) { + make_reg_value_descriptors(desc, sizeof(desc), addr, value); + trace_allwinner_i2c_read(allwinner_i2c_get_regname(addr), + addr, value, desc); + } +} + +static void allwinner_i2c_trace_write(uint8_t addr, uint8_t value) +{ + char desc[256] = { 0 }; + + if (trace_event_get_state_backends(TRACE_ALLWINNER_I2C_WRITE)) { + make_reg_value_descriptors(desc, sizeof(desc), addr, value); + trace_allwinner_i2c_write(allwinner_i2c_get_regname(addr), + addr, value, desc); + } +} + static inline bool allwinner_i2c_is_reset(AWI2CState *s) { return s->srst & TWI_SRST_MASK; @@ -271,7 +377,7 @@ static uint64_t allwinner_i2c_read(void *opaque, hwaddr offset, break; } - trace_allwinner_i2c_read(allwinner_i2c_get_regname(offset), offset, value); + allwinner_i2c_trace_read((uint8_t)offset, (uint8_t)value); return (uint64_t)value; } @@ -283,7 +389,7 @@ static void allwinner_i2c_write(void *opaque, hwaddr offset, value &= 0xff; - trace_allwinner_i2c_write(allwinner_i2c_get_regname(offset), offset, value); + allwinner_i2c_trace_write((uint8_t)offset, (uint8_t)value); switch (offset) { case TWI_ADDR_REG: diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index 8e88aa24c1..963946bfdb 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -16,9 +16,8 @@ i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x" i2c_ack(void) "" # allwinner_i2c.c - -allwinner_i2c_read(const char* reg_name, uint64_t offset, uint64_t value) "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64 -allwinner_i2c_write(const char* reg_name, uint64_t offset, uint64_t value) "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64 +allwinner_i2c_read(const char *regname, uint8_t addr, uint8_t value, const char *desc) " read %6s(0x%02x): 0x%02x %s" +allwinner_i2c_write(const char *regname, uint8_t addr, uint8_t value, const char *desc) "write %6s(0x%02x): 0x%02x %s" # aspeed_i2c.c From patchwork Mon Feb 20 08:12:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: qianfan X-Patchwork-Id: 13146143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 554FBC636CC for ; Mon, 20 Feb 2023 08:13:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pU1IV-00028z-Qs; Mon, 20 Feb 2023 03:13:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pU1IU-00028W-0M; Mon, 20 Feb 2023 03:13:18 -0500 Received: from m12.mail.163.com ([220.181.12.198]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pU1IQ-0001Nc-HI; Mon, 20 Feb 2023 03:13:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=W8ose XLLoGmg6ep9d/aMwd6HC+YABeP2tHYrtdkhkk4=; b=ohAa7LQiIqyZWS7ptb9pr fnA21EDWonHq6gAurDSixsD3WAF9Gsqs2KQG7HkaE/1oQOgdjUZ7xJyV95tx/7Xr DfZ2LspzPsBUvGP47SaAtgRZVQtXVQ7AnVkAGZAKJKVPoOfUEsKwMxDwv5xpokah NWXBM1r1/CXtzoKwOJADCM= Received: from DESKTOP-B1R4FVG.localdomain (unknown [218.201.129.20]) by zwqz-smtp-mta-g2-4 (Coremail) with SMTP id _____wCnPYyDK_NjSU3yAQ--.59158S3; Mon, 20 Feb 2023 16:12:52 +0800 (CST) From: qianfanguijin@163.com To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Strahinja Jankovic , Peter Maydell , Beniamino Galvani , qianfan Zhao Subject: [PATCH v2 2/3] hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs Date: Mon, 20 Feb 2023 16:12:51 +0800 Message-Id: <20230220081252.25348-2-qianfanguijin@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220081252.25348-1-qianfanguijin@163.com> References: <20230220081252.25348-1-qianfanguijin@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wCnPYyDK_NjSU3yAQ--.59158S3 X-Coremail-Antispam: 1Uf129KBjvJXoWxGFyxCFW3KFyrAFWUWF43Awb_yoW5Kw4rpF Wqgr45KF4Yqa97WrnIqFn8GF18Jry8C3y8Krsa9FyIvFnrW3ZFqr1ktrWakrn8GrWrJw43 tFs8tFyxWFn0qaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRcVy7UUUUU= X-Originating-IP: [218.201.129.20] X-CM-SenderInfo: htld0w5dqj3xxmlqqiywtou0bp/1tbiGgYc7VaEEUbKKAABsL Received-SPF: pass client-ip=220.181.12.198; envelope-from=qianfanguijin@163.com; helo=m12.mail.163.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: qianfan Zhao TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect) register on SUN6i based SoCs, we should lower interrupt when the guest set this bit. The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no device connected on the i2c bus, next is the trace log: allwinner_i2c_write write CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN allwinner_i2c_write write CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN allwinner_i2c_read read CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN allwinner_i2c_read read STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE ... Fix it. Signed-off-by: qianfan Zhao Reviewed-by: Strahinja Jankovic Tested-by: Strahinja Jankovic Reviewed-by: Peter Maydell --- hw/i2c/allwinner-i2c.c | 26 ++++++++++++++++++++++++-- include/hw/i2c/allwinner-i2c.h | 6 ++++++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c index fa650e7e02..819638d740 100644 --- a/hw/i2c/allwinner-i2c.c +++ b/hw/i2c/allwinner-i2c.c @@ -463,10 +463,16 @@ static void allwinner_i2c_write(void *opaque, hwaddr offset, s->stat = STAT_FROM_STA(STAT_IDLE); s->cntr &= ~TWI_CNTR_M_STP; } - if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) { - /* Interrupt flag cleared */ + + if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) { + /* Write 0 to clear this flag */ + qemu_irq_lower(s->irq); + } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) { + /* Write 1 to clear this flag */ + s->cntr &= ~TWI_CNTR_INT_FLAG; qemu_irq_lower(s->irq); } + if ((s->cntr & TWI_CNTR_A_ACK) == 0) { if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) { s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK); @@ -557,9 +563,25 @@ static const TypeInfo allwinner_i2c_type_info = { .class_init = allwinner_i2c_class_init, }; +static void allwinner_i2c_sun6i_init(Object *obj) +{ + AWI2CState *s = AW_I2C(obj); + + s->irq_clear_inverted = true; +} + +static const TypeInfo allwinner_i2c_sun6i_type_info = { + .name = TYPE_AW_I2C_SUN6I, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AWI2CState), + .instance_init = allwinner_i2c_sun6i_init, + .class_init = allwinner_i2c_class_init, +}; + static void allwinner_i2c_register_types(void) { type_register_static(&allwinner_i2c_type_info); + type_register_static(&allwinner_i2c_sun6i_type_info); } type_init(allwinner_i2c_register_types) diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h index 4f378b86ba..0e325d265e 100644 --- a/include/hw/i2c/allwinner-i2c.h +++ b/include/hw/i2c/allwinner-i2c.h @@ -28,6 +28,10 @@ #include "qom/object.h" #define TYPE_AW_I2C "allwinner.i2c" + +/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */ +#define TYPE_AW_I2C_SUN6I TYPE_AW_I2C "-sun6i" + OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C) #define AW_I2C_MEM_SIZE 0x24 @@ -50,6 +54,8 @@ struct AWI2CState { uint8_t srst; uint8_t efr; uint8_t lcr; + + bool irq_clear_inverted; }; #endif /* ALLWINNER_I2C_H */ From patchwork Mon Feb 20 08:12:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: qianfan X-Patchwork-Id: 13146144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0848C636CC for ; Mon, 20 Feb 2023 08:14:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pU1Il-0002lS-00; Mon, 20 Feb 2023 03:13:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pU1Ij-0002jp-8k; Mon, 20 Feb 2023 03:13:33 -0500 Received: from m12.mail.163.com ([220.181.12.215]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pU1Ig-0001Pw-7B; Mon, 20 Feb 2023 03:13:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=c0oaO KazxYJZtJyXvhbpUehZRKXiMqRZrek0/PzmKMg=; b=kyjvdRPugiZBcKiCDmXRo 61NegRmOdO8XoCihyXU8mFHgykpbuj2DbP4zNTTrQBMENjep7DvndWpr3pp7VotX bvjlXBKbHqFPl/kyYAlZwvZnGHRrDx6z0eiqD7dDN0p4QmE+J8jiXPN82stjXC8L knMjBmtHcJMssSNILu13qM= Received: from DESKTOP-B1R4FVG.localdomain (unknown [218.201.129.20]) by zwqz-smtp-mta-g2-4 (Coremail) with SMTP id _____wCnPYyDK_NjSU3yAQ--.59158S4; Mon, 20 Feb 2023 16:12:53 +0800 (CST) From: qianfanguijin@163.com To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Strahinja Jankovic , Peter Maydell , Beniamino Galvani , qianfan Zhao Subject: [PATCH v2 3/3] hw: arm: allwinner-h3: Fix and complete H3 i2c devices Date: Mon, 20 Feb 2023 16:12:52 +0800 Message-Id: <20230220081252.25348-3-qianfanguijin@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220081252.25348-1-qianfanguijin@163.com> References: <20230220081252.25348-1-qianfanguijin@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wCnPYyDK_NjSU3yAQ--.59158S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxAFyDXw4ftrWkKryrWF1Utrb_yoWrtF1Upr WUCrs0gFWrW34xZr1vkwn3Zr1rta48Cr1DCa4SgFyfKr4jgw1qqw1Ivw4UCFy8XF4kuayY qryxKFW8G3WUtaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0p_vtCUUUUUU= X-Originating-IP: [218.201.129.20] X-CM-SenderInfo: htld0w5dqj3xxmlqqiywtou0bp/1tbiGgUc7VaEEUbKEQAAsw Received-SPF: pass client-ip=220.181.12.215; envelope-from=qianfanguijin@163.com; helo=m12.mail.163.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: qianfan Zhao Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi. The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear control register's INT_FLAG bit. Signed-off-by: qianfan Zhao Reviewed-by: Strahinja Jankovic Reviewed-by: Peter Maydell --- hw/arm/allwinner-h3.c | 29 +++++++++++++++++++++++++---- include/hw/arm/allwinner-h3.h | 6 ++++++ 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index bfce3c8d92..69d0ad6f50 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -54,6 +54,8 @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_DEV_UART2] = 0x01c28800, [AW_H3_DEV_UART3] = 0x01c28c00, [AW_H3_DEV_TWI0] = 0x01c2ac00, + [AW_H3_DEV_TWI1] = 0x01c2b000, + [AW_H3_DEV_TWI2] = 0x01c2b400, [AW_H3_DEV_EMAC] = 0x01c30000, [AW_H3_DEV_DRAMCOM] = 0x01c62000, [AW_H3_DEV_DRAMCTL] = 0x01c63000, @@ -64,6 +66,7 @@ const hwaddr allwinner_h3_memmap[] = { [AW_H3_DEV_GIC_VCPU] = 0x01c86000, [AW_H3_DEV_RTC] = 0x01f00000, [AW_H3_DEV_CPUCFG] = 0x01f01c00, + [AW_H3_DEV_R_TWI] = 0x01f02400, [AW_H3_DEV_SDRAM] = 0x40000000 }; @@ -107,8 +110,6 @@ struct AwH3Unimplemented { { "uart1", 0x01c28400, 1 * KiB }, { "uart2", 0x01c28800, 1 * KiB }, { "uart3", 0x01c28c00, 1 * KiB }, - { "twi1", 0x01c2b000, 1 * KiB }, - { "twi2", 0x01c2b400, 1 * KiB }, { "scr", 0x01c2c400, 1 * KiB }, { "gpu", 0x01c40000, 64 * KiB }, { "hstmr", 0x01c60000, 4 * KiB }, @@ -123,7 +124,6 @@ struct AwH3Unimplemented { { "r_prcm", 0x01f01400, 1 * KiB }, { "r_twd", 0x01f01800, 1 * KiB }, { "r_cir-rx", 0x01f02000, 1 * KiB }, - { "r_twi", 0x01f02400, 1 * KiB }, { "r_uart", 0x01f02800, 1 * KiB }, { "r_pio", 0x01f02c00, 1 * KiB }, { "r_pwm", 0x01f03800, 1 * KiB }, @@ -151,8 +151,11 @@ enum { AW_H3_GIC_SPI_UART2 = 2, AW_H3_GIC_SPI_UART3 = 3, AW_H3_GIC_SPI_TWI0 = 6, + AW_H3_GIC_SPI_TWI1 = 7, + AW_H3_GIC_SPI_TWI2 = 8, AW_H3_GIC_SPI_TIMER0 = 18, AW_H3_GIC_SPI_TIMER1 = 19, + AW_H3_GIC_SPI_R_TWI = 44, AW_H3_GIC_SPI_MMC0 = 60, AW_H3_GIC_SPI_EHCI0 = 72, AW_H3_GIC_SPI_OHCI0 = 73, @@ -227,7 +230,10 @@ static void allwinner_h3_init(Object *obj) object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I); - object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C); + object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I); + object_initialize_child(obj, "twi1", &s->i2c1, TYPE_AW_I2C_SUN6I); + object_initialize_child(obj, "twi2", &s->i2c2, TYPE_AW_I2C_SUN6I); + object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I); } static void allwinner_h3_realize(DeviceState *dev, Error **errp) @@ -432,6 +438,21 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0)); + sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1)); + + sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2)); + + sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI)); + /* Unimplemented devices */ for (i = 0; i < ARRAY_SIZE(unimplemented); i++) { create_unimplemented_device(unimplemented[i].device_name, diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h index 1d7ce20589..59e0f822d2 100644 --- a/include/hw/arm/allwinner-h3.h +++ b/include/hw/arm/allwinner-h3.h @@ -84,6 +84,8 @@ enum { AW_H3_DEV_UART3, AW_H3_DEV_EMAC, AW_H3_DEV_TWI0, + AW_H3_DEV_TWI1, + AW_H3_DEV_TWI2, AW_H3_DEV_DRAMCOM, AW_H3_DEV_DRAMCTL, AW_H3_DEV_DRAMPHY, @@ -93,6 +95,7 @@ enum { AW_H3_DEV_GIC_VCPU, AW_H3_DEV_RTC, AW_H3_DEV_CPUCFG, + AW_H3_DEV_R_TWI, AW_H3_DEV_SDRAM }; @@ -133,6 +136,9 @@ struct AwH3State { AwSidState sid; AwSdHostState mmc0; AWI2CState i2c0; + AWI2CState i2c1; + AWI2CState i2c2; + AWI2CState r_twi; AwSun8iEmacState emac; AwRtcState rtc; GICState gic;