From patchwork Mon Feb 20 12:23:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 07A4FC64EC7 for ; Mon, 20 Feb 2023 12:26:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7F17910E1E8; Mon, 20 Feb 2023 12:26:45 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 50B0510E196 for ; Mon, 20 Feb 2023 12:26:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676896003; x=1708432003; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=es/2XTA68Z83uxaRGBXPv/1tu/4i+iVizQvpnyIDy8M=; b=l2WXoRqzbbSWZOtRNSf7IG62d2hwk6K5Als4NFQSEr36F1kgWfi29gVI 3wDeUrpAXNPamf5bh1u9wT4lRZJh+6p9s+pdWpsFhQLbqUQtfLiaUwbO9 Ff3fmsa4jW7ytshJjGvxvJLspaIjN8n3ycwyK3gQtpuZ+DzTBIjlzpidO 4ocog6qLBBeZ1aOEY9QPNwEFQQ23rDdWSAaH23euxMxTmXa1DHjhJt7Jh 7lRmX2iKihyTyo6pnIK8KWub4nTRF/chAbFIHQZFhynvh0BxFvj1PQstl ITvS/M5y1eY8cF9d7Jf3IPEHm3TNHNQJHw8AHfhyxhL7hpGJSb1FMqbdY g==; X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073405" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073405" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:43 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142073" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142073" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:41 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:48 +0530 Message-Id: <20230220122401.3495507-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 01/14] drm/i915/display: Add new member to configure PCON color conversion X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The decision to use DFP output format conversion capabilities should be during compute_config phase. This patch adds new member to crtc_state to represent the final output_format to the sink. In case of a DFP this can be different than the output_format, as per the format conversion done via the PCON. This will help to store only the format conversion capabilities of the DP device in intel_dp->dfp, and use crtc_state to compute and store the configuration for color/format conversion for a given mode. v2: modified the new member to crtc_state to represent the final output_format that eaches the sink, after possible conversion by PCON kind of devices. (Ville) v3: Addressed comments from Ville: -Added comments to clarify difference between sink_format and output_format. -Corrected the order of setting sink_format and output_format. -Added readout for sink_format in get_pipe_config hooks. v4: Set sink_format for intel_sdvo too. (Ville) v5: Rebased. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä (v3) --- drivers/gpu/drm/i915/display/icl_dsi.c | 1 + drivers/gpu/drm/i915/display/intel_crt.c | 1 + .../drm/i915/display/intel_crtc_state_dump.c | 5 +-- drivers/gpu/drm/i915/display/intel_display.c | 5 +++ .../drm/i915/display/intel_display_types.h | 11 +++++- drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++------ drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + drivers/gpu/drm/i915/display/intel_dvo.c | 1 + drivers/gpu/drm/i915/display/intel_hdmi.c | 24 +++++++------ drivers/gpu/drm/i915/display/intel_lvds.c | 1 + drivers/gpu/drm/i915/display/intel_sdvo.c | 1 + drivers/gpu/drm/i915/display/intel_tv.c | 1 + drivers/gpu/drm/i915/display/vlv_dsi.c | 1 + 13 files changed, 62 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index def3aff4d717..2d17b2a7e1d5 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1575,6 +1575,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder, &pipe_config->hw.adjusted_mode; int ret; + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; ret = intel_panel_compute_config(intel_connector, adjusted_mode); diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 8f2ebead0826..e925e21d87fc 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -393,6 +393,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder, if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return -EINVAL; + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; return 0; diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 766633566fd6..185cd1971aa5 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -178,10 +178,11 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); drm_dbg_kms(&i915->drm, - "active: %s, output_types: %s (0x%x), output format: %s\n", + "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n", str_yes_no(pipe_config->hw.active), buf, pipe_config->output_types, - output_formats(pipe_config->output_format)); + output_formats(pipe_config->output_format), + output_formats(pipe_config->sink_format)); drm_dbg_kms(&i915->drm, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0bb429d3e8d7..cc44f0629f2c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3103,6 +3103,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, return false; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; + pipe_config->sink_format = pipe_config->output_format; pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; pipe_config->shared_dpll = NULL; @@ -3562,6 +3563,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, break; } + pipe_config->sink_format = pipe_config->output_format; + pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp); pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; @@ -3960,6 +3963,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, bdw_get_pipemisc_output_format(crtc); } + pipe_config->sink_format = pipe_config->output_format; + pipe_config->gamma_mode = intel_de_read(dev_priv, GAMMA_MODE(crtc->pipe)); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 748b0cd411fa..c28835d9db6f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1273,9 +1273,18 @@ struct intel_crtc_state { /* HDMI High TMDS char rate ratio */ bool hdmi_high_tmds_clock_ratio; - /* Output format RGB/YCBCR etc */ + /* + * Output format RGB/YCBCR etc., that is coming out + * at the end of the pipe. + */ enum intel_output_format output_format; + /* + * Sink output format RGB/YCBCR etc., that is going + * into the sink. + */ + enum intel_output_format sink_format; + /* enable pipe gamma? */ bool gamma_enable; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b77bd4565864..81fbef30c469 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -806,11 +806,12 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, static enum intel_output_format intel_dp_output_format(struct intel_connector *connector, - bool ycbcr_420_output) + enum intel_output_format sink_format) { struct intel_dp *intel_dp = intel_attached_dp(connector); - if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output) + if (!connector->base.ycbcr_420_allowed || + sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) return INTEL_OUTPUT_FORMAT_RGB; if (intel_dp->dfp.rgb_to_ycbcr && @@ -849,8 +850,14 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector, const struct drm_display_mode *mode) { const struct drm_display_info *info = &connector->base.display_info; - enum intel_output_format output_format = - intel_dp_output_format(connector, drm_mode_is_420_only(info, mode)); + enum intel_output_format output_format, sink_format; + + if (drm_mode_is_420_only(info, mode)) + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + else + sink_format = INTEL_OUTPUT_FORMAT_RGB; + + output_format = intel_dp_output_format(connector, sink_format); return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); } @@ -2036,23 +2043,28 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); - crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only); - - if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) { + if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { drm_dbg_kms(&i915->drm, "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); - crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; + } else if (ycbcr_420_only) { + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + } else { + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; } + crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); + ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, respect_downstream_limits); if (ret) { - if (intel_dp_is_ycbcr420(intel_dp, crtc_state) || - !connector->base.ycbcr_420_allowed || + if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || !drm_mode_is_420_also(info, adjusted_mode)) return ret; - crtc_state->output_format = intel_dp_output_format(connector, true); + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + crtc_state->output_format = intel_dp_output_format(connector, + crtc_state->sink_format); ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, respect_downstream_limits); } diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index de856f4375fb..054b179d0b6a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -284,6 +284,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return -EINVAL; + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->has_pch_encoder = false; diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index eb2dcd866cc8..9884678743b6 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -271,6 +271,7 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder, if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return -EINVAL; + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; return 0; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index c7e9e1fbed37..c0ae618360c3 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2171,13 +2171,13 @@ static bool intel_hdmi_has_audio(struct intel_encoder *encoder, static enum intel_output_format intel_hdmi_output_format(const struct intel_crtc_state *crtc_state, - struct intel_connector *connector, - bool ycbcr_420_output) + struct intel_connector *connector) { if (!crtc_state->has_hdmi_sink) return INTEL_OUTPUT_FORMAT_RGB; - if (connector->base.ycbcr_420_allowed && ycbcr_420_output) + if (connector->base.ycbcr_420_allowed && + crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) return INTEL_OUTPUT_FORMAT_YCBCR420; else return INTEL_OUTPUT_FORMAT_RGB; @@ -2195,23 +2195,25 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); int ret; - crtc_state->output_format = - intel_hdmi_output_format(crtc_state, connector, ycbcr_420_only); - - if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) { + if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) { drm_dbg_kms(&i915->drm, "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); - crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; + } else if (ycbcr_420_only) { + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + } else { + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; } + crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector); ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); if (ret) { - if (intel_hdmi_is_ycbcr420(crtc_state) || - !connector->base.ycbcr_420_allowed || + if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || !drm_mode_is_420_also(info, adjusted_mode)) return ret; - crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector, true); + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector); ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); } diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index a504b3a7fbd5..a7783da37dfd 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -436,6 +436,7 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder, crtc_state->pipe_bpp = lvds_bpp; } + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; /* diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index e12ba458636c..34ee9dd82a78 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -1351,6 +1351,7 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); pipe_config->pipe_bpp = 8*3; + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c index 3b5ff84dc615..6f7ac225293e 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.c +++ b/drivers/gpu/drm/i915/display/intel_tv.c @@ -1204,6 +1204,7 @@ intel_tv_compute_config(struct intel_encoder *encoder, if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return -EINVAL; + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n"); diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 8d2e6e151ba0..82c30feb7a91 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -280,6 +280,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder, int ret; drm_dbg_kms(&dev_priv->drm, "\n"); + pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; ret = intel_panel_compute_config(intel_connector, adjusted_mode); From patchwork Mon Feb 20 12:23:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E69DC678D5 for ; Mon, 20 Feb 2023 12:26:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B99D610E678; Mon, 20 Feb 2023 12:26:50 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 650DD10E196 for ; Mon, 20 Feb 2023 12:26:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676896005; x=1708432005; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2ZSP3fxIP3mHUeh9DmXYA3Yrdv7fa0atObf3LxUC8ts=; b=mlQGetF4RnqHK2+zPJis6zONpPZzT6hjJuCAQRNutFpo7RAaJAmafSuc 3vC3UDvu7p/YfyTA6rDlIqqGeY0xlE0blKDqlHtDPD/kO/QbgC/ys1WhV RFNY6h6B7G573aOrz7bkZ5DoLP0cCHuF0uzr1ldoH7HgDjmPm4eH7jrI5 WezrHGssqCWD9aWMtC3HJlnA00/JOkeLW46haOCuoLRRsLnqJsmP72Sey IdvvCmWy0fDYZkUlxGwauAMSjn/IWRFC+YCBoEIZxT+/GOWf7GlPYIWiZ TlJSajQj7AudNjclWBO9XXFT7LHlvzuND/KuFMkjLvU+Rvx3keV6gTo9w w==; X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073411" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073411" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:45 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142077" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142077" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:43 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:49 +0530 Message-Id: <20230220122401.3495507-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 02/14] drm/i915/display: Add new member in intel_dp to store ycbcr420 passthrough cap X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" New member to store the YCBCR20 Pass through capability of the DP sink. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index c28835d9db6f..1be15a1caa39 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1733,6 +1733,7 @@ struct intel_dp { int pcon_max_frl_bw; u8 max_bpc; bool ycbcr_444_to_420; + bool ycbcr420_passthrough; bool rgb_to_ycbcr; } dfp; From patchwork Mon Feb 20 12:23:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146368 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13D51C64EC4 for ; Mon, 20 Feb 2023 12:26:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EC3510E675; Mon, 20 Feb 2023 12:26:48 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3993010E196 for ; Mon, 20 Feb 2023 12:26:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676896007; x=1708432007; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HLqbAgnG7ddsVNXhrVNXyx+IsQ9LGhRvKGbday0RzkE=; b=FiFMhxOowoD+Yez5xcoAKFKkeQ3eR3K3VRTobl0mDt1eoQBUqSEBMbEy nexc1ftHSD9eGmFmWwH8+l2fV3ze4XFl6qnGe9Zpkw1i0aIqt/I7n3++L BEJLmefuMOLjGhqQRF4PC6bUybJwMOv0coOYcfgWbyRMmE6FDgV1eJ4Gc 2jnrY/ZqaftkNG7ovUE2gM0WMyrs15RYMcFqMczB+gisnGdv+UYgO3a7t bFZMp9WS7JSM5f4hpEsqK/xxrbhemKnuusgqrjdixhNX2nA2xKXSv5aaB DaRy+LBIueLacGQpgJrQEG4A1bHi+Z/DEVTdXODbaEhAyjB6f5OGkoKTf Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073417" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073417" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:47 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142081" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142081" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:45 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:50 +0530 Message-Id: <20230220122401.3495507-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 03/14] drm/i915/dp: Add Scaler constraint for YCbCr420 output X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For YCbCr420 output, scaler is required for downsampling. Scaler can be used only when source size smaller than max_src_w and max_src_h as defined by for the platform. So go for native YCbCr420 only if there are no scaler constraints. v2: Corrected max-width based on Display Version. v3: Updated max-width as per latest Bspec change. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 41 ++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 81fbef30c469..f99bf52171fd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -804,11 +804,36 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, return 0; } +static bool +ycbcr420_scaler_constraints(struct drm_i915_private *i915, + const struct drm_display_mode *mode) +{ + int max_src_w, max_src_h; + + if (DISPLAY_VER(i915) < 11) { + max_src_w = 4096; + max_src_h = 4096; + } else if (DISPLAY_VER(i915) < 12) { + max_src_w = 5120; + max_src_h = 4096; + } else if (DISPLAY_VER(i915) < 14) { + max_src_w = 5120; + max_src_h = 8192; + } else { + max_src_w = 4096; + max_src_h = 8192; + } + + return mode->hdisplay > max_src_w || mode->vdisplay > max_src_h; +} + static enum intel_output_format intel_dp_output_format(struct intel_connector *connector, + const struct drm_display_mode *mode, enum intel_output_format sink_format) { struct intel_dp *intel_dp = intel_attached_dp(connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); if (!connector->base.ycbcr_420_allowed || sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) @@ -820,8 +845,15 @@ intel_dp_output_format(struct intel_connector *connector, if (intel_dp->dfp.ycbcr_444_to_420) return INTEL_OUTPUT_FORMAT_YCBCR444; - else + + /* + * For YCbCr420 output, scaler is required for downsampling + * So go for native YCbCr420 only if there are no scaler constraints. + */ + if (!ycbcr420_scaler_constraints(i915, mode)) return INTEL_OUTPUT_FORMAT_YCBCR420; + + return INTEL_OUTPUT_FORMAT_RGB; } int intel_dp_min_bpp(enum intel_output_format output_format) @@ -857,7 +889,7 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector, else sink_format = INTEL_OUTPUT_FORMAT_RGB; - output_format = intel_dp_output_format(connector, sink_format); + output_format = intel_dp_output_format(connector, mode, sink_format); return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); } @@ -2053,7 +2085,8 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; } - crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format); + crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode, + crtc_state->sink_format); ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, respect_downstream_limits); @@ -2063,7 +2096,7 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, return ret; crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - crtc_state->output_format = intel_dp_output_format(connector, + crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode, crtc_state->sink_format); ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, respect_downstream_limits); From patchwork Mon Feb 20 12:23:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88297C64ED8 for ; Mon, 20 Feb 2023 12:26:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9E9BB10E67E; Mon, 20 Feb 2023 12:26:54 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 50DD210E678 for ; Mon, 20 Feb 2023 12:26:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676896009; x=1708432009; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tC5anRmFGjbd/waJ3NISjuqyp2NlQr8eDzVfYA/f9d0=; b=lVZSWAycWTruIFpUdquovindXw7TZTn1RfHCmKoOZDx53uHOvXWKHV7H DmRmyIC0KTLJDm81npglTqgi0TvJaGjHII+Q1kWwcmr6kaWKJR/bwDiyp ih0E8TDMqWHsq8UaUNZB6/RMiIMqAbhoN7xJKfbIRHhyIkLB5eP8ahFzg 2GHWgC6xjmN8ORXevoGGw4JjRI7AuirBSyFN+OubdFmRs1oR4/O2MdOCO XnWZ/+2KlH/rz9lOpCGGCY1Rq0lYejTeigpxpskqsIF/pIUXOgGD+35In kO0jGT4WohYT+jsNI5WVSAZrEapN2bjJ/+dlE4AX11r611XJoendOt8Un g==; X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073421" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073421" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:49 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142085" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142085" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:47 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:51 +0530 Message-Id: <20230220122401.3495507-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 04/14] drm/i915/dp: Replace intel_dp.dfp members with the new crtc_state sink_format X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The decision to use DFP output format conversion capabilities should be during compute_config phase. This patch uses the members of intel_dp->dfp to only store the format conversion capabilities of the DP device and uses the crtc_state sink_format member, to program the protocol-converter for colorspace/format conversion. v2: Use sink_format to determine the color conversion config for the pcon (Ville). v3: Fix typo: missing 'break' in switch case (lkp kernel test robot). v4: Add helper to check if DP supports YCBCR420. v5: Simplify logic for computing output_format, based on the given sink_format. (Ville). Added scaler constraint for YCbCr420 output. v6: Split the patch for Scaler constraint for Ycbcr420. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 192 +++++++++++++++++------- 1 file changed, 135 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f99bf52171fd..9b6d2af2817b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -804,6 +804,67 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, return 0; } +static bool source_can_output(struct intel_dp *intel_dp, + enum intel_output_format format) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + bool is_branch = drm_dp_is_branch(intel_dp->dpcd); + + if (format == INTEL_OUTPUT_FORMAT_RGB) + return true; + + /* + * No YCbCr output support on gmch platforms. + * Also, ILK doesn't seem capable of DP YCbCr output. + * The displayed image is severly corrupted. SNB+ is fine. + */ + if (HAS_GMCH(i915) || IS_IRONLAKE(i915)) + return false; + + if (format == INTEL_OUTPUT_FORMAT_YCBCR444) + return true; + + /* Platform < Gen 11 cannot output YCbCr420 format */ + if (DISPLAY_VER(i915) < 11) + return false; + + /* If branch device then PCONs should support YCbCr420 Passthrough */ + if (format == INTEL_OUTPUT_FORMAT_YCBCR420) + return !is_branch || intel_dp->dfp.ycbcr420_passthrough; + + return false; +} + +static bool +dfp_can_convert_from_rgb(struct intel_dp *intel_dp, + enum intel_output_format sink_format) +{ + if (!drm_dp_is_branch(intel_dp->dpcd)) + return false; + + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) + return intel_dp->dfp.rgb_to_ycbcr; + + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) + return intel_dp->dfp.rgb_to_ycbcr && + intel_dp->dfp.ycbcr_444_to_420; + + return false; +} + +static bool +dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp, + enum intel_output_format sink_format) +{ + if (!drm_dp_is_branch(intel_dp->dpcd)) + return false; + + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) + return intel_dp->dfp.ycbcr_444_to_420; + + return false; +} + static bool ycbcr420_scaler_constraints(struct drm_i915_private *i915, const struct drm_display_mode *mode) @@ -835,24 +896,23 @@ intel_dp_output_format(struct intel_connector *connector, struct intel_dp *intel_dp = intel_attached_dp(connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); - if (!connector->base.ycbcr_420_allowed || - sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) - return INTEL_OUTPUT_FORMAT_RGB; + /* + * For YCbCr420 output, scaler is required for downsampling. + * So go for native YCbCr420 only if there are no scaler constraints. + */ + if ((sink_format != INTEL_OUTPUT_FORMAT_YCBCR420 || + !ycbcr420_scaler_constraints(i915, mode)) && + source_can_output(intel_dp, sink_format)) + return sink_format; - if (intel_dp->dfp.rgb_to_ycbcr && - intel_dp->dfp.ycbcr_444_to_420) + if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) && + dfp_can_convert_from_rgb(intel_dp, sink_format)) return INTEL_OUTPUT_FORMAT_RGB; - if (intel_dp->dfp.ycbcr_444_to_420) + if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) && + dfp_can_convert_from_ycbcr444(intel_dp, sink_format)) return INTEL_OUTPUT_FORMAT_YCBCR444; - /* - * For YCbCr420 output, scaler is required for downsampling - * So go for native YCbCr420 only if there are no scaler constraints. - */ - if (!ycbcr420_scaler_constraints(i915, mode)) - return INTEL_OUTPUT_FORMAT_YCBCR420; - return INTEL_OUTPUT_FORMAT_RGB; } @@ -2774,6 +2834,8 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + bool ycbcr444_to_420 = false; + bool rgb_to_ycbcr = false; u8 tmp; if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) @@ -2790,8 +2852,35 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", str_enable_disable(intel_dp->has_hdmi_sink)); - tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && - intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; + if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { + switch (crtc_state->output_format) { + case INTEL_OUTPUT_FORMAT_YCBCR420: + /* + * sink_format is YCbCr420, output_format is also YCbCr420: + * Passthrough. + */ + break; + case INTEL_OUTPUT_FORMAT_YCBCR444: + /* + * sink_format is YCbCr420, output_format is YCbCr444: + * Downsample. + */ + ycbcr444_to_420 = true; + break; + case INTEL_OUTPUT_FORMAT_RGB: + /* + * sink_format is YCbCr420, output_format is RGB: + * Convert to YCbCr444 and Downsample. + */ + rgb_to_ycbcr = true; + ycbcr444_to_420 = true; + break; + default: + break; + } + } + + tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) @@ -2799,13 +2888,12 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", str_enable_disable(intel_dp->dfp.ycbcr_444_to_420)); - tmp = intel_dp->dfp.rgb_to_ycbcr ? - DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; + tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0; if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) drm_dbg_kms(&i915->drm, - "Failed to %s protocol converter RGB->YCbCr conversion mode\n", - str_enable_disable(tmp)); + "Failed to %s protocol converter RGB->YCbCr conversion mode\n", + str_enable_disable(tmp)); } bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) @@ -4595,57 +4683,47 @@ intel_dp_update_dfp(struct intel_dp *intel_dp, intel_dp_get_pcon_dsc_cap(intel_dp); } +static bool +intel_dp_can_ycbcr420(struct intel_dp *intel_dp) +{ + if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) + return true; + /* + * If source cannot support YCbCr420, and PCON has color conv. support: + * Source sends YCbCr444, PCON converts YCbCr444->420 Or + * Source sends RGB444, PCON converts RGB->YCbCr444 + YCbCr444->YCbCr420) + */ + if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) && + dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) + return true; + + if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) && + dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420)) + return INTEL_OUTPUT_FORMAT_YCBCR444; + + return false; +} + static void intel_dp_update_420(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); struct intel_connector *connector = intel_dp->attached_connector; - bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr; - - /* No YCbCr output support on gmch platforms */ - if (HAS_GMCH(i915)) - return; - - /* - * ILK doesn't seem capable of DP YCbCr output. The - * displayed image is severly corrupted. SNB+ is fine. - */ - if (IS_IRONLAKE(i915)) - return; - is_branch = drm_dp_is_branch(intel_dp->dpcd); - ycbcr_420_passthrough = + intel_dp->dfp.ycbcr420_passthrough = drm_dp_downstream_420_passthrough(intel_dp->dpcd, intel_dp->downstream_ports); /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ - ycbcr_444_to_420 = + intel_dp->dfp.ycbcr_444_to_420 = dp_to_dig_port(intel_dp)->lspcon.active || drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, intel_dp->downstream_ports); - rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, - intel_dp->downstream_ports, - DP_DS_HDMI_BT709_RGB_YCBCR_CONV); - - if (DISPLAY_VER(i915) >= 11) { - /* Let PCON convert from RGB->YCbCr if possible */ - if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) { - intel_dp->dfp.rgb_to_ycbcr = true; - intel_dp->dfp.ycbcr_444_to_420 = true; - connector->base.ycbcr_420_allowed = true; - } else { - /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */ - intel_dp->dfp.ycbcr_444_to_420 = - ycbcr_444_to_420 && !ycbcr_420_passthrough; + intel_dp->dfp.rgb_to_ycbcr = + drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, + intel_dp->downstream_ports, + DP_DS_HDMI_BT709_RGB_YCBCR_CONV); - connector->base.ycbcr_420_allowed = - !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough; - } - } else { - /* 4:4:4->4:2:0 conversion is the only way */ - intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420; - - connector->base.ycbcr_420_allowed = ycbcr_444_to_420; - } + connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp); drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", From patchwork Mon Feb 20 12:23:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D716C64EC4 for ; Mon, 20 Feb 2023 12:26:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C7B310E682; Mon, 20 Feb 2023 12:26:57 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2A1B410E67C for ; Mon, 20 Feb 2023 12:26:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676896011; x=1708432011; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wa1kbalr1Vs6a7pXCNN2753VR1pKtn+4p6/cCZn2bJc=; b=FALLAq/TKn2ZYmJXL+jkM9keHnQ7Rn9TsrFa+eVri+sAmxOwnUTW5mEx 3H1VHlPEmhTvF+eVlwN/8iwfa6x6m8dtJec+L8DrVNNUh0XlBCejHVQqA r1sJ/7i4Fu9xbueQOXwANPIPdHpJLf1GSjgjwCOsr3LMN5NXGBCPlOswB Ab//xMroTgU/U6er9mgHHt2f2Dqqvp3k73krtqY/4+L/2Z9H4soQFdjZI UJSptojuL3J4/ghH1c/NxjQPYi9bC6AiwEpCUW0Nq3W/hAWoGwQPq4lBd lBQ/Kec9/PLhMYhZSgwr97GcphWFRTMpiuDKuBd1/aHixmwEXY44LxpAz g==; X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073423" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073423" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:50 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142090" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142090" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:49 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:52 +0530 Message-Id: <20230220122401.3495507-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 05/14] drm/i915/dp: Compute output format with/without DSC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we compute the output format first and later try DSC if the bandwidth without compression is not sufficient for that output format. Since we do not support DSC with YCbCr420 format, this creates problem for YCbCr420 only modes, that can be still be set if DFP has color conversion and DSC capabilities. So compute output format, first without DSC and inturn compute the link config without DSC. If cannot be supported without DSC, compute the output format with DSC and continue. With this apporach, check can be added for YCbCr420 output, which cannot be supported with DSC. v2: Rebased Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 84 ++++++++++++++++++------- 1 file changed, 61 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9b6d2af2817b..b8585f83f660 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -888,20 +888,37 @@ ycbcr420_scaler_constraints(struct drm_i915_private *i915, return mode->hdisplay > max_src_w || mode->vdisplay > max_src_h; } +static bool +ycbcr420_constraints(struct drm_i915_private *i915, + const struct drm_display_mode *mode, + bool with_dsc) +{ + /* + * DSC with YCbCr420 is a constraint as currently we do not support compression + * with 420 format. + */ + if (with_dsc) + return true; + + return ycbcr420_scaler_constraints(i915, mode); +} + static enum intel_output_format intel_dp_output_format(struct intel_connector *connector, const struct drm_display_mode *mode, - enum intel_output_format sink_format) + enum intel_output_format sink_format, + bool with_dsc) { struct intel_dp *intel_dp = intel_attached_dp(connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); /* * For YCbCr420 output, scaler is required for downsampling. - * So go for native YCbCr420 only if there are no scaler constraints. + * DSC1.1 supports compression only with 444 formats. + * So go for native YCbCr420 only if there are no scaler and dsc constraints. */ if ((sink_format != INTEL_OUTPUT_FORMAT_YCBCR420 || - !ycbcr420_scaler_constraints(i915, mode)) && + !ycbcr420_constraints(i915, mode, with_dsc)) && source_can_output(intel_dp, sink_format)) return sink_format; @@ -949,7 +966,7 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector, else sink_format = INTEL_OUTPUT_FORMAT_RGB; - output_format = intel_dp_output_format(connector, mode, sink_format); + output_format = intel_dp_output_format(connector, mode, sink_format, false); return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); } @@ -1731,7 +1748,8 @@ static int intel_dp_compute_link_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, - bool respect_downstream_limits) + bool respect_downstream_limits, + bool with_dsc) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); @@ -1742,6 +1760,20 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, bool joiner_needs_dsc = false; int ret; + if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay, + adjusted_mode->crtc_clock)) + pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe); + + /* + * Pipe joiner needs compression up to display 12 due to bandwidth + * limitation. DG2 onwards pipe joiner can be enabled without + * compression. + */ + joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes; + + if (joiner_needs_dsc && !with_dsc) + return -EINVAL; + limits.min_rate = intel_dp_common_rate(intel_dp, 0); limits.max_rate = intel_dp_max_link_rate(intel_dp); @@ -1771,23 +1803,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, limits.max_lane_count, limits.max_rate, limits.max_bpp, adjusted_mode->crtc_clock); - if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay, - adjusted_mode->crtc_clock)) - pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe); - - /* - * Pipe joiner needs compression up to display 12 due to bandwidth - * limitation. DG2 onwards pipe joiner can be enabled without - * compression. - */ - joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes; - /* * Optimize for slow and wide for everything, because there are some * eDP 1.3 and 1.4 panels don't work well with fast and narrow. */ ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits); + if (ret && !with_dsc) + return -EINVAL; + if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) { drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n", str_yes_no(ret), str_yes_no(joiner_needs_dsc), @@ -2123,7 +2147,8 @@ static int intel_dp_compute_output_format(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state, - bool respect_downstream_limits) + bool respect_downstream_limits, + bool with_dsc) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -2146,10 +2171,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, } crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode, - crtc_state->sink_format); + crtc_state->sink_format, with_dsc); ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, - respect_downstream_limits); + respect_downstream_limits, with_dsc); if (ret) { if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || !drm_mode_is_420_also(info, adjusted_mode)) @@ -2157,9 +2182,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; crtc_state->output_format = intel_dp_output_format(connector, adjusted_mode, - crtc_state->sink_format); + crtc_state->sink_format, + with_dsc); ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, - respect_downstream_limits); + respect_downstream_limits, with_dsc); } return ret; @@ -2225,9 +2251,21 @@ intel_dp_compute_config(struct intel_encoder *encoder, * Try to respect downstream TMDS clock limits first, if * that fails assume the user might know something we don't. */ - ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true); + ret = intel_dp_compute_output_format(encoder, pipe_config, + conn_state, true, false); if (ret) - ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false); + ret = intel_dp_compute_output_format(encoder, pipe_config, + conn_state, false, false); + + /* Try with DSC */ + if (ret) { + ret = intel_dp_compute_output_format(encoder, pipe_config, + conn_state, true, true); + if (ret) + ret = intel_dp_compute_output_format(encoder, pipe_config, + conn_state, false, true); + } + if (ret) return ret; From patchwork Mon Feb 20 12:23:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C47DC05027 for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073430" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073430" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:53 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142094" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142094" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:51 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:53 +0530 Message-Id: <20230220122401.3495507-7-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 06/14] drm/i915/display: Use sink_format instead of ycbcr420_output flag X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Start passing the sink_format, to all functions that take a bool ycbcr420_output as parameter. This will make the functions generic, and will serve as a slight step towards 4:2:2 support later. v2: Rebased. Suggested-by: Ville Syrj_l_ Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++-------- drivers/gpu/drm/i915/display/intel_hdmi.c | 50 ++++++++++++----------- drivers/gpu/drm/i915/display/intel_hdmi.h | 5 ++- 3 files changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b8585f83f660..61726742e8bb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1005,7 +1005,8 @@ static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp) static enum drm_mode_status intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, - int clock, int bpc, bool ycbcr420_output, + int clock, int bpc, + enum intel_output_format sink_format, bool respect_downstream_limits) { int tmds_clock, min_tmds_clock, max_tmds_clock; @@ -1013,7 +1014,7 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, if (!respect_downstream_limits) return MODE_OK; - tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output); + tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); min_tmds_clock = intel_dp->dfp.min_tmds_clock; max_tmds_clock = intel_dp_max_tmds_clock(intel_dp); @@ -1036,6 +1037,7 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_info *info = &connector->base.display_info; enum drm_mode_status status; bool ycbcr_420_only; + enum intel_output_format sink_format; /* If PCON supports FRL MODE, check FRL bandwidth constraints */ if (intel_dp->dfp.pcon_max_frl_bw) { @@ -1062,18 +1064,22 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, ycbcr_420_only = drm_mode_is_420_only(info, mode); + if (ycbcr_420_only && connector->base.ycbcr_420_allowed) + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + else + sink_format = INTEL_OUTPUT_FORMAT_RGB; + /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, ycbcr_420_only, true); + 8, sink_format, true); if (status != MODE_OK) { - if (ycbcr_420_only || - !connector->base.ycbcr_420_allowed || + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || !drm_mode_is_420_also(info, mode)) return status; - + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, true, true); + 8, sink_format, true); if (status != MODE_OK) return status; } @@ -1309,19 +1315,10 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); } -static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) -{ - return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || - (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && - intel_dp->dfp.ycbcr_444_to_420); -} - static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, int bpc, bool respect_downstream_limits) { - bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state); int clock = crtc_state->hw.adjusted_mode.crtc_clock; /* @@ -1341,8 +1338,8 @@ static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, for (; bpc >= 8; bpc -= 2) { if (intel_hdmi_bpc_possible(crtc_state, bpc, - intel_dp->has_hdmi_sink, ycbcr420_output) && - intel_dp_tmds_clock_valid(intel_dp, clock, bpc, ycbcr420_output, + intel_dp->has_hdmi_sink) && + intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format, respect_downstream_limits) == MODE_OK) return bpc; } diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index c0ae618360c3..99928ca5a435 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1793,11 +1793,6 @@ static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; } -static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) -{ - return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; -} - static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_downstream_limits, bool has_hdmi_sink) @@ -1871,10 +1866,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, return MODE_OK; } -int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output) +int intel_hdmi_tmds_clock(int clock, int bpc, + enum intel_output_format sink_format) { /* YCBCR420 TMDS rate requirement is half the pixel clock */ - if (ycbcr420_output) + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) clock /= 2; /* @@ -1901,7 +1897,8 @@ static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bp } static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, - int bpc, bool has_hdmi_sink, bool ycbcr420_output) + int bpc, bool has_hdmi_sink, + enum intel_output_format sink_format) { const struct drm_display_info *info = &connector->display_info; const struct drm_hdmi_info *hdmi = &info->hdmi; @@ -1911,7 +1908,7 @@ static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, if (!has_hdmi_sink) return false; - if (ycbcr420_output) + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; else return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; @@ -1919,7 +1916,7 @@ static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, if (!has_hdmi_sink) return false; - if (ycbcr420_output) + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; else return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; @@ -1933,7 +1930,8 @@ static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, static enum drm_mode_status intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, - bool has_hdmi_sink, bool ycbcr420_output) + bool has_hdmi_sink, + enum intel_output_format sink_format) { struct drm_i915_private *i915 = to_i915(connector->dev); struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); @@ -1946,12 +1944,12 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, * least one color depth is accepted. */ for (bpc = 12; bpc >= 8; bpc -= 2) { - int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output); + int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); if (!intel_hdmi_source_bpc_possible(i915, bpc)) continue; - if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output)) + if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format)) continue; status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); @@ -1976,6 +1974,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector, int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); bool ycbcr_420_only; + enum intel_output_format sink_format; if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) clock *= 2; @@ -2000,14 +1999,17 @@ intel_hdmi_mode_valid(struct drm_connector *connector, ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); - status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only); + sink_format = ycbcr_420_only ? INTEL_OUTPUT_FORMAT_YCBCR420 : INTEL_OUTPUT_FORMAT_RGB; + + status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); if (status != MODE_OK) { if (ycbcr_420_only || !connector->ycbcr_420_allowed || !drm_mode_is_420_also(&connector->display_info, mode)) return status; - status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true); + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); if (status != MODE_OK) return status; } @@ -2016,7 +2018,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector, } bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, - int bpc, bool has_hdmi_sink, bool ycbcr420_output) + int bpc, bool has_hdmi_sink) { struct drm_atomic_state *state = crtc_state->uapi.state; struct drm_connector_state *connector_state; @@ -2027,7 +2029,8 @@ bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, if (connector_state->crtc != crtc_state->uapi.crtc) continue; - if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output)) + if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, + crtc_state->sink_format)) return false; } @@ -2045,14 +2048,13 @@ static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc return false; /* Display Wa_1405510057:icl,ehl */ - if (intel_hdmi_is_ycbcr420(crtc_state) && + if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 && bpc == 10 && DISPLAY_VER(dev_priv) == 11 && (adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start) % 8 == 2) return false; - return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink, - intel_hdmi_is_ycbcr420(crtc_state)); + return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); } static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, @@ -2060,7 +2062,6 @@ static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, int clock, bool respect_downstream_limits) { struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); - bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state); int bpc; /* @@ -2078,7 +2079,8 @@ static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, bpc = 8; for (; bpc >= 8; bpc -= 2) { - int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output); + int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, + crtc_state->sink_format); if (hdmi_bpc_possible(crtc_state, bpc) && hdmi_port_clock_valid(intel_hdmi, tmds_clock, @@ -2108,7 +2110,7 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder, return bpc; crtc_state->port_clock = - intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state)); + intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); /* * pipe_bpp could already be below 8bpc due to @@ -2292,7 +2294,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, return ret; } - if (intel_hdmi_is_ycbcr420(pipe_config)) { + if (pipe_config->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { ret = intel_panel_fitting(pipe_config, conn_state); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h index 774dda2376ed..d1e27247b657 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.h +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h @@ -9,6 +9,7 @@ #include enum hdmi_infoframe_type; +enum intel_output_format; enum port; struct drm_connector; struct drm_connector_state; @@ -45,8 +46,8 @@ void intel_read_infoframe(struct intel_encoder *encoder, bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, - int bpc, bool has_hdmi_sink, bool ycbcr420_output); -int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output); + int bpc, bool has_hdmi_sink); +int intel_hdmi_tmds_clock(int clock, int bpc, enum intel_output_format sink_format); int intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, int output_format, bool hdmi_all_bpp, int hdmi_max_chunk_bytes); From patchwork Mon Feb 20 12:23:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB037C636CC for ; Mon, 20 Feb 2023 12:27:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0758510E67F; Mon, 20 Feb 2023 12:27:01 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 221BD10E67F for ; Mon, 20 Feb 2023 12:26:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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20 Feb 2023 04:26:53 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:54 +0530 Message-Id: <20230220122401.3495507-8-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 07/14] drm/i915/dp: Rearrange check for illegal mode and comments in mode_valid X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Check for MODE_H_ILLEGAL before calculating max rates, lanes etc. Move comments about compressed bpp U6.4 format closer to where it is used. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 61726742e8bb..f39e3dbe50f5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1136,6 +1136,9 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (target_clock > max_dotclk) return MODE_CLOCK_HIGH; + if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) + return MODE_H_ILLEGAL; + max_link_clock = intel_dp_max_link_rate(intel_dp); max_lanes = intel_dp_max_lane_count(intel_dp); @@ -1143,13 +1146,6 @@ intel_dp_mode_valid(struct drm_connector *_connector, mode_rate = intel_dp_link_required(target_clock, intel_dp_mode_min_output_bpp(connector, mode)); - if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) - return MODE_H_ILLEGAL; - - /* - * Output bpp is stored in 6.4 format so right shift by 4 to get the - * integer value since we support only integer values of bpp. - */ if (HAS_DSC(dev_priv) && drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { /* @@ -1158,6 +1154,10 @@ intel_dp_mode_valid(struct drm_connector *_connector, */ int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + /* + * Output bpp is stored in 6.4 format so right shift by 4 to get the + * integer value since we support only integer values of bpp. + */ if (intel_dp_is_edp(intel_dp)) { dsc_max_output_bpp = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; From patchwork Mon Feb 20 12:23:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83AB9C64EC4 for ; Mon, 20 Feb 2023 12:27:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E7AFA10E687; Mon, 20 Feb 2023 12:27:02 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1429D10E67F for ; Mon, 20 Feb 2023 12:26:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676896017; x=1708432017; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lkrjLQF3LaGY6LE35iO88qw992OsT1NYDX86va4aTs8=; b=OwEM4OGgjCADuwpGDrOYzoh5p63B477hCGVuNtr1RY7vJlXSiUnst5yP 6ammO1zcDZ9Lav6wY/5I7mgxI83DYQTNR6qhl7uTnZesaSc8iKWLFzwtB SDfP7XGL0CLcuZB/V6KyStUsbOu5DAj/ELzpdOvIEYuNJ5S8sGZdfaa01 EVLII6FkezZbDzFp5kgdTYZJa1TSCM6Zne1fEzC5QIL+8+W/W9H3y48+r EGYB6b648Hwn/EpXV+KFbzSHLSSSoA+I1ofPOd6YhJy3vgtUJoyROIkEN XXAClx++6A1Yn8KV1XGYlOJDFNfm7tLYz9kBdeu7zeydnjsudlKohQUV5 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073445" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073445" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:56 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142100" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142100" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:55 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:55 +0530 Message-Id: <20230220122401.3495507-9-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 08/14] drm/i915/dp: Consider output_format while computing dsc bpp for mode_valid X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During modevalid step, the pipe bpp is computed assuming RGB output format. When checking with DSC, consider the output_format and compute the input bpp for DSC appropriately. v2: For DP-MST we currently use RGB output format only, so continue using RGB while computing dsc_bpp for MST case. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 28 ++++++++++++++++----- drivers/gpu/drm/i915/display/intel_dp.h | 4 ++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 3 files changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f39e3dbe50f5..dfd7af97ea55 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1148,11 +1148,21 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (HAS_DSC(dev_priv) && drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + int pipe_bpp; + enum intel_output_format output_format, sink_format; + const struct drm_display_info *info = &connector->base.display_info; + + if (drm_mode_is_420_only(info, mode)) + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + else + sink_format = INTEL_OUTPUT_FORMAT_RGB; + + output_format = intel_dp_output_format(connector, mode, sink_format, true); /* * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, output_format, U8_MAX); /* * Output bpp is stored in 6.4 format so right shift by 4 to get the @@ -1492,12 +1502,15 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return -EINVAL; } -int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, + enum intel_output_format output_format, + u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int i, num_bpc; u8 dsc_bpc[3] = {0}; u8 dsc_max_bpc; + int pipe_bpp = 0; /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ if (DISPLAY_VER(i915) >= 12) @@ -1508,11 +1521,13 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, dsc_bpc); for (i = 0; i < num_bpc; i++) { - if (dsc_max_bpc >= dsc_bpc[i]) - return dsc_bpc[i] * 3; + if (dsc_max_bpc >= dsc_bpc[i]) { + pipe_bpp = dsc_bpc[i] * 3; + break; + } } - return 0; + return intel_dp_output_bpp(output_format, pipe_bpp); } static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp) @@ -1626,7 +1641,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; if (compute_pipe_bpp) - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); + pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, pipe_config->output_format, + conn_state->max_requested_bpc); else pipe_bpp = pipe_config->pipe_bpp; diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index ef39e4f7a329..2f4136e43f38 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -102,7 +102,9 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); -int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, + enum intel_output_format output_format, + u8 dsc_max_bpc); u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 054b179d0b6a..d005f1aad337 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -910,7 +910,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, INTEL_OUTPUT_FORMAT_RGB, U8_MAX); if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { dsc_max_output_bpp = From patchwork Mon Feb 20 12:23:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13ADDC64EC4 for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073452" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073452" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:58 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142104" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142104" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:57 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:56 +0530 Message-Id: <20230220122401.3495507-10-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 09/14] drm/i915/dp: Check if mode can be supported with dsc compressed bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use compressed bpp to calculate mode_rate during dp_mode_valid. Check if this can be supported with max lane count and link rate combination. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index dfd7af97ea55..60090fbbca5f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1143,8 +1143,6 @@ intel_dp_mode_valid(struct drm_connector *_connector, max_lanes = intel_dp_max_lane_count(intel_dp); max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); - mode_rate = intel_dp_link_required(target_clock, - intel_dp_mode_min_output_bpp(connector, mode)); if (HAS_DSC(dev_priv) && drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { @@ -1200,7 +1198,12 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) return MODE_CLOCK_HIGH; - if (mode_rate > max_rate && !dsc) + if (dsc) + mode_rate = intel_dp_link_required(target_clock, dsc_max_output_bpp); + else + mode_rate = intel_dp_link_required(target_clock, + intel_dp_mode_min_output_bpp(connector, mode)); + if (mode_rate > max_rate) return MODE_CLOCK_HIGH; status = intel_dp_mode_valid_downstream(connector, mode, target_clock); From patchwork Mon Feb 20 12:23:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DAF1C636CC for ; Mon, 20 Feb 2023 12:27:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C92A910E692; Mon, 20 Feb 2023 12:27:11 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id AE69710E67F for ; Mon, 20 Feb 2023 12:27:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676896020; x=1708432020; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IV0rBDhDpVaymXwtwfMSq7QHPRpZhZkTTvHtxrs594g=; b=K4fFObunEQQjSBzVZjUcBCWjpuIMCoRZqeWTAEkfAZ5t26T2pbX4Jokb tcFYARGMvJHJc+r1HPOGoYsXty5VFJuLy6pBAOxHDxj+cX5ANFt/QDcHG ksAEJPAi8ZtmY0SQotBcazGosCK0TUvpc/6NtzcvVRKGln2JYHn1Lf36Y 0rnVnSML8HmfvIByUHFcUyITzfK/792BhkHddUnejscBnqqtmerDT0qhh ZLu3hB1zWyxv1woVUc0oxLV8QJgFyAY2Jhpds/Oz2JJzn2xq3zL1s0hVG 1J4BDAVAIloX5fbLobYSq/WoyR9TIpj6M43MpUaVXlfV4Q8A8Orff9PU2 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073457" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073457" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:27:00 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142108" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142108" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:26:58 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:57 +0530 Message-Id: <20230220122401.3495507-11-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 10/14] drm/i915/display: Add helper function to check if sink_format is 420 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add an inline helper function to check if the sink_format is set to YCBCR420 format. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++++++ drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +++--- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1be15a1caa39..9bcccf02a2b1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -2067,4 +2067,10 @@ to_intel_frontbuffer(struct drm_framebuffer *fb) return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; } +static inline bool +intel_crtc_has_420_sink_format(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420; +} + #endif /* __INTEL_DISPLAY_TYPES_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 60090fbbca5f..a2baec2f7b03 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2192,7 +2192,7 @@ intel_dp_compute_output_format(struct intel_encoder *encoder, ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state, respect_downstream_limits, with_dsc); if (ret) { - if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || + if (intel_crtc_has_420_sink_format(crtc_state) || !drm_mode_is_420_also(info, adjusted_mode)) return ret; @@ -2906,7 +2906,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", str_enable_disable(intel_dp->has_hdmi_sink)); - if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { + if (intel_crtc_has_420_sink_format(crtc_state)) { switch (crtc_state->output_format) { case INTEL_OUTPUT_FORMAT_YCBCR420: /* diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 99928ca5a435..573781484e73 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2048,7 +2048,7 @@ static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc return false; /* Display Wa_1405510057:icl,ehl */ - if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 && + if (intel_crtc_has_420_sink_format(crtc_state) && bpc == 10 && DISPLAY_VER(dev_priv) == 11 && (adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start) % 8 == 2) @@ -2210,7 +2210,7 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, crtc_state->output_format = intel_hdmi_output_format(crtc_state, connector); ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); if (ret) { - if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || + if (intel_crtc_has_420_sink_format(crtc_state) || !drm_mode_is_420_also(info, adjusted_mode)) return ret; @@ -2294,7 +2294,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, return ret; } - if (pipe_config->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) { + if (intel_crtc_has_420_sink_format(pipe_config)) { ret = intel_panel_fitting(pipe_config, conn_state); if (ret) return ret; From patchwork Mon Feb 20 12:23:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E48CC05027 for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073463" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073463" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:27:02 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142111" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142111" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:27:00 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:58 +0530 Message-Id: <20230220122401.3495507-12-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 11/14] drm/i915/dp: Avoid DSC with output_format YCBCR420 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently, DSC with YCBCR420 is not supported. Return -EINVAL when trying with DSC with output_format as YCBCR420. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a2baec2f7b03..74293f23dd67 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1643,6 +1643,10 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_supports_dsc(intel_dp, pipe_config)) return -EINVAL; + /* Currently DSC with YCBCR420 format is not supported */ + if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + return -EINVAL; + if (compute_pipe_bpp) pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, pipe_config->output_format, conn_state->max_requested_bpc); From patchwork Mon Feb 20 12:23:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CA8DC05027 for ; Mon, 20 Feb 2023 12:27:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F33DD10E68D; Mon, 20 Feb 2023 12:27:18 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5A17910E68B for ; Mon, 20 Feb 2023 12:27:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676896024; x=1708432024; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EiAoXnjdosHOdUei3uX0V7PRK+FMP0XNK3W+1BFqRqE=; b=RX7Wml2xQLSPt3DGgHEDm9Wf5UkCgmrNc0ns9U1+UAqEsbBlmsTGZprl iM/CdcUsDE3Lh0qm2x2euJmVgfC1U/tu9jkK9IGwUOpvC2YtxOmqm8RXi Rl2HDFW5OrzeoG+gX/HQ90PJz6Ibak/9j54sweIerf/GaCm7o3Vtp6iE9 ePWFLKpiyVOCnbqtiQ7HnVcQV/9uChO3Ww6km5e93tAKu9MXTKyPe2kqu h08HSr/7dJLqxrM0z1GrqwA3NBeC0L9al5FtDaozEezVrkmIWJMoeRlXl FkInRm9gbZXJK6IfCwu7uZt+SByzQy+gC2e3AaI4j1VtZvX2wD1bjU+um A==; X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073468" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073468" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:27:04 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142115" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142115" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:27:02 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:53:59 +0530 Message-Id: <20230220122401.3495507-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 12/14] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we use the highest input BPC supported by DP sink while using DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same input BPC that is used between Source and the PCON without DSC, which might not work even with the maximum FRL rate supported by HDMI2.1 sink. This patch calculates the max BPC that can be sufficient with either RGB or YCBCR420 format for the maximum FRL rate supported. v2: Rebase v3: Use the sink_format in the functions instead of ycbcr420 flag. v4: Rebase Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 61 +++++++++++++++++++++++-- 1 file changed, 58 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 74293f23dd67..d1f3c5d00cd8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -116,6 +116,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) return dig_port->base.type == INTEL_OUTPUT_EDP; } +static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp); static void intel_dp_unset_edid(struct intel_dp *intel_dp); /* Is link rate UHBR and thus 128b/132b? */ @@ -1623,6 +1624,39 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return drm_dsc_compute_rc_parameters(vdsc_cfg); } +static int +intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int max_bpc) +{ + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; + int i, num_bpc; + u8 dsc_bpc[3] = {0}; + int req_rate_gbps; + int max_frl_rate = connector->display_info.hdmi.max_lanes * + connector->display_info.hdmi.max_frl_rate_per_lane; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (dsc_bpc[i] > max_bpc) + continue; + + req_rate_gbps = DIV_ROUND_UP(dsc_bpc[i] * 3 * adjusted_mode->clock, 1000000); + + /* YCBCR420 reduces data rate by 2 */ + if (intel_crtc_has_420_sink_format(pipe_config)) + req_rate_gbps /= 2; + + if (req_rate_gbps < max_frl_rate) + return dsc_bpc[i] * 3; + } + + return 0; +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1631,6 +1665,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, bool compute_pipe_bpp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; @@ -1647,12 +1683,31 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) return -EINVAL; - if (compute_pipe_bpp) + /* + * In cases where PCON with HDMI2.1 as branch device, if PCON supports + * DSC but HDMI2.1 sink does not supports DSC, there can be issues due + * to the bpc used. + * With DSC, a source-PCON pair can support the mode with higher bpcs. + * But PCON->Sink pair, cannot support the same bpc without sink having + * DSC support. + * So use the max BPC as input BPC that will be sufficient to show the + * mode without DSC from PCON->HDMI2.1 + */ + if (intel_dp_is_hdmi_2_1_sink(intel_dp) && + !connector->display_info.hdmi.dsc_cap.v_1p2) { + pipe_bpp = intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, pipe_config, + conn_state->max_requested_bpc); + if (!pipe_bpp) { + drm_dbg_kms(&dev_priv->drm, + "No BPC possible to support the mode without HDMI2.1 DSC\n"); + return -EINVAL; + } + } else if (compute_pipe_bpp) { pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, pipe_config->output_format, conn_state->max_requested_bpc); - else + } else { pipe_bpp = pipe_config->pipe_bpp; - + } if (intel_dp->force_dsc_bpc) { pipe_bpp = intel_dp->force_dsc_bpc * 3; drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp); From patchwork Mon Feb 20 12:24:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41010C636CC for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073471" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073471" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:27:06 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142122" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142122" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:27:04 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:54:00 +0530 Message-Id: <20230220122401.3495507-14-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 13/14] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During FRL bandwidth check for downstream HDMI2.1 sink, the min BPC supported is incorrectly taken for DP, and the check does not consider ybcr420 only modes. This patch fixes the bandwidth calculation similar to the TMDS case, by taking min 8Bpc and considering Ycbcr420 only modes. v2: Rebase Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 64 +++++++++++++++++-------- 1 file changed, 45 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d1f3c5d00cd8..f8105201486b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -118,6 +118,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp); static void intel_dp_unset_edid(struct intel_dp *intel_dp); +static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) @@ -1029,6 +1030,32 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, return MODE_OK; } +static enum drm_mode_status +intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock, + int bpc, enum intel_output_format sink_format) +{ + int target_bw; + int max_frl_bw; + int bpp = bpc * 3; + + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) + target_clock /= 2; + + target_bw = bpp * target_clock; + + /* check for MAX FRL BW for both PCON and HDMI2.1 sink */ + max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw, + intel_dp_hdmi_sink_max_frl(intel_dp)); + + /* converting bw from Gbps to Kbps*/ + max_frl_bw = max_frl_bw * 1000000; + + if (target_bw > max_frl_bw) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, @@ -1037,24 +1064,30 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, struct intel_dp *intel_dp = intel_attached_dp(connector); const struct drm_display_info *info = &connector->base.display_info; enum drm_mode_status status; - bool ycbcr_420_only; + bool ycbcr_420_only = drm_mode_is_420_only(info, mode); enum intel_output_format sink_format; + ycbcr_420_only = drm_mode_is_420_only(info, mode); + /* If PCON supports FRL MODE, check FRL bandwidth constraints */ if (intel_dp->dfp.pcon_max_frl_bw) { - int target_bw; - int max_frl_bw; - int bpp = intel_dp_mode_min_output_bpp(connector, mode); - - target_bw = bpp * target_clock; - max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; - - /* converting bw from Gbps to Kbps*/ - max_frl_bw = max_frl_bw * 1000000; + if (ycbcr_420_only && connector->base.ycbcr_420_allowed) + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + else + sink_format = INTEL_OUTPUT_FORMAT_RGB; - if (target_bw > max_frl_bw) - return MODE_CLOCK_HIGH; + /* Assume 8bpc for the HDMI2.1 FRL BW check */ + status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); + if (status != MODE_OK) { + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || + !drm_mode_is_420_also(info, mode)) + return status; + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); + if (status != MODE_OK) + return status; + } return MODE_OK; } @@ -1063,13 +1096,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; - ycbcr_420_only = drm_mode_is_420_only(info, mode); - - if (ycbcr_420_only && connector->base.ycbcr_420_allowed) - sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - else - sink_format = INTEL_OUTPUT_FORMAT_RGB; - /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, sink_format, true); From patchwork Mon Feb 20 12:24:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ankit Nautiyal X-Patchwork-Id: 13146376 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 089A4C05027 for ; Mon, 20 Feb 2023 12:27:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8702610E68C; Mon, 20 Feb 2023 12:27:10 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 04F7510E68B for ; Mon, 20 Feb 2023 12:27:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676896028; x=1708432028; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fKefoFpNeRKuteZTseb8akBlfJ1+qtugN2l/lBc58J8=; b=BauwiNtO3E3QrSwYU8aXlyrOKaDhI3Whc8eNXdsl1xOHvtdtAnrdPVkZ hSlrcAy7a7lylu5q1UabjuGj1qoZg7LU324d9JHa943ZoklrEFIkD97ww CzvOksb2bU/TE+iVvoeNFexnfrPVxvgwbVuT+kiIzJzMq5NQ4zip+O1K+ qCpMZUs8j/3gSl9x17Jf9SgcKD1iKc41e3WkUMlHRDuhPNZ3Ua+gQRpr/ Yx+stPAoxpOSdCAS+7j9DyI0AXluP+FHKaSmHSWxR149oA8+OKjelMnqN WyLPPJqom+hITh5fINs8oEl62DSIavW/oqa4AG4bUCsgPQcwIwELej/y/ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="397073477" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="397073477" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:27:07 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10626"; a="621142128" X-IronPort-AV: E=Sophos;i="5.97,312,1669104000"; d="scan'208";a="621142128" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Feb 2023 04:27:06 -0800 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Feb 2023 17:54:01 +0530 Message-Id: <20230220122401.3495507-15-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> References: <20230220122401.3495507-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 14/14] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a wrapper function to check dp_downstream clock/bandwidth constraints. Based on whether the sink supports FRL/TMDS the wrapper calls the appropriate FRL/TMDS functions. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 51 +++++++++++-------------- 1 file changed, 23 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f8105201486b..838b72a555ba 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1056,6 +1056,18 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock, return MODE_OK; } +static enum drm_mode_status +intel_dp_hdmi_bw_check(struct intel_dp *intel_dp, + int target_clock, int bpc, + enum intel_output_format sink_format, + bool is_frl) +{ + if (is_frl) + return intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); + + return intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, sink_format, true); +} + static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, @@ -1065,48 +1077,31 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_info *info = &connector->base.display_info; enum drm_mode_status status; bool ycbcr_420_only = drm_mode_is_420_only(info, mode); + bool is_frl; enum intel_output_format sink_format; + int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw heck */ - ycbcr_420_only = drm_mode_is_420_only(info, mode); + if (ycbcr_420_only && connector->base.ycbcr_420_allowed) + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + else + sink_format = INTEL_OUTPUT_FORMAT_RGB; /* If PCON supports FRL MODE, check FRL bandwidth constraints */ - if (intel_dp->dfp.pcon_max_frl_bw) { - - if (ycbcr_420_only && connector->base.ycbcr_420_allowed) - sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - else - sink_format = INTEL_OUTPUT_FORMAT_RGB; - - /* Assume 8bpc for the HDMI2.1 FRL BW check */ - status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); - if (status != MODE_OK) { - if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || - !drm_mode_is_420_also(info, mode)) - return status; - sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); - if (status != MODE_OK) - return status; - } + is_frl = intel_dp->dfp.pcon_max_frl_bw ? true : false; - return MODE_OK; - } - - if (intel_dp->dfp.max_dotclock && + if (!is_frl && intel_dp->dfp.max_dotclock && target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; - /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ - status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, sink_format, true); + status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, is_frl); if (status != MODE_OK) { if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || !drm_mode_is_420_also(info, mode)) return status; sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, sink_format, true); + status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, is_frl); + } else { if (status != MODE_OK) return status; }