From patchwork Tue Feb 21 10:50:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 13147627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69BCEC64EC4 for ; Tue, 21 Feb 2023 10:52:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=WhW9lSU/uVS+wDfkK9tqN8J/2IhNoz2bBbLyH5P6obc=; b=vDPTvFUGYQuMB1 tsVD3T7yMqocVShjNXF9aIvq6GhywYpGwK7c6wTpMcRuk3vapu1w6L+ya0yodJ5pXrq4jqUK8l/gE nrugioDI64+1niNZCfRaq2SAVdipMwYAxsZOWXgzm8aytvsKNxeICyUbfNRT9jOEZq+8G8DsObGzD Qp60AYB5kVYanaFrpyQr/MoSrJTPYwG09k10OfTOPrdVuLXCziGyqTM5rb6khvu+GfizwH/Sx5Ecr M8Uzt4QPoAm0CEdJXrQHQsf3zO9P/b3FCFWW6bryuXv36jvPHNRlXsXyoFnbJB9AkS1ICn2/MT+UT Z62r4mnK926OoAu8iANQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUQEU-007RqW-My; Tue, 21 Feb 2023 10:50:50 +0000 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUQER-007Ro0-Ax for linux-arm-kernel@lists.infradead.org; Tue, 21 Feb 2023 10:50:48 +0000 Received: by mail-ed1-x52b.google.com with SMTP id ec43so14843779edb.8 for ; Tue, 21 Feb 2023 02:50:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura.hr; s=sartura; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=pYjWLgQYUyf0rfB+O28fl3yoRQb/M04CEuNH5hkz1cs=; b=p2wzYBo3W+HrqRwhYizv8ezrYEbXHvTHEGP4HDkZqnrL1td9lLY1poI37muWJ7sd3y Bd24g575XQwvAkILeyYn1CiV7LmkE+VFqxzYM8GiLqM3nPNvVOE2MTvW+j6Uf+petFQV /fL4aVnW6Awf9JyCMGMvLK/ckLO2+5LEFuVgo1wLs5cAY3yPZ+PoRu73RTIa/sfZJYxP vwZv0CpqP0copFJkNX++pG1KyBQarJ1StdWJlc+fh/vsDYKyjAhOSV/ZrQAPiQbQdXLQ v5eA2Qr9dqfCgE2gdryWm2viN/kqaT7cnzY9+2w7KioLjpVxTe90Et9jd6dIgH/ieg83 9hGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=pYjWLgQYUyf0rfB+O28fl3yoRQb/M04CEuNH5hkz1cs=; b=l5GD9PqcvXg1Og9bxdgYbOdHcBLczULhyhTTFe8J4wynpX1ElvJyzLY5OxUQXemUsu x8Sl88PnZI/0JGuVfmdwnXL7KVLGbHgbgGaURYK3BUmMX+NYIA+yFbsvGSi2DtbA+xOw qMvGjodd2Jm1akbR706kyMx+Jf9rWPTYchN8JjoDCVyZyr7UpFYah7SGNskIAHbzzvlp EsB+pWJ3XUwPSFLU1+EiGvbgDf4J9PMZo7zulxan05jUWlgi6/9MlNlz1fgXTWqTRMtA 7MGROJTsKxEQ+XD4y5RsRqGO4hmogxeRq021HMDTzm2Ks03ny/Yc0aCa7umdSGI3tYPz Psiw== X-Gm-Message-State: AO0yUKV4b4DBQ+qXK9CDQA9NYh/eP1rlwNhrWbAnkhZ+GNeItx5WaQMv CAHJ2TunCc7j/ZhKDaxxOXeSCA== X-Google-Smtp-Source: AK7set+cFpf8rY+4xMoIg5FcZ+hPP4nkQ6KLR86qzt/E74X3ahuDQFPJBCZTgVf2Pbt3I5AlZXx3Cg== X-Received: by 2002:a17:907:e8d:b0:8b1:2e8f:d524 with SMTP id ho13-20020a1709070e8d00b008b12e8fd524mr19296846ejc.27.1676976642934; Tue, 21 Feb 2023 02:50:42 -0800 (PST) Received: from fedora.. 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[88.207.97.58]) by smtp.googlemail.com with ESMTPSA id bk26-20020a170906b0da00b0089d5aaf85besm6955802ejb.219.2023.02.21.02.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 02:50:42 -0800 (PST) From: Robert Marko To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lars.povlsen@microchip.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, arnd@arndb.de, alexandre.belloni@bootlin.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v2 1/3] arm64: dts: microchip: sparx5: do not use PSCI on reference boards Date: Tue, 21 Feb 2023 11:50:37 +0100 Message-Id: <20230221105039.316819-1-robert.marko@sartura.hr> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230221_025047_414485_C54602AD X-CRM114-Status: GOOD ( 14.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that is shipped does not implement it as well. I have tried flashing the latest BSP 2022.12 U-boot which did not work. After contacting Microchip, they confirmed that there is no ATF for the SoC nor PSCI implementation which is unfortunate in 2023. So, disable PSCI as otherwise kernel crashes as soon as it tries probing PSCI with, and the crash is only visible if earlycon is used. Since PSCI is not implemented, switch core bringup to use spin-tables which are implemented in the vendor U-boot and actually work. Tested on PCB134 with eMMC (VSC5640EV). Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko Acked-by: Steen Hegelund --- Changes in v2: * As suggested by Arnd, disable PSCI only on reference boards --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 +- arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 0367a00a269b3..5eae6e7fd248e 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -61,7 +61,7 @@ arm-pmu { interrupt-affinity = <&cpu0>, <&cpu1>; }; - psci { + psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi index 9d1a082de3e29..32bb76b3202a0 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -6,6 +6,18 @@ /dts-v1/; #include "sparx5.dtsi" +&psci { + status = "disabled"; +}; + +&cpu0 { + enable-method = "spin-table"; +}; + +&cpu1 { + enable-method = "spin-table"; +}; + &uart0 { status = "okay"; }; From patchwork Tue Feb 21 10:50:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 13147625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D43E4C64EC4 for ; Tue, 21 Feb 2023 10:51:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6zg1iZB2qN4Iq7ttG8vlvZWLSep4i1uLBHyep2zmxvo=; b=Um1frAVb0Xgv2P XZnpEXBEsTWVIsN6y7ZgRGRsjXK+ez0NDt9skfeqU62fFdwfZeuqbpUT4mHefWR/fA4qdYGE/xHpB o5DkJFKrV/zfMRubpsHf5BZdUHwv1q/ABBLDk3AATRe1zeJ+J6rNjsHRnDrlIFsrFmYqyxVaP9cBa lF39Da7lJoZbBpU6UFvGnC/8PJtdyStmbVx1VLVd0S/AwHNvFFAQP1+46+Tlyo7310u/5IkXTrD5b XSy1NsftUob99aOAzWMCuPOB+QvF1qOf8cwMoVCCdxEzCtNpq1ngrQJddjEeye2re6jR+0gT88jT5 pFqX4pj6xOdUwQxIIvnw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUQEc-007Rt7-Im; Tue, 21 Feb 2023 10:50:58 +0000 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUQER-007Rom-Ps for linux-arm-kernel@lists.infradead.org; Tue, 21 Feb 2023 10:50:49 +0000 Received: by mail-ed1-x52a.google.com with SMTP id f13so14812431edz.6 for ; Tue, 21 Feb 2023 02:50:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura.hr; s=sartura; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ApMcsU4SYE3sBKMbTvqLq1Sm/IwL/ogI22P3eYaAobA=; b=nJjAKok+QWjwzqcccLIOmTbIbYB7wJCQ3D4e0bzfmx4InfttIlr0yypLruxx/+4TBN BAjbEUZrs9H2PfZWhEgfN5NWdPLdpGNMWpeS+FQEouQKqZEQOkdQTHOLjfocyJTQLae4 dHwsK+bTdn1ds5WVdfsuIpV31GXbgKBnmIRLe6l9eUBsS41hFJzc8zxwTXdSehlw/H1r WAKBKUd/1ur1Rvq/uZxgTH9qPFOCCXcXynLucOvaU92XYzNs+Y0yTzonOK5h6E87PH2j /mlN8FyMW25orWMqoP6XMJ4ri64t5ELg/8hkZkWwSQieKMyqD8etdJMNRC/7ipoL0IFk L2Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ApMcsU4SYE3sBKMbTvqLq1Sm/IwL/ogI22P3eYaAobA=; b=zAI1thCGhF/LWiLkZdPc1lq8cbtWyfL8BBhDrhTew4Z377mtI08nCtGsm4ZX8Zex7N hXScUZ4k3Xcc0G8SExqnmazcgWcVhnu1O8BkrMO/HedBlRaGG4fYu7034ncV6wqGc/uD 5Dv8ZqA/oZQRviYroNQN5Xt95hje+hex+xEERiiobyNyi1lONkhfqHYCf3Vzry13dXgd aG4Vr7HgYp7V04qAQP+ix3mh+L0M886fQW+s/J3Q3yifV90uBrRk5lba2qu82La5XEXY DzoEiUxJZBLYBayvHhFJAXveoB2oR3vvDmWPVgSKfof4GP/Sjzjax1qlmp9AAvSf4mMG MU2Q== X-Gm-Message-State: AO0yUKVuw5/5nk7xaiVECGtNmLqsxPlO6WMJ7vWH0hpcVa86gfNA2li8 GFTpQ8iHUigP3qBIQfBzu1Q3SM/4hE49yPIv X-Google-Smtp-Source: AK7set+j0uiYd+nc5Eev9K2O5LttZtylg7DcBJhMz47XtJ2xRc+wNr3o7Q7QoDVUb89hIiYpT/WZGQ== X-Received: by 2002:a17:906:9750:b0:8b3:946d:51c8 with SMTP id o16-20020a170906975000b008b3946d51c8mr17519162ejy.29.1676976644132; Tue, 21 Feb 2023 02:50:44 -0800 (PST) Received: from fedora.. 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[88.207.97.58]) by smtp.googlemail.com with ESMTPSA id bk26-20020a170906b0da00b0089d5aaf85besm6955802ejb.219.2023.02.21.02.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 02:50:43 -0800 (PST) From: Robert Marko To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lars.povlsen@microchip.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, arnd@arndb.de, alexandre.belloni@bootlin.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v2 2/3] arm64: dts: microchip: sparx5: correct CPU address-cells Date: Tue, 21 Feb 2023 11:50:38 +0100 Message-Id: <20230221105039.316819-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230221105039.316819-1-robert.marko@sartura.hr> References: <20230221105039.316819-1-robert.marko@sartura.hr> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230221_025047_856290_B0C34147 X-CRM114-Status: GOOD ( 11.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There is no reason for CPU node #address-cells to be set at 2, so lets change them to 1 and update the reg property accordingly. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 5eae6e7fd248e..a4fabacf5c2f7 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -24,7 +24,7 @@ chosen { }; cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { @@ -39,14 +39,14 @@ core1 { cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x0>; + reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x1>; + reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; }; From patchwork Tue Feb 21 10:50:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 13147626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E241C6379F for ; Tue, 21 Feb 2023 10:52:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=l38ZDRrGvEMP5B9Vc0PVy85mn1fpNeNjxrhYNKZy9Uc=; b=p9tpkqAZyE/UBR EjRjPLMk4Bo5cRGvApJ/mhM/R5y1EbfAOwzEWVmGFPaKvihoRiOaDSnR3oWQTcP6Wg8n6n18HBtUd 9V94wa/71JEaXUFK9p0pqJpM5JYH9YQOYBIB9sMUZ0Q9k5s81wvhXq40niZyA2Yp4L9PcBwSbHPDF LQha6ZDVGom/Vl+b1xavIiq/W/j4giGnNAtI/HuBz5IF0f73a6r29WEN2uUl0aAGHAIfV9FqNKky5 gtR3BOJrI6M1tjbx55qmJ7TOAv6uOpEtiRGnBOaNiMpRGUMLMymm2FrfwF9MyNVUpnjUMnoiBN2Do FyvTU0cwjsVW+Az5Qt9g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUQEl-007Rux-0c; Tue, 21 Feb 2023 10:51:07 +0000 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUQER-007Roz-Pt for linux-arm-kernel@lists.infradead.org; Tue, 21 Feb 2023 10:50:50 +0000 Received: by mail-ed1-x52a.google.com with SMTP id b12so15329282edd.4 for ; Tue, 21 Feb 2023 02:50:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura.hr; s=sartura; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0gk2DSmgvASQ5V9ePr4xMv7HQyGXDamFtmo/+7H0H7Q=; b=z6QrFp/Krt2zgU4roCx/tRFt9FnkDlEc8AOluIPbFpZzT/A/IB2zZiuh8MulzCnAgi Sd50gCC86ozaK7xkP1UFO3Wz0vOZxDo/RDTKjmmV52tUsiuXE6BasomSPjWwmNj6NVJc tPJajapj7D1Y3dPhQDI9SyPSgCLYvy01oSwgr4T3RlITMT2i76EEQMRwCruEsWzFPPDi afhbSbVjO7IzBMnWErmwWAgvcjkhLyPx4MMjD0MbUQ/e/8zv2tTKKQwQSfUH6xyr76Oz h+bnoIH5do3PEjNSm6vUX/Oce8OVjcG/Un0suI8PY2sFvSHfTVJ2aV81VECSNfBYMz8+ ze0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0gk2DSmgvASQ5V9ePr4xMv7HQyGXDamFtmo/+7H0H7Q=; b=7xmmDQ096RqOSvvZVBp3QEYEhXjHTuvDfpBr7huJpN2GS2poVQm1LbgNKREVj4Sf61 DtvX7KShrJXZPNsqCp235cLL5eMomB4QpC5Bnb7MsLGjwTRltNvVfNMUUR4Y9OBtgHoD /LEjcwM49WfOmNuUJIiDp4hys/4LYVJx3ibZoS9Upz9lEUx5L26oZB4g8qj7U58lq8L3 7YZC9t+UFkzYYyEozruu5EDP83JYuKMQJXOXG+PZBmmburrkncSrVqyUtZW4InbExPLM PJQA/P+JvsVfpFgKHfuXSlZYxK2s2OySCkb6hWAYEp5ZiOMaVcD7CfC/YgTjz3xx2LhV RtCg== X-Gm-Message-State: AO0yUKURoJLP0pL5opxLUgYQc01v1EUY7aYRwAS4Z3kbWstwIzxByxPN bQ6iHkpx/9xKym1J5JRpdp7gXQ== X-Google-Smtp-Source: AK7set/x+xrpGP3FABf85L02cSovpPeNu1WquJ0oYlJzMGgDuyd4gj7BOgNrzBcofGxfp1/Yzv0rHw== X-Received: by 2002:a17:906:ad82:b0:8af:40b0:3dd1 with SMTP id la2-20020a170906ad8200b008af40b03dd1mr11760401ejb.27.1676976645348; Tue, 21 Feb 2023 02:50:45 -0800 (PST) Received: from fedora.. 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[88.207.97.58]) by smtp.googlemail.com with ESMTPSA id bk26-20020a170906b0da00b0089d5aaf85besm6955802ejb.219.2023.02.21.02.50.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 02:50:44 -0800 (PST) From: Robert Marko To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lars.povlsen@microchip.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, arnd@arndb.de, alexandre.belloni@bootlin.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v2 3/3] arm64: dts: microchip: sparx5: add missing L1/L2 cache information Date: Tue, 21 Feb 2023 11:50:39 +0100 Message-Id: <20230221105039.316819-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230221105039.316819-1-robert.marko@sartura.hr> References: <20230221105039.316819-1-robert.marko@sartura.hr> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230221_025047_861557_F31D8A46 X-CRM114-Status: GOOD ( 12.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently, when booting on SparX-5 you will get the following error: [ 0.050132] Early cacheinfo failed, ret = -22 This is due to L2 cache node missing cache-level property to indicate its level, so populate it to let the kernel know its L2 cache. However, that alone is enough to get rid of the error, but then the following warnings appear: [ 0.050162] cacheinfo: Unable to detect cache hierarchy for CPU 0 [ 0.093256] cacheinfo: Unable to detect cache hierarchy for CPU 1 So, lets completely populate both the L1 and L2 cache info based off the SoC datasheet[1] and ARM A53 technical reference manual[2]. Now "lscpu -C" provides: NAME ONE-SIZE ALL-SIZE WAYS TYPE LEVEL SETS PHY-LINE COHERENCY-SIZE L1d 32K 64K 4 Data 1 128 64 L1i 32K 64K 2 Instruction 1 256 64 L2 256K 256K 16 Unified 2 256 64 Tested on PCB134 (eMMC). [1] https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/DataSheets/SparX-5_Family_L2L3_Enterprise_25G_Ethernet_Switches_Datasheet_00003823D.pdf [2] https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System/About-the-L1-memory-system?lang=en Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index a4fabacf5c2f7..950ba78bf73f3 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -41,6 +41,12 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0x0>; enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set next-level-cache = <&L2_0>; }; cpu1: cpu@1 { @@ -48,10 +54,21 @@ cpu1: cpu@1 { device_type = "cpu"; reg = <0x1>; enable-method = "psci"; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set next-level-cache = <&L2_0>; }; L2_0: l2-cache0 { compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <256>; // 256KB(size)/64(line-size)=4096ways/16-way set + cache-level = <2>; }; };