From patchwork Wed Feb 22 18:39:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149470 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9E9FC6FA99 for ; Wed, 22 Feb 2023 18:41:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TsL1LxuK6cQV0DDuNWg22Akcg6l93ucbJD1naIBAoV8=; b=aP3HDK585I3xUQ QEcccuCK5k7d9Q/yYVMT0WhC6pCuiah7NngCy9kGt376l/2shSql0sns2VGfIQrtCYFe+99Ylorwi VYbHZo8c+4vC6czwD5KOZyu0AovWTKW+7afpLXVa7k0j7eo5w3DT3gwuQheVEnnR9Yf1WlilyyD3Q 36iJXxY3eyd0o1YheSN7cANs4+p/D0ggXjOvxRfjWjBLDc41t1xoMLhJwK7jaR4xDX72i5H5Z1DvB 1DI6b0clP//ClJvePf6+tcYx7hEbPu9hHkDtpUPKvStoeIbtJ3WZ0YjVfAGALlgPPQyPmpNaec2q0 BU1vgg022DjXhBxkLEuA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2P-00DTq4-DS; Wed, 22 Feb 2023 18:40:21 +0000 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu25-00DTfQ-QE; Wed, 22 Feb 2023 18:40:03 +0000 Received: by mail-wr1-x434.google.com with SMTP id t15so8859369wrz.7; Wed, 22 Feb 2023 10:40:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=foDA/GXxUeG6qywVw7pPHlQfm+Orh3kvLzj/my6QoE8=; b=B9+WOGfkjvzGfunEXkLYy8KTjSrl99QhGvrJByDf0VqgZLm54rAB8+A9V8YhbSMxEv BBVeVV1Kk+uc/mDULVvKuDcXyq/JGZ14j1nhe6Fiqk4cjafKSUB3jOUazpz0YqspXaot o1vYvzu4/0RXvgATzshU0UETf2CZIIkkM2YOMMXZb/Y6z6pqxT5LKQYFNsfd3StDvWPI jIUEIwgzsmqfLOoEgnnRUMLE54hbtE/zjEspIUang04Lj4OZ+F+IwDpkUW6Xjxnzd/5k j8l4oMQcFZTAtrFtuzIXALV+kn6wQE+4Fi+ThhcG3XuAubClZdzey8Y7wEAnJJxKJdZx q9SA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=foDA/GXxUeG6qywVw7pPHlQfm+Orh3kvLzj/my6QoE8=; b=Hdytpc0k4Hptwz01LFRc6XrKk6mgd6FaNpEyDTK7+zTaExNxzUxyqhDdBhZRMeZZMh 8mFWPkw21XzkTOUB/SVGirBlSpnfCGLSCdwkmFDJ760jACtgchmq7akJw4l0LnzOXEh9 NhEdel6TdLIHJvDZk3Qc06ezCW4N2MT4+IkK8g9HoPuMWQZwwz0ZFOaKUj3rDmDXd0ol pI7dtB2HR/lG+gCPMozjcs4lgUtz7s2lQZvjwyrdx+Mjpa4NmKMHVRplK4PpJRmMBS9F 7eLox81yWt5R45xXVEdxZX3j7H0kPeDPPfWhr4VRl6SmaXML7T8nkFZ0KBtYe2MXiAYs JcWg== X-Gm-Message-State: AO0yUKW/q7yGiO0zuSW8ZWGKzI/ZgDbvmp3S8qbQRGiUEsv48/WwKMSv xxj8S1kVuj2q8nY1SzATUuM= X-Google-Smtp-Source: AK7set9VipcuXxYpnZ45Df1zEkwY+VzCevZIE9fa4nfCbZ7L/fI0ChM6/Zx2yWmI9RnPiMQlYfZ5Nw== X-Received: by 2002:a5d:67cc:0:b0:2c5:6016:496 with SMTP id n12-20020a5d67cc000000b002c560160496mr8555585wrw.27.1677091199479; Wed, 22 Feb 2023 10:39:59 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.39.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:39:59 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 01/16] pinctrl: ralink: reintroduce ralink,rt2880-pinmux compatible string Date: Wed, 22 Feb 2023 21:39:17 +0300 Message-Id: <20230222183932.33267-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104001_897682_40886A86 X-CRM114-Status: GOOD ( 12.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL There have been stable releases with the ralink,rt2880-pinmux compatible string included. Having it removed breaks the ABI. Reintroduce it. Fixes: e5981cd46183 ("pinctrl: ralink: add new compatible strings for each pinctrl subdriver") Signed-off-by: Arınç ÜNAL --- drivers/pinctrl/ralink/pinctrl-mt7620.c | 1 + drivers/pinctrl/ralink/pinctrl-mt7621.c | 1 + drivers/pinctrl/ralink/pinctrl-rt2880.c | 1 + drivers/pinctrl/ralink/pinctrl-rt305x.c | 1 + drivers/pinctrl/ralink/pinctrl-rt3883.c | 1 + 5 files changed, 5 insertions(+) diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c index 4e8d26bb3430..06b86c726839 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -372,6 +372,7 @@ static int mt7620_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id mt7620_pinctrl_match[] = { { .compatible = "ralink,mt7620-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, mt7620_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/ralink/pinctrl-mt7621.c index eddc0ba6d468..fb5824922e78 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -97,6 +97,7 @@ static int mt7621_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id mt7621_pinctrl_match[] = { { .compatible = "ralink,mt7621-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, mt7621_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/ralink/pinctrl-rt2880.c index 3e2f1aaaf095..d7a65fcc7755 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c @@ -41,6 +41,7 @@ static int rt2880_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id rt2880_pinctrl_match[] = { { .compatible = "ralink,rt2880-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt2880_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/ralink/pinctrl-rt305x.c index bdaee5ce1ee0..f6092c64383e 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -118,6 +118,7 @@ static int rt305x_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id rt305x_pinctrl_match[] = { { .compatible = "ralink,rt305x-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt305x_pinctrl_match); diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/ralink/pinctrl-rt3883.c index 392208662355..5f766d76bafa 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/ralink/pinctrl-rt3883.c @@ -88,6 +88,7 @@ static int rt3883_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id rt3883_pinctrl_match[] = { { .compatible = "ralink,rt3883-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, {} }; MODULE_DEVICE_TABLE(of, rt3883_pinctrl_match); From patchwork Wed Feb 22 18:39:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149471 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB451C678DB for ; Wed, 22 Feb 2023 18:41:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uTSwAUKnGLQ/KdWSnzzT00O/zrx6LQ+bxpFmoWKJJzw=; b=Isv2FxQ/zUEKzr 4AEZk2Ld66vDA9y0/N6BcoNt0mh+oFbn847sZ4L2WVOBXI4UQtYGICKIZsw+cn6tPubcAC79a/+F4 7nVTu9u8DY5+cbTRAk1fn89ON4FFHtj5TfKb7+A2eb1b3OhA//YPh5grfrxI6FtlhWrhSLmqYxySq PLRYVCGc63eLmtFqnxZNVBqQ5JPItQMbw6fPK3R81sKh5BMJ3eN3ZFHuzh6fQDG6XvguQQFiD6eHO d0iF1xhj/0wyTcFVHK6XPenVsOodXFBGl0MdCsHxh6pd9oHBcma5K+3stAg2GfMIr6VRDYP+TqU2y zyPAB4NjnSdRvN6l7XwQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2p-00DU4y-IT; Wed, 22 Feb 2023 18:40:48 +0000 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2D-00DTj2-Vq; Wed, 22 Feb 2023 18:40:13 +0000 Received: by mail-wr1-x432.google.com with SMTP id i11so2585633wrp.5; Wed, 22 Feb 2023 10:40:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fxit4cASxxHL2nm1xYvDVxIdY14POx45+l2xWlfbrB8=; b=llZRZ6E9KMqHcgEWIp1r+RA3hxjZpkIGflmlHx7+dk6rqpu9dvNStfDRr6gBs6YsnF ToFasIk+nTjzAmCpFOoD0r9fXxdCGnVxALwwc7iSLqjvdQG6aQP2/p2B+26ZMtOrcQUk P2G7j1XBx6TfFi6EvCdd0OyHQpMWk+mN/x3Mvx5/hgj6GuhXHZTwqZiiE8qnrAghcSEy ieVI7lcTzJxo8xc+sXiLQ2roVdoprar+8UuTjCxfnbkkNhp5mKH7KYfl0JXF2m4FlsGF y+9J/RrfsI7wtn4TDkq/OhtqP/pSNjxnueSZthEUOwnPVEWgqhn1du3skR2hjRtzHoRX GgLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fxit4cASxxHL2nm1xYvDVxIdY14POx45+l2xWlfbrB8=; b=4iLU/irVFqWpF0janpddLyAQ1KCPPlzFLSwfkreipDnnEsuu/pYiye9KhPQAGStini cBSOLOdDmGNPAyBXjgCXUBLomrwdO6mymiGbXOcSbf29Ce3dqiOPUQJXa6UZY7iz4F7/ M+Zw3CBTlZfYJprk3YjO67bmQf1mILcm/RM1hDgsmOKs8DNCBT58YBF7Nzua2EgJmKRo hmd3fhvRS2USImU+vvdZikMvaqUXhkf0pqDjPiCXIUE4RIPERFkm+laIXaZTOvHEufZJ 7rsa0anVXBUUrERd972J+TDwgywK05beX1jRFE9ymJfCdj/WJZKwAfPlv8vJ8Q5cupMm gd4g== X-Gm-Message-State: AO0yUKWEBK26suOjg3GcKm1zQbulyc85bTdW+TqAqS4L2OabVeXY1Aid bCAB4wdMooRG5fpNiX3LyiY= X-Google-Smtp-Source: AK7set9Up+ufj2qC9Aht1MB/gSjPPDEHD7mb82o3uQ/byVmKxtfMDrBUFf6MoAEKSkWeh/wg56t8hQ== X-Received: by 2002:a05:6000:1cd:b0:2c5:8575:c37 with SMTP id t13-20020a05600001cd00b002c585750c37mr8183636wrx.66.1677091208546; Wed, 22 Feb 2023 10:40:08 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.39.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:08 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 02/16] pinctrl: ralink: add mediatek compatible strings Date: Wed, 22 Feb 2023 21:39:18 +0300 Message-Id: <20230222183932.33267-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104010_098953_A2269E04 X-CRM114-Status: GOOD ( 12.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Ralink was acquired by MediaTek in 2011. These SoCs have been rebranded as MediaTek. Add new compatible strings to reflect that. Signed-off-by: Arınç ÜNAL --- drivers/pinctrl/ralink/pinctrl-mt7620.c | 1 + drivers/pinctrl/ralink/pinctrl-mt7621.c | 1 + drivers/pinctrl/ralink/pinctrl-rt2880.c | 1 + drivers/pinctrl/ralink/pinctrl-rt305x.c | 1 + drivers/pinctrl/ralink/pinctrl-rt3883.c | 1 + 5 files changed, 5 insertions(+) diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c index 06b86c726839..88b0c6a4ee18 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -371,6 +371,7 @@ static int mt7620_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id mt7620_pinctrl_match[] = { + { .compatible = "mediatek,mt7620-pinctrl" }, { .compatible = "ralink,mt7620-pinctrl" }, { .compatible = "ralink,rt2880-pinmux" }, {} diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/ralink/pinctrl-mt7621.c index fb5824922e78..2128a94f6d1b 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -96,6 +96,7 @@ static int mt7621_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id mt7621_pinctrl_match[] = { + { .compatible = "mediatek,mt7621-pinctrl" }, { .compatible = "ralink,mt7621-pinctrl" }, { .compatible = "ralink,rt2880-pinmux" }, {} diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/ralink/pinctrl-rt2880.c index d7a65fcc7755..e57b1c5d03dd 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c @@ -40,6 +40,7 @@ static int rt2880_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id rt2880_pinctrl_match[] = { + { .compatible = "mediatek,rt2880-pinctrl" }, { .compatible = "ralink,rt2880-pinctrl" }, { .compatible = "ralink,rt2880-pinmux" }, {} diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/ralink/pinctrl-rt305x.c index f6092c64383e..ca62997e716c 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -117,6 +117,7 @@ static int rt305x_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id rt305x_pinctrl_match[] = { + { .compatible = "mediatek,rt305x-pinctrl" }, { .compatible = "ralink,rt305x-pinctrl" }, { .compatible = "ralink,rt2880-pinmux" }, {} diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/ralink/pinctrl-rt3883.c index 5f766d76bafa..b687c70d3555 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/ralink/pinctrl-rt3883.c @@ -87,6 +87,7 @@ static int rt3883_pinctrl_probe(struct platform_device *pdev) } static const struct of_device_id rt3883_pinctrl_match[] = { + { .compatible = "mediatek,rt3883-pinctrl" }, { .compatible = "ralink,rt3883-pinctrl" }, { .compatible = "ralink,rt2880-pinmux" }, {} From patchwork Wed Feb 22 18:39:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149472 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06C73C636D6 for ; Wed, 22 Feb 2023 18:42:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DjXjezdrY6/neobtjQozi6todP+VJ3GFN2dQtIcN4g4=; b=IPcNJW5/c2YQ6A MYS+roGXkm9FfUXI0zk7oR2vx4Zzq43Lugyhc+YqJF6aqL9HDOynvTuZIMwDQoENuFMiZK/bsiLa3 Z8pph7xKTIN5lixxfEzlp5Nwx2/+0hhZF1J85QUhLR+0rCyfJWdFsaT5X37LMUxyNaXrxXubDsTRX 5bZ10KZfHwl3qkuc7k3xx0f4wRqvs1LeRhhGIQjlviZiDg1qW8j+jhPcEpoyesYxt83C7JGKswtPB MyVBAigKc2w+Fn4wqnX8TYhKAGxgYdazU94B7R9PVbr7rGisrp9aphXbLt2LfM91s+ZZnflSvO42f 6kMTl6utK5JSYnOCzvnw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu3G-00DUL4-5Y; Wed, 22 Feb 2023 18:41:16 +0000 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2I-00DTk5-ME; Wed, 22 Feb 2023 18:40:16 +0000 Received: by mail-wr1-x429.google.com with SMTP id l1so8476506wry.10; Wed, 22 Feb 2023 10:40:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bkrh5PmCKY97yVWMrE2rxg0O6ScEmnhgtHgZ694XhHo=; b=pl//qR2xGMfXRxwoPgmQOuAtveiqYg+PzSqwy/kO2G9BIgMD8EbSE1BIA+jaSQGadd tHou+DQnlJnpXsUgKZsJ/suRzx4U2wmWUVNopvLbYafjMidYDP8T4Mqw6bjiL8vbh2ua nsHtXy38P6lQJtcYJRq01Zcn6iWcNEexz1QF7dq68XKbvCy+tXN3tSZ3vS7tlfOOtQdw o8Aq5tCQxPLAT5q85jBocgKiIEPd6ZoRlSjIwRY3OzA/nrHY7djDYOUrsPCn9h6rK6FC kDnT/mNC7yOJRNOuc8Ym2L+V5JVAqN2vTc8+uVydneNgyhjM2/9PhP9z15qo195q5/ry TXjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bkrh5PmCKY97yVWMrE2rxg0O6ScEmnhgtHgZ694XhHo=; b=45Oow/RwU9xl8Y9X/DeD8IxeJsgaULBxvdZYrG2dxWLIJ/HvlJWyZ+8wmH5vC2/i2m TZHPJsj/grJZU4PpgkhEm7Q9gIig67kMlb59zxvyzkVN9/sahn71m4JfEMRATRmu68ac uRTRo6+UfXa8jVDhuH2pGZBZzIj3EjpUzBkcR8RJxr2/siYbCyu983Kz+P4wBGK2oicZ ILuQoTFjDemS6UryXm6h9A7b29ce+yifvwGhT4L1VQeHKByDeFlIIHcL6IIt6LZz3Okw VfvhQdm9JBscMvCu+Cm9LO90IAXT1TGWn9639DSqKww/Z4gp/8jic0N7nxOmdMdWA7mV kBYA== X-Gm-Message-State: AO0yUKU85iw8j1+4Zm1m9DJWU1sb+jGMnnHBFKZT9VbGMx96YAIPKCnp uRw0IqW1LBWpnVj7/pTgXvo= X-Google-Smtp-Source: AK7set/++D2xBRox8aFcmSpjULrFCbdHcRtHW2lgb8/1HHdLRWC8O09ROG+CaPS9xdSF25M9R4+yvA== X-Received: by 2002:a05:6000:1284:b0:2c3:f026:9085 with SMTP id f4-20020a056000128400b002c3f0269085mr8394442wrx.13.1677091210888; Wed, 22 Feb 2023 10:40:10 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:10 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 03/16] pinctrl: ralink: rt305x: add compatible string for every SoC Date: Wed, 22 Feb 2023 21:39:19 +0300 Message-Id: <20230222183932.33267-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104014_769275_8C9C4DF7 X-CRM114-Status: GOOD ( 12.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Add a compatible string for every SoC, or SoCs that use the same pinmux data. This ensures that the pin muxing information of every SoC, or a set of SoCs that use the same pinmux data can be properly documented. Signed-off-by: Arınç ÜNAL --- drivers/pinctrl/ralink/pinctrl-rt305x.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/ralink/pinctrl-rt305x.c index ca62997e716c..a112a83085ea 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -118,6 +118,8 @@ static int rt305x_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id rt305x_pinctrl_match[] = { { .compatible = "mediatek,rt305x-pinctrl" }, + { .compatible = "mediatek,rt3352-pinctrl" }, + { .compatible = "mediatek,rt5350-pinctrl" }, { .compatible = "ralink,rt305x-pinctrl" }, { .compatible = "ralink,rt2880-pinmux" }, {} From patchwork Wed Feb 22 18:39:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4E1DC64EC7 for ; Wed, 22 Feb 2023 18:43:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=x+MAx18O51yn9zVCYrkkN/IOXuxXlJ0jPwE5QEbt/xA=; b=J0Ra3KpvqqV+Vn wFjhysKls/vM3CUrL7Tjm9pQQWHMK1HsgyHpU+LWgm/vbl+3qma5YogbbourDwawz4+kxNebmFGIc wG6xlJGNKLhx0UmiAAKHWTg/KeQ3VVnRrSkwutrQuB9kMrRCooOAQ+ta0xqgFfrrkPW6FzUT/IO1G vhGOQ7538H7BmqJkdkumoPmav2YkNPRk7NPS52TSr4P9ABNlotikqPkCBfNC3/4dN2CwhfHnk3BaB d0qNUIXRKrFKzQVmteceuzknN9MW0T5mZ9FhR6JN78a2iYO3TJEPD4PhTqhltoxKaQIXtbTKgHZME nmktcscAafpW/hMY0S+g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu3u-00DUiH-5V; Wed, 22 Feb 2023 18:41:54 +0000 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2I-00DTel-9O; Wed, 22 Feb 2023 18:40:17 +0000 Received: by mail-wr1-x432.google.com with SMTP id bt28so2089687wrb.8; Wed, 22 Feb 2023 10:40:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gDJeWiKsHoEvat6KQzjaepU8kGEjsYs/weaALQ++4bc=; b=fm41A8LCYTfuLR7EOjHQfUe6AVmR/8xV5zqhF+JPsPu4MTTrOCrBb8w7T4zwdtzaaz i1TgOCuLEUoolIt9CXxD0H2oT7Rpbx76SvXkkYo74zcWHRoksECPguG195nLkqt2WVdX AuhcNYDMZ3rpTJNg7JzOfmMWoJCjURd9g7D/jlSa+uz2uufR1HAbxxLYSZgz8bqXQOjM mNrU22F6RC9CypjZW1NIcc7BtUv9ZaIiw1Ifyid4YiFdZXHFiwdQ43p0ozNja5ouApI8 wVdFzNoceGwZWU8Jq2uJjeGz4SXg4/ZVCEayjQmiA09asGw6FvOnn7rpWqILrd6ba83W ZsJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gDJeWiKsHoEvat6KQzjaepU8kGEjsYs/weaALQ++4bc=; b=m5G1cy3vvbBZquhtbCRIqsqESSc9QEG+v2YVfuFsqpfNyFOiE1I3I49lEmjtqLaW5i HFzyU+JDi1CH4c11QF7GLD+BRVIiAd4gLq1MdK7yjfx7G23A39IbBpyKzNAZpOW97S8D +IGzLr4X/3QBzJT2hZWwAfLtbAxDUVj+6NekQMTsl4nyI63oCSnsOhu4W7ffqsRQJdcn oDqrFudNXlpdtKQ68CN9vAP/WYri4elR8J+fkv51Oxhwr3Ha7sFMkTe8bq6rJBX+Cwex 6hXE4YfNlXXaP1mfokfiOzYblb5ex7dVIwrVxd7E7+PPj5DMyJpeTC/YFAWvBUmQ6H1V yvQw== X-Gm-Message-State: AO0yUKUMoJCVllabVLBbOru9IYor4yYPpWWP4m/ea+LzH81woyLQS3dp DyStv0DEzQyRBEI3nuGCmSJADOxvY1XDAWTn X-Google-Smtp-Source: AK7set+kWteGUe+mRh0DvI5tIZSuoatRYLKah8QWqbG4Yk5iUHcrwj7IJ7lO4lAJSqpfSlZpT8L0Ng== X-Received: by 2002:a5d:66ce:0:b0:2c7:453:d3b9 with SMTP id k14-20020a5d66ce000000b002c70453d3b9mr6259972wrw.37.1677091213593; Wed, 22 Feb 2023 10:40:13 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:13 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 04/16] pinctrl: ralink: mt7620: split out to mt76x8 Date: Wed, 22 Feb 2023 21:39:20 +0300 Message-Id: <20230222183932.33267-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104014_475399_D38C5C49 X-CRM114-Status: GOOD ( 17.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Split the driver out to pinctrl-mt76x8.c. Remove including the unnecessary headers since is_mt76x8() is not being used anymore. Introduce a new compatible string to be able to document the pin muxing information properly. Signed-off-by: Arınç ÜNAL --- drivers/pinctrl/ralink/Kconfig | 5 + drivers/pinctrl/ralink/Makefile | 1 + drivers/pinctrl/ralink/pinctrl-mt7620.c | 257 +-------------------- drivers/pinctrl/ralink/pinctrl-mt76x8.c | 283 ++++++++++++++++++++++++ 4 files changed, 290 insertions(+), 256 deletions(-) create mode 100644 drivers/pinctrl/ralink/pinctrl-mt76x8.c diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index 1e4c5e43d69b..c5fe4c31aaea 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -17,6 +17,11 @@ config PINCTRL_MT7621 depends on RALINK && SOC_MT7621 select PINCTRL_RALINK +config PINCTRL_MT76X8 + bool "MT76X8 pinctrl subdriver" + depends on RALINK && SOC_MT7620 + select PINCTRL_RALINK + config PINCTRL_RT2880 bool "RT2880 pinctrl subdriver" depends on RALINK && SOC_RT288X diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makefile index 0ebbe552526d..be9acf2e27fd 100644 --- a/drivers/pinctrl/ralink/Makefile +++ b/drivers/pinctrl/ralink/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_RALINK) += pinctrl-ralink.o obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o +obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c index 88b0c6a4ee18..b2245fd65c72 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -#include -#include #include #include #include @@ -112,262 +110,9 @@ static struct ralink_pmx_group mt7620a_pinmux_data[] = { { 0 } }; -static struct ralink_pmx_func pwm1_grp_mt76x8[] = { - FUNC("sdxc d6", 3, 19, 1), - FUNC("utif", 2, 19, 1), - FUNC("gpio", 1, 19, 1), - FUNC("pwm1", 0, 19, 1), -}; - -static struct ralink_pmx_func pwm0_grp_mt76x8[] = { - FUNC("sdxc d7", 3, 18, 1), - FUNC("utif", 2, 18, 1), - FUNC("gpio", 1, 18, 1), - FUNC("pwm0", 0, 18, 1), -}; - -static struct ralink_pmx_func uart2_grp_mt76x8[] = { - FUNC("sdxc d5 d4", 3, 20, 2), - FUNC("pwm", 2, 20, 2), - FUNC("gpio", 1, 20, 2), - FUNC("uart2", 0, 20, 2), -}; - -static struct ralink_pmx_func uart1_grp_mt76x8[] = { - FUNC("sw_r", 3, 45, 2), - FUNC("pwm", 2, 45, 2), - FUNC("gpio", 1, 45, 2), - FUNC("uart1", 0, 45, 2), -}; - -static struct ralink_pmx_func i2c_grp_mt76x8[] = { - FUNC("-", 3, 4, 2), - FUNC("debug", 2, 4, 2), - FUNC("gpio", 1, 4, 2), - FUNC("i2c", 0, 4, 2), -}; - -static struct ralink_pmx_func refclk_grp_mt76x8[] = { FUNC("refclk", 0, 37, 1) }; -static struct ralink_pmx_func perst_grp_mt76x8[] = { FUNC("perst", 0, 36, 1) }; -static struct ralink_pmx_func wdt_grp_mt76x8[] = { FUNC("wdt", 0, 38, 1) }; -static struct ralink_pmx_func spi_grp_mt76x8[] = { FUNC("spi", 0, 7, 4) }; - -static struct ralink_pmx_func sd_mode_grp_mt76x8[] = { - FUNC("jtag", 3, 22, 8), - FUNC("utif", 2, 22, 8), - FUNC("gpio", 1, 22, 8), - FUNC("sdxc", 0, 22, 8), -}; - -static struct ralink_pmx_func uart0_grp_mt76x8[] = { - FUNC("-", 3, 12, 2), - FUNC("-", 2, 12, 2), - FUNC("gpio", 1, 12, 2), - FUNC("uart0", 0, 12, 2), -}; - -static struct ralink_pmx_func i2s_grp_mt76x8[] = { - FUNC("antenna", 3, 0, 4), - FUNC("pcm", 2, 0, 4), - FUNC("gpio", 1, 0, 4), - FUNC("i2s", 0, 0, 4), -}; - -static struct ralink_pmx_func spi_cs1_grp_mt76x8[] = { - FUNC("-", 3, 6, 1), - FUNC("refclk", 2, 6, 1), - FUNC("gpio", 1, 6, 1), - FUNC("spi cs1", 0, 6, 1), -}; - -static struct ralink_pmx_func spis_grp_mt76x8[] = { - FUNC("pwm_uart2", 3, 14, 4), - FUNC("utif", 2, 14, 4), - FUNC("gpio", 1, 14, 4), - FUNC("spis", 0, 14, 4), -}; - -static struct ralink_pmx_func gpio_grp_mt76x8[] = { - FUNC("pcie", 3, 11, 1), - FUNC("refclk", 2, 11, 1), - FUNC("gpio", 1, 11, 1), - FUNC("gpio", 0, 11, 1), -}; - -static struct ralink_pmx_func p4led_kn_grp_mt76x8[] = { - FUNC("jtag", 3, 30, 1), - FUNC("utif", 2, 30, 1), - FUNC("gpio", 1, 30, 1), - FUNC("p4led_kn", 0, 30, 1), -}; - -static struct ralink_pmx_func p3led_kn_grp_mt76x8[] = { - FUNC("jtag", 3, 31, 1), - FUNC("utif", 2, 31, 1), - FUNC("gpio", 1, 31, 1), - FUNC("p3led_kn", 0, 31, 1), -}; - -static struct ralink_pmx_func p2led_kn_grp_mt76x8[] = { - FUNC("jtag", 3, 32, 1), - FUNC("utif", 2, 32, 1), - FUNC("gpio", 1, 32, 1), - FUNC("p2led_kn", 0, 32, 1), -}; - -static struct ralink_pmx_func p1led_kn_grp_mt76x8[] = { - FUNC("jtag", 3, 33, 1), - FUNC("utif", 2, 33, 1), - FUNC("gpio", 1, 33, 1), - FUNC("p1led_kn", 0, 33, 1), -}; - -static struct ralink_pmx_func p0led_kn_grp_mt76x8[] = { - FUNC("jtag", 3, 34, 1), - FUNC("rsvd", 2, 34, 1), - FUNC("gpio", 1, 34, 1), - FUNC("p0led_kn", 0, 34, 1), -}; - -static struct ralink_pmx_func wled_kn_grp_mt76x8[] = { - FUNC("rsvd", 3, 35, 1), - FUNC("rsvd", 2, 35, 1), - FUNC("gpio", 1, 35, 1), - FUNC("wled_kn", 0, 35, 1), -}; - -static struct ralink_pmx_func p4led_an_grp_mt76x8[] = { - FUNC("jtag", 3, 39, 1), - FUNC("utif", 2, 39, 1), - FUNC("gpio", 1, 39, 1), - FUNC("p4led_an", 0, 39, 1), -}; - -static struct ralink_pmx_func p3led_an_grp_mt76x8[] = { - FUNC("jtag", 3, 40, 1), - FUNC("utif", 2, 40, 1), - FUNC("gpio", 1, 40, 1), - FUNC("p3led_an", 0, 40, 1), -}; - -static struct ralink_pmx_func p2led_an_grp_mt76x8[] = { - FUNC("jtag", 3, 41, 1), - FUNC("utif", 2, 41, 1), - FUNC("gpio", 1, 41, 1), - FUNC("p2led_an", 0, 41, 1), -}; - -static struct ralink_pmx_func p1led_an_grp_mt76x8[] = { - FUNC("jtag", 3, 42, 1), - FUNC("utif", 2, 42, 1), - FUNC("gpio", 1, 42, 1), - FUNC("p1led_an", 0, 42, 1), -}; - -static struct ralink_pmx_func p0led_an_grp_mt76x8[] = { - FUNC("jtag", 3, 43, 1), - FUNC("rsvd", 2, 43, 1), - FUNC("gpio", 1, 43, 1), - FUNC("p0led_an", 0, 43, 1), -}; - -static struct ralink_pmx_func wled_an_grp_mt76x8[] = { - FUNC("rsvd", 3, 44, 1), - FUNC("rsvd", 2, 44, 1), - FUNC("gpio", 1, 44, 1), - FUNC("wled_an", 0, 44, 1), -}; - -#define MT76X8_GPIO_MODE_MASK 0x3 - -#define MT76X8_GPIO_MODE_P4LED_KN 58 -#define MT76X8_GPIO_MODE_P3LED_KN 56 -#define MT76X8_GPIO_MODE_P2LED_KN 54 -#define MT76X8_GPIO_MODE_P1LED_KN 52 -#define MT76X8_GPIO_MODE_P0LED_KN 50 -#define MT76X8_GPIO_MODE_WLED_KN 48 -#define MT76X8_GPIO_MODE_P4LED_AN 42 -#define MT76X8_GPIO_MODE_P3LED_AN 40 -#define MT76X8_GPIO_MODE_P2LED_AN 38 -#define MT76X8_GPIO_MODE_P1LED_AN 36 -#define MT76X8_GPIO_MODE_P0LED_AN 34 -#define MT76X8_GPIO_MODE_WLED_AN 32 -#define MT76X8_GPIO_MODE_PWM1 30 -#define MT76X8_GPIO_MODE_PWM0 28 -#define MT76X8_GPIO_MODE_UART2 26 -#define MT76X8_GPIO_MODE_UART1 24 -#define MT76X8_GPIO_MODE_I2C 20 -#define MT76X8_GPIO_MODE_REFCLK 18 -#define MT76X8_GPIO_MODE_PERST 16 -#define MT76X8_GPIO_MODE_WDT 14 -#define MT76X8_GPIO_MODE_SPI 12 -#define MT76X8_GPIO_MODE_SDMODE 10 -#define MT76X8_GPIO_MODE_UART0 8 -#define MT76X8_GPIO_MODE_I2S 6 -#define MT76X8_GPIO_MODE_CS1 4 -#define MT76X8_GPIO_MODE_SPIS 2 -#define MT76X8_GPIO_MODE_GPIO 0 - -static struct ralink_pmx_group mt76x8_pinmux_data[] = { - GRP_G("pwm1", pwm1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_PWM1), - GRP_G("pwm0", pwm0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_PWM0), - GRP_G("uart2", uart2_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART2), - GRP_G("uart1", uart1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART1), - GRP_G("i2c", i2c_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_I2C), - GRP("refclk", refclk_grp_mt76x8, 1, MT76X8_GPIO_MODE_REFCLK), - GRP("perst", perst_grp_mt76x8, 1, MT76X8_GPIO_MODE_PERST), - GRP("wdt", wdt_grp_mt76x8, 1, MT76X8_GPIO_MODE_WDT), - GRP("spi", spi_grp_mt76x8, 1, MT76X8_GPIO_MODE_SPI), - GRP_G("sdmode", sd_mode_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_SDMODE), - GRP_G("uart0", uart0_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_UART0), - GRP_G("i2s", i2s_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_I2S), - GRP_G("spi cs1", spi_cs1_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_CS1), - GRP_G("spis", spis_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_SPIS), - GRP_G("gpio", gpio_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_GPIO), - GRP_G("wled_an", wled_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_WLED_AN), - GRP_G("p0led_an", p0led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P0LED_AN), - GRP_G("p1led_an", p1led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P1LED_AN), - GRP_G("p2led_an", p2led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P2LED_AN), - GRP_G("p3led_an", p3led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P3LED_AN), - GRP_G("p4led_an", p4led_an_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P4LED_AN), - GRP_G("wled_kn", wled_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_WLED_KN), - GRP_G("p0led_kn", p0led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P0LED_KN), - GRP_G("p1led_kn", p1led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P1LED_KN), - GRP_G("p2led_kn", p2led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P2LED_KN), - GRP_G("p3led_kn", p3led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P3LED_KN), - GRP_G("p4led_kn", p4led_kn_grp_mt76x8, MT76X8_GPIO_MODE_MASK, - 1, MT76X8_GPIO_MODE_P4LED_KN), - { 0 } -}; - static int mt7620_pinctrl_probe(struct platform_device *pdev) { - if (is_mt76x8()) - return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); - else - return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); + return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); } static const struct of_device_id mt7620_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-mt76x8.c b/drivers/pinctrl/ralink/pinctrl-mt76x8.c new file mode 100644 index 000000000000..5a6a82a58180 --- /dev/null +++ b/drivers/pinctrl/ralink/pinctrl-mt76x8.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include "pinctrl-ralink.h" + +#define MT76X8_GPIO_MODE_MASK 0x3 + +#define MT76X8_GPIO_MODE_P4LED_KN 58 +#define MT76X8_GPIO_MODE_P3LED_KN 56 +#define MT76X8_GPIO_MODE_P2LED_KN 54 +#define MT76X8_GPIO_MODE_P1LED_KN 52 +#define MT76X8_GPIO_MODE_P0LED_KN 50 +#define MT76X8_GPIO_MODE_WLED_KN 48 +#define MT76X8_GPIO_MODE_P4LED_AN 42 +#define MT76X8_GPIO_MODE_P3LED_AN 40 +#define MT76X8_GPIO_MODE_P2LED_AN 38 +#define MT76X8_GPIO_MODE_P1LED_AN 36 +#define MT76X8_GPIO_MODE_P0LED_AN 34 +#define MT76X8_GPIO_MODE_WLED_AN 32 +#define MT76X8_GPIO_MODE_PWM1 30 +#define MT76X8_GPIO_MODE_PWM0 28 +#define MT76X8_GPIO_MODE_UART2 26 +#define MT76X8_GPIO_MODE_UART1 24 +#define MT76X8_GPIO_MODE_I2C 20 +#define MT76X8_GPIO_MODE_REFCLK 18 +#define MT76X8_GPIO_MODE_PERST 16 +#define MT76X8_GPIO_MODE_WDT 14 +#define MT76X8_GPIO_MODE_SPI 12 +#define MT76X8_GPIO_MODE_SDMODE 10 +#define MT76X8_GPIO_MODE_UART0 8 +#define MT76X8_GPIO_MODE_I2S 6 +#define MT76X8_GPIO_MODE_CS1 4 +#define MT76X8_GPIO_MODE_SPIS 2 +#define MT76X8_GPIO_MODE_GPIO 0 + +static struct ralink_pmx_func pwm1_grp[] = { + FUNC("sdxc d6", 3, 19, 1), + FUNC("utif", 2, 19, 1), + FUNC("gpio", 1, 19, 1), + FUNC("pwm1", 0, 19, 1), +}; + +static struct ralink_pmx_func pwm0_grp[] = { + FUNC("sdxc d7", 3, 18, 1), + FUNC("utif", 2, 18, 1), + FUNC("gpio", 1, 18, 1), + FUNC("pwm0", 0, 18, 1), +}; + +static struct ralink_pmx_func uart2_grp[] = { + FUNC("sdxc d5 d4", 3, 20, 2), + FUNC("pwm", 2, 20, 2), + FUNC("gpio", 1, 20, 2), + FUNC("uart2", 0, 20, 2), +}; + +static struct ralink_pmx_func uart1_grp[] = { + FUNC("sw_r", 3, 45, 2), + FUNC("pwm", 2, 45, 2), + FUNC("gpio", 1, 45, 2), + FUNC("uart1", 0, 45, 2), +}; + +static struct ralink_pmx_func i2c_grp[] = { + FUNC("-", 3, 4, 2), + FUNC("debug", 2, 4, 2), + FUNC("gpio", 1, 4, 2), + FUNC("i2c", 0, 4, 2), +}; + +static struct ralink_pmx_func refclk_grp[] = { FUNC("refclk", 0, 37, 1) }; +static struct ralink_pmx_func perst_grp[] = { FUNC("perst", 0, 36, 1) }; +static struct ralink_pmx_func wdt_grp[] = { FUNC("wdt", 0, 38, 1) }; +static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 7, 4) }; + +static struct ralink_pmx_func sd_mode_grp[] = { + FUNC("jtag", 3, 22, 8), + FUNC("utif", 2, 22, 8), + FUNC("gpio", 1, 22, 8), + FUNC("sdxc", 0, 22, 8), +}; + +static struct ralink_pmx_func uart0_grp[] = { + FUNC("-", 3, 12, 2), + FUNC("-", 2, 12, 2), + FUNC("gpio", 1, 12, 2), + FUNC("uart0", 0, 12, 2), +}; + +static struct ralink_pmx_func i2s_grp[] = { + FUNC("antenna", 3, 0, 4), + FUNC("pcm", 2, 0, 4), + FUNC("gpio", 1, 0, 4), + FUNC("i2s", 0, 0, 4), +}; + +static struct ralink_pmx_func spi_cs1_grp[] = { + FUNC("-", 3, 6, 1), + FUNC("refclk", 2, 6, 1), + FUNC("gpio", 1, 6, 1), + FUNC("spi cs1", 0, 6, 1), +}; + +static struct ralink_pmx_func spis_grp[] = { + FUNC("pwm_uart2", 3, 14, 4), + FUNC("utif", 2, 14, 4), + FUNC("gpio", 1, 14, 4), + FUNC("spis", 0, 14, 4), +}; + +static struct ralink_pmx_func gpio_grp[] = { + FUNC("pcie", 3, 11, 1), + FUNC("refclk", 2, 11, 1), + FUNC("gpio", 1, 11, 1), + FUNC("gpio", 0, 11, 1), +}; + +static struct ralink_pmx_func p4led_kn_grp[] = { + FUNC("jtag", 3, 30, 1), + FUNC("utif", 2, 30, 1), + FUNC("gpio", 1, 30, 1), + FUNC("p4led_kn", 0, 30, 1), +}; + +static struct ralink_pmx_func p3led_kn_grp[] = { + FUNC("jtag", 3, 31, 1), + FUNC("utif", 2, 31, 1), + FUNC("gpio", 1, 31, 1), + FUNC("p3led_kn", 0, 31, 1), +}; + +static struct ralink_pmx_func p2led_kn_grp[] = { + FUNC("jtag", 3, 32, 1), + FUNC("utif", 2, 32, 1), + FUNC("gpio", 1, 32, 1), + FUNC("p2led_kn", 0, 32, 1), +}; + +static struct ralink_pmx_func p1led_kn_grp[] = { + FUNC("jtag", 3, 33, 1), + FUNC("utif", 2, 33, 1), + FUNC("gpio", 1, 33, 1), + FUNC("p1led_kn", 0, 33, 1), +}; + +static struct ralink_pmx_func p0led_kn_grp[] = { + FUNC("jtag", 3, 34, 1), + FUNC("rsvd", 2, 34, 1), + FUNC("gpio", 1, 34, 1), + FUNC("p0led_kn", 0, 34, 1), +}; + +static struct ralink_pmx_func wled_kn_grp[] = { + FUNC("rsvd", 3, 35, 1), + FUNC("rsvd", 2, 35, 1), + FUNC("gpio", 1, 35, 1), + FUNC("wled_kn", 0, 35, 1), +}; + +static struct ralink_pmx_func p4led_an_grp[] = { + FUNC("jtag", 3, 39, 1), + FUNC("utif", 2, 39, 1), + FUNC("gpio", 1, 39, 1), + FUNC("p4led_an", 0, 39, 1), +}; + +static struct ralink_pmx_func p3led_an_grp[] = { + FUNC("jtag", 3, 40, 1), + FUNC("utif", 2, 40, 1), + FUNC("gpio", 1, 40, 1), + FUNC("p3led_an", 0, 40, 1), +}; + +static struct ralink_pmx_func p2led_an_grp[] = { + FUNC("jtag", 3, 41, 1), + FUNC("utif", 2, 41, 1), + FUNC("gpio", 1, 41, 1), + FUNC("p2led_an", 0, 41, 1), +}; + +static struct ralink_pmx_func p1led_an_grp[] = { + FUNC("jtag", 3, 42, 1), + FUNC("utif", 2, 42, 1), + FUNC("gpio", 1, 42, 1), + FUNC("p1led_an", 0, 42, 1), +}; + +static struct ralink_pmx_func p0led_an_grp[] = { + FUNC("jtag", 3, 43, 1), + FUNC("rsvd", 2, 43, 1), + FUNC("gpio", 1, 43, 1), + FUNC("p0led_an", 0, 43, 1), +}; + +static struct ralink_pmx_func wled_an_grp[] = { + FUNC("rsvd", 3, 44, 1), + FUNC("rsvd", 2, 44, 1), + FUNC("gpio", 1, 44, 1), + FUNC("wled_an", 0, 44, 1), +}; + +static struct ralink_pmx_group mt76x8_pinmux_data[] = { + GRP_G("pwm1", pwm1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_PWM1), + GRP_G("pwm0", pwm0_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_PWM0), + GRP_G("uart2", uart2_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART2), + GRP_G("uart1", uart1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART1), + GRP_G("i2c", i2c_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_I2C), + GRP("refclk", refclk_grp, 1, MT76X8_GPIO_MODE_REFCLK), + GRP("perst", perst_grp, 1, MT76X8_GPIO_MODE_PERST), + GRP("wdt", wdt_grp, 1, MT76X8_GPIO_MODE_WDT), + GRP("spi", spi_grp, 1, MT76X8_GPIO_MODE_SPI), + GRP_G("sdmode", sd_mode_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_SDMODE), + GRP_G("uart0", uart0_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_UART0), + GRP_G("i2s", i2s_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_I2S), + GRP_G("spi cs1", spi_cs1_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_CS1), + GRP_G("spis", spis_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_SPIS), + GRP_G("gpio", gpio_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_GPIO), + GRP_G("wled_an", wled_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_WLED_AN), + GRP_G("p0led_an", p0led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P0LED_AN), + GRP_G("p1led_an", p1led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P1LED_AN), + GRP_G("p2led_an", p2led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P2LED_AN), + GRP_G("p3led_an", p3led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P3LED_AN), + GRP_G("p4led_an", p4led_an_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P4LED_AN), + GRP_G("wled_kn", wled_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_WLED_KN), + GRP_G("p0led_kn", p0led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P0LED_KN), + GRP_G("p1led_kn", p1led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P1LED_KN), + GRP_G("p2led_kn", p2led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P2LED_KN), + GRP_G("p3led_kn", p3led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P3LED_KN), + GRP_G("p4led_kn", p4led_kn_grp, MT76X8_GPIO_MODE_MASK, + 1, MT76X8_GPIO_MODE_P4LED_KN), + { 0 } +}; + +static int mt76x8_pinctrl_probe(struct platform_device *pdev) +{ + return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); +} + +static const struct of_device_id mt76x8_pinctrl_match[] = { + { .compatible = "mediatek,mt76x8-pinctrl" }, + { .compatible = "ralink,mt7620-pinctrl" }, + { .compatible = "ralink,rt2880-pinmux" }, + {} +}; +MODULE_DEVICE_TABLE(of, mt76x8_pinctrl_match); + +static struct platform_driver mt76x8_pinctrl_driver = { + .probe = mt76x8_pinctrl_probe, + .driver = { + .name = "mt76x8-pinctrl", + .of_match_table = mt76x8_pinctrl_match, + }, +}; + +static int __init mt76x8_pinctrl_init(void) +{ + return platform_driver_register(&mt76x8_pinctrl_driver); +} +core_initcall_sync(mt76x8_pinctrl_init); From patchwork Wed Feb 22 18:39:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A78AC636D6 for ; Wed, 22 Feb 2023 18:43:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=uZwJRPXZs77vuH/Gd69qYbSmVlrBg7wk5L/mQKW180g=; b=vGQP7ci7zI+j5I 3l98osuO/F7mz4n2FlRxYBPp8enY87w9QnLQUdfKAYw5a71UcKWmVmWQ2W8C2jAvcNmiK6SLJu0VH 25NRFSn9d+CS7zDXndSggdfhwwSpJW7wJAUjWHeCTQmiy6XOAxnYGYuKFrvlEgShuqLoASSMsV+Yi bMvvgcc5vSbDrP62jb/sCMJpYuzA16YaAI+2hkwBf3wBRDrX9zp/4S7xD0Y0wK1CiWXhw8m8IJ1gO SbN1aHULMytDttTu0vyuxdyPDSUFxlcBuQ69HMQUSnuKsA0fqh5MkjkAf7F5htfjKvft7HYto29d+ 4WKqOZCw4bO0MwVPof/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu4a-00DV4Y-8E; Wed, 22 Feb 2023 18:42:36 +0000 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2K-00DTj2-KP; Wed, 22 Feb 2023 18:40:21 +0000 Received: by mail-wr1-x432.google.com with SMTP id i11so2585873wrp.5; Wed, 22 Feb 2023 10:40:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jciLvdWgNLtDZYNXWCTKtcFwh8hKkwj5mNvYj7E7jy8=; b=gzLSdcWmk17q5fgmGe4SYE31y/iZZTWFOQ8pfeKBDzBtXt9K9y64cmn9zspuu7b7Vm UDj/O8P3PmlDD34JmJcJHls76v/RyQA2yGeJd+tYI9RfGfksUYpGtfrT61PpGaPdiChO yOuI+QQ/4SO/yPEHYUctZT9yUQpJXhu0z7htLV7vdyl19qD7treIcaFyR+fbGZEK0tdU aWXgFxRjuj4pD1Mtz1dYn2DrBQM078C3ZzqWnkxQ23JR2+BLgxS2inUSsl0dOO2Ic09w rT4CgtS0A3tfs6JqJ3NityR9vBEOoCBOY7Ew6TVfkX94itvtsJsykJhtkvzZaskIRuNF 5QVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jciLvdWgNLtDZYNXWCTKtcFwh8hKkwj5mNvYj7E7jy8=; b=GpdjsQ9pz6T3VryzGUGidaMsEe5mjf12aExonWUnBc+FvaQY+EpjyzpihfsaNjaZgy s9k8FlQEIkJOfgH/P3gs0/lJdwanwBLhrRUrf9vcprSWvTXGy9AZupiu+0CJqQhUpYX2 esVmlgnkKlgv86GYsEKMWUsHqaZCRZlTPNQJGhgNLDLRUnz6a8whi3BSGOqodZnTqDVH RXUPE+/HCJZOGS2FbMTKaFAJHr9Le6GzHnP5lNizNoZyrAK8RHIbObbYKqV7q1fMh/ZW t70Cs7HEq/N/ARBQ4erbxI4/9uxGaECGZIb5+vuqp5Ckyi4prqPBm3DJRsG7QqYIkK4W x/Xw== X-Gm-Message-State: AO0yUKXtz+GPPkMqDTT58wI+hkqmRtHezMkxM6YH4iA8lFDHV/OuhD97 G8R1NZURCXsdru5yufFxulI= X-Google-Smtp-Source: AK7set89sFjsOE6l12qDpJRNcCJSRTTPOb5W/pWB1HJIfrz+NCyi2UWFzdfCCD7d9kw7288BmnRdKA== X-Received: by 2002:adf:f887:0:b0:2c7:f82:827a with SMTP id u7-20020adff887000000b002c70f82827amr147423wrp.19.1677091215986; Wed, 22 Feb 2023 10:40:15 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:15 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 05/16] pinctrl: ralink: move to mediatek as mtmips Date: Wed, 22 Feb 2023 21:39:21 +0300 Message-Id: <20230222183932.33267-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104016_937642_B7FE78E4 X-CRM114-Status: GOOD ( 17.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Ralink was acquired by MediaTek in 2011. These SoCs have been rebranded as MediaTek. Move the driver to mediatek pinctrl directory. Rename the ralink core driver to mtmips. Signed-off-by: Arınç ÜNAL --- drivers/pinctrl/Kconfig | 1 - drivers/pinctrl/Makefile | 1 - drivers/pinctrl/mediatek/Kconfig | 51 ++++++++++- drivers/pinctrl/mediatek/Makefile | 63 +++++++------ .../{ralink => mediatek}/pinctrl-mt7620.c | 34 +++---- .../{ralink => mediatek}/pinctrl-mt7621.c | 30 +++---- .../{ralink => mediatek}/pinctrl-mt76x8.c | 60 ++++++------- .../pinctrl-mtmips.c} | 90 +++++++++---------- .../pinctrl-mtmips.h} | 16 ++-- .../{ralink => mediatek}/pinctrl-rt2880.c | 20 ++--- .../{ralink => mediatek}/pinctrl-rt305x.c | 44 ++++----- .../{ralink => mediatek}/pinctrl-rt3883.c | 28 +++--- drivers/pinctrl/ralink/Kconfig | 40 --------- drivers/pinctrl/ralink/Makefile | 9 -- 14 files changed, 246 insertions(+), 241 deletions(-) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-mt7620.c (81%) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-mt7621.c (80%) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-mt76x8.c (81%) rename drivers/pinctrl/{ralink/pinctrl-ralink.c => mediatek/pinctrl-mtmips.c} (74%) rename drivers/pinctrl/{ralink/pinctrl-ralink.h => mediatek/pinctrl-mtmips.h} (75%) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-rt2880.c (71%) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-rt305x.c (75%) rename drivers/pinctrl/{ralink => mediatek}/pinctrl-rt3883.c (80%) delete mode 100644 drivers/pinctrl/ralink/Kconfig delete mode 100644 drivers/pinctrl/ralink/Makefile diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index dcb53c4a9584..8a6012770640 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -537,7 +537,6 @@ source "drivers/pinctrl/nomadik/Kconfig" source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" -source "drivers/pinctrl/ralink/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/spear/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d5939840bb2a..ada6ed1d4e91 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -66,7 +66,6 @@ obj-y += nomadik/ obj-y += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM) += qcom/ -obj-$(CONFIG_PINCTRL_RALINK) += ralink/ obj-$(CONFIG_PINCTRL_RENESAS) += renesas/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index a71874fed3d6..3a6b99b23f35 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only menu "MediaTek pinctrl drivers" - depends on ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_MEDIATEK || RALINK || COMPILE_TEST config EINT_MTK tristate "MediaTek External Interrupt Support" @@ -22,6 +22,12 @@ config PINCTRL_MTK config PINCTRL_MTK_V2 tristate +config PINCTRL_MTK_MTMIPS + bool + depends on RALINK + select PINMUX + select GENERIC_PINCONF + config PINCTRL_MTK_MOORE bool depends on OF @@ -43,6 +49,49 @@ config PINCTRL_MTK_PARIS select OF_GPIO select PINCTRL_MTK_V2 +# For MIPS SoCs +config PINCTRL_MT7620 + bool "MediaTek MT7620 pin control" + depends on SOC_MT7620 || COMPILE_TEST + depends on RALINK + default SOC_MT7620 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_MT7621 + bool "MediaTek MT7621 pin control" + depends on SOC_MT7621 || COMPILE_TEST + depends on RALINK + default SOC_MT7621 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_MT76X8 + bool "MediaTek MT76X8 pin control" + depends on SOC_MT7620 || COMPILE_TEST + depends on RALINK + default SOC_MT7620 + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT2880 + bool "MediaTek RT2880 pin control" + depends on SOC_RT288X || COMPILE_TEST + depends on RALINK + default SOC_RT288X + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT305X + bool "MediaTek RT305X pin control" + depends on SOC_RT305X || COMPILE_TEST + depends on RALINK + default SOC_RT305X + select PINCTRL_MTK_MTMIPS + +config PINCTRL_RT3883 + bool "MediaTek RT3883 pin control" + depends on SOC_RT3883 || COMPILE_TEST + depends on RALINK + default SOC_RT3883 + select PINCTRL_MTK_MTMIPS + # For ARMv7 SoCs config PINCTRL_MT2701 bool "MediaTek MT2701 pin control" diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 44d197af516a..680f7e8526e0 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -1,32 +1,39 @@ # SPDX-License-Identifier: GPL-2.0 # Core -obj-$(CONFIG_EINT_MTK) += mtk-eint.o -obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o -obj-$(CONFIG_PINCTRL_MTK_V2) += pinctrl-mtk-common-v2.o -obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o -obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o +obj-$(CONFIG_EINT_MTK) += mtk-eint.o +obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o +obj-$(CONFIG_PINCTRL_MTK_V2) += pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_MTMIPS) += pinctrl-mtmips.o +obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o +obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o # SoC Drivers -obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o -obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o -obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o -obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o -obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o -obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o -obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o -obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o -obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o -obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o -obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o -obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o -obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o -obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o -obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o -obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o -obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o -obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o -obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o -obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o -obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o -obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o +obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o +obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o +obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o +obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o +obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o +obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o +obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o +obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o +obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o +obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o +obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o +obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o +obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o +obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o +obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o +obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o +obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o +obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o +obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o +obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o +obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o +obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o +obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o +obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o +obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o +obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o +obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o +obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o +obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/mediatek/pinctrl-mt7620.c similarity index 81% rename from drivers/pinctrl/ralink/pinctrl-mt7620.c rename to drivers/pinctrl/mediatek/pinctrl-mt7620.c index b2245fd65c72..1a2dbbdd25f1 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7620.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7620.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define MT7620_GPIO_MODE_UART0_SHIFT 2 #define MT7620_GPIO_MODE_UART0_MASK 0x7 @@ -52,20 +52,20 @@ #define MT7620_GPIO_MODE_EPHY 15 #define MT7620_GPIO_MODE_PA 20 -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -static struct ralink_pmx_func mdio_grp[] = { +static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; +static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), }; -static struct ralink_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; -static struct ralink_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; -static struct ralink_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; -static struct ralink_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; -static struct ralink_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; -static struct ralink_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; -static struct ralink_pmx_func uartf_grp[] = { +static struct mtmips_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; +static struct mtmips_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; +static struct mtmips_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; +static struct mtmips_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; +static struct mtmips_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; +static struct mtmips_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; +static struct mtmips_pmx_func uartf_grp[] = { FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), @@ -74,20 +74,20 @@ static struct ralink_pmx_func uartf_grp[] = { FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func wdt_grp[] = { +static struct mtmips_pmx_func wdt_grp[] = { FUNC("wdt rst", 0, 17, 1), FUNC("wdt refclk", 0, 17, 1), }; -static struct ralink_pmx_func pcie_rst_grp[] = { +static struct mtmips_pmx_func pcie_rst_grp[] = { FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) }; -static struct ralink_pmx_func nd_sd_grp[] = { +static struct mtmips_pmx_func nd_sd_grp[] = { FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) }; -static struct ralink_pmx_group mt7620a_pinmux_data[] = { +static struct mtmips_pmx_group mt7620a_pinmux_data[] = { GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, MT7620_GPIO_MODE_UART0_SHIFT), @@ -112,7 +112,7 @@ static struct ralink_pmx_group mt7620a_pinmux_data[] = { static int mt7620_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt7620a_pinmux_data); + return mtmips_pinctrl_init(pdev, mt7620a_pinmux_data); } static const struct of_device_id mt7620_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/mediatek/pinctrl-mt7621.c similarity index 80% rename from drivers/pinctrl/ralink/pinctrl-mt7621.c rename to drivers/pinctrl/mediatek/pinctrl-mt7621.c index 2128a94f6d1b..96c5ef942cf4 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt7621.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7621.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define MT7621_GPIO_MODE_UART1 1 #define MT7621_GPIO_MODE_I2C 2 @@ -34,40 +34,40 @@ #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 #define MT7621_GPIO_MODE_SDHCI_GPIO 1 -static struct ralink_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; -static struct ralink_pmx_func uart3_grp[] = { +static struct mtmips_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; +static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; +static struct mtmips_pmx_func uart3_grp[] = { FUNC("uart3", 0, 5, 4), FUNC("i2s", 2, 5, 4), FUNC("spdif3", 3, 5, 4), }; -static struct ralink_pmx_func uart2_grp[] = { +static struct mtmips_pmx_func uart2_grp[] = { FUNC("uart2", 0, 9, 4), FUNC("pcm", 2, 9, 4), FUNC("spdif2", 3, 9, 4), }; -static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; -static struct ralink_pmx_func wdt_grp[] = { +static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; +static struct mtmips_pmx_func wdt_grp[] = { FUNC("wdt rst", 0, 18, 1), FUNC("wdt refclk", 2, 18, 1), }; -static struct ralink_pmx_func pcie_rst_grp[] = { +static struct mtmips_pmx_func pcie_rst_grp[] = { FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) }; -static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; -static struct ralink_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; -static struct ralink_pmx_func spi_grp[] = { +static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; +static struct mtmips_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 34, 7), FUNC("nand1", 2, 34, 7), }; -static struct ralink_pmx_func sdhci_grp[] = { +static struct mtmips_pmx_func sdhci_grp[] = { FUNC("sdhci", 0, 41, 8), FUNC("nand2", 2, 41, 8), }; -static struct ralink_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; +static struct mtmips_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; -static struct ralink_pmx_group mt7621_pinmux_data[] = { +static struct mtmips_pmx_group mt7621_pinmux_data[] = { GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, @@ -92,7 +92,7 @@ static struct ralink_pmx_group mt7621_pinmux_data[] = { static int mt7621_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt7621_pinmux_data); + return mtmips_pinctrl_init(pdev, mt7621_pinmux_data); } static const struct of_device_id mt7621_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-mt76x8.c b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c similarity index 81% rename from drivers/pinctrl/ralink/pinctrl-mt76x8.c rename to drivers/pinctrl/mediatek/pinctrl-mt76x8.c index 5a6a82a58180..1d463bcfb1bd 100644 --- a/drivers/pinctrl/ralink/pinctrl-mt76x8.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define MT76X8_GPIO_MODE_MASK 0x3 @@ -35,173 +35,173 @@ #define MT76X8_GPIO_MODE_SPIS 2 #define MT76X8_GPIO_MODE_GPIO 0 -static struct ralink_pmx_func pwm1_grp[] = { +static struct mtmips_pmx_func pwm1_grp[] = { FUNC("sdxc d6", 3, 19, 1), FUNC("utif", 2, 19, 1), FUNC("gpio", 1, 19, 1), FUNC("pwm1", 0, 19, 1), }; -static struct ralink_pmx_func pwm0_grp[] = { +static struct mtmips_pmx_func pwm0_grp[] = { FUNC("sdxc d7", 3, 18, 1), FUNC("utif", 2, 18, 1), FUNC("gpio", 1, 18, 1), FUNC("pwm0", 0, 18, 1), }; -static struct ralink_pmx_func uart2_grp[] = { +static struct mtmips_pmx_func uart2_grp[] = { FUNC("sdxc d5 d4", 3, 20, 2), FUNC("pwm", 2, 20, 2), FUNC("gpio", 1, 20, 2), FUNC("uart2", 0, 20, 2), }; -static struct ralink_pmx_func uart1_grp[] = { +static struct mtmips_pmx_func uart1_grp[] = { FUNC("sw_r", 3, 45, 2), FUNC("pwm", 2, 45, 2), FUNC("gpio", 1, 45, 2), FUNC("uart1", 0, 45, 2), }; -static struct ralink_pmx_func i2c_grp[] = { +static struct mtmips_pmx_func i2c_grp[] = { FUNC("-", 3, 4, 2), FUNC("debug", 2, 4, 2), FUNC("gpio", 1, 4, 2), FUNC("i2c", 0, 4, 2), }; -static struct ralink_pmx_func refclk_grp[] = { FUNC("refclk", 0, 37, 1) }; -static struct ralink_pmx_func perst_grp[] = { FUNC("perst", 0, 36, 1) }; -static struct ralink_pmx_func wdt_grp[] = { FUNC("wdt", 0, 38, 1) }; -static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 7, 4) }; +static struct mtmips_pmx_func refclk_grp[] = { FUNC("refclk", 0, 37, 1) }; +static struct mtmips_pmx_func perst_grp[] = { FUNC("perst", 0, 36, 1) }; +static struct mtmips_pmx_func wdt_grp[] = { FUNC("wdt", 0, 38, 1) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 7, 4) }; -static struct ralink_pmx_func sd_mode_grp[] = { +static struct mtmips_pmx_func sd_mode_grp[] = { FUNC("jtag", 3, 22, 8), FUNC("utif", 2, 22, 8), FUNC("gpio", 1, 22, 8), FUNC("sdxc", 0, 22, 8), }; -static struct ralink_pmx_func uart0_grp[] = { +static struct mtmips_pmx_func uart0_grp[] = { FUNC("-", 3, 12, 2), FUNC("-", 2, 12, 2), FUNC("gpio", 1, 12, 2), FUNC("uart0", 0, 12, 2), }; -static struct ralink_pmx_func i2s_grp[] = { +static struct mtmips_pmx_func i2s_grp[] = { FUNC("antenna", 3, 0, 4), FUNC("pcm", 2, 0, 4), FUNC("gpio", 1, 0, 4), FUNC("i2s", 0, 0, 4), }; -static struct ralink_pmx_func spi_cs1_grp[] = { +static struct mtmips_pmx_func spi_cs1_grp[] = { FUNC("-", 3, 6, 1), FUNC("refclk", 2, 6, 1), FUNC("gpio", 1, 6, 1), FUNC("spi cs1", 0, 6, 1), }; -static struct ralink_pmx_func spis_grp[] = { +static struct mtmips_pmx_func spis_grp[] = { FUNC("pwm_uart2", 3, 14, 4), FUNC("utif", 2, 14, 4), FUNC("gpio", 1, 14, 4), FUNC("spis", 0, 14, 4), }; -static struct ralink_pmx_func gpio_grp[] = { +static struct mtmips_pmx_func gpio_grp[] = { FUNC("pcie", 3, 11, 1), FUNC("refclk", 2, 11, 1), FUNC("gpio", 1, 11, 1), FUNC("gpio", 0, 11, 1), }; -static struct ralink_pmx_func p4led_kn_grp[] = { +static struct mtmips_pmx_func p4led_kn_grp[] = { FUNC("jtag", 3, 30, 1), FUNC("utif", 2, 30, 1), FUNC("gpio", 1, 30, 1), FUNC("p4led_kn", 0, 30, 1), }; -static struct ralink_pmx_func p3led_kn_grp[] = { +static struct mtmips_pmx_func p3led_kn_grp[] = { FUNC("jtag", 3, 31, 1), FUNC("utif", 2, 31, 1), FUNC("gpio", 1, 31, 1), FUNC("p3led_kn", 0, 31, 1), }; -static struct ralink_pmx_func p2led_kn_grp[] = { +static struct mtmips_pmx_func p2led_kn_grp[] = { FUNC("jtag", 3, 32, 1), FUNC("utif", 2, 32, 1), FUNC("gpio", 1, 32, 1), FUNC("p2led_kn", 0, 32, 1), }; -static struct ralink_pmx_func p1led_kn_grp[] = { +static struct mtmips_pmx_func p1led_kn_grp[] = { FUNC("jtag", 3, 33, 1), FUNC("utif", 2, 33, 1), FUNC("gpio", 1, 33, 1), FUNC("p1led_kn", 0, 33, 1), }; -static struct ralink_pmx_func p0led_kn_grp[] = { +static struct mtmips_pmx_func p0led_kn_grp[] = { FUNC("jtag", 3, 34, 1), FUNC("rsvd", 2, 34, 1), FUNC("gpio", 1, 34, 1), FUNC("p0led_kn", 0, 34, 1), }; -static struct ralink_pmx_func wled_kn_grp[] = { +static struct mtmips_pmx_func wled_kn_grp[] = { FUNC("rsvd", 3, 35, 1), FUNC("rsvd", 2, 35, 1), FUNC("gpio", 1, 35, 1), FUNC("wled_kn", 0, 35, 1), }; -static struct ralink_pmx_func p4led_an_grp[] = { +static struct mtmips_pmx_func p4led_an_grp[] = { FUNC("jtag", 3, 39, 1), FUNC("utif", 2, 39, 1), FUNC("gpio", 1, 39, 1), FUNC("p4led_an", 0, 39, 1), }; -static struct ralink_pmx_func p3led_an_grp[] = { +static struct mtmips_pmx_func p3led_an_grp[] = { FUNC("jtag", 3, 40, 1), FUNC("utif", 2, 40, 1), FUNC("gpio", 1, 40, 1), FUNC("p3led_an", 0, 40, 1), }; -static struct ralink_pmx_func p2led_an_grp[] = { +static struct mtmips_pmx_func p2led_an_grp[] = { FUNC("jtag", 3, 41, 1), FUNC("utif", 2, 41, 1), FUNC("gpio", 1, 41, 1), FUNC("p2led_an", 0, 41, 1), }; -static struct ralink_pmx_func p1led_an_grp[] = { +static struct mtmips_pmx_func p1led_an_grp[] = { FUNC("jtag", 3, 42, 1), FUNC("utif", 2, 42, 1), FUNC("gpio", 1, 42, 1), FUNC("p1led_an", 0, 42, 1), }; -static struct ralink_pmx_func p0led_an_grp[] = { +static struct mtmips_pmx_func p0led_an_grp[] = { FUNC("jtag", 3, 43, 1), FUNC("rsvd", 2, 43, 1), FUNC("gpio", 1, 43, 1), FUNC("p0led_an", 0, 43, 1), }; -static struct ralink_pmx_func wled_an_grp[] = { +static struct mtmips_pmx_func wled_an_grp[] = { FUNC("rsvd", 3, 44, 1), FUNC("rsvd", 2, 44, 1), FUNC("gpio", 1, 44, 1), FUNC("wled_an", 0, 44, 1), }; -static struct ralink_pmx_group mt76x8_pinmux_data[] = { +static struct mtmips_pmx_group mt76x8_pinmux_data[] = { GRP_G("pwm1", pwm1_grp, MT76X8_GPIO_MODE_MASK, 1, MT76X8_GPIO_MODE_PWM1), GRP_G("pwm0", pwm0_grp, MT76X8_GPIO_MODE_MASK, @@ -257,7 +257,7 @@ static struct ralink_pmx_group mt76x8_pinmux_data[] = { static int mt76x8_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, mt76x8_pinmux_data); + return mtmips_pinctrl_init(pdev, mt76x8_pinmux_data); } static const struct of_device_id mt76x8_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-ralink.c b/drivers/pinctrl/mediatek/pinctrl-mtmips.c similarity index 74% rename from drivers/pinctrl/ralink/pinctrl-ralink.c rename to drivers/pinctrl/mediatek/pinctrl-mtmips.c index 770862f45b3f..efd77b6c56a1 100644 --- a/drivers/pinctrl/ralink/pinctrl-ralink.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.c @@ -19,23 +19,23 @@ #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #include "../core.h" #include "../pinctrl-utils.h" #define SYSC_REG_GPIO_MODE 0x60 #define SYSC_REG_GPIO_MODE2 0x64 -struct ralink_priv { +struct mtmips_priv { struct device *dev; struct pinctrl_pin_desc *pads; struct pinctrl_desc *desc; - struct ralink_pmx_func **func; + struct mtmips_pmx_func **func; int func_count; - struct ralink_pmx_group *groups; + struct mtmips_pmx_group *groups; const char **group_names; int group_count; @@ -43,27 +43,27 @@ struct ralink_priv { int max_pins; }; -static int ralink_get_group_count(struct pinctrl_dev *pctrldev) +static int mtmips_get_group_count(struct pinctrl_dev *pctrldev) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); return p->group_count; } -static const char *ralink_get_group_name(struct pinctrl_dev *pctrldev, +static const char *mtmips_get_group_name(struct pinctrl_dev *pctrldev, unsigned int group) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); return (group >= p->group_count) ? NULL : p->group_names[group]; } -static int ralink_get_group_pins(struct pinctrl_dev *pctrldev, +static int mtmips_get_group_pins(struct pinctrl_dev *pctrldev, unsigned int group, const unsigned int **pins, unsigned int *num_pins) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); if (group >= p->group_count) return -EINVAL; @@ -74,35 +74,35 @@ static int ralink_get_group_pins(struct pinctrl_dev *pctrldev, return 0; } -static const struct pinctrl_ops ralink_pctrl_ops = { - .get_groups_count = ralink_get_group_count, - .get_group_name = ralink_get_group_name, - .get_group_pins = ralink_get_group_pins, +static const struct pinctrl_ops mtmips_pctrl_ops = { + .get_groups_count = mtmips_get_group_count, + .get_group_name = mtmips_get_group_name, + .get_group_pins = mtmips_get_group_pins, .dt_node_to_map = pinconf_generic_dt_node_to_map_all, .dt_free_map = pinconf_generic_dt_free_map, }; -static int ralink_pmx_func_count(struct pinctrl_dev *pctrldev) +static int mtmips_pmx_func_count(struct pinctrl_dev *pctrldev) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); return p->func_count; } -static const char *ralink_pmx_func_name(struct pinctrl_dev *pctrldev, +static const char *mtmips_pmx_func_name(struct pinctrl_dev *pctrldev, unsigned int func) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); return p->func[func]->name; } -static int ralink_pmx_group_get_groups(struct pinctrl_dev *pctrldev, +static int mtmips_pmx_group_get_groups(struct pinctrl_dev *pctrldev, unsigned int func, const char * const **groups, unsigned int * const num_groups) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); if (p->func[func]->group_count == 1) *groups = &p->group_names[p->func[func]->groups[0]]; @@ -114,10 +114,10 @@ static int ralink_pmx_group_get_groups(struct pinctrl_dev *pctrldev, return 0; } -static int ralink_pmx_group_enable(struct pinctrl_dev *pctrldev, +static int mtmips_pmx_group_enable(struct pinctrl_dev *pctrldev, unsigned int func, unsigned int group) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); u32 mode = 0; u32 reg = SYSC_REG_GPIO_MODE; int i; @@ -158,11 +158,11 @@ static int ralink_pmx_group_enable(struct pinctrl_dev *pctrldev, return 0; } -static int ralink_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev, +static int mtmips_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev, struct pinctrl_gpio_range *range, unsigned int pin) { - struct ralink_priv *p = pinctrl_dev_get_drvdata(pctrldev); + struct mtmips_priv *p = pinctrl_dev_get_drvdata(pctrldev); if (!p->gpio[pin]) { dev_err(p->dev, "pin %d is not set to gpio mux\n", pin); @@ -172,28 +172,28 @@ static int ralink_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev, return 0; } -static const struct pinmux_ops ralink_pmx_group_ops = { - .get_functions_count = ralink_pmx_func_count, - .get_function_name = ralink_pmx_func_name, - .get_function_groups = ralink_pmx_group_get_groups, - .set_mux = ralink_pmx_group_enable, - .gpio_request_enable = ralink_pmx_group_gpio_request_enable, +static const struct pinmux_ops mtmips_pmx_group_ops = { + .get_functions_count = mtmips_pmx_func_count, + .get_function_name = mtmips_pmx_func_name, + .get_function_groups = mtmips_pmx_group_get_groups, + .set_mux = mtmips_pmx_group_enable, + .gpio_request_enable = mtmips_pmx_group_gpio_request_enable, }; -static struct pinctrl_desc ralink_pctrl_desc = { +static struct pinctrl_desc mtmips_pctrl_desc = { .owner = THIS_MODULE, - .name = "ralink-pinctrl", - .pctlops = &ralink_pctrl_ops, - .pmxops = &ralink_pmx_group_ops, + .name = "mtmips-pinctrl", + .pctlops = &mtmips_pctrl_ops, + .pmxops = &mtmips_pmx_group_ops, }; -static struct ralink_pmx_func gpio_func = { +static struct mtmips_pmx_func gpio_func = { .name = "gpio", }; -static int ralink_pinctrl_index(struct ralink_priv *p) +static int mtmips_pinctrl_index(struct mtmips_priv *p) { - struct ralink_pmx_group *mux = p->groups; + struct mtmips_pmx_group *mux = p->groups; int i, j, c = 0; /* count the mux functions */ @@ -248,7 +248,7 @@ static int ralink_pinctrl_index(struct ralink_priv *p) return 0; } -static int ralink_pinctrl_pins(struct ralink_priv *p) +static int mtmips_pinctrl_pins(struct mtmips_priv *p) { int i, j; @@ -313,10 +313,10 @@ static int ralink_pinctrl_pins(struct ralink_priv *p) return 0; } -int ralink_pinctrl_init(struct platform_device *pdev, - struct ralink_pmx_group *data) +int mtmips_pinctrl_init(struct platform_device *pdev, + struct mtmips_pmx_group *data) { - struct ralink_priv *p; + struct mtmips_priv *p; struct pinctrl_dev *dev; int err; @@ -324,23 +324,23 @@ int ralink_pinctrl_init(struct platform_device *pdev, return -ENOTSUPP; /* setup the private data */ - p = devm_kzalloc(&pdev->dev, sizeof(struct ralink_priv), GFP_KERNEL); + p = devm_kzalloc(&pdev->dev, sizeof(struct mtmips_priv), GFP_KERNEL); if (!p) return -ENOMEM; p->dev = &pdev->dev; - p->desc = &ralink_pctrl_desc; + p->desc = &mtmips_pctrl_desc; p->groups = data; platform_set_drvdata(pdev, p); /* init the device */ - err = ralink_pinctrl_index(p); + err = mtmips_pinctrl_index(p); if (err) { dev_err(&pdev->dev, "failed to load index\n"); return err; } - err = ralink_pinctrl_pins(p); + err = mtmips_pinctrl_pins(p); if (err) { dev_err(&pdev->dev, "failed to load pins\n"); return err; diff --git a/drivers/pinctrl/ralink/pinctrl-ralink.h b/drivers/pinctrl/mediatek/pinctrl-mtmips.h similarity index 75% rename from drivers/pinctrl/ralink/pinctrl-ralink.h rename to drivers/pinctrl/mediatek/pinctrl-mtmips.h index e6037be1e153..a7c3dd724431 100644 --- a/drivers/pinctrl/ralink/pinctrl-ralink.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.h @@ -3,8 +3,8 @@ * Copyright (C) 2012 John Crispin */ -#ifndef _PINCTRL_RALINK_H__ -#define _PINCTRL_RALINK_H__ +#ifndef _PINCTRL_MTMIPS_H__ +#define _PINCTRL_MTMIPS_H__ #define FUNC(name, value, pin_first, pin_count) \ { name, value, pin_first, pin_count } @@ -19,9 +19,9 @@ .func = _func, .gpio = _gpio, \ .func_count = ARRAY_SIZE(_func) } -struct ralink_pmx_group; +struct mtmips_pmx_group; -struct ralink_pmx_func { +struct mtmips_pmx_func { const char *name; const char value; @@ -35,7 +35,7 @@ struct ralink_pmx_func { int enabled; }; -struct ralink_pmx_group { +struct mtmips_pmx_group { const char *name; int enabled; @@ -43,11 +43,11 @@ struct ralink_pmx_group { const char mask; const char gpio; - struct ralink_pmx_func *func; + struct mtmips_pmx_func *func; int func_count; }; -int ralink_pinctrl_init(struct platform_device *pdev, - struct ralink_pmx_group *data); +int mtmips_pinctrl_init(struct platform_device *pdev, + struct mtmips_pmx_group *data); #endif diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/mediatek/pinctrl-rt2880.c similarity index 71% rename from drivers/pinctrl/ralink/pinctrl-rt2880.c rename to drivers/pinctrl/mediatek/pinctrl-rt2880.c index e57b1c5d03dd..d3b21e6242e1 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt2880.c @@ -4,7 +4,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define RT2880_GPIO_MODE_I2C BIT(0) #define RT2880_GPIO_MODE_UART0 BIT(1) @@ -15,15 +15,15 @@ #define RT2880_GPIO_MODE_SDRAM BIT(6) #define RT2880_GPIO_MODE_PCI BIT(7) -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 7, 8) }; -static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) }; -static struct ralink_pmx_func pci_grp[] = { FUNC("pci", 0, 40, 32) }; +static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 7, 8) }; +static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) }; +static struct mtmips_pmx_func pci_grp[] = { FUNC("pci", 0, 40, 32) }; -static struct ralink_pmx_group rt2880_pinmux_data_act[] = { +static struct mtmips_pmx_group rt2880_pinmux_data_act[] = { GRP("i2c", i2c_grp, 1, RT2880_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT2880_GPIO_MODE_SPI), GRP("uartlite", uartlite_grp, 1, RT2880_GPIO_MODE_UART0), @@ -36,7 +36,7 @@ static struct ralink_pmx_group rt2880_pinmux_data_act[] = { static int rt2880_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, rt2880_pinmux_data_act); + return mtmips_pinctrl_init(pdev, rt2880_pinmux_data_act); } static const struct of_device_id rt2880_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/mediatek/pinctrl-rt305x.c similarity index 75% rename from drivers/pinctrl/ralink/pinctrl-rt305x.c rename to drivers/pinctrl/mediatek/pinctrl-rt305x.c index a112a83085ea..3f46808ba11c 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt305x.c @@ -5,7 +5,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define RT305X_GPIO_MODE_UART0_SHIFT 2 #define RT305X_GPIO_MODE_UART0_MASK 0x7 @@ -31,9 +31,9 @@ #define RT3352_GPIO_MODE_LNA 18 #define RT3352_GPIO_MODE_PA 20 -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartf_grp[] = { +static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartf_grp[] = { FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), @@ -42,28 +42,28 @@ static struct ralink_pmx_func uartf_grp[] = { FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func rt5350_led_grp[] = { FUNC("led", 0, 22, 5) }; -static struct ralink_pmx_func rt5350_cs1_grp[] = { +static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; +static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func rt5350_led_grp[] = { FUNC("led", 0, 22, 5) }; +static struct mtmips_pmx_func rt5350_cs1_grp[] = { FUNC("spi_cs1", 0, 27, 1), FUNC("wdg_cs1", 1, 27, 1), }; -static struct ralink_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) }; -static struct ralink_pmx_func rt3352_rgmii_grp[] = { +static struct mtmips_pmx_func sdram_grp[] = { FUNC("sdram", 0, 24, 16) }; +static struct mtmips_pmx_func rt3352_rgmii_grp[] = { FUNC("rgmii", 0, 24, 12) }; -static struct ralink_pmx_func rgmii_grp[] = { FUNC("rgmii", 0, 40, 12) }; -static struct ralink_pmx_func rt3352_lna_grp[] = { FUNC("lna", 0, 36, 2) }; -static struct ralink_pmx_func rt3352_pa_grp[] = { FUNC("pa", 0, 38, 2) }; -static struct ralink_pmx_func rt3352_led_grp[] = { FUNC("led", 0, 40, 5) }; -static struct ralink_pmx_func rt3352_cs1_grp[] = { +static struct mtmips_pmx_func rgmii_grp[] = { FUNC("rgmii", 0, 40, 12) }; +static struct mtmips_pmx_func rt3352_lna_grp[] = { FUNC("lna", 0, 36, 2) }; +static struct mtmips_pmx_func rt3352_pa_grp[] = { FUNC("pa", 0, 38, 2) }; +static struct mtmips_pmx_func rt3352_led_grp[] = { FUNC("led", 0, 40, 5) }; +static struct mtmips_pmx_func rt3352_cs1_grp[] = { FUNC("spi_cs1", 0, 45, 1), FUNC("wdg_cs1", 1, 45, 1), }; -static struct ralink_pmx_group rt3050_pinmux_data[] = { +static struct mtmips_pmx_group rt3050_pinmux_data[] = { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -76,7 +76,7 @@ static struct ralink_pmx_group rt3050_pinmux_data[] = { { 0 } }; -static struct ralink_pmx_group rt3352_pinmux_data[] = { +static struct mtmips_pmx_group rt3352_pinmux_data[] = { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -92,7 +92,7 @@ static struct ralink_pmx_group rt3352_pinmux_data[] = { { 0 } }; -static struct ralink_pmx_group rt5350_pinmux_data[] = { +static struct mtmips_pmx_group rt5350_pinmux_data[] = { GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK, @@ -107,11 +107,11 @@ static struct ralink_pmx_group rt5350_pinmux_data[] = { static int rt305x_pinctrl_probe(struct platform_device *pdev) { if (soc_is_rt5350()) - return ralink_pinctrl_init(pdev, rt5350_pinmux_data); + return mtmips_pinctrl_init(pdev, rt5350_pinmux_data); else if (soc_is_rt305x() || soc_is_rt3350()) - return ralink_pinctrl_init(pdev, rt3050_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3050_pinmux_data); else if (soc_is_rt3352()) - return ralink_pinctrl_init(pdev, rt3352_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3352_pinmux_data); else return -EINVAL; } diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/mediatek/pinctrl-rt3883.c similarity index 80% rename from drivers/pinctrl/ralink/pinctrl-rt3883.c rename to drivers/pinctrl/mediatek/pinctrl-rt3883.c index b687c70d3555..758350ce2ebe 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt3883.c +++ b/drivers/pinctrl/mediatek/pinctrl-rt3883.c @@ -3,7 +3,7 @@ #include #include #include -#include "pinctrl-ralink.h" +#include "pinctrl-mtmips.h" #define RT3883_GPIO_MODE_UART0_SHIFT 2 #define RT3883_GPIO_MODE_UART0_MASK 0x7 @@ -39,9 +39,9 @@ #define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 #define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK) -static struct ralink_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct ralink_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct ralink_pmx_func uartf_grp[] = { +static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct mtmips_pmx_func uartf_grp[] = { FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8), FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8), FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8), @@ -50,21 +50,21 @@ static struct ralink_pmx_func uartf_grp[] = { FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4), FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4), }; -static struct ralink_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -static struct ralink_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; -static struct ralink_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; -static struct ralink_pmx_func lna_a_grp[] = { FUNC("lna a", 0, 32, 3) }; -static struct ralink_pmx_func lna_g_grp[] = { FUNC("lna g", 0, 35, 3) }; -static struct ralink_pmx_func pci_grp[] = { +static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; +static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 17, 5) }; +static struct mtmips_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) }; +static struct mtmips_pmx_func lna_a_grp[] = { FUNC("lna a", 0, 32, 3) }; +static struct mtmips_pmx_func lna_g_grp[] = { FUNC("lna g", 0, 35, 3) }; +static struct mtmips_pmx_func pci_grp[] = { FUNC("pci-dev", 0, 40, 32), FUNC("pci-host2", 1, 40, 32), FUNC("pci-host1", 2, 40, 32), FUNC("pci-fnc", 3, 40, 32) }; -static struct ralink_pmx_func ge1_grp[] = { FUNC("ge1", 0, 72, 12) }; -static struct ralink_pmx_func ge2_grp[] = { FUNC("ge2", 0, 84, 12) }; +static struct mtmips_pmx_func ge1_grp[] = { FUNC("ge1", 0, 72, 12) }; +static struct mtmips_pmx_func ge2_grp[] = { FUNC("ge2", 0, 84, 12) }; -static struct ralink_pmx_group rt3883_pinmux_data[] = { +static struct mtmips_pmx_group rt3883_pinmux_data[] = { GRP("i2c", i2c_grp, 1, RT3883_GPIO_MODE_I2C), GRP("spi", spi_grp, 1, RT3883_GPIO_MODE_SPI), GRP("uartf", uartf_grp, RT3883_GPIO_MODE_UART0_MASK, @@ -83,7 +83,7 @@ static struct ralink_pmx_group rt3883_pinmux_data[] = { static int rt3883_pinctrl_probe(struct platform_device *pdev) { - return ralink_pinctrl_init(pdev, rt3883_pinmux_data); + return mtmips_pinctrl_init(pdev, rt3883_pinmux_data); } static const struct of_device_id rt3883_pinctrl_match[] = { diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig deleted file mode 100644 index c5fe4c31aaea..000000000000 --- a/drivers/pinctrl/ralink/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -menu "Ralink pinctrl drivers" - depends on RALINK - -config PINCTRL_RALINK - bool "Ralink pinctrl driver" - select PINMUX - select GENERIC_PINCONF - -config PINCTRL_MT7620 - bool "MT7620 pinctrl subdriver" - depends on RALINK && SOC_MT7620 - select PINCTRL_RALINK - -config PINCTRL_MT7621 - bool "MT7621 pinctrl subdriver" - depends on RALINK && SOC_MT7621 - select PINCTRL_RALINK - -config PINCTRL_MT76X8 - bool "MT76X8 pinctrl subdriver" - depends on RALINK && SOC_MT7620 - select PINCTRL_RALINK - -config PINCTRL_RT2880 - bool "RT2880 pinctrl subdriver" - depends on RALINK && SOC_RT288X - select PINCTRL_RALINK - -config PINCTRL_RT305X - bool "RT305X pinctrl subdriver" - depends on RALINK && SOC_RT305X - select PINCTRL_RALINK - -config PINCTRL_RT3883 - bool "RT3883 pinctrl subdriver" - depends on RALINK && SOC_RT3883 - select PINCTRL_RALINK - -endmenu diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makefile deleted file mode 100644 index be9acf2e27fd..000000000000 --- a/drivers/pinctrl/ralink/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PINCTRL_RALINK) += pinctrl-ralink.o - -obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o -obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o -obj-$(CONFIG_PINCTRL_MT76X8) += pinctrl-mt76x8.o -obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o -obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o -obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o From patchwork Wed Feb 22 18:39:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4537C636D6 for ; Wed, 22 Feb 2023 18:43:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gXkP3q0PiBkBwK8b9EQn1TC7kozjcgghymMyIgc3HLg=; b=fdReCb3WcOj8xy ymNtfir/PDNOesQESTBmXKQ0T0XjBzXX5RguNIKjKZm3NnYjrZDsENZhr35R9QFOn31ua2pUfpsIB 5jxGFqcIjxluUThSbfkhNFtccVFA9hfZk7kcPdfXwgMc/alTK+Ba/Z6tuCryqseykbczdQPUyQQot cl6NChBh7xo2ugUYM8ADyWrXWfm8n23nqgbwvfcjZLGCULM4v0xUALW28gtIRxgKQaRXewl5H190W 8lAXwzFkDEuuEX6vg5Oc1A/xiT/LcaPzTSoliM2LQGqSws11QOkMqI/CQt/vv6nh7bDP9aE5rSLo+ egLcL5qKCDKCe/BPQLRg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu4w-00DVIm-5K; Wed, 22 Feb 2023 18:42:58 +0000 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2Q-00DToh-6y; Wed, 22 Feb 2023 18:40:23 +0000 Received: by mail-wr1-x42f.google.com with SMTP id bo30so8192048wrb.0; Wed, 22 Feb 2023 10:40:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5e/ZXnR3dtECd1NLYQLnE3pN49tDwVf5mdK22wA4HAI=; b=e0L1GfVCQaNJwuNE7XclNZMlRZNRUbEPHBJfd0XncqutQGUyeH29zyH1a4dp3yp8ue 2FPJ56gfS2drYpxkrIOaFPx1wEFXcX/dJxdpRZ01GwaJYdXbHgiyOTtFMlAuGw62AJf5 sxctNZ3H+RjC1XDulEZ2dxOd+kFwAIfCHAvIU6SGnX2Y2L3x/Fi2U06YQbWxRi5kngAb NWwBFJCNZzrDFpfydVfRtYZBlzXrcdnqhjiEnFpR8Rhym7L2u9agpN6KJ1Knadw1wIS9 GxI9UstKeSXnA0ao+IqVc8xn92gc+q9w9YY45GOYxf4PmitUzueaMTNTX7h+wjdNz08k PKGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5e/ZXnR3dtECd1NLYQLnE3pN49tDwVf5mdK22wA4HAI=; b=Gzl+ngvWVYbjq49cf2zJGRKzgs7DMBj1cUZaGGNpXd6iESDsMmr2EK3axKfq3iLYNJ /pWp5AxZd0jlCTqvWdTm01e/pUc1eXaOMlIj9oLlyGUe4cCJvjs6QC+qij5gLb5IboKB hc4VbRJYfnW8A2HMIxqFXqeKxH/zhUR44q+J3pI8tOOk0akJE8uqrlA9Nk7By40b9BXr 8WMoWjQrDEycXk8P1oC4bBVkU4RLwdsP1deFTat/cRnRHsyMIaXodeqeEP1HywpkMXjI BGqDAUYYceE6vKHGkPfK4Ak5q3pA0/eKBstxuWQYrc8TF9C58+qJns9tuCyYhLsDpzhO hXDA== X-Gm-Message-State: AO0yUKUAAp8xGuvbWjlLc4Yyp50Gt2ka+ZiKeSm05aoXRT1U7J4rSDkN 6oryaKZNYcZ0fWfbA3QwYnY= X-Google-Smtp-Source: AK7set8tOiP8tGMuQ3l6IstW96Nd9dQl0IaddFW3GsuMpCs2zDBluc4RNWftK0pXdEQZNEzjhGbM2g== X-Received: by 2002:a05:6000:1246:b0:2c5:5ef8:fa36 with SMTP id j6-20020a056000124600b002c55ef8fa36mr8713882wrx.70.1677091218257; Wed, 22 Feb 2023 10:40:18 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:17 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 06/16] pinctrl: mediatek: remove OF_GPIO as reverse dependency Date: Wed, 22 Feb 2023 21:39:22 +0300 Message-Id: <20230222183932.33267-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104022_325865_1FDFCDC4 X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL The OF_GPIO option is enabled by default when GPIOLIB is enabled, and cannot be disabled. Remove it as a reverse dependency where GPIOLIB is also set as a reverse dependency. Signed-off-by: Arınç ÜNAL --- drivers/pinctrl/mediatek/Kconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 3a6b99b23f35..809037b146a2 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -17,7 +17,6 @@ config PINCTRL_MTK select GENERIC_PINCONF select GPIOLIB select EINT_MTK - select OF_GPIO config PINCTRL_MTK_V2 tristate @@ -35,7 +34,6 @@ config PINCTRL_MTK_MOORE select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GPIOLIB - select OF_GPIO select EINT_MTK select PINCTRL_MTK_V2 @@ -46,7 +44,6 @@ config PINCTRL_MTK_PARIS select GENERIC_PINCONF select GPIOLIB select EINT_MTK - select OF_GPIO select PINCTRL_MTK_V2 # For MIPS SoCs From patchwork Wed Feb 22 18:39:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149482 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6FAA3C636D6 for ; Wed, 22 Feb 2023 18:45:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=h2P/iPEqcOmhOOgW0yg3fwlOEkwnS2leul1UgkoLHl0=; b=f7SjxeCwjWobo3 8weTYfdE5QtszgpfubmgJoKUaQclXo8i1q+bl6QBD5B8LeIEg4HXoPZgjHxhjb0jSFnugNTUYTaMK JUVwvfpI6LgbdA2RoSUEETL/26rk6KYJo0EPsmG0znQuCghIp4Yq+38IsLWhPzcZsWHDZwjoCR3AK T33nBHGh3vyQW+rKcaY9U61APJ9PLHvb9qy6mk6hAAEXrlEc7eoKQevO0knkL7/MHvPk8O9qnQ8RF VZQ/QBJ1QzPEYFeT9BCL/f5tBLerA368hZy7d26/H6F6N/m+zSoJszu39ldk6NwMEBHL9nUyZnTve js5CVlDLVkI0wuMRiKSQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu62-00DVvx-0i; Wed, 22 Feb 2023 18:44:06 +0000 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2S-00DTqB-9O; Wed, 22 Feb 2023 18:40:28 +0000 Received: by mail-wr1-x42b.google.com with SMTP id r7so8586795wrz.6; Wed, 22 Feb 2023 10:40:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=93GncC/YMq/sLoJhUEjsPCJ56rRoBeF7sm8+y73s7Mk=; b=E+Vb5T8FT+Ye+67Qb+aNplspFmHXbtd5U08wTEttHwIwNpkiYDC8uD5NQSx/f/ZpjF Os7FrxTTU43Zrp7+2dvjzaLH+pm8N/PBaigLPTcEXubTqWPFoPtdDvC3maibU+2t1Fof Fu+Bh1plW8gl8lieS+ZhJjtNR94xLuyKtLJ+9xTTgrAmzr+tb2utmVMJ1jPnJ6p6NR+H yGWNnJEI8BZ5jNTqP7ETWO3fShvvgJ7N0W9zDWt3iWiniUUO9PjA+7k8SLmfyG4VXiaR 454D6qbHzW6vIBUJ9oMgKrqwDvnNC/G/D21tMlDnBp+71Et5NfMRxGLtKPU/O2qarBey /PFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=93GncC/YMq/sLoJhUEjsPCJ56rRoBeF7sm8+y73s7Mk=; b=RoVIYm5dVOF47eKiC2EwGoeVyugsD1A03QpJPt21VrvaxtSOfnSCK4e7zFMamNyd3D b7TLonqow10ZGCc/vqN3q6uMQmrzP9peNoMr9gUlJqdtGRUtPUIEi6X18JQNWK/rWFEp xWVawSWUet5hw89pia1jPcUhTG/t4bbl/hyAQr8010CbZycRVoB92/Zd77hGYrXlkk3X xpLZC/j8yOVEAYDA8vUOvXCRh5APkI3weT9TK1nOdpxEx8NA1Fb9cWnUpseSCIKeQPIy VQikryQDB6MQQ3u+58ljJysovrQ6PhB1qbs3W9q1k0/y2oKKOL6KU18tYSPzpfaf72X/ 8V2A== X-Gm-Message-State: AO0yUKVP92IUw+qZ+yknzvCJixCrLn4KC4VxHTsYiDJatv9LjXaB+XDu RtjSn9v1Ws5wr5vMH98M2kY= X-Google-Smtp-Source: AK7set+5TsQLLq8jvQah+3Ch7FDP4duQj6VzOpjRIUXYKG9wJPfXn9hnPOz+M9oBSvDU76T6n9ORQA== X-Received: by 2002:a5d:67c8:0:b0:2c6:75be:f2d7 with SMTP id n8-20020a5d67c8000000b002c675bef2d7mr6843257wrw.51.1677091220529; Wed, 22 Feb 2023 10:40:20 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:20 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 07/16] dt-bindings: pinctrl: ralink: add new compatible strings Date: Wed, 22 Feb 2023 21:39:23 +0300 Message-Id: <20230222183932.33267-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104024_412502_DB631063 X-CRM114-Status: GOOD ( 10.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Add the ralink,rt2880-pinmux compatible string. It had been removed from the driver which broke the ABI. Add the mediatek compatible strings. Change the compatible string on the examples with the mediatek compatible strings. Signed-off-by: Arınç ÜNAL --- .../devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml | 7 +++++-- .../devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml | 7 +++++-- .../devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml | 7 +++++-- .../devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml | 7 +++++-- .../devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml | 7 +++++-- 5 files changed, 25 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml index 1e63ea34146a..531b5f616c3d 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -17,7 +17,10 @@ description: properties: compatible: - const: ralink,mt7620-pinctrl + enum: + - mediatek,mt7620-pinctrl + - ralink,mt7620-pinctrl + - ralink,rt2880-pinmux patternProperties: '-pins$': @@ -647,7 +650,7 @@ additionalProperties: false examples: - | pinctrl { - compatible = "ralink,mt7620-pinctrl"; + compatible = "mediatek,mt7620-pinctrl"; i2c_pins: i2c0-pins { pinmux { diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml index 1b1d37b981d9..74923ca35c81 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml @@ -17,7 +17,10 @@ description: properties: compatible: - const: ralink,mt7621-pinctrl + enum: + - mediatek,mt7621-pinctrl + - ralink,mt7621-pinctrl + - ralink,rt2880-pinmux patternProperties: '-pins$': @@ -251,7 +254,7 @@ additionalProperties: false examples: - | pinctrl { - compatible = "ralink,mt7621-pinctrl"; + compatible = "mediatek,mt7621-pinctrl"; i2c_pins: i2c0-pins { pinmux { diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml index 7fd0df880a76..aceea6248614 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -17,7 +17,10 @@ description: properties: compatible: - const: ralink,rt2880-pinctrl + enum: + - mediatek,rt2880-pinctrl + - ralink,rt2880-pinctrl + - ralink,rt2880-pinmux patternProperties: '-pins$': @@ -131,7 +134,7 @@ additionalProperties: false examples: - | pinctrl { - compatible = "ralink,rt2880-pinctrl"; + compatible = "mediatek,rt2880-pinctrl"; i2c_pins: i2c0-pins { pinmux { diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml index 4d66ca752a30..4c87fe201809 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -18,7 +18,10 @@ description: properties: compatible: - const: ralink,rt305x-pinctrl + enum: + - mediatek,rt305x-pinctrl + - ralink,rt305x-pinctrl + - ralink,rt2880-pinmux patternProperties: '-pins$': @@ -264,7 +267,7 @@ additionalProperties: false examples: - | pinctrl { - compatible = "ralink,rt305x-pinctrl"; + compatible = "mediatek,rt305x-pinctrl"; i2c_pins: i2c0-pins { pinmux { diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml index 008d93181aea..71049a2b2779 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -17,7 +17,10 @@ description: properties: compatible: - const: ralink,rt3883-pinctrl + enum: + - mediatek,rt3883-pinctrl + - ralink,rt3883-pinctrl + - ralink,rt2880-pinmux patternProperties: '-pins$': @@ -251,7 +254,7 @@ additionalProperties: false examples: - | pinctrl { - compatible = "ralink,rt3883-pinctrl"; + compatible = "mediatek,rt3883-pinctrl"; i2c_pins: i2c0-pins { pinmux { From patchwork Wed Feb 22 18:39:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A40FC636D6 for ; Wed, 22 Feb 2023 18:44:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lgyhWq9slyU1QCZ9EJ9ila7l4JimhVDcELAJtwMuMQk=; b=YMeiqUU4+lAW/e ag9tHnkrGN7LhZAm6pc+0q6dfl2vbb8ttL57YOjQ0T8y/SanI57RjYumBjlpnU7s9ySQgiPMOpp9s GDVE+rjMzh9UPNPmlF+xvqgmvZN7/0wFFDgF/C/jrjw2inRkQ2+kYNjseb13tb1AHhUpJiQ8mcV6l OemM8dsHPbXLYRcsFwzfuHIcXlR0RkYgzXikheREVpo34yCNcxVy90qTccGk3d5suc3yChARPWPWb UhwKdvTM2aXbbMjeGhrHc4BK4UoSh1d3iwf9y5T6iCEJa5gSkGgnOLvMR9gGJ/pjEcCE/3lK5AJbh 6bPluM/+P1BGxwDJQ56w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu5Z-00DVep-Ge; Wed, 22 Feb 2023 18:43:37 +0000 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2R-00DTfQ-FV; Wed, 22 Feb 2023 18:40:26 +0000 Received: by mail-wr1-x434.google.com with SMTP id t15so8860196wrz.7; Wed, 22 Feb 2023 10:40:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ER0vFI5ErhPpjBGFO4kcWk4X1/JJbNjdl3KY04hLIxU=; b=fr+C4nCniGBv/+XrMWb+6QS0YLPvFrIVUeIH1AiW92b0gF4mU5BCEKXz/gP5f3vm9q X8qwt2biAAHZP+vh3zkfHTY7Zfjx9Bo0OhkXafnAA/klJDLmMeQjvYpw4ILaL8l1cLHu vTbqfyjndrLYZQljI+Is0w+Zz4RhqqwnFRYVtzCjFQIfskP7ETx1D7vzvL+F7osCT7/L q0P4KckrybXqS/yas96RskQE3ttlpD5sDnx0GwVefIVosFGy+8GsBgW8MK4XiU/i0Fmh pyb1fFOq+HyviNflqtVLB7SlneKR17VlqH1Q6/0BbfzevyeoNSaaiKa06f+9Az8p+3BU /1Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ER0vFI5ErhPpjBGFO4kcWk4X1/JJbNjdl3KY04hLIxU=; b=sOjGOuI9M0Hc5f6FH91J+/W2At9SQIrnuIeIBTVRa1dITZEM1+DYgtURgtRAu4gB73 hh05Usvn6QfWYkDC8RGwPWEmt8+gWqpz6cBgsrxFDHAPLqHJZ+x2bIo18Cg99wG1PT99 MEN0iMGSw+ULm9EYQAZF30XkSmxKfnbD7dSR6MK9d6vM5m3FC06bY7MLtWgxdrBdFyAk fSXiPj/khmBdft92A5f7UoUV6uRuT008U4I/urqn6u3w/C/zlg6vqVdhkxOJ7m5pMsD0 zcxRtEGD8he/S0OrToYjI8nWxOlMBBph7V0tDFzcttAsXDCZKjb6XXrIuQsBlJXg5Lsq 8Oow== X-Gm-Message-State: AO0yUKUIPReYScg3/VJC9J/ntz4ZagZ9CGMhlaDw/NW8ogsWJmglrd0I awNhu9/oEELGgciKYQDmY68= X-Google-Smtp-Source: AK7set+hUEzBr/atsckOQnBk4amaaKvrW6cIYsaW6dVu0IN7hMFgpj+XblzOrIPYeGOhOG/wQdNDrA== X-Received: by 2002:a5d:5087:0:b0:2c5:60a9:9cd2 with SMTP id a7-20020a5d5087000000b002c560a99cd2mr7204948wrt.28.1677091222807; Wed, 22 Feb 2023 10:40:22 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:22 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 08/16] dt-bindings: pinctrl: ralink: rename to mediatek Date: Wed, 22 Feb 2023 21:39:24 +0300 Message-Id: <20230222183932.33267-9-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104023_577179_6AA3D7D1 X-CRM114-Status: UNSURE ( 9.65 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Ralink was acquired by MediaTek in 2011. These SoCs have been rebranded as MediaTek. Rename the schemas to mediatek. Signed-off-by: Arınç ÜNAL --- ...ink,mt7620-pinctrl.yaml => mediatek,mt7620-pinctrl.yaml} | 6 +++--- ...ink,mt7621-pinctrl.yaml => mediatek,mt7621-pinctrl.yaml} | 6 +++--- ...ink,rt2880-pinctrl.yaml => mediatek,rt2880-pinctrl.yaml} | 6 +++--- ...ink,rt305x-pinctrl.yaml => mediatek,rt305x-pinctrl.yaml} | 6 +++--- ...ink,rt3883-pinctrl.yaml => mediatek,rt3883-pinctrl.yaml} | 6 +++--- 5 files changed, 15 insertions(+), 15 deletions(-) rename Documentation/devicetree/bindings/pinctrl/{ralink,mt7620-pinctrl.yaml => mediatek,mt7620-pinctrl.yaml} (98%) rename Documentation/devicetree/bindings/pinctrl/{ralink,mt7621-pinctrl.yaml => mediatek,mt7621-pinctrl.yaml} (97%) rename Documentation/devicetree/bindings/pinctrl/{ralink,rt2880-pinctrl.yaml => mediatek,rt2880-pinctrl.yaml} (95%) rename Documentation/devicetree/bindings/pinctrl/{ralink,rt305x-pinctrl.yaml => mediatek,rt305x-pinctrl.yaml} (97%) rename Documentation/devicetree/bindings/pinctrl/{ralink,rt3883-pinctrl.yaml => mediatek,rt3883-pinctrl.yaml} (97%) diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml index 531b5f616c3d..3bf58da8a394 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,mt7620-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ralink MT7620 Pin Controller +title: MediaTek MT7620 Pin Controller maintainers: - Arınç ÜNAL - Sergio Paracuellos description: - Ralink MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. + MediaTek MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml similarity index 97% rename from Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml index 74923ca35c81..4dfe3da5fd40 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,mt7621-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ralink MT7621 Pin Controller +title: MediaTek MT7621 Pin Controller maintainers: - Arınç ÜNAL - Sergio Paracuellos description: - Ralink MT7621 pin controller for MT7621 SoC. + MediaTek MT7621 pin controller for MT7621 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml similarity index 95% rename from Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml index aceea6248614..7395e4434e64 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,rt2880-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ralink RT2880 Pin Controller +title: MediaTek RT2880 Pin Controller maintainers: - Arınç ÜNAL - Sergio Paracuellos description: - Ralink RT2880 pin controller for RT2880 SoC. + MediaTek RT2880 pin controller for RT2880 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml similarity index 97% rename from Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml index 4c87fe201809..61fcf3ab1091 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,rt305x-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ralink RT305X Pin Controller +title: MediaTek RT305X Pin Controller maintainers: - Arınç ÜNAL - Sergio Paracuellos description: - Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 + MediaTek RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 SoCs. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml similarity index 97% rename from Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml index 71049a2b2779..ab20f67c47f0 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,rt3883-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,rt3883-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ralink RT3883 Pin Controller +title: MediaTek RT3883 Pin Controller maintainers: - Arınç ÜNAL - Sergio Paracuellos description: - Ralink RT3883 pin controller for RT3883 SoC. + MediaTek RT3883 pin controller for RT3883 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. From patchwork Wed Feb 22 18:39:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52450C636D6 for ; Wed, 22 Feb 2023 18:45:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+zvm3nKrea6Kw7MVa5mq6aM2cndkUh9HQvTpL/CG0vA=; b=pEVwi5KJ2gsY+a PsKmXZNO25D0yVBa+He6kz30xj51mMqxKUrIrd1oWEO9+ZyCXTjZ4vdIiLZjXo/sJduJS/PqPlYoX aFE1k9u34oBhdv72HrsV5WEiOORis2gptsmWOn+HHGTHbDHK3jXQDCUoWq8ssFm8jvqYEmuMlKo+p nEsqfSEPC5aWfarmdmyTQ4+MMfm/N1zi05DAzuUcgbo06YZLueb7NNc11JnSrYJRhxCFRxknDzBkT 85GCE2vTGc+SPgHUrK5PClEe/Did9bhdksAbKg2t1eQKDi3debjuSj0D3dEmTcKw8B0i3cG4wJRQn nZAVGOc6BGEf3IdtHOOQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu6a-00DWH4-PE; Wed, 22 Feb 2023 18:44:40 +0000 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2T-00DTj2-Ia; Wed, 22 Feb 2023 18:40:30 +0000 Received: by mail-wr1-x432.google.com with SMTP id i11so2586209wrp.5; Wed, 22 Feb 2023 10:40:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+o8MOEwE/dVfgMCl7bmAyjT+NEpiVZUInhrQfgLr0Hc=; b=Yx2QEGus5g1VMWhkonYwCdyHoxp3C8oP8Q0n3M8/VPVHeQKFGxLnPfR4bUiZq1Ossb esiN/rcW1ZRqywDyPJdN2Pxi6Yj7sIGXsgd7dCzmLH9IWXNLdGLLqqtIa47hnCRHuwdX DDIfSX5akeCRMItSM+XSqNg4lauRkvOOG9cG6XU80bJL469BaReUKJ1MbOA4pKvjZQXR TFm3r5RI2wEp6FLz1iTW1QhZD7ao14+7umhOcDt1oISGA9H9GKUnJgrIAU3Dd3BWh6d2 xQ6VfilK6Csvq5wZ8lgvbOL/EOIvW2jKvKFS4VJ6MvyzHxm4oR+D2ODo4Ji6ZVVg6EgC hi6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+o8MOEwE/dVfgMCl7bmAyjT+NEpiVZUInhrQfgLr0Hc=; b=X/dRbPVcDt+cbjXA3jiZFKgru85GkdGQ1E/R4fmDE2iS9dTupM+SdPmSPEOPhTqC3W u4b7EMXeDnWAmReNN2QQrti47S/ARPy7DfcpefonRWS/n66nDMh4JyS14o0anvde9Faj zece4kuLxiPKbfazK1rhAQlOyyR+/BKuuT1/j7sEtWbhh5BwAIbzFDdNxRdpLtYJVCqD Vwvl6E/GVGH6U0dYy0NAJ1kFCaVljv5HG0NJoFNXFcKfXWRn1UZsRBkLmT2PYtbEPE09 0aotO5foj+ayhRA4PvhqxvEXzkkMKRiKKV+Rw61YsWE5dA732tGI9/ZCqcIc5nxibEQ2 e4QQ== X-Gm-Message-State: AO0yUKWDDMdkxipmMqEY/64ZUnrxPAM7K09exdRyh2Hes34GuJ/lZRTM ytBUyB6Y8sS93KW1gSGKm2k= X-Google-Smtp-Source: AK7set8b55tFD4C1QYxIyA5oqOb4rTVXxGtnb3DL9lq2HAxP0/eGyZXITvhlPkLgw/mSUH+jnV4anw== X-Received: by 2002:a5d:5912:0:b0:2c5:58aa:35cb with SMTP id v18-20020a5d5912000000b002c558aa35cbmr8652823wrd.47.1677091225071; Wed, 22 Feb 2023 10:40:25 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:24 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 09/16] dt-bindings: pinctrl: mediatek: rt305x: split binding Date: Wed, 22 Feb 2023 21:39:25 +0300 Message-Id: <20230222183932.33267-10-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104025_705023_C0648467 X-CRM114-Status: GOOD ( 16.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL The RT3352 and RT5350 SoCs each contain different pin muxing information, therefore, should be split. This can be done now that there are compatible strings to distinguish them from other SoCs. Split the schema out to mediatek,rt3352-pinctrl.yaml and mediatek,rt5350-pinctrl.yaml. Signed-off-by: Arınç ÜNAL --- .../pinctrl/mediatek,rt305x-pinctrl.yaml | 78 +----- .../pinctrl/mediatek,rt3352-pinctrl.yaml | 247 ++++++++++++++++++ .../pinctrl/mediatek,rt5350-pinctrl.yaml | 210 +++++++++++++++ 3 files changed, 462 insertions(+), 73 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml index 61fcf3ab1091..1e6c7e7f2fe2 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml @@ -11,8 +11,7 @@ maintainers: - Sergio Paracuellos description: - MediaTek RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 - SoCs. + MediaTek RT305X pin controller for RT3050, RT3052, and RT3350 SoCs. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. @@ -36,21 +35,9 @@ patternProperties: function: description: A string containing the name of the function to mux to the group. - anyOf: - - description: For RT3050, RT3052 and RT3350 SoCs - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, - pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, - uartlite] - - - description: For RT3352 SoC - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, - lna, mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, - spi_cs1, uartf, uartlite, wdg_cs1] - - - description: For RT5350 SoC - enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, - pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf, - uartlite, wdg_cs1] + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, + pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, + uartlite] groups: description: @@ -69,17 +56,7 @@ patternProperties: then: properties: groups: - anyOf: - - description: For RT3050, RT3052 and RT3350 SoCs - enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, - uartlite] - - - description: For RT3352 SoC - enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, - uartf, uartlite] - - - description: For RT5350 SoC - enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite] + enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite] - if: properties: @@ -126,24 +103,6 @@ patternProperties: groups: enum: [jtag] - - if: - properties: - function: - const: led - then: - properties: - groups: - enum: [led] - - - if: - properties: - function: - const: lna - then: - properties: - groups: - enum: [lna] - - if: properties: function: @@ -153,15 +112,6 @@ patternProperties: groups: enum: [mdio] - - if: - properties: - function: - const: pa - then: - properties: - groups: - enum: [pa] - - if: properties: function: @@ -216,15 +166,6 @@ patternProperties: groups: enum: [spi] - - if: - properties: - function: - const: spi_cs1 - then: - properties: - groups: - enum: [spi_cs1] - - if: properties: function: @@ -243,15 +184,6 @@ patternProperties: groups: enum: [uartlite] - - if: - properties: - function: - const: wdg_cs1 - then: - properties: - groups: - enum: [spi_cs1] - additionalProperties: false additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml new file mode 100644 index 000000000000..7a74c1602afc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml @@ -0,0 +1,247 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,rt3352-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek RT3352 Pin Controller + +maintainers: + - Arınç ÜNAL + - Sergio Paracuellos + +description: + MediaTek RT3352 pin controller for RT3352 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + enum: + - mediatek,rt3352-pinctrl + - ralink,rt305x-pinctrl + - ralink,rt2880-pinmux + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, lna, + mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, + uartf, uartlite, wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, + uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: lna + then: + properties: + groups: + enum: [lna] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: pa + then: + properties: + groups: + enum: [pa] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: rgmii + then: + properties: + groups: + enum: [rgmii] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "mediatek,rt3352-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml new file mode 100644 index 000000000000..5184cea62640 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,rt5350-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek RT5350 Pin Controller + +maintainers: + - Arınç ÜNAL + - Sergio Paracuellos + +description: + MediaTek RT5350 pin controller for RT5350 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + enum: + - mediatek,rt5350-pinctrl + - ralink,rt305x-pinctrl + - ralink,rt2880-pinmux + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, + pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf, uartlite, + wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "mediatek,rt5350-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; From patchwork Wed Feb 22 18:39:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E783DC64ED6 for ; Wed, 22 Feb 2023 18:46:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+anWu892RNdqKou9rHc2zuCqO07hepcTeMTwkWKsMno=; b=iUZ0oQiEoU4KQ3 ZCfB+m38mpLQ+hAn6VvGMoA2lRs6+Rz7faLH8ww3bIfDm2FT+cwmJbWB1/5y7nkWuP3kqjFOAuq26 RfbQXe5M1BUyMqTUujC+JccM6Qa8Q9j5Z3CRuZpMD2oP1cA3Z6uo26E1QtTTLfajJn8DkHwvSg5m3 7xI5VAa9UyN0J1A+xMOzSA/KT0k2cSXYEJ04G/CpIJyRZuIrBp99lKM9xMAg6Vkm6qINuPz2sKTJ1 N/YkHeldwPy2FM9VXsWpmnXfwBOJT8t/XpbB8kIhxM1NbZqxKG26cPXyax6jATdTrbKvtQkT+VYw+ XfH0w+NO8JIZbnm0KNXg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu76-00DWZl-Mh; Wed, 22 Feb 2023 18:45:13 +0000 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2W-00DTfQ-3Z; Wed, 22 Feb 2023 18:40:31 +0000 Received: by mail-wr1-x434.google.com with SMTP id t15so8860348wrz.7; Wed, 22 Feb 2023 10:40:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FZAXOY6skhIgWMHQuHhCgThWWhEcbCZfRHE799lczRY=; b=W5fkHDeLRkjhFl9HxsxfQlmavtyQs2oxPZLNPWk0Vpt4xjZ7kqrL9pqdTgV7Q2jZu/ xcrSyQpqdkY6G5c/dhdlc+UXnJid6tYXoCjeayCzkOkvlGyRcmLYIdDFszSn9tnbwlEM AU6ft70VjLH5qFA2mr1idZ1v0V2mvVdLs4MREG/1E47EO6fpOuJKNxFbtwOG8cB+4jPV GluvLCjIBBS4yiM2r0TkigRUKAcdEXxbOOhNKJfSKLQEnUmCxwPo7zRbiq7WdD+GFGSG IndIcVsGyqADNx1S/Kq8r1/0W5b8GOCdDnCnDSTuw6eQA//LVWajR56r4TYvd/W3xdGQ Mjjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FZAXOY6skhIgWMHQuHhCgThWWhEcbCZfRHE799lczRY=; b=Lq7UzrafcVsT4gcabM+xKUj82dKBeoFk8Dc40eZTIIkJ56UslQ0cDXY68VvGdQrVED UHFFdEyFumE9Ht3t23p1qsDRRX3e5VBBoN3CVccLc+6XKty43LVev0+I5TpULNB99Jgj HdAn0jVhaWPtbY4ifxwr8k6uprPO500QHtCczZkpcnrEMIwV1U8m+tTPf/pWQnra71IT gEqGnne4YqQLSrguzTfv44lqx0HCbo/CrLgrs2nWy9o01QIPk66KncSdGdxd8R/P/uPI iomnbvLVaIutIV8cY27uMxJmZ7d5pi65MTMPgfK1f1RedCOxx03lmM+5ONIu3sRUuLNH FNYw== X-Gm-Message-State: AO0yUKX+eATJBi8qj275yXw5Ya0SO3Rb9Ll8RsPcbBE2+LZGUD82d6pl eD3T/dTS8pDTm430tIHobIXm5JCK3b3uPT9g X-Google-Smtp-Source: AK7set8yraodPeN66IMk83Fp6Duc8wdW7dUqDxPoDS0lnxcj7WrgTEibf0h3hfYo16EAc1o1BBO8gQ== X-Received: by 2002:a5d:40cc:0:b0:2c7:d6e:7e6e with SMTP id b12-20020a5d40cc000000b002c70d6e7e6emr1716277wrq.24.1677091227379; Wed, 22 Feb 2023 10:40:27 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:27 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 10/16] dt-bindings: pinctrl: mediatek: mt7620: split binding Date: Wed, 22 Feb 2023 21:39:26 +0300 Message-Id: <20230222183932.33267-11-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104028_367148_B5F7EA6A X-CRM114-Status: GOOD ( 11.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL The MT7628 and MT7688 SoCs contain different pin muxing information, therefore, should be split. This can be done now that there are compatible strings to distinguish them from other SoCs. Split the schema out to mediatek,mt76x8-pinctrl.yaml. Signed-off-by: Arınç ÜNAL --- .../pinctrl/mediatek,mt7620-pinctrl.yaml | 375 +-------------- .../pinctrl/mediatek,mt76x8-pinctrl.yaml | 454 ++++++++++++++++++ 2 files changed, 462 insertions(+), 367 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml index 3bf58da8a394..ea4a1194fbc4 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -11,7 +11,7 @@ maintainers: - Sergio Paracuellos description: - MediaTek MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. + MediaTek MT7620 pin controller for MT7620 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. @@ -35,19 +35,10 @@ patternProperties: function: description: A string containing the name of the function to mux to the group. - anyOf: - - description: For MT7620 SoC - enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, pa, - pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, refclk, - rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, wdt refclk, - wdt rst, wled] - - - description: For MT7628 and MT7688 SoCs - enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn, - p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, - p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2, - refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi, spi cs1, - spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -] + enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, + pa, pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, + refclk, rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, + wdt refclk, wdt rst, wled] groups: description: @@ -59,24 +50,6 @@ patternProperties: - function allOf: - - if: - properties: - function: - const: antenna - then: - properties: - groups: - enum: [i2s] - - - if: - properties: - function: - const: debug - then: - properties: - groups: - enum: [i2c] - - if: properties: function: @@ -93,17 +66,8 @@ patternProperties: then: properties: groups: - anyOf: - - description: For MT7620 SoC - enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, - spi, spi refclk, uartf, uartlite, wdt, wled] - - - description: For MT7628 and MT7688 SoCs - enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, - p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, - p4led_an, p4led_kn, perst, pwm0, pwm1, refclk, - sdmode, spi, spi cs1, spis, uart0, uart1, uart2, - wdt, wled_an, wled_kn] + enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi, + spi refclk, uartf, uartlite, wdt, wled] - if: properties: @@ -132,15 +96,6 @@ patternProperties: groups: enum: [i2c] - - if: - properties: - function: - const: i2s - then: - properties: - groups: - enum: [i2s] - - if: properties: function: @@ -150,17 +105,6 @@ patternProperties: groups: enum: [uartf] - - if: - properties: - function: - const: jtag - then: - properties: - groups: - enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, - p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, - sdmode] - - if: properties: function: @@ -179,96 +123,6 @@ patternProperties: groups: enum: [nd_sd] - - if: - properties: - function: - const: p0led_an - then: - properties: - groups: - enum: [p0led_an] - - - if: - properties: - function: - const: p0led_kn - then: - properties: - groups: - enum: [p0led_kn] - - - if: - properties: - function: - const: p1led_an - then: - properties: - groups: - enum: [p1led_an] - - - if: - properties: - function: - const: p1led_kn - then: - properties: - groups: - enum: [p1led_kn] - - - if: - properties: - function: - const: p2led_an - then: - properties: - groups: - enum: [p2led_an] - - - if: - properties: - function: - const: p2led_kn - then: - properties: - groups: - enum: [p2led_kn] - - - if: - properties: - function: - const: p3led_an - then: - properties: - groups: - enum: [p3led_an] - - - if: - properties: - function: - const: p3led_kn - then: - properties: - groups: - enum: [p3led_kn] - - - if: - properties: - function: - const: p4led_an - then: - properties: - groups: - enum: [p4led_an] - - - if: - properties: - function: - const: p4led_kn - then: - properties: - groups: - enum: [p4led_kn] - - if: properties: function: @@ -278,15 +132,6 @@ patternProperties: groups: enum: [pa] - - if: - properties: - function: - const: pcie - then: - properties: - groups: - enum: [gpio] - - if: properties: function: @@ -305,15 +150,6 @@ patternProperties: groups: enum: [pcie] - - if: - properties: - function: - const: pcm - then: - properties: - groups: - enum: [i2s] - - if: properties: function: @@ -341,51 +177,6 @@ patternProperties: groups: enum: [uartf] - - if: - properties: - function: - const: perst - then: - properties: - groups: - enum: [perst] - - - if: - properties: - function: - const: pwm - then: - properties: - groups: - enum: [uart1, uart2] - - - if: - properties: - function: - const: pwm0 - then: - properties: - groups: - enum: [pwm0] - - - if: - properties: - function: - const: pwm1 - then: - properties: - groups: - enum: [pwm1] - - - if: - properties: - function: - const: pwm_uart2 - then: - properties: - groups: - enum: [spis] - - if: properties: function: @@ -393,12 +184,7 @@ patternProperties: then: properties: groups: - anyOf: - - description: For MT7620 SoC - enum: [mdio] - - - description: For MT7628 and MT7688 SoCs - enum: [gpio, refclk, spi cs1] + enum: [mdio] - if: properties: @@ -418,15 +204,6 @@ patternProperties: groups: enum: [rgmii2] - - if: - properties: - function: - const: rsvd - then: - properties: - groups: - enum: [p0led_an, p0led_kn, wled_an, wled_kn] - - if: properties: function: @@ -436,42 +213,6 @@ patternProperties: groups: enum: [nd_sd] - - if: - properties: - function: - const: sdxc - then: - properties: - groups: - enum: [sdmode] - - - if: - properties: - function: - const: sdxc d5 d4 - then: - properties: - groups: - enum: [uart2] - - - if: - properties: - function: - const: sdxc d6 - then: - properties: - groups: - enum: [pwm1] - - - if: - properties: - function: - const: sdxc d7 - then: - properties: - groups: - enum: [pwm0] - - if: properties: function: @@ -481,15 +222,6 @@ patternProperties: groups: enum: [spi] - - if: - properties: - function: - const: spi cs1 - then: - properties: - groups: - enum: [spi cs1] - - if: properties: function: @@ -499,51 +231,6 @@ patternProperties: groups: enum: [spi refclk] - - if: - properties: - function: - const: spis - then: - properties: - groups: - enum: [spis] - - - if: - properties: - function: - const: sw_r - then: - properties: - groups: - enum: [uart1] - - - if: - properties: - function: - const: uart0 - then: - properties: - groups: - enum: [uart0] - - - if: - properties: - function: - const: uart1 - then: - properties: - groups: - enum: [uart1] - - - if: - properties: - function: - const: uart2 - then: - properties: - groups: - enum: [uart2] - - if: properties: function: @@ -562,25 +249,6 @@ patternProperties: groups: enum: [uartlite] - - if: - properties: - function: - const: utif - then: - properties: - groups: - enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, - p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode, spis] - - - if: - properties: - function: - const: wdt - then: - properties: - groups: - enum: [wdt] - - if: properties: function: @@ -608,33 +276,6 @@ patternProperties: groups: enum: [wled] - - if: - properties: - function: - const: wled_an - then: - properties: - groups: - enum: [wled_an] - - - if: - properties: - function: - const: wled_kn - then: - properties: - groups: - enum: [wled_kn] - - - if: - properties: - function: - const: "-" - then: - properties: - groups: - enum: [i2c, spi cs1, uart0] - additionalProperties: false additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml new file mode 100644 index 000000000000..c818c8947866 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml @@ -0,0 +1,454 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt76x8-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT76X8 Pin Controller + +maintainers: + - Arınç ÜNAL + - Sergio Paracuellos + +description: + MediaTek MT76X8 pin controller for MT7628 and MT7688 SoCs. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + enum: + - mediatek,mt76x8-pinctrl + - ralink,mt7620-pinctrl + - ralink,rt2880-pinmux + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn, + p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, + p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, + pwm_uart2, refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, + spi, spi cs1, spis, sw_r, uart0, uart1, uart2, utif, wdt, + wled_an, wled_kn, -] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: antenna + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: debug + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, + p2led_an, p2led_kn, p3led_an, p3led_kn, p4led_an, + p4led_kn, perst, pwm0, pwm1, refclk, sdmode, spi, + spi cs1, spis, uart0, uart1, uart2, wdt, wled_an, + wled_kn] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, + p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, + sdmode] + + - if: + properties: + function: + const: p0led_an + then: + properties: + groups: + enum: [p0led_an] + + - if: + properties: + function: + const: p0led_kn + then: + properties: + groups: + enum: [p0led_kn] + + - if: + properties: + function: + const: p1led_an + then: + properties: + groups: + enum: [p1led_an] + + - if: + properties: + function: + const: p1led_kn + then: + properties: + groups: + enum: [p1led_kn] + + - if: + properties: + function: + const: p2led_an + then: + properties: + groups: + enum: [p2led_an] + + - if: + properties: + function: + const: p2led_kn + then: + properties: + groups: + enum: [p2led_kn] + + - if: + properties: + function: + const: p3led_an + then: + properties: + groups: + enum: [p3led_an] + + - if: + properties: + function: + const: p3led_kn + then: + properties: + groups: + enum: [p3led_kn] + + - if: + properties: + function: + const: p4led_an + then: + properties: + groups: + enum: [p4led_an] + + - if: + properties: + function: + const: p4led_kn + then: + properties: + groups: + enum: [p4led_kn] + + - if: + properties: + function: + const: pcie + then: + properties: + groups: + enum: [gpio] + + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: perst + then: + properties: + groups: + enum: [perst] + + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [uart1, uart2] + + - if: + properties: + function: + const: pwm0 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: pwm1 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: pwm_uart2 + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: refclk + then: + properties: + groups: + enum: [gpio, refclk, spi cs1] + + - if: + properties: + function: + const: rsvd + then: + properties: + groups: + enum: [p0led_an, p0led_kn, wled_an, wled_kn] + + - if: + properties: + function: + const: sdxc + then: + properties: + groups: + enum: [sdmode] + + - if: + properties: + function: + const: sdxc d5 d4 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: sdxc d6 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: sdxc d7 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi cs1 + then: + properties: + groups: + enum: [spi cs1] + + - if: + properties: + function: + const: spis + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: sw_r + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart0 + then: + properties: + groups: + enum: [uart0] + + - if: + properties: + function: + const: uart1 + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: utif + then: + properties: + groups: + enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, + p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode, spis] + + - if: + properties: + function: + const: wdt + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wled_an + then: + properties: + groups: + enum: [wled_an] + + - if: + properties: + function: + const: wled_kn + then: + properties: + groups: + enum: [wled_kn] + + - if: + properties: + function: + const: "-" + then: + properties: + groups: + enum: [i2c, spi cs1, uart0] + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "mediatek,mt76x8-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; From patchwork Wed Feb 22 18:39:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 297BAC61DA4 for ; Wed, 22 Feb 2023 18:46:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DFMhd30xFQ+bjfGH8Ms5Qha2oHUYmjiI8rcZCcyqqUY=; b=fIETEEKWPVWG3l 1OlACHRi0f1VnWrLJnwlIOEM+/uUGJXxRTpwEhSMHM4tnF1bg5LolJSnEEE9BSlkOX4t6wrDJllrr rDrZxKbDJRbvLV7qwX/hj8PyK38h097NUQ4QTFFIaOoHcFQX8RWYoAAKhz3aUHHdh3CSvYFQhZuLy WK+v+qiQMQAjlBaQgdigbMoN2Yn+DXMWAjWQmAc7jMoszIUrqh5PQ3X1z2n9cD42IZtLqiUXw385g zH4wrRd9C1/q2TxLeRC4cnnzyWKo/p7PV+uXSfSdFlTmAUR4q1JdKMNdOEy0KNuU4QTFv6vTV0y5B bLnuzJQEVCldCJJqQPQg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu7e-00DWse-T6; Wed, 22 Feb 2023 18:45:48 +0000 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2Y-00DTvd-Rh; Wed, 22 Feb 2023 18:40:32 +0000 Received: by mail-wr1-x432.google.com with SMTP id v3so8678490wrp.2; Wed, 22 Feb 2023 10:40:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pb3s2WfXtxyN5ca68ejOPubf8a8GMk5C8l935KnSJi4=; b=TH9c+7lDaHFNxfnvz2Yx+/7tDuONcI+e4TKhn+LtTzYBCJiRIQLyqgJ624+2fb4Cek 3+ef2gBgyXu5sSaVqChdSshg8XsuQyuBFf+MfGkC/wRnTCJmf9SIKkosPOCnx9eBilT/ FuIFuwwFma9/BmVEQir0VAlk7pT9OCU/rM2Iki4oeCJGXXm2FClwIVW8QQ2BQJLSS+GG s/W8RbUBhduSoG+MDAwGYlSFIcPuxKVc9fEuR97zdd5KyxFX/82D6iYogyLpXXnet56/ 2KiF4BE0DY2Jis6WBk6k2UCNnwTHnqnvYpk2ytgjENNlgLedc9vAFMRoS1Dt7t5XUMt9 e9/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pb3s2WfXtxyN5ca68ejOPubf8a8GMk5C8l935KnSJi4=; b=ssbKcOOKy12u5iIBZ4qOLGw4ynIA1lbGFHp6kTBv1FYuqpmpelpPA0D3wEUp/xIBSq 8/F421OEJxzruBYJi0V6uaznbMxwHAVFh3ksIjogFveeQGrdu89HgJfO8bUBh05IyMRS ellvkw0fYmsKlsdzPDcRacWRJqzP7cGI/J0qkLu9mlVA93knhb9U4Q+D+4DGFW+PGGGS jgkdkt9NL4Mz75Y3ebo1lp6EKMAvOxUAHYUqFfmu78yUatWdRjThaSQN/v3CgWRWO5e3 ERh+IwJ1WngrwEXMr99DBLGHY0Vw9a8fGmnuG4I9tsmvErq22jYecsOXT6NKDj+HBX6Q C8UQ== X-Gm-Message-State: AO0yUKWfTlZZZF5w0fhBzXP91bNdeQ/jwjaY85DKpg8An1zky+RvgQDo M1WXqhoLdKzXO1gdMuMsUuc= X-Google-Smtp-Source: AK7set+IPymHO1XxqQ3hy1/GK0MeXI/BbYuMYgxuI9Cmu6brAd4AXFNhXCDcT9YwA2IVPhnbkAf+OA== X-Received: by 2002:a05:6000:18c:b0:2c5:8d7d:baa3 with SMTP id p12-20020a056000018c00b002c58d7dbaa3mr6806434wrx.42.1677091229663; Wed, 22 Feb 2023 10:40:29 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:29 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 11/16] MAINTAINERS: move ralink pinctrl to mediatek mips pinctrl Date: Wed, 22 Feb 2023 21:39:27 +0300 Message-Id: <20230222183932.33267-12-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104030_967560_5E96ACB5 X-CRM114-Status: GOOD ( 11.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL The Ralink pinctrl driver is now under the name of MediaTek MIPS pin controller. Move the maintainer information accordingly. Add dt-binding schema files. Add linux-mediatek@lists.infradead.org as an associated mailing list. Signed-off-by: Arınç ÜNAL --- MAINTAINERS | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8a851eb053ca..a75e6ffc0866 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16541,6 +16541,28 @@ F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml F: Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml F: drivers/pinctrl/mediatek/ +PIN CONTROLLER - MEDIATEK MIPS +M: Arınç ÜNAL +M: Sergio Paracuellos +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +L: linux-mips@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml +F: drivers/pinctrl/mediatek/pinctrl-mt7620.c +F: drivers/pinctrl/mediatek/pinctrl-mt7621.c +F: drivers/pinctrl/mediatek/pinctrl-mt76x8.c +F: drivers/pinctrl/mediatek/pinctrl-mtmips.* +F: drivers/pinctrl/mediatek/pinctrl-rt2880.c +F: drivers/pinctrl/mediatek/pinctrl-rt305x.c +F: drivers/pinctrl/mediatek/pinctrl-rt3883.c + PIN CONTROLLER - MICROCHIP AT91 M: Ludovic Desroches L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -17486,13 +17508,6 @@ L: linux-mips@vger.kernel.org S: Maintained F: arch/mips/boot/dts/ralink/mt7621* -RALINK PINCTRL DRIVER -M: Arınç ÜNAL -M: Sergio Paracuellos -L: linux-mips@vger.kernel.org -S: Maintained -F: drivers/pinctrl/ralink/ - RALINK RT2X00 WIRELESS LAN DRIVER M: Stanislaw Gruszka M: Helmut Schaa From patchwork Wed Feb 22 18:39:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0011EC61DA4 for ; Wed, 22 Feb 2023 18:48:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=QKlh4eFn7gD16YTKDFsTH6uF+XliFe7olcn/acaP1Lo=; b=GZLQmF5Tl2zpi0 X9YHT9xUeTmu4I3bcrYzYupUyoi//VPU/r6SL6f81yBHz39/X0xX7mMIP2hzK4hrY2KbGpVNi3mKY qkEwoC7rPHzmW5+PkHAucYaxSHfVHtf7FrCUWZSpEIBEfpIAx3vmwDb1jg+Zmw01a/BWyvx4o8oII Qmk1yyzVL+YUuQ1tepi4X4mI+X51P93p8uMrj7bjpio6lDOzvdNuT+Qma9m8iGRPQZ/NArT/n3HZL b7HR/+Dvfr0ESnTAiOIHMnFelsENVusoBmDMDnA2dG9FGp6/ArQAdszbBPEjkqg3sIO92uxiQLLXR VOAdgkH39aViQCLergQA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu9A-00DXgH-BT; Wed, 22 Feb 2023 18:47:20 +0000 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2d-00DTxA-NR; Wed, 22 Feb 2023 18:40:37 +0000 Received: by mail-wr1-x433.google.com with SMTP id p8so8880699wrt.12; Wed, 22 Feb 2023 10:40:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QKQy0Roxug4kkR5po0rLyjUzaL22dO97ot74i0woU9E=; b=nNOOQ7DgV8lPHE+nfWbX3cWwCtl/7owyKvNHmLHcylpRUFHwaxcssFOmWZDMPuzzVz zCEmDKpncYSFJaprUGjsxDzUbPyLDYX1HmiY7tq+p/MUYd74vyCyrPLOGO1SdpZoLskP iZYGKS1EHhwjlmv7DTd3j7lYR2vI/493G3StlNrJnIBipXtY2ECt4nw7ZBvIXg32aJyI 8LZBucpTIuuCVtFHfLE9uc5+Ak+hejscMtlw5IKhC7kgChN/mL5KyathBwmsqDCOWDi1 N1wPqpM40IUXVKmT/k1UTXP5gvOkz/8CwnrA0jquzzO713stT75SYkR9Osr8pdLzMjcw K2ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QKQy0Roxug4kkR5po0rLyjUzaL22dO97ot74i0woU9E=; b=zFDcdK2qyWzye49v/UnyyeUBQ7wrb3zvVXD0mOLkSnihHn2LH7hpRwMBO8XQTU+8ON TIrC/HBVmHs+Mg3IscP0CZoQP2Dtu1wMQvc3yUEPHDvDGEDW5m+rCOkG3g1Pi2z+Wx+c d/wYKc5uiCg+eRNsBba3mlti9fDWGkm8YJ9c9vbeCxZI7pXJSpXD24vO6e1Nn0YcjhA1 bVF6KTDgTpY6cVSV9BxorTFCo/QkxArhWlDnnwCcZWrmXRhDQqCptMjh8yGCgJmPZobS QrTv04u68h1LEBKmM0TVnAE/iK0tyvQH2trRLeYFtNDZ+58fQ2uxUOg3o7Oszzm+xTIy GVqA== X-Gm-Message-State: AO0yUKVSn+8klkd6epHIVQkH/icGoo37HV6eDOiliZeVUT/Lyg+M+sdb 8on6htM67IFn0iaEOfK/WBI= X-Google-Smtp-Source: AK7set88JNw8RxRWRdD2IFAfAkRWDGKxya6LpvIZWMWrlzdQGVzUwktZKapYh/fpkyfou4aD51W42A== X-Received: by 2002:a5d:6090:0:b0:2c5:9990:288e with SMTP id w16-20020a5d6090000000b002c59990288emr7671369wrt.18.1677091231890; Wed, 22 Feb 2023 10:40:31 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:31 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 12/16] dt-bindings: pinctrl: mediatek: mt6795: rename to mediatek,mt6795-pinctrl Date: Wed, 22 Feb 2023 21:39:28 +0300 Message-Id: <20230222183932.33267-13-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104035_791857_55A3CD13 X-CRM114-Status: GOOD ( 10.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Rename mediatek,pinctrl-mt6795.yaml to mediatek,mt6795-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- ...ediatek,pinctrl-mt6795.yaml => mediatek,mt6795-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{mediatek,pinctrl-mt6795.yaml => mediatek,mt6795-pinctrl.yaml} (98%) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml index 9399e0215526..c5131f053b61 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek MT6795 Pin Controller From patchwork Wed Feb 22 18:39:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5E66C61DA4 for ; Wed, 22 Feb 2023 18:47:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=U7My7F58+jdSKUV0xFeRihGmUjoInfvodzwuEvpVe/I=; b=bYNREsn3AS8/7P Xu6M1cPejP+9svQMZVRl3nnd//5lolrRFoj0+d6GWuPD1tSxNnyuyOqMVBRm9GFdBXguwvzGjfZeq eOhG1lgnebC40+TUS8TM15DdCZs3jER3qe/fEkYKdptzAWZY3cK0OCVjKjYVEpDV2TRswUN4Utu/M +wEgnog5JEs0l1Z8Rc69FpoAvvnb44KJYlUlr8DIL5tDXGL7yNZ03cZzjvxfQA5TBqmeXgDFvGs6o +HAPWtMWmCMRQhi4J8OuLZHpD7L2ch9OqCplzxDjUlyzmsGQCa61Wdcp0lNtyXUg4493bX5DfeWtQ xNYotGkHlQwG9IGfLd7g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu8K-00DXFt-OD; Wed, 22 Feb 2023 18:46:29 +0000 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2c-00DTel-MH; Wed, 22 Feb 2023 18:40:36 +0000 Received: by mail-wr1-x432.google.com with SMTP id bt28so2090402wrb.8; Wed, 22 Feb 2023 10:40:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UcArEGHX/fk4tdd7xlvhQYvzSJ8gqoZ4AEIyQIgQrNU=; b=AR3MjkftLOM10sT3eRRIRv3jttbYHUx5N7LjAquL7S+7THBL4C7hugZCKNdCHq/wZ2 fMkseRfTBsJTi/fV5prmF8t2TNDDRjJRtSK6FUZ/zo7FRf8ywkXtipOg3uBR9Y/Y47JR 3FNNzx+se451S5z4q9o28Hay2RgOaeXLWNO2WcU7KamknJkox2nIXg2AiB+DNOcCnVtm rTa7QuelafRefkSveHJ9LnD2M9GaKvwWoKTxfvaz+4Epkc0Scm6Y/WzAS5I3NE7ZKfBG VFmVo4TtB1rzZEySAoSCYvrUJlef+G+AAA5h/fyKvLEoqA9/r3rMnnEmwLbtHncv9yq9 isIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UcArEGHX/fk4tdd7xlvhQYvzSJ8gqoZ4AEIyQIgQrNU=; b=LASD3+82Xn9xfjlf+OrYuozw0e5JaxC2F1CxV16EK+W9zD1Z7kkreg71TvLe0ZTFx1 ztbD9YSQ+x04rGZCthz9Wx7BfGwgpCBL+SNHFaWQJlAR6hvIxHzFmuM/tcE85zM6Ulpq P7w1VnFrR1gmECULRajvhBZi0gRNX6LeHX4QfZ1gpwpwmAT34SYUOFLImNhbdr/D48ze QJ5eIgRmHcmFdqWR267g8k9sSgQIFDseSTvohdlaGSGGRQ3Uc7qZozrAhhdPGEbvMpfl MZgUO6zqyUIEU3h2+bnzFZWa8wAW99h7zHLLUbyAMA5Jhhsg822R5VV0ZOygSmhG+hE8 c5Ug== X-Gm-Message-State: AO0yUKVW9FgqdqjrAPphxgU70YkPfPkgHjFUUMnrMVZoiGx4omB50gov 3bfhRDSx28t33dA0ee7lF9k= X-Google-Smtp-Source: AK7set/PI5j55Nw4TKwVmwP/MNB3vBBcm1slvLkmfdv12lERhBSSRt/I8s1yrUOc05aaohWWABC82Q== X-Received: by 2002:a5d:4d4b:0:b0:2c5:5d15:4e25 with SMTP id a11-20020a5d4d4b000000b002c55d154e25mr8455403wru.16.1677091234179; Wed, 22 Feb 2023 10:40:34 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:33 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 13/16] dt-bindings: pinctrl: mediatek: mt8186: rename to mediatek,mt8186-pinctrl Date: Wed, 22 Feb 2023 21:39:29 +0300 Message-Id: <20230222183932.33267-14-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104034_791857_DB4CB579 X-CRM114-Status: GOOD ( 10.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Rename pinctrl-mt8186.yaml to mediatek,mt8186-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- .../{pinctrl-mt8186.yaml => mediatek,mt8186-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8186.yaml => mediatek,mt8186-pinctrl.yaml} (99%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml similarity index 99% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml index 26573a793b57..32d64416eb16 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek MT8186 Pin Controller From patchwork Wed Feb 22 18:39:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149497 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9608C636D6 for ; Wed, 22 Feb 2023 18:49:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=17tXmCbmyuoas+WssyR52qa5tBkwif63CsRnydlS8QM=; b=gNndynV9NvxzF6 rsfzekyHhoAi9wRBCUlGuoJ2Uucw4WNNCP8Hjpgxonz9tjIrYH7eRYMc4yMWy5viJrgWacrRei3xx HnvqNx8GZEzBn4BpHLuSinTgO0jHRaHpOEOPnCz6H1ku9K00gA4DF6nUmf7QrxD5gNXrNXC5vMrNV AG9r1CrxLDgCYziga+YIPB4l4OHWxFptRkhOesEVjXOEoDPJK9Q9/fMwBcBpF1pvLsTn/0LxldGSg JPj0KOwkzlWFW4t6L9kHn12vUK3pqnvyQeJ+dn3ylDYi/Ef0fxHC8tW7QoClQEfdu4Px4AyuUVLkz /U9ffX5KLpIjc/BQI5NQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu9t-00DY1O-TP; Wed, 22 Feb 2023 18:48:06 +0000 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2e-00DTk5-Pi; Wed, 22 Feb 2023 18:40:38 +0000 Received: by mail-wr1-x429.google.com with SMTP id l1so8477421wry.10; Wed, 22 Feb 2023 10:40:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4GQZ8qAd7vUgU+4b+W6RunOVqNL3/02QMSg5OECyOek=; b=gF5UguTKx+5wO9R3iI8jUuMqngJiy/plOyL8nDKrrZLjiNoG8lU4qTQrFco4KH74/J rqDNvM4M88vtto8ZkGxGpwrmBw8v+y9fLTrunl+jXRH97Je6IHZc+HmwjGhjSAn3xI/M gvq5oZ8uj5Se7L1o7z3nvW4gV5kxpT2wuHgfFdyFXkW5BN53mcHMLLxa7T+/PC13dXVB QL1M/0bm/Xt+1B9c1K8RO2XD3otMxlyWSsPTTF2yHKVd/WksCfexnaVf+oxq4F27rk7S Fjr7yPS15/vu0h8cXZKokU12XFSJBfOYx6p0LnPyHFQSytV4A6zjt9qp4/jVmUGzDmu7 R4gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4GQZ8qAd7vUgU+4b+W6RunOVqNL3/02QMSg5OECyOek=; b=mhS4RoNHQ6CN/vSWFD83ewX/cKBjskKc7xlGZV3K1HPK/0HtnH5SyleSoaR3tysZlS k+TEn/bkzoauwafE5Y9pgCzHj60XnPm5AyprJDftv0/UnNxM8kdu5OCsS/aPlthmZWWo gDazLVQUDYCLOKJ3v9LYXHRbbTN6syzhcprqdNUIkoGV+ha/QyiQhjIbs1uuFca4ZPpl +UUbRrkQ9EopBw7jhQqKLip3ferMv5KLF2t+mnfKdPoiQBCrCt9ePALjm7Yss82V+pam CrU4HgFv6SSP6sButwBnrVeA1Hf6xgjy0F6qtOoHXzP3s8qTMZo9se8G4fYbT5DMW5+l zoow== X-Gm-Message-State: AO0yUKU2Lc9PSDw1SdAG6PdLDDGZoKqkrBxdwGVTc0erq5Uuck4kkTVP 6AJUb/a3dtPCI2sjhJpsDIM= X-Google-Smtp-Source: AK7set/fFzM3NYHNQny0U269a5WUM4hhg0gF5WL2JKE+SiZW5s9bqU947q6Qe/lLwGBgPYWyFND8sQ== X-Received: by 2002:a05:6000:170a:b0:2c5:a38f:ca3a with SMTP id n10-20020a056000170a00b002c5a38fca3amr6617920wrc.10.1677091236355; Wed, 22 Feb 2023 10:40:36 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:36 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 14/16] dt-bindings: pinctrl: mediatek: mt8192: rename to mediatek,mt8192-pinctrl Date: Wed, 22 Feb 2023 21:39:30 +0300 Message-Id: <20230222183932.33267-15-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104036_886927_D40B81C9 X-CRM114-Status: GOOD ( 10.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Rename pinctrl-mt8192.yaml to mediatek,mt8192-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- .../{pinctrl-mt8192.yaml => mediatek,mt8192-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8192.yaml => mediatek,mt8192-pinctrl.yaml} (98%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml similarity index 98% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml index e0e943e5b874..e764cb0f8c1a 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek MT8192 Pin Controller From patchwork Wed Feb 22 18:39:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7FD25C636D6 for ; Wed, 22 Feb 2023 18:50:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cajFbH+H6N730u1e5CUy71r1G08eDQGGfEnaonfXU4s=; b=eXqBJoz8lqefwa oApUEYs+67fbE17DlMzdBf54bT8u3y1T7cDPtcAx89C8Ev6NLsqJgY0A27IvV5Dj6OxZjuc9qZ8br cwKHRbEW7nhwfxUdyylQk4TN+qQsk+4oY7g6apRwSLOWM0RElVte+m+UewftBIak1VelX5++k6ags /LLaUcqTspyYlaU/vu0/a25AWcQzFD1D9T3dQ1Jgi72FDyB7mt89ltaa4QdH6EkCN+WS1+WkuIhXh v6vG8dr+0PTwwnwRabTGhWkVukQ4iTCn3bNm2GAaevOp5C3jZ0C3bRi7A2GsT5EmLFSLROwK+JwFP Y+pDSaxf44Ep5e0wTtIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUuAl-00DYRu-EC; Wed, 22 Feb 2023 18:49:00 +0000 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2h-00DTvd-5g; Wed, 22 Feb 2023 18:40:40 +0000 Received: by mail-wr1-x432.google.com with SMTP id v3so8678774wrp.2; Wed, 22 Feb 2023 10:40:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PeXXWoYtcN7Md4fHV+U+ymSCKklKj3szjzv05DFaWBc=; b=CSWzu0RDifPIC5mVxgRnFfoFU8+34A0WTuQKE35mzW/6ggRyLHF3l6iM1+kgmTXwCu oCZS7EVL3DR/F5WVbsc5h/HkBDQ4ldhlfPPAq6fD45M6m5tbIGX4H0M3vtHvYoT/CSen sz4kd819EHvEaKI3aslUVvNWnqUDABjbGwIc0Hsge/5GBEmvdHvRAjJIhDHCb3JcqZnz E3t9NlAKw0VbYlt2CSdN0SCF5PvZ5MCDMn7q2slkvbNTQBExh/qsagyjOCYNzkBP8DbU nD1sWl3EL3jCc2o3CqrjKreER41SXYBR/X4ywF1wHtcfB4qb7TcoBLpgjqiz+CcAH7J8 YICQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PeXXWoYtcN7Md4fHV+U+ymSCKklKj3szjzv05DFaWBc=; b=O/BsUJ/wPqyT56yoPC+dODyohXyJJMSIGBPEIhKJwMf3da9VeU/BPunuu1F4B3lONg sKtWsnXZmaCY+sB/HdXSPZMdShBa3xWDfDz3lZ6q6+IwCwZztHLJMoHTxCve9uFw5WC4 1eArLLC5B8JxSTIJ4AmBRiuV9d+EaJczCplTvPYG4vg2dUthoCFRBgtZ/sVUz4SQ9JH2 WKKqa9ULgM7QDFEQynsKZ6aHYGQioIhxE9Ifdqoe3nrCu/cvYaiMFx7/FgTk3tumwOhV lwpq5u5Vd1TUgbZ1/utr2fpiNNvgDZvgGd6qmffWSOMYo5GViSffTIbECt89M6G5RfMz 0ajQ== X-Gm-Message-State: AO0yUKWwL4+Hp/hv8pC0z46m4u9wscFFICwLhCmLv5UEaSk7ZJYgRZ3V UTpEpsrzb0BkENcTjE/n3cM= X-Google-Smtp-Source: AK7set8Uz83OUsrFm9m3xtosfJbhI2niwL6prvque1JZYsakJ64OCWj+zmdlRdhG4BeR7sPUaUU1tg== X-Received: by 2002:a5d:5486:0:b0:2c6:1482:33fa with SMTP id h6-20020a5d5486000000b002c6148233famr6770139wrv.59.1677091238565; Wed, 22 Feb 2023 10:40:38 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:38 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 15/16] dt-bindings: pinctrl: mediatek: mt8195: rename to mediatek,mt8195-pinctrl Date: Wed, 22 Feb 2023 21:39:31 +0300 Message-Id: <20230222183932.33267-16-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104039_251664_9866A6E5 X-CRM114-Status: GOOD ( 10.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Rename pinctrl-mt8195.yaml to mediatek,mt8195-pinctrl.yaml to be on par with the compatible string and other mediatek dt-binding schemas. Signed-off-by: Arınç ÜNAL Acked-by: Rob Herring --- .../{pinctrl-mt8195.yaml => mediatek,mt8195-pinctrl.yaml} | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) rename Documentation/devicetree/bindings/pinctrl/{pinctrl-mt8195.yaml => mediatek,mt8195-pinctrl.yaml} (99%) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml similarity index 99% rename from Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml rename to Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml index 66fe17e9e4d3..7b3dfc14eedc 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml# +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek MT8195 Pin Controller From patchwork Wed Feb 22 18:39:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13149499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6FD5EC61DA4 for ; Wed, 22 Feb 2023 18:51:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jKTuc9B1PYtwcvvgdazxUWnJulMICbS0JqI4Sx6PjHA=; b=NUpLjct+efUKaE Z8rnydnfs4g8JnpvzKlFvGLeR0riygbl/Wrel6zNntPklAQ/TMRZP6B2iCUI27EdYSp9e/SckNX++ wGUGcp3FmwNBsxQVhccnt4jj0N/er0W4khdDLMkbXt8hsHCm23mlXw7PXcUFYOOYnNB6ZRzJ2T9N5 0i/DGn/zG4+hEbxWYvMtDBhw9FdGDGcoTIyNndO8YuRdybi7CIhMxAoa2tMFEXUguVagsPYt4LOKq KOFPCaXiut9hduG9pOkI6TSuASCHY6k0+SvHO+LbyGT2LSasYkKB3jWMleaE22fLZDqdLKPmUwjFW vsiFyyzbgVFobFK3kOrw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUuBr-00DYzB-By; Wed, 22 Feb 2023 18:50:09 +0000 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pUu2k-00DTj2-3a; Wed, 22 Feb 2023 18:40:48 +0000 Received: by mail-wr1-x432.google.com with SMTP id i11so2586829wrp.5; Wed, 22 Feb 2023 10:40:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JGSNKz0q0gsC5HLgSbrlpiQsXVswleKhPPANT6X3ZpI=; b=GYafZWwDleHBnO/XlsX3CZ/87Pf2sxrXHGv2JBHFJGTRi8Ixhpk48QnV+XQomsohF0 XDEZlJPvVH696bvNEENlheCJ3Q4r0OXlLdTzl4Eu+7yL2gK07lKLFFHI11IXY156SXAK 5MWPBI9C5zJtNnkw917bVtQavhldG/kIlDvzD0UpO1GGzkwxYpll4MV1QznCs9p66oKN In5i/CTJVS3wYms2I3Sy64sOd9TZA5it7XCiwD2YITSM3Fpz8XH/gTJmS1MLKjOxonyh AnBRPnTKxGCNi6mrDd0KkFlK/pIsSX3y6YrXex69P6Z8iIK9S6rAN60s/Jz0hEF5Xptd WqNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JGSNKz0q0gsC5HLgSbrlpiQsXVswleKhPPANT6X3ZpI=; b=ceWASq6i0WLwO2NcE2ibkLs906quzRF1w1quR7WWN07geuPNy/FNGmUYnWgBmIbMbv j7HGOwbLg4M/azuBLY8vHJeLNrBx5fMHH9EdFRWUv6vnRms78/viRpXvbNY3eGvQU/4K vFon1SlDTEW/yfOt5GE2S88v8wdQReGSUVOzCHhoVYncOYO4ORzLfqlAsaU2PTSSE3m6 byqhpTj2tBFA49pU03uGuJImQjeojS/Y0MnHN5sjw/OfbCwiPp1h+6fFo78d79U/Q/J2 0QaDh0Oy7FCs0mwAHROvdHWNuQX4J8qwwFtBdZGbUilcbEOInbVCbRlrd5RhRGR0zzce rg3Q== X-Gm-Message-State: AO0yUKUliwbYk8AUL4dps8VExgyMQnZwfoVYAAubZpmqNrr4l48oBbc5 vz3DDC8FskQpMjm7OV+0uVA= X-Google-Smtp-Source: AK7set9XZ6fejEokWr/EtWMPZHKgIkMVbfEKSDaxuwCBb7P6IStu3GLCN2B9q0DPRJkFROsTrHVOKQ== X-Received: by 2002:adf:dfd0:0:b0:2c5:54a7:3646 with SMTP id q16-20020adfdfd0000000b002c554a73646mr7460724wrn.5.1677091240944; Wed, 22 Feb 2023 10:40:40 -0800 (PST) Received: from arinc9-PC.lan ([37.120.152.236]) by smtp.gmail.com with ESMTPSA id l18-20020a5d4112000000b002c56179d39esm9372845wrp.44.2023.02.22.10.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 10:40:40 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sergio Paracuellos , Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Matthias Brugger , Sean Wang , William Dean , Daniel Golle , Daniel Santos , Luiz Angelo Daros de Luca , Frank Wunderlich , Landen Chao , DENG Qingfang , Sean Wang , erkin.bozoglu@xeront.com Subject: [RFC PATCH 16/16] dt-bindings: pinctrl: mediatek: improve schemas Date: Wed, 22 Feb 2023 21:39:32 +0300 Message-Id: <20230222183932.33267-17-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230222183932.33267-1-arinc.unal@arinc9.com> References: <20230222183932.33267-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230222_104042_469710_D587D3B4 X-CRM114-Status: GOOD ( 18.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Some schemas include "MediaTek", some "Mediatek". Rename all to "MediaTek" to address the naming inconsistency. Change the style of description properties to plain style where there's no need to preserve the line endings, and vice versa. Fit the schemas to 80 columns for each line. Set patternProperties to '^.*mux.*$' on mediatek,mt7986-pinctrl.yaml. Signed-off-by: Arınç ÜNAL --- .../pinctrl/mediatek,mt65xx-pinctrl.yaml | 24 +++--- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 33 +++++---- .../pinctrl/mediatek,mt6795-pinctrl.yaml | 33 +++++---- .../pinctrl/mediatek,mt7620-pinctrl.yaml | 2 +- .../pinctrl/mediatek,mt7621-pinctrl.yaml | 2 +- .../pinctrl/mediatek,mt7622-pinctrl.yaml | 26 +++---- .../pinctrl/mediatek,mt76x8-pinctrl.yaml | 2 +- .../pinctrl/mediatek,mt7981-pinctrl.yaml | 35 +++++---- .../pinctrl/mediatek,mt7986-pinctrl.yaml | 64 ++++++++-------- .../pinctrl/mediatek,mt8183-pinctrl.yaml | 26 ++++--- .../pinctrl/mediatek,mt8186-pinctrl.yaml | 47 ++++++------ .../pinctrl/mediatek,mt8188-pinctrl.yaml | 74 ++++++++++--------- .../pinctrl/mediatek,mt8192-pinctrl.yaml | 47 ++++++------ .../pinctrl/mediatek,mt8195-pinctrl.yaml | 38 +++++----- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 28 +++---- .../pinctrl/mediatek,rt2880-pinctrl.yaml | 2 +- .../pinctrl/mediatek,rt305x-pinctrl.yaml | 2 +- .../pinctrl/mediatek,rt3352-pinctrl.yaml | 2 +- .../pinctrl/mediatek,rt3883-pinctrl.yaml | 2 +- .../pinctrl/mediatek,rt5350-pinctrl.yaml | 2 +- 20 files changed, 256 insertions(+), 235 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index a55c8e4ff26e..206fa8ba9502 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT65xx Pin Controller +title: MediaTek MT65xx Pin Controller maintainers: - Sean Wang -description: |+ - The Mediatek's Pin controller is used to control SoC pins. +description: + The MediaTek's Pin controller is used to control SoC pins. properties: compatible: @@ -30,7 +30,7 @@ properties: pins-are-numbered: $ref: /schemas/types.yaml#/definitions/flag - description: | + description: Specify the subnodes are using numbered pinmux to specify pins. (UNUSED) deprecated: true @@ -38,10 +38,10 @@ properties: "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. mediatek,pctl-regmap: $ref: /schemas/types.yaml#/definitions/phandle-array @@ -49,7 +49,7 @@ properties: maxItems: 1 minItems: 1 maxItems: 2 - description: | + description: Should be phandles of the syscfg node. interrupt-controller: true @@ -77,7 +77,7 @@ patternProperties: '(^pins|pins?$)': type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer @@ -95,7 +95,7 @@ patternProperties: bias-disable: true bias-pull-up: - description: | + description: Besides generic pinconfig options, it can be used as the pull up settings for 2 pull resistors, R0 and R1. User can configure those special pins. Some macros have been defined for this usage, such @@ -117,7 +117,7 @@ patternProperties: input-schmitt-disable: true drive-strength: - description: | + description: Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index a2141eb0854e..17046d204087 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -4,15 +4,15 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT6779 Pin Controller +title: MediaTek MT6779 Pin Controller maintainers: - Andy Teng - Sean Wang description: - The MediaTek pin controller on MT6779 is used to control pin - functions, pull up/down resistance and drive strength options. + The MediaTek pin controller on MT6779 is used to control pin functions, pull + up/down resistance and drive strength options. properties: compatible: @@ -29,22 +29,22 @@ properties: "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. interrupt-controller: true interrupts: maxItems: 1 - description: | + description: Specifies the summary IRQ. "#interrupt-cells": @@ -118,19 +118,20 @@ patternProperties: patternProperties: '-pins*$': type: object - description: | + description: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. $ref: "/schemas/pinctrl/pincfg-node.yaml" properties: pinmux: description: integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are defined - as macros in boot/dts/-pinfunc.h directly. + Supported pin number and mux varies for different SoCs, and are + defined as macros in boot/dts/-pinfunc.h directly. bias-disable: true @@ -159,7 +160,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -170,7 +172,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml index c5131f053b61..5bd78e88fea3 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT6795 Pin Controller +title: MediaTek MT6795 Pin Controller maintainers: - AngeloGioacchino Del Regno - Sean Wang -description: | - The Mediatek's Pin controller is used to control SoC pins. +description: + The MediaTek's MT6795 Pin controller is used to control SoC pins. properties: compatible: @@ -22,8 +22,8 @@ properties: '#gpio-cells': description: | Number of cells in GPIO specifier. Since the generic GPIO binding is used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. const: 2 gpio-ranges: @@ -65,8 +65,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -86,11 +86,10 @@ patternProperties: properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] @@ -100,7 +99,7 @@ patternProperties: - type: boolean - enum: [100, 101, 102, 103] description: mt6795 pull down PUPD/R0/R1 type define value. - description: | + description: For normal pull down type, it is not necessary to specify R1R0 values; When pull down type is PUPD/R0/R1, adding R1R0 defines will set different resistance values. @@ -110,10 +109,10 @@ patternProperties: - type: boolean - enum: [100, 101, 102, 103] description: mt6795 pull up PUPD/R0/R1 type define value. - description: | + description: For normal pull up type, it is not necessary to specify R1R0 - values; When pull up type is PUPD/R0/R1, adding R1R0 defines - will set different resistance values. + values; When pull up type is PUPD/R0/R1, adding R1R0 defines will + set different resistance values. bias-disable: true @@ -132,7 +131,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -143,7 +143,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml index ea4a1194fbc4..2a5495a3a717 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | MediaTek MT7620 pin controller for MT7620 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml index 4dfe3da5fd40..1fc227c27bd0 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | MediaTek MT7621 pin controller for MT7621 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index ac93eb8f01a6..740a26e1ede1 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -4,12 +4,12 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT7622 Pin Controller +title: MediaTek MT7622 Pin Controller maintainers: - Sean Wang -description: |+ +description: The MediaTek's MT7622 Pin controller is used to control SoC pins. properties: @@ -29,10 +29,10 @@ properties: "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. interrupt-controller: true @@ -68,18 +68,18 @@ patternProperties: '^mux(-|$)': type: object additionalProperties: false - description: | + description: pinmux configuration nodes. $ref: "/schemas/pinctrl/pinmux-node.yaml" properties: function: - description: | + description: A string containing the name of the function to mux to the group. enum: [emmc, eth, i2c, i2s, ir, led, flash, pcie, pmic, pwm, sd, spi, tdm, uart, watchdog, wifi] groups: - description: | + description: An array of strings. Each string contains the name of a group. drive-strength: @@ -247,7 +247,7 @@ patternProperties: '^conf(-|$)': type: object additionalProperties: false - description: | + description: pinconf configuration nodes. $ref: "/schemas/pinctrl/pincfg-node.yaml" @@ -258,7 +258,7 @@ patternProperties: Valid values are the same as the pinmux node. pins: - description: | + description: An array of strings. Each string contains the name of a pin. enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, TXD0, RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS, @@ -315,14 +315,14 @@ patternProperties: enum: [0, 1] mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml index c818c8947866..48d563886e57 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | MediaTek MT76X8 pin controller for MT7628 and MT7688 SoCs. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml index 74c66fbcb2ae..10717cee9058 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT7981 Pin Controller +title: MediaTek MT7981 Pin Controller maintainers: - Daniel Golle @@ -37,7 +37,7 @@ properties: "#gpio-cells": const: 2 - description: > + description: Number of cells in GPIO specifier. Since the generic GPIO binding is used, the amount of cells must be specified as 2. See the below mentioned gpio binding representation for description of particular cells. @@ -111,7 +111,9 @@ patternProperties: "watchdog1" "watchdog" 13 "udi" "udi" 9, 10, 11, 12, 13 "drv_vbus" "usb" 14 - "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 + "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25 + "snfi" "flash" 16, 17, 18, 19, 20, 21 "spi0" "spi" 16, 17, 18, 19 "spi0_wp_hold" "spi" 20, 21 @@ -148,7 +150,7 @@ patternProperties: "wf5g_led0" "led" 31 "wf5g_led1" "led" 35 "mt7531_int" "eth" 38 - "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22 + "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 $ref: /schemas/pinctrl/pinmux-node.yaml @@ -256,7 +258,8 @@ patternProperties: then: properties: groups: - enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0, wf5g_led1] + enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0, + wf5g_led1] - if: properties: function: @@ -275,7 +278,8 @@ patternProperties: properties: groups: items: - enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, spi2_wp_hold] + enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, + spi2_wp_hold] maxItems: 4 - if: properties: @@ -332,13 +336,14 @@ patternProperties: JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTRST_N, WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTCLK, WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI, - SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, - SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, - SPI2_HOLD, SPI2_WP, UART0_RXD, UART0_TXD, PCIE_CLK_REQ, - PCIE_WAKE_N, SMI_MDC, SMI_MDIO, GBE_INT, GBE_RESET, - WF_DIG_RESETB, WF_CBA_RESETB, WF_XO_REQ, WF_TOP_CLK, - WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, WF_HB4, WF_HB0, - WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, WF_HB9, WF_HB10] + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, + SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, + UART0_TXD, PCIE_CLK_REQ, PCIE_WAKE_N, SMI_MDC, SMI_MDIO, + GBE_INT, GBE_RESET, WF_DIG_RESETB, WF_CBA_RESETB, + WF_XO_REQ, WF_TOP_CLK, WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, + WF_HB4, WF_HB0, WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, + WF_HB9, WF_HB10] maxItems: 57 bias-disable: true @@ -348,7 +353,7 @@ patternProperties: - type: boolean description: normal pull up. - enum: [100, 101, 102, 103] - description: > + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in dt-bindings/pinctrl/mt65xx.h. @@ -357,7 +362,7 @@ patternProperties: - type: boolean description: normal pull down. - enum: [100, 101, 102, 103] - description: > + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in dt-bindings/pinctrl/mt65xx.h. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml index 216b356cd519..f5e982375b44 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -4,12 +4,12 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT7986 Pin Controller +title: MediaTek MT7986 Pin Controller maintainers: - Sean Wang -description: |+ +description: The MediaTek's MT7986 Pin controller is used to control SoC pins. properties: @@ -37,15 +37,15 @@ properties: "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. interrupt-controller: true @@ -72,7 +72,7 @@ patternProperties: additionalProperties: false patternProperties: - '.*mux.*': + '^.*mux.*$': type: object additionalProperties: false description: | @@ -81,7 +81,7 @@ patternProperties: The following table shows the effective values of "group", "function" properties and chip pinout pins - groups function pins (in pin#) + groups function pins (in pin#) --------------------------------------------------------------------- "watchdog" "watchdog" 0 "wifi_led" "led" 1, 2 @@ -97,8 +97,9 @@ patternProperties: "pwm1_0" "pwm" 22, "snfi" "flash" 23, 24, 25, 26, 27, 28 "spi1_2" "spi" 29, 30, 31, 32 - "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, - 31, 32 + "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 32 + "spi1_1" "spi" 23, 24, 25, 26 "uart1_2_rx_tx" "uart" 29, 30 "uart1_2_cts_rts" "uart" 31, 32 @@ -115,8 +116,9 @@ patternProperties: "pcie_pereset" "pcie" 41 "uart1" "uart" 42, 43, 44, 45 "uart2" "uart" 46, 47, 48, 49 - "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 57, - 59, 60, 61 + "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, + 60, 61 + "pcm" "audio" 62, 63, 64, 65 "i2s" "audio" 62, 63, 64, 65 "switch_int" "eth" 66 @@ -129,18 +131,17 @@ patternProperties: $ref: "/schemas/pinctrl/pinmux-node.yaml" properties: function: - description: | + description: A string containing the name of the function to mux to the group. There is no "audio", "pcie" functions on mt7986b, you can only use those functions on mt7986a. enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart, watchdog, wifi] groups: - description: | + description: An array of strings. Each string contains the name of a group. - There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", - and "i2s" groups on mt7986b, you can only use those groups on - mt7986a. + There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", and + "i2s" groups on mt7986b, you can only use those groups on mt7986a. required: - function - groups @@ -258,7 +259,7 @@ patternProperties: '.*conf.*': type: object additionalProperties: false - description: | + description: pinconf configuration nodes. $ref: "/schemas/pinctrl/pincfg-node.yaml" @@ -271,16 +272,17 @@ patternProperties: items: enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7, - GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14, - GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, SPI0_MISO, SPI0_CS, - SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, SPI1_CS, - SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, - UART0_RXD, UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, - UART1_CTS, UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, - UART2_RTS, EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, - EMMC_DATA_3, EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, - EMMC_DATA_7, EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, - PCM_DRX, PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO, + GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, + GPIO_14, GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, + SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, + UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, UART1_CTS, + UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, + EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, EMMC_DATA_3, + EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, EMMC_DATA_7, + EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, PCM_DRX, + PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO, WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK, WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0, WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9, @@ -297,7 +299,7 @@ patternProperties: - type: boolean description: normal pull up. - enum: [100, 101, 102, 103] - description: | + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in dt-bindings/pinctrl/mt65xx.h. @@ -306,7 +308,7 @@ patternProperties: - type: boolean description: normal pull down. - enum: [100, 101, 102, 103] - description: | + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in dt-bindings/pinctrl/mt65xx.h. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index c30cd0d010dd..3b1be7949e8c 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -4,12 +4,12 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT8183 Pin Controller +title: MediaTek MT8183 Pin Controller maintainers: - Sean Wang -description: |+ +description: The MediaTek's MT8183 Pin controller is used to control SoC pins. properties: @@ -37,15 +37,15 @@ properties: "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. gpio-ranges: minItems: 1 maxItems: 5 - description: | + description: GPIO valid number range. interrupt-controller: true @@ -74,7 +74,7 @@ patternProperties: '^pins': type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer @@ -139,7 +139,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -150,7 +151,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -159,14 +161,14 @@ patternProperties: enum: [0, 1, 2, 3] mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml index 32d64416eb16..c7abc13a167d 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT8186 Pin Controller +title: MediaTek MT8186 Pin Controller maintainers: - Sean Wang -description: | - The Mediatek's Pin controller is used to control SoC pins. +description: + The MediaTek's MT8186 Pin controller is used to control SoC pins. properties: compatible: @@ -19,10 +19,10 @@ properties: gpio-controller: true '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. const: 2 gpio-ranges: @@ -31,13 +31,13 @@ properties: gpio-line-names: true reg: - description: | + description: Physical address base for gpio base registers. There are 8 different GPIO physical address base in mt8186. maxItems: 8 reg-names: - description: | + description: Gpio base register names. items: - const: iocfg0 @@ -60,9 +60,9 @@ properties: mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - Identifying i2c pins pull up/down type which is RSEL. It can support - RSEL define or si unit value(ohm) to set different resistance. + description: + Identifying i2c pins pull up/down type which is RSEL. It can support RSEL + define or si unit value(ohm) to set different resistance. # PIN CONFIGURATION NODES patternProperties: @@ -77,8 +77,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -98,11 +98,10 @@ patternProperties: properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] @@ -129,10 +128,10 @@ patternProperties: For pull down type is RSEL, it can add RSEL define & resistance value(ohm) to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" - define in mt8186. It can also support resistance value(ohm) - "75000" & "5000" in mt8186. + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" define in + mt8186. It can also support resistance value(ohm) "75000" & "5000" + in mt8186. An example of using RSEL define: pincontroller { i2c0_pin { @@ -174,10 +173,10 @@ patternProperties: For pull up type is RSEL, it can add RSEL define & resistance value(ohm) to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" - define in mt8186. It can also support resistance value(ohm) - "1000" & "5000" & "10000" & "75000" in mt8186. + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" define in + mt8186. It can also support resistance value(ohm) "1000" & "5000" + & "10000" & "75000" in mt8186. An example of using si unit resistance value(ohm): &pio { mediatek,rsel-resistance-in-si-unit; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml index 7e750f1e643d..51b3d1247614 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -9,7 +9,7 @@ title: MediaTek MT8188 Pin Controller maintainers: - Hui Liu -description: | +description: The MediaTek's MT8188 Pin controller is used to control SoC pins. properties: @@ -19,10 +19,10 @@ properties: gpio-controller: true '#gpio-cells': - description: | - Number of cells in GPIO specifier, should be two. The first cell - is the pin number, the second cell is used to specify optional - parameters which are defined in . + description: + Number of cells in GPIO specifier, should be two. The first cell is the + pin number, the second cell is used to specify optional parameters which + are defined in . const: 2 gpio-ranges: @@ -59,10 +59,11 @@ properties: mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - We provide two methods to select the resistance for I2C when pull up or pull down. - The first is by RSEL definition value, another one is by resistance value(ohm). - This flag is used to identify if the method is resistance(si unit) value. + description: + We provide two methods to select the resistance for I2C when pull up or + pull down. The first is by RSEL definition value, another one is by + resistance value(ohm). This flag is used to identify if the method is + resistance(si unit) value. # PIN CONFIGURATION NODES patternProperties: @@ -75,16 +76,16 @@ patternProperties: type: object $ref: "/schemas/pinctrl/pincfg-node.yaml" additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnode representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are defined as macros in dt-bindings/pinctrl/mediatek,-pinfunc.h @@ -106,18 +107,21 @@ patternProperties: - enum: [75000, 5000] description: mt8188 pull down RSEL type si unit value(ohm). description: | - For pull down type is normal, it doesn't need add RSEL & R1R0 define - and resistance value. + For pull down type is normal, it doesn't need add RSEL & R1R0 + define and resistance value. For pull down type is PUPD/R0/R1 type, it can add R1R0 define to set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & - "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" - define in mt8188. - For pull down type is RSEL, it can add RSEL define & resistance value(ohm) - to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" - & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" - define in mt8188. It can also support resistance value(ohm) "75000" & "5000" in mt8188. + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8188. + For pull down type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8188. It can also support resistance value(ohm) "75000" & "5000" + in mt8188. bias-pull-up: oneOf: @@ -131,17 +135,19 @@ patternProperties: description: | For pull up type is normal, it don't need add RSEL & R1R0 define and resistance value. - For pull up type is PUPD/R0/R1 type, it can add R1R0 define to - set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & - "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11" - define in mt8188. - For pull up type is RSEL, it can add RSEL define & resistance value(ohm) - to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit". - It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" - & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" - & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" - define in mt8188. It can also support resistance value(ohm) - "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8188. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to set + different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8188. + For pull up type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8188. It can also support resistance value(ohm) "1000" & "1500" + & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8188. bias-disable: true diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml index e764cb0f8c1a..88a466769938 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT8192 Pin Controller +title: MediaTek MT8192 Pin Controller maintainers: - Sean Wang -description: | - The Mediatek's Pin controller is used to control SoC pins. +description: + The MediaTek's MT8192 Pin controller is used to control SoC pins. properties: compatible: @@ -19,10 +19,10 @@ properties: gpio-controller: true '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. const: 2 gpio-ranges: @@ -32,13 +32,13 @@ properties: gpio-line-names: true reg: - description: | - Physical address base for gpio base registers. There are 11 GPIO - physical address base in mt8192. + description: + Physical address base for gpio base registers. There are 11 GPIO physical + address base in mt8192. maxItems: 11 reg-names: - description: | + description: Gpio base register names. maxItems: 11 @@ -59,25 +59,26 @@ patternProperties: patternProperties: '^pins': type: object - description: | + description: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. $ref: "pinmux-node.yaml" properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are defined - as macros in dt-bindings/pinctrl/-pinfunc.h directly. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. drive-strength: - description: | - It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See - dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. + description: + It can support some arguments, such as MTK_DRIVE_4mA, + MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. It can only + support 2/4/6/8/10/12/14/16mA in mt8192. enum: [2, 4, 6, 8, 10, 12, 14, 16] drive-strength-microamp: @@ -91,8 +92,8 @@ patternProperties: description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_ defines in dt-bindings/pinctrl/mt65xx.h. - enum: [200, 201, 202, 203] - description: RSEL pull down type. See MTK_PULL_SET_RSEL_ - defines in dt-bindings/pinctrl/mt65xx.h. + description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. bias-pull-up: oneOf: @@ -102,8 +103,8 @@ patternProperties: description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_ defines in dt-bindings/pinctrl/mt65xx.h. - enum: [200, 201, 202, 203] - description: RSEL pull up type. See MTK_PULL_SET_RSEL_ - defines in dt-bindings/pinctrl/mt65xx.h. + description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. bias-disable: true diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml index 7b3dfc14eedc..c1c8c99ba139 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT8195 Pin Controller +title: MediaTek MT8195 Pin Controller maintainers: - Sean Wang -description: | - The Mediatek's Pin controller is used to control SoC pins. +description: + The MediaTek's MT8195 Pin controller is used to control SoC pins. properties: compatible: @@ -19,10 +19,10 @@ properties: gpio-controller: true '#gpio-cells': - description: | + description: Number of cells in GPIO specifier. Since the generic GPIO binding is used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. const: 2 gpio-ranges: @@ -32,13 +32,13 @@ properties: gpio-line-names: true reg: - description: | - Physical address base for gpio base registers. There are 8 GPIO - physical address base in mt8195. + description: + Physical address base for gpio base registers. There are 8 GPIO physical + address base in mt8195. maxItems: 8 reg-names: - description: | + description: Gpio base register names. maxItems: 8 @@ -53,9 +53,9 @@ properties: mediatek,rsel-resistance-in-si-unit: type: boolean - description: | - Identifying i2c pins pull up/down type which is RSEL. It can support - RSEL define or si unit value(ohm) to set different resistance. + description: + Identifying i2c pins pull up/down type which is RSEL. It can support RSEL + define or si unit value(ohm) to set different resistance. # PIN CONFIGURATION NODES patternProperties: @@ -70,8 +70,8 @@ patternProperties: A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. + configuration, pullups, drive strength, input enable/disable and input + schmitt. An example of using macro: pincontroller { /* GPIO0 set as multifunction GPIO0 */ @@ -91,7 +91,7 @@ patternProperties: properties: pinmux: - description: | + description: Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are defined as macros in dt-bindings/pinctrl/-pinfunc.h @@ -174,9 +174,9 @@ patternProperties: & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" - define in mt8195. It can also support resistance value(ohm) - "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & - "75000" in mt8195. + define in mt8195. It can also support resistance value(ohm) "1000" + & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" + in mt8195. An example of using RSEL define: pincontroller { i2c0-pins { diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml index 4b96884a1afc..1cd9d6e55866 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek MT8365 Pin Controller +title: MediaTek MT8365 Pin Controller maintainers: - Zhiyong Tao - Bernhard Rosenkränzer -description: | +description: The MediaTek's MT8365 Pin controller is used to control SoC pins. properties: @@ -26,17 +26,17 @@ properties: maxItems: 1 minItems: 1 maxItems: 2 - description: | + description: Should be phandles of the syscfg node. gpio-controller: true "#gpio-cells": const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. interrupt-controller: true @@ -54,7 +54,7 @@ patternProperties: "pins$": type: object additionalProperties: false - description: | + description: A pinctrl node should contain at least one subnode representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer @@ -72,7 +72,7 @@ patternProperties: bias-disable: true bias-pull-up: - description: | + description: Besides generic pinconfig options, it can be used as the pull up settings for 2 pull resistors, R0 and R1. User can configure those special pins. @@ -120,7 +120,8 @@ patternProperties: mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -131,7 +132,8 @@ patternProperties: mediatek,pull-down-adv: description: | Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: + configure those special pins. Valid arguments are described as + below: 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. @@ -140,14 +142,14 @@ patternProperties: enum: [0, 1, 2, 3] mediatek,tdsel: - description: | + description: An integer describing the steps for output level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 15. $ref: /schemas/types.yaml#/definitions/uint32 mediatek,rdsel: - description: | + description: An integer describing the steps for input level shifter duty cycle when asserted (high pulse width adjustment). Valid arguments are from 0 to 63. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml index 7395e4434e64..fa03560a13f8 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt2880-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | MediaTek RT2880 pin controller for RT2880 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml index 1e6c7e7f2fe2..11b46aee36d4 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt305x-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | MediaTek RT305X pin controller for RT3050, RT3052, and RT3350 SoCs. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml index 7a74c1602afc..c88b9fefb9ef 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3352-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | MediaTek RT3352 pin controller for RT3352 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml index ab20f67c47f0..bafc2b820dd8 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt3883-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | MediaTek RT3883 pin controller for RT3883 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml index 5184cea62640..070a9d59e639 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,rt5350-pinctrl.yaml @@ -10,7 +10,7 @@ maintainers: - Arınç ÜNAL - Sergio Paracuellos -description: +description: | MediaTek RT5350 pin controller for RT5350 SoC. The pin controller can only set the muxing of pin groups. Muxing individual pins is not supported. There is no pinconf support.