From patchwork Fri Feb 24 17:01:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A677DC7EE23 for ; Fri, 24 Feb 2023 17:01:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229942AbjBXRBj (ORCPT ); Fri, 24 Feb 2023 12:01:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229700AbjBXRBh (ORCPT ); Fri, 24 Feb 2023 12:01:37 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E2D86B16B for ; Fri, 24 Feb 2023 09:01:36 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id m3-20020a17090ade0300b00229eec90a7fso6897859pjv.0 for ; Fri, 24 Feb 2023 09:01:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=vZvIhYFmeKjhMfSClOcNvYFcw+7eVoiwutwql0vi/jk=; b=ZeNg+0N8YaWAFggGX5OHDLm4z7gM8lBbNQqDT+/4n7T2dBGC6mrVfc66/MOw9KdHtw WTEL4n9NgznWy+PyzdWpsV+ZjchPt6HC+pJPzJOjVb/v3JzSKUE1SZvhOFdnX/yYpwEv CGlzMk/GRJF3q1ePaAifGhFZjra5Mj5w8Riow0xB1E5gzgIUk+XD6RxJ26pTQnhfgMGr 2r8UiPdyuB9LYPqB/PsJJ4T0shfI5eOAuL9kZslksj28fTWziVfyFLcrdHD1w9Sd5dAV Q/EdnOxx8QEERVmqrr4JWlCLwzbw86dDzff2voTFkdWcHIdoAiZ4RlVw924LIkQb+UEb 3RIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=vZvIhYFmeKjhMfSClOcNvYFcw+7eVoiwutwql0vi/jk=; b=kP6CXV33U2opPcmm8A/Qse/0BSFAXeYcXBHA+MoDr/UbhsTJllSMh9IK3kngaYLL8L NMFU52qJPui2NLb5ZzGsMQh4HsIrjfxGLpBAsv2JGOWH1uoc/gr9NnrxkHvgPhKmVT+V TMo2PBrWij84f1SZQGiS34I8u45VC4xdzGaASpXXP/4uvaWT9RfFPonkU6tQlwHp2Q58 3i/FlHAC9JeI81HQXgD+kwRT1vN40RaxhWr8Wxe0omtTcv2INpkV3E/J8aRmiVcPCUqe usQFstwqFdirNSwAPOT2ZLT7SE+9hsq/tGvjm3hkbubkUHlQqON4bss0butgNA5W7Cx8 RA1w== X-Gm-Message-State: AO0yUKU2MNgCDcpSGEQD+GJjJyt7XkkWe+kordJ9BDpnLm+RNOMinl6Z Go63fYOHOVtrIvzK8ek/FGK1gQ== X-Google-Smtp-Source: AK7set93R37VeqYtz2Q7nwYYxsKvvHYRwi1MVAY3nHlm44LAzi8Mx7/WrgqwZadC+nBgZvMUyvCxDA== X-Received: by 2002:a17:902:f94e:b0:19b:e73:809c with SMTP id kx14-20020a170902f94e00b0019b0e73809cmr15771534plb.1.1677258096226; Fri, 24 Feb 2023 09:01:36 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.01.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:01:34 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Guo Ren , Andy Chiu , Paul Walmsley , Albert Ou , Guo Ren , Heiko Stuebner , Nick Knight , Jisheng Zhang Subject: [PATCH -next v14 01/19] riscv: Rename __switch_to_aux -> fpu Date: Fri, 24 Feb 2023 17:01:00 +0000 Message-Id: <20230224170118.16766-2-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Guo Ren The name of __switch_to_aux is not clear and rename it with the determine function: __switch_to_fpu. Next we could add other regs' switch. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Signed-off-by: Greentime Hu Reviewed-by: Anup Patel Reviewed-by: Palmer Dabbelt Signed-off-by: Andy Chiu Tested-by: Heiko Stuebner Reviewed-by: Heiko Stuebner Reviewed-by: Conor Dooley --- arch/riscv/include/asm/switch_to.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 60f8ca01d36e..4b96b13dee27 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -46,7 +46,7 @@ static inline void fstate_restore(struct task_struct *task, } } -static inline void __switch_to_aux(struct task_struct *prev, +static inline void __switch_to_fpu(struct task_struct *prev, struct task_struct *next) { struct pt_regs *regs; @@ -66,7 +66,7 @@ static __always_inline bool has_fpu(void) static __always_inline bool has_fpu(void) { return false; } #define fstate_save(task, regs) do { } while (0) #define fstate_restore(task, regs) do { } while (0) -#define __switch_to_aux(__prev, __next) do { } while (0) +#define __switch_to_fpu(__prev, __next) do { } while (0) #endif extern struct task_struct *__switch_to(struct task_struct *, @@ -77,7 +77,7 @@ do { \ struct task_struct *__prev = (prev); \ struct task_struct *__next = (next); \ if (has_fpu()) \ - __switch_to_aux(__prev, __next); \ + __switch_to_fpu(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) From patchwork Fri Feb 24 17:01:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151522 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAFCEC7EE23 for ; Fri, 24 Feb 2023 17:01:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230062AbjBXRBt (ORCPT ); Fri, 24 Feb 2023 12:01:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230020AbjBXRBr (ORCPT ); Fri, 24 Feb 2023 12:01:47 -0500 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED79A6B17D for ; Fri, 24 Feb 2023 09:01:45 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id c1so143092plg.4 for ; Fri, 24 Feb 2023 09:01:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=XWIh5JYM/EDcmnt1NZcIDsk8fqXi2dgnlyZIt5otLpA=; b=CkEh5N1u65jga/8/+cP905MaHCut3aB6loenHefv+U8jkhCrs19W4Qb1cMDb8KMC+N r9sGfZjVnun034ebJLM7qzEaeu8QYshK/WRUptnj/gU4u/o239xQpzhkv/ltpBV6Vmni izHRiqYpREQhVb0uPZE/3UkMK7FHbY5nz4h1mZ+9D8YdOYQEBBSXX9Jy5dCdd8wEfUeq 0ALwmbuoJbSlbNTso8Zo5zIt0f9Vw8v0Z+iexClMoOxjD8No3qwCGsGHOHVaGEdga8XQ EllgbJg6u7v9ij/zs/qI7SQ4MdprhcPmpzvPwlauFXr8zz1xxnREQswQsESIGZxApU77 I8pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=XWIh5JYM/EDcmnt1NZcIDsk8fqXi2dgnlyZIt5otLpA=; b=Vn0ez9gsQFiDEBn2hxDg4eA09TYVG2q7HB4HMfXvH9h8aX679ohr+Xrz7SEHpn+dXu paYNV1bvZlQLw+HtCqyshike93KO+6gxdfKNX4OpMVyh9tl6Frsjp+nwAVPZdlPtUfxA 8yj6ZR4968cmRvHGu238DLY3F9xmTEzkZ0C5/EzF1idBns1pT6pTmy9Uupne/WgvycqK M1SeG/tav9gs/3dmzfREFn1t5nvzQFnOpB80V5xOU1izOKzYNA5V0pnuACVZptahqaTm WEaR4YATmyDMV0gr21XCsXJZFMRCqIGL68218sdW4U/qXrv6decRKDeXPHdU/cp09+dS ZeXQ== X-Gm-Message-State: AO0yUKW0bb0iY6QGAdK1ijjIKY8Q0GuzmjzPbAVzhcFvGzWlmPdjgqkx 5noNkHkG5qdDlJW5a3xDQzG97A== X-Google-Smtp-Source: AK7set+rxZVEgTVbq1zk3TW3EwLZSNHkhuoPmsE4flU3gpU7EajZ0u4rvvMg2wo6T+YDKSk/mF8JDA== X-Received: by 2002:a17:903:244c:b0:19a:d453:4ac with SMTP id l12-20020a170903244c00b0019ad45304acmr20244323pls.61.1677258105180; Fri, 24 Feb 2023 09:01:45 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:01:44 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Guo Ren , Andy Chiu , Paul Walmsley , Albert Ou , Heiko Stuebner , Conor Dooley , Andrew Jones , Atish Patra , Jisheng Zhang , Dao Lu , Vincent Chen , Guo Ren , Tsukasa OI Subject: [PATCH -next v14 02/19] riscv: Extending cpufeature.c to detect V-extension Date: Fri, 24 Feb 2023 17:01:01 +0000 Message-Id: <20230224170118.16766-3-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Guo Ren Add V-extension into riscv_isa_ext_keys array and detect it with isa string parsing. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Signed-off-by: Greentime Hu Suggested-by: Vineet Gupta Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/vector.h | 26 ++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 11 +++++++++++ 4 files changed, 39 insertions(+) create mode 100644 arch/riscv/include/asm/vector.h diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 8f3994a7f0ca..8dd673bbcb3b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -22,6 +22,7 @@ #define RISCV_ISA_EXT_m ('m' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') +#define RISCV_ISA_EXT_v ('v' - 'a') /* * These macros represent the logical IDs of each multi-letter RISC-V ISA diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h new file mode 100644 index 000000000000..427a3b51df72 --- /dev/null +++ b/arch/riscv/include/asm/vector.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2020 SiFive + */ + +#ifndef __ASM_RISCV_VECTOR_H +#define __ASM_RISCV_VECTOR_H + +#include + +#ifdef CONFIG_RISCV_ISA_V + +#include + +static __always_inline bool has_vector(void) +{ + return riscv_has_extension_likely(RISCV_ISA_EXT_v); +} + +#else /* ! CONFIG_RISCV_ISA_V */ + +static __always_inline bool has_vector(void) { return false; } + +#endif /* CONFIG_RISCV_ISA_V */ + +#endif /* ! __ASM_RISCV_VECTOR_H */ diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h index 46dc3f5ee99f..c52bb7bbbabe 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -21,5 +21,6 @@ #define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) #endif /* _UAPI_ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 59d58ee0f68d..4b82a01f5603 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -99,6 +99,7 @@ void __init riscv_fill_hwcap(void) isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; + isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; elf_hwcap = 0; @@ -255,6 +256,16 @@ void __init riscv_fill_hwcap(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_F; } + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + /* + * ISA string in device tree might have 'v' flag, but + * CONFIG_RISCV_ISA_V is disabled in kernel. + * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled. + */ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + elf_hwcap &= ~COMPAT_HWCAP_ISA_V; + } + memset(print_str, 0, sizeof(print_str)); for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) From patchwork Fri Feb 24 17:01:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D566DC7EE23 for ; Fri, 24 Feb 2023 17:01:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229967AbjBXRB4 (ORCPT ); Fri, 24 Feb 2023 12:01:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230015AbjBXRBz (ORCPT ); Fri, 24 Feb 2023 12:01:55 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D67726B14C for ; Fri, 24 Feb 2023 09:01:50 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id c23so12209484pjo.4 for ; Fri, 24 Feb 2023 09:01:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=6oiv3GoujeROo2FqQ+/nZWilhp/M74Q6K5tii11K258=; b=LzukB1Ftb+M5MWrggVI5waWvR8vdX9YlggE3kHxi8SvIjlY0WBOiK4Qk3G3OqOlO+f o5iaGOv+Jk2u8xArSYJs6lcf60wopis1zkgscxl32hQGXXj6NznYuElTTliv6eE6WFtX vYCEzbORkh7x72EFmJlHoWNak1fiIhIExMW6ok0bp6YEHwqHZmOAc+JXJKkT1oU+sgvP mqQocNe0SaEEwYe3sAIKO0aobzHcm653wN7DvJhk29olHwR0DG+X5KL0mgzPHbUHsFcy 9Spe6QGK7lxIRlAN2q77nG4M3PRMa3rM4YlNmqNXuW+fZ1ewL6TxFYBhefbMENXnJm2M vCeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=6oiv3GoujeROo2FqQ+/nZWilhp/M74Q6K5tii11K258=; b=xOBjW2Ks2n4bOAALh8kp3G3E9qF4zsMkeniyhmnZudmnVOIgXHSNdC/9gOj3N3UU9d KH2KmIZ+WNbd7v3unRgRSFG31W2BeMulkq31uIbyl7L5nifS5zgtMr014x/G0IZTjpG/ tkFJTaTK+z51KscEmoLRKpDVaZap7Q2O3oWVpZrySqhM4Z5UvIWrvwKmcEl2+R433Fp4 OnrAPGNk2/JJQrXhfQ1/Xl1+bEySvy35U8QQKB374bdPFN5Z/0UZ/efLt/RagVDIG5YN cW/KxJmFxrzrCy2jjRNkbBDn9f9Kk/3DW/oOHJ2U6qGW5T/EwUMwFfApxGCASaz8xHJb b0tQ== X-Gm-Message-State: AO0yUKXSqeHNIljz6Co2epcBWadXXOzG9BusGaJK29znk+0sYlF884mL nQ6AKZfK43d3KgqSg/HODgrgVQ== X-Google-Smtp-Source: AK7set9y+i1eXYSbsemD/Nfvo8qLXh5WeFiF1PxWHM/91G0NMz9WVkIIPYNpAJsYETY0ho8DaVVAOg== X-Received: by 2002:a17:902:c40d:b0:198:e13e:e73e with SMTP id k13-20020a170902c40d00b00198e13ee73emr20251145plk.53.1677258110286; Fri, 24 Feb 2023 09:01:50 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:01:48 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Atish Patra , Anup Patel , Guo Ren Subject: [PATCH -next v14 03/19] riscv: Add new csr defines related to vector extension Date: Fri, 24 Feb 2023 17:01:02 +0000 Message-Id: <20230224170118.16766-4-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu Follow the riscv vector spec to add new csr numbers. [guoren@linux.alibaba.com: first porting for new vector related csr] Acked-by: Guo Ren Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Reviewed-by: Palmer Dabbelt Suggested-by: Vineet Gupta Signed-off-by: Andy Chiu [andyc: added SR_FS_VS] Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner --- arch/riscv/include/asm/csr.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 0e571f6483d9..add51662b7c3 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -24,16 +24,24 @@ #define SR_FS_CLEAN _AC(0x00004000, UL) #define SR_FS_DIRTY _AC(0x00006000, UL) +#define SR_VS _AC(0x00000600, UL) /* Vector Status */ +#define SR_VS_OFF _AC(0x00000000, UL) +#define SR_VS_INITIAL _AC(0x00000200, UL) +#define SR_VS_CLEAN _AC(0x00000400, UL) +#define SR_VS_DIRTY _AC(0x00000600, UL) + #define SR_XS _AC(0x00018000, UL) /* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL) #define SR_XS_INITIAL _AC(0x00008000, UL) #define SR_XS_CLEAN _AC(0x00010000, UL) #define SR_XS_DIRTY _AC(0x00018000, UL) +#define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */ + #ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ #else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ #endif #ifdef CONFIG_64BIT @@ -297,6 +305,12 @@ #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#define CSR_VSTART 0x8 +#define CSR_VCSR 0xf +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 + #ifdef CONFIG_RISCV_M_MODE # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE From patchwork Fri Feb 24 17:01:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151524 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3032FC7EE2E for ; Fri, 24 Feb 2023 17:02:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229620AbjBXRCL (ORCPT ); Fri, 24 Feb 2023 12:02:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230063AbjBXRCJ (ORCPT ); Fri, 24 Feb 2023 12:02:09 -0500 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A7176C1AA for ; Fri, 24 Feb 2023 09:01:56 -0800 (PST) Received: by mail-pl1-x630.google.com with SMTP id h14so107648plf.10 for ; Fri, 24 Feb 2023 09:01:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=Tr4IaNHJV/yxI3LzfdUHpHdNHRqmUrR0SAE9fALA7gA=; b=X53N55kzCDwGxM9gSR6D8s5MXnNjsLx2+RUlkJVVBzk/V6dMb3r0KJppvVhw26wVPU L78d/fw+nkpxWlEmjRU/BJIeKiyDiGmx1NCAuv4cO1ME8iBNadGmWyTkWdxSWKiDufvH xvL9sKASZJFov+erCKEqqs/RsdbhdVvJqczJEYLwXQlheOA4sqEN9vpANkdfOU7zffZf rLHX+d2iPWPwwmExzo/fXrBgbUNzdABXZGquLl4gKl3F4uvqAYTNS8TF/bq1M+VNiHs/ Af0/y6LCGtlX7758PWKW3He8yEpTsCFMt1tQilv0SMyR/Eulu4uywRYkQ+JFysGs6ECD VUBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Tr4IaNHJV/yxI3LzfdUHpHdNHRqmUrR0SAE9fALA7gA=; b=qtpZQiOLcJEg0vGiReesDDHinKVi2We+dSi1MCT4czDhtuvWr/fEChsI0q+crIwgmo HPkkUPVvjxPAiw+yEy/4RodamyNU6XwkdYw4ByMOgsXRcNeThQtfikZH7+B3BHQUPDAD G+6KTjQe9O+IYllzuJp43+vnRZ77xFu5PZbOPbNukipzAbg87BSQDuYJpx8D2h9Gr6oa giT5EX/rRjjGIM9vrQ1F5+kEcRmN/vbx2fsPabATiwtyS9Oe8mEeP4+zM67+kKbzQ0Qc 3shwyjAG6LZ+vAldoPNJY4o0uffR7tCZ3fkXaCl3ISeZil7PcG6TAge+ozzjcP6Yaekw kWrw== X-Gm-Message-State: AO0yUKUOODOWcrqBhaRaXmbXPsDEGSbGPIm7tA8Y5PUcrCXAzM3zdb6+ c29C2fb/PJ5NPiCiYHTufCzrHA== X-Google-Smtp-Source: AK7set+8aW8jIXiwNWQYy8PDbH2Lpbn0VJvyhHm3YPV4EoNE/73HyNmBg8yX59BdCxrIImwbAxeIjA== X-Received: by 2002:a17:903:11d0:b0:19c:b7da:fc44 with SMTP id q16-20020a17090311d000b0019cb7dafc44mr8203309plh.34.1677258115602; Fri, 24 Feb 2023 09:01:55 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:01:54 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Vincent Chen , Guo Ren , Masahiro Yamada , Alexandre Ghiti Subject: [PATCH -next v14 04/19] riscv: Clear vector regfile on bootup Date: Fri, 24 Feb 2023 17:01:03 +0000 Message-Id: <20230224170118.16766-5-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu clear vector registers on boot if kernel supports V. Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta [vineetg: broke this out to a seperate patch] Signed-off-by: Andy Chiu Acked-by: Conor Dooley --- arch/riscv/kernel/head.S | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4bf6c449d78b..3fd6a4bd9c3e 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -392,7 +392,7 @@ ENTRY(reset_regs) #ifdef CONFIG_FPU csrr t0, CSR_MISA andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D) - beqz t0, .Lreset_regs_done + beqz t0, .Lreset_regs_done_fpu li t1, SR_FS csrs CSR_STATUS, t1 @@ -430,8 +430,31 @@ ENTRY(reset_regs) fmv.s.x f31, zero csrw fcsr, 0 /* note that the caller must clear SR_FS */ +.Lreset_regs_done_fpu: #endif /* CONFIG_FPU */ -.Lreset_regs_done: + +#ifdef CONFIG_RISCV_ISA_V + csrr t0, CSR_MISA + li t1, COMPAT_HWCAP_ISA_V + and t0, t0, t1 + beqz t0, .Lreset_regs_done_vector + + /* + * Clear vector registers and reset vcsr + * VLMAX has a defined value, VLEN is a constant, + * and this form of vsetvli is defined to set vl to VLMAX. + */ + li t1, SR_VS + csrs CSR_STATUS, t1 + csrs CSR_VCSR, x0 + vsetvli t1, x0, e8, m8, ta, ma + vmv.v.i v0, 0 + vmv.v.i v8, 0 + vmv.v.i v16, 0 + vmv.v.i v24, 0 + /* note that the caller must clear SR_VS */ +.Lreset_regs_done_vector: +#endif /* CONFIG_RISCV_ISA_V */ ret END(reset_regs) #endif /* CONFIG_RISCV_M_MODE */ From patchwork Fri Feb 24 17:01:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CB65C7EE2D for ; Fri, 24 Feb 2023 17:02:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230057AbjBXRCQ (ORCPT ); Fri, 24 Feb 2023 12:02:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230055AbjBXRCP (ORCPT ); Fri, 24 Feb 2023 12:02:15 -0500 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0714E6C187 for ; Fri, 24 Feb 2023 09:02:02 -0800 (PST) Received: by mail-pj1-x102e.google.com with SMTP id y15-20020a17090aa40f00b00237ad8ee3a0so1133781pjp.2 for ; Fri, 24 Feb 2023 09:02:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=NUxvG1XG6bOZdb2vYKQcTDKK4B2zTq/9lRnOgI0kuro=; b=G0iOZJZU7g0E+B7ftGmEs4i8CQpL/Z0a/Aep9Cro6JqfVmeywMvkv+84OYPhgWTAT7 c2p2zdzp6vyBY92oth6ReHpW3TbslG2tSkC6VH6t9Z3CjuSJCLw/KLG2XckV0LJ6/Fyx i7Tlxs8TMGPmCPV1cw8f6C0NRhSRFwNXz26Huf55J11yozjRu133bYWrhf0qrG+fnfBS 4maHfEVg80sB7J9tyvL1nuBmW4qHULVT+V9y2imf7P9jQkJuyLrcaW6D9CGs5o57yEVT rJEreQYHlG1gmEjkdOpcVTB6Lg0x+oBvIru137QoeIkQs+nQCFBgeu4bDOHDJWT0GjP2 NwOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=NUxvG1XG6bOZdb2vYKQcTDKK4B2zTq/9lRnOgI0kuro=; b=4fTl7JL63uCVuYUyNQOGQugJMDk4D79EuMTc44cQLcN84SwsilG4bIex1NbcM+fEm3 pFUlm2txPSyVnR4/barV84fm0rIULd6JT26v0rDvBz8WRBkpQzkcBN05HNmwY/cS8izn NXCV6AvivE+GMEVQee1WXNhsuepUzuOh7x1Q/sN4oEM9eBOGEuMLR8Ypc/BVSgxJ0WLU NOXMlitY1MLh+KxhQ1EzZBQ25+DCi6+z8iHlgPjJqTJGDdDDNl4CG0SRcYHV31SDxxqC C0ROrOPdRhXULXTVgTPAj0NQyMKjh/Ao8fXiotT47zR326cIQ4Nno0nJviMRdF/G8JSX rLhg== X-Gm-Message-State: AO0yUKWhmo2nbIgRSUU4wbngxHLd0tlxFp8d3SuoTlwOWNViBnx7yL/r mBn5WyEoQHwRnEvfQzRHSmRwig== X-Google-Smtp-Source: AK7set8PG3CgJDVTtyOMQ2Hcj3pVUAvU3+qxMsC1I6XUdc2RpmwQZtCO2jyHZbw+gZEpuPNqFUGVjw== X-Received: by 2002:a17:902:e545:b0:198:ec2c:d4e6 with SMTP id n5-20020a170902e54500b00198ec2cd4e6mr20124361plf.38.1677258122140; Fri, 24 Feb 2023 09:02:02 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:02:01 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Han-Kuan Chen , Andy Chiu , Paul Walmsley , Albert Ou , Guo Ren , Nicolas Saenz Julienne , Frederic Weisbecker , Changbin Du , Jisheng Zhang , Andrew Bresticker , Alexandre Ghiti Subject: [PATCH -next v14 05/19] riscv: Disable Vector Instructions for kernel itself Date: Fri, 24 Feb 2023 17:01:04 +0000 Message-Id: <20230224170118.16766-6-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Guo Ren Disable vector instructions execution for kernel mode at its entrances. Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Han-Kuan Chen Signed-off-by: Han-Kuan Chen Co-developed-by: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta [vineetg: split off vecreg file clearing] Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- arch/riscv/kernel/entry.S | 6 +++--- arch/riscv/kernel/head.S | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 99d38fdf8b18..e38676d9a0d6 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -77,10 +77,10 @@ _save_context: * Disable user-mode memory access as it should only be set in the * actual user copy routines. * - * Disable the FPU to detect illegal usage of floating point in kernel - * space. + * Disable the FPU/Vector to detect illegal usage of floating point + * or vector in kernel space. */ - li t0, SR_SUM | SR_FS + li t0, SR_SUM | SR_FS_VS REG_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0 diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3fd6a4bd9c3e..e16bb2185d55 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -140,10 +140,10 @@ secondary_start_sbi: .option pop /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS_VS csrc CSR_STATUS, t0 /* Set trap vector to spin forever to help debug */ @@ -234,10 +234,10 @@ pmp_done: .option pop /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS_VS csrc CSR_STATUS, t0 #ifdef CONFIG_RISCV_BOOT_SPINWAIT From patchwork Fri Feb 24 17:01:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151526 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BD84C7EE2D for ; Fri, 24 Feb 2023 17:02:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230064AbjBXRCU (ORCPT ); Fri, 24 Feb 2023 12:02:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230055AbjBXRCT (ORCPT ); Fri, 24 Feb 2023 12:02:19 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9337C6C19A for ; Fri, 24 Feb 2023 09:02:07 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id h14so108134plf.10 for ; Fri, 24 Feb 2023 09:02:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=koVyRaRqxsrDWUrYBU8SOpV584+iZ/LEAwINA8yYDNw=; b=gNJplNOUBbEPEsbUXzNCR/S7URO5fxtOMyxTHZNyo4yuJxk9N8FBXkdiHuVgPQsrS+ NUD/gQo/p8OXfyhY5kl3CqFsxqeEnbh8hvNEYTFiQGQGDqJC8jVMAQILU+x0sUviRAaM B1aziI3RtiOJZv3GoFoyP2+TOVhBjTCJCLn70Hb7sRkiKt+bh6KRk9YtS/UEEBq8NJ/M KUVy/2Rk42caR8b6A9qzHRpOyQ/D3wTSdQLvyIRcNB30yxaElo8br98e355JAbJV+7vT ASTjQ+kObzzTjL1tIpsplGBgVFWSEF7L93/45e5gKu/v2OPKMEbNP+ZIYNMbDaLdR8Ml X3iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=koVyRaRqxsrDWUrYBU8SOpV584+iZ/LEAwINA8yYDNw=; b=qXS2Agt5kGp6jfA+KWDoe0F8Bde8PWYrNp8zLUAF2odonFFvUqUVbW5QV4cFWxhXZw +PkcVXyNSh+CIzgij8YhX0N7hdNmJ7yN8MJKG7Sio8JzJEZ6vJKE0J0y4beaF3OwYN8m m51/Mz/5IO+aMQ5crrgPElbZO4ScPiiB7Bp/FM9FG4i+TprOha9fdFaTxZZjeJBRF3+p v1o58jv8fZJ05qTV9AUR6lMTmwszrTwSKQXci94FHL5nwCmI5oqCsExwNmR3fFw/nvxR SdcSorHRActWFlhEZuersbSJ1LyFMdPasgZEfnUFT2OMlWFGNr1Wr5HNaOErXJFnyJYn +dyg== X-Gm-Message-State: AO0yUKW54AA8wzXCWdyEcQXh+6UyMgbFCEeXROvWAwMj6Bm9wU0oZ3N2 NyA83lBT/zyQnXgYF3Ye9Pq/Ew== X-Google-Smtp-Source: AK7set87gGJjD+nHWmm9FxzEE29v4LyYPmGs1/TwwamuxjFalRbTlle2D/CceQqh2G+WOHETlNFp4w== X-Received: by 2002:a17:902:f988:b0:19c:e0fe:ed1e with SMTP id ky8-20020a170902f98800b0019ce0feed1emr886986plb.69.1677258126886; Fri, 24 Feb 2023 09:02:06 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.02.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:02:06 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Guo Ren Subject: [PATCH -next v14 06/19] riscv: Introduce Vector enable/disable helpers Date: Fri, 24 Feb 2023 17:01:05 +0000 Message-Id: <20230224170118.16766-7-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu These are small and likely to be frequently called so implement as inline routines (vs. function call). Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta [vineetg: create new patch from meshup, introduced asm variant] Signed-off-by: Andy Chiu [andy.chiu: remove calls from asm thus remove asm vaiant] Reviewed-by: Conor Dooley --- arch/riscv/include/asm/vector.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 427a3b51df72..dfe5a321b2b4 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -11,12 +11,23 @@ #ifdef CONFIG_RISCV_ISA_V #include +#include static __always_inline bool has_vector(void) { return riscv_has_extension_likely(RISCV_ISA_EXT_v); } +static __always_inline void riscv_v_enable(void) +{ + csr_set(CSR_SSTATUS, SR_VS); +} + +static __always_inline void riscv_v_disable(void) +{ + csr_clear(CSR_SSTATUS, SR_VS); +} + #else /* ! CONFIG_RISCV_ISA_V */ static __always_inline bool has_vector(void) { return false; } From patchwork Fri Feb 24 17:01:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BFF7C7EE2E for ; Fri, 24 Feb 2023 17:02:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229504AbjBXRC1 (ORCPT ); Fri, 24 Feb 2023 12:02:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230055AbjBXRCZ (ORCPT ); Fri, 24 Feb 2023 12:02:25 -0500 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB5386B151 for ; Fri, 24 Feb 2023 09:02:16 -0800 (PST) Received: by mail-pj1-x102c.google.com with SMTP id y2so12816706pjg.3 for ; Fri, 24 Feb 2023 09:02:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=jdBCcSWmD/x09vfaLkK8fboQxvooLDnkzeel7XCFY9U=; b=bZZevSe2DQytVTGOyFQ2xDnTw4PQL3rigDBvzkiepYBQx/QHxvAQAmL2vOoZX8HUmD TXtGgHS6RG0EzPPRNc1AY0KbRvPhnyy1R1qMeUAGqAHlTzpyeauB1qV8Gbu1SN/Zz6E9 o7UKRmu99/FyIPJmWYe8037CRfiiUausqb7IjxXETTwtCm1MBjjPmHQK0TgZRQsmQ8W1 PurxMJG2xi94kXD2y/n9Y/VDzhksTH1r6CKgTrSFronmPumFPHyEHimlXQNzEMl/M1zf QfnF9MWDYNysGvzdFaTQAjfyMkYrBdYRBezTWS/sr9xVJzgWEj080N/i1aUTHl4W0pb5 CKVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=jdBCcSWmD/x09vfaLkK8fboQxvooLDnkzeel7XCFY9U=; b=s2P52YvHUaHFrqb21St8pKM2NrSr6yQjyyyvFBShOiPH8cGG7zTRoxwZNg7ywOrNIt jk9k9Np47njV+VuZukRSGJvy/XaTxJG/QtnqXp9Ii1Jhzd2oW87Gn/pOpR2X3Vsa/lHK 24ZfnWRP3+40udWrQHoc37bY0AGCa8eLE5e4reJmZ1C/20cdfxf9cX68uL4Sxioj9lHy HRLIX89seNBdzoUd+SKa0TlKi1QpZ4tn6qnElRD1Uqj5IbJQvqymgOrpe1VVmQnCT0MW yNnoi5dCoM1PYaVeAa+A5xvaczsCfKZMqL73Q6dFMs8a992k1vxyv9fCIV/NKGYDBnFD 6OLQ== X-Gm-Message-State: AO0yUKWLk/pq8i4btMJFLys5tq/yGeFDYpmYBz/zvwZS39R+rGFiFpfQ 7c+KMxtTQG9hgKta7LblHQbyOQ== X-Google-Smtp-Source: AK7set/VIz4IdFcCcmfDfMawU19KMH70KUxyj7igMRlChX/KsDv5plpD+hAzyc5Oik79mqw8pbV61g== X-Received: by 2002:a17:902:d4cb:b0:19a:b033:2bb0 with SMTP id o11-20020a170902d4cb00b0019ab0332bb0mr21485385plg.46.1677258136106; Fri, 24 Feb 2023 09:02:16 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.02.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:02:15 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Guo Ren , Heiko Stuebner , Changbin Du , Masahiro Yamada , Li Zhengyu , Conor Dooley , Andrew Jones , Jisheng Zhang , Tsukasa OI , Richard Henderson Subject: [PATCH -next v14 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context Date: Fri, 24 Feb 2023 17:01:06 +0000 Message-Id: <20230224170118.16766-8-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu This patch is used to detect the size of CPU vector registers and use riscv_v_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in a SMP system. [guoren@linux.alibaba.com: add has_vector checking] Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- arch/riscv/include/asm/vector.h | 5 +++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/cpufeature.c | 2 ++ arch/riscv/kernel/vector.c | 21 +++++++++++++++++++++ 4 files changed, 29 insertions(+) create mode 100644 arch/riscv/kernel/vector.c diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index dfe5a321b2b4..692d3ee2d2d3 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -13,6 +13,9 @@ #include #include +extern unsigned long riscv_v_vsize; +void riscv_v_setup_vsize(void); + static __always_inline bool has_vector(void) { return riscv_has_extension_likely(RISCV_ISA_EXT_v); @@ -31,6 +34,8 @@ static __always_inline void riscv_v_disable(void) #else /* ! CONFIG_RISCV_ISA_V */ static __always_inline bool has_vector(void) { return false; } +#define riscv_v_vsize (0) +#define riscv_v_setup_vsize() do {} while (0) #endif /* CONFIG_RISCV_ISA_V */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 4cf303a779ab..48d345a5f326 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o +obj-$(CONFIG_RISCV_ISA_V) += vector.o obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += cpu_ops.o diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 4b82a01f5603..e6d53e2e672b 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -22,6 +22,7 @@ #include #include #include +#include #define NUM_ALPHA_EXTS ('z' - 'a' + 1) @@ -257,6 +258,7 @@ void __init riscv_fill_hwcap(void) } if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + riscv_v_setup_vsize(); /* * ISA string in device tree might have 'v' flag, but * CONFIG_RISCV_ISA_V is disabled in kernel. diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c new file mode 100644 index 000000000000..082baf2a061f --- /dev/null +++ b/arch/riscv/kernel/vector.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 SiFive + * Author: Andy Chiu + */ +#include + +#include +#include + +unsigned long riscv_v_vsize __read_mostly; +EXPORT_SYMBOL_GPL(riscv_v_vsize); + +void riscv_v_setup_vsize(void) +{ + /* There are 32 vector registers with vlenb length. */ + riscv_v_enable(); + riscv_v_vsize = csr_read(CSR_VLENB) * 32; + riscv_v_disable(); +} + From patchwork Fri Feb 24 17:01:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19878C7EE2D for ; Fri, 24 Feb 2023 17:02:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230076AbjBXRC3 (ORCPT ); Fri, 24 Feb 2023 12:02:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230063AbjBXRC2 (ORCPT ); Fri, 24 Feb 2023 12:02:28 -0500 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E0716B171 for ; Fri, 24 Feb 2023 09:02:22 -0800 (PST) Received: by mail-pj1-x1036.google.com with SMTP id qa18-20020a17090b4fd200b0023750b675f5so3464303pjb.3 for ; Fri, 24 Feb 2023 09:02:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=oeU1EzgQZPviUx8x1M7BAweIqWoiI9GPVL7R1I1QzEM=; b=mCv4sAOXa6oisDiWg8GBB0kENtNWNon7JU+fper8v5+3Jca7jjEYPtzqjo+GDcKTRe dKQWOL/12E3JIHbfMwmwsjVqTzcMkbdGG0tU2mJCvYQhmq2qZtul4aVJpiv9vTjB2CEG s2tX/NYrLjyVC7gK5UbMStg2KZWL7aa4Th2HZJgW6NBSord4riefsGbIYHn2TtO11swN gpFObbkXYjqCIwmOjipi67WxH6YeSk5gFZRxq4VLihFHoq1RXGxXpVyTI0MwPSBGb/Wc j16z5G28M6/5z1avj7DaB5K928ZA9BM+KnG83aMj2BQffJAhGslMpHuHFemuhEJgOv/N 5HZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=oeU1EzgQZPviUx8x1M7BAweIqWoiI9GPVL7R1I1QzEM=; b=J3+JZKL/ak03XgM03+D3q9tpDLmjFQ0sYcD26NWANlP9B26K45Aw6genKMld9GyWHO 8zUDI7ZsuEYsRPYx+pAaxkryioEuO2cqn7dTYoJmn8BDqI6Qm+GuZHuo8y6ORs7Br0g1 9TnOYeIcBYst5OKd1kdGJuniGbPzqMUTxL5f7SE1+p/sa0Q+3sCqoJ1DRESs/eoJWVG/ DgELoxkVRUW+wvvEEIrkSImAx9ma9VrFOwMbsX6aBz+1iiuA1epmCjcJcKr25P8S5ueB ILXUuK/tV5U9QjE3x6NTA5eZ/oBEea0W6ExldmeS2MLOWtK2x7+RqMQHqop0iHJ8G/BH kUbw== X-Gm-Message-State: AO0yUKURDpdiRlvfdpCSlM94HiqXB1Oim2VYGIb3mufAEehMhGch3oAC DI5GSIYPoQz6/q8tO1wEdAyaPw== X-Google-Smtp-Source: AK7set82aDGPKd/oN7NmcHtGanjLX/28ckwBJ2M7mKySEAYrKIk1lgwMUdj//Im6eaBTyENN/Kiv2w== X-Received: by 2002:a17:902:c950:b0:19a:b44b:cca6 with SMTP id i16-20020a170902c95000b0019ab44bcca6mr19680763pla.24.1677258141591; Fri, 24 Feb 2023 09:02:21 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.02.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:02:20 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Guo Ren , Richard Henderson Subject: [PATCH -next v14 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Date: Fri, 24 Feb 2023 17:01:07 +0000 Message-Id: <20230224170118.16766-9-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu Add vector state context struct to be added later in thread_struct. And prepare low-level helper functions to save/restore vector contexts. This include Vector Regfile and CSRs holding dynamic configuration state (vstart, vl, vtype, vcsr). The Vec Register width could be implementation defined, but same for all processes, so that is saved separately. This is not yet wired into final thread_struct - will be done when __switch_to actually starts doing this in later patches. Given the variable (and potentially large) size of regfile, they are saved in dynamically allocated memory, pointed to by datap pointer in __riscv_v_ext_state. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta [vineetg: merged bits from 2 different patches] Signed-off-by: Andy Chiu [andy.chiu: use inline asm to save/restore context, remove asm vaiant] Acked-by: Conor Dooley --- arch/riscv/include/asm/vector.h | 84 ++++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/ptrace.h | 17 ++++++ 2 files changed, 101 insertions(+) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 692d3ee2d2d3..9c025f2efdc3 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -12,6 +12,9 @@ #include #include +#include + +#define CSR_STR(x) __ASM_STR(x) extern unsigned long riscv_v_vsize; void riscv_v_setup_vsize(void); @@ -21,6 +24,26 @@ static __always_inline bool has_vector(void) return riscv_has_extension_likely(RISCV_ISA_EXT_v); } +static inline void __riscv_v_vstate_clean(struct pt_regs *regs) +{ + regs->status = (regs->status & ~(SR_VS)) | SR_VS_CLEAN; +} + +static inline void riscv_v_vstate_off(struct pt_regs *regs) +{ + regs->status = (regs->status & ~SR_VS) | SR_VS_OFF; +} + +static inline void riscv_v_vstate_on(struct pt_regs *regs) +{ + regs->status = (regs->status & ~(SR_VS)) | SR_VS_INITIAL; +} + +static inline bool riscv_v_vstate_query(struct pt_regs *regs) +{ + return (regs->status & SR_VS) != 0; +} + static __always_inline void riscv_v_enable(void) { csr_set(CSR_SSTATUS, SR_VS); @@ -31,11 +54,72 @@ static __always_inline void riscv_v_disable(void) csr_clear(CSR_SSTATUS, SR_VS); } +static __always_inline void __vstate_csr_save(struct __riscv_v_ext_state *dest) +{ + asm volatile ( + "csrr %0, " CSR_STR(CSR_VSTART) "\n\t" + "csrr %1, " CSR_STR(CSR_VTYPE) "\n\t" + "csrr %2, " CSR_STR(CSR_VL) "\n\t" + "csrr %3, " CSR_STR(CSR_VCSR) "\n\t" + : "=r" (dest->vstart), "=r" (dest->vtype), "=r" (dest->vl), + "=r" (dest->vcsr) : :); +} + +static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src) +{ + asm volatile ( + "vsetvl x0, %2, %1\n\t" + "csrw " CSR_STR(CSR_VSTART) ", %0\n\t" + "csrw " CSR_STR(CSR_VCSR) ", %3\n\t" + : : "r" (src->vstart), "r" (src->vtype), "r" (src->vl), + "r" (src->vcsr) :); +} + +static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, void *datap) +{ + riscv_v_enable(); + __vstate_csr_save(save_to); + asm volatile ( + "vsetvli t4, x0, e8, m8, ta, ma\n\t" + "vse8.v v0, (%0)\n\t" + "add %0, %0, t4\n\t" + "vse8.v v8, (%0)\n\t" + "add %0, %0, t4\n\t" + "vse8.v v16, (%0)\n\t" + "add %0, %0, t4\n\t" + "vse8.v v24, (%0)\n\t" + : : "r" (datap) : "t4", "memory"); + riscv_v_disable(); +} + +static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_from, + void *datap) +{ + riscv_v_enable(); + asm volatile ( + "vsetvli t4, x0, e8, m8, ta, ma\n\t" + "vle8.v v0, (%0)\n\t" + "add %0, %0, t4\n\t" + "vle8.v v8, (%0)\n\t" + "add %0, %0, t4\n\t" + "vle8.v v16, (%0)\n\t" + "add %0, %0, t4\n\t" + "vle8.v v24, (%0)\n\t" + : : "r" (datap) : "t4"); + __vstate_csr_restore(restore_from); + riscv_v_disable(); +} + #else /* ! CONFIG_RISCV_ISA_V */ +struct pt_regs; + static __always_inline bool has_vector(void) { return false; } +static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } #define riscv_v_vsize (0) #define riscv_v_setup_vsize() do {} while (0) +#define riscv_v_vstate_off(regs) do {} while (0) +#define riscv_v_vstate_on(regs) do {} while (0) #endif /* CONFIG_RISCV_ISA_V */ diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 882547f6bd5c..586786d023c4 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -77,6 +77,23 @@ union __riscv_fp_state { struct __riscv_q_ext_state q; }; +struct __riscv_v_ext_state { + unsigned long vstart; + unsigned long vl; + unsigned long vtype; + unsigned long vcsr; + void *datap; + /* + * In signal handler, datap will be set a correct user stack offset + * and vector registers will be copied to the address of datap + * pointer. + * + * In ptrace syscall, datap will be set to zero and the vector + * registers will be copied to the address right after this + * structure. + */ +}; + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ From patchwork Fri Feb 24 17:01:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09EDBC7EE23 for ; Fri, 24 Feb 2023 17:02:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230055AbjBXRCm (ORCPT ); Fri, 24 Feb 2023 12:02:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230063AbjBXRCk (ORCPT ); Fri, 24 Feb 2023 12:02:40 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F66A6B16B for ; Fri, 24 Feb 2023 09:02:33 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id oe18-20020a17090b395200b00236a0d55d3aso3371226pjb.3 for ; Fri, 24 Feb 2023 09:02:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=cuVHwM8SAGoISZORc0pFtR8N61ah6dOlzZHoRJOSLIo=; b=YLJq0mLp+iQ+Vdr7xn4MIfa4VsG27uMObLT3tuc1EasV5G+NQ+79wengfpOI3VZ4dF Vv44pQ46QPD0Eak+Y4kb86nedFZs59tFUeeYY/PBGCGO7u5CgdLwadKz+tYVtgIfuWov 0o/1rIrBE/tiR8QhoYTv2S3VGGnDpMuW9nvzpBBSI25Fxij+UmvaQhxA66iahVpMDxvx WCsntwA2t0dqMAWTLpiL58uVxq2WoT6DSxAb358omCo6owqfL69WuUNliAKUkBrshe8m ucbMZair0NvvbcLgG0CwGVddJEnTHHdYOYaZNAUY+2KOaMuX0eFb+4ow/oBB+/ExFz1+ ggaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cuVHwM8SAGoISZORc0pFtR8N61ah6dOlzZHoRJOSLIo=; b=LeO3s26gtA2ql3Jqrhq7nPTmRIFFc4eKiQx6TC4yYbSz6vo3sa77QIDTDceWfl6reR JRbDl0SJgXNC+Rfln04iQ+WRZv36Tm8T5i9HJRCzHV3/8U7FqRSKkV2vDXutEG2sT5iC CUXbtGBWYlAfvwk2BuUjhZGr2GVkws7Z5Os30yzb0Hx4O25no0ouiTOGakVU1OFTzsID P5QhaJ+8RYQnzTuPJN7VKTJNtBCWbKiABu5e7GSGWI7xlUxslDsa5Wtke0ZmGrRZ0DXE m66Pla5H/wjbWnVucE8pEiQ3wV6CwOjD/W0k+4YEw1mNv7HhPnFPKgta2ODDZrzleiNR 3RQQ== X-Gm-Message-State: AO0yUKVw4xGg7ER2jjvgz6pmdPBW8WChVwUJX5Kget9xuqyVutEZK/oS +PFxS1CAPx9DGVMydUh6i0qyPg== X-Google-Smtp-Source: AK7set/iEoKSIyULmeDYOrjpIv5td8+55ORgojii3FjvyrzjZRbRGpCctznPLg4f2d43QLaRVqysnQ== X-Received: by 2002:a17:902:e543:b0:19c:d932:f063 with SMTP id n3-20020a170902e54300b0019cd932f063mr2255172plf.67.1677258152778; Fri, 24 Feb 2023 09:02:32 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.02.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:02:30 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Nick Knight , Vincent Chen , Ruinland Tsai , Andy Chiu , Paul Walmsley , Albert Ou , Guo Ren , Kefeng Wang , Sunil V L , Heiko Stuebner , Jisheng Zhang , Conor Dooley , Dmitry Vyukov , "Eric W. Biederman" Subject: [PATCH -next v14 09/19] riscv: Add task switch support for vector Date: Fri, 24 Feb 2023 17:01:08 +0000 Message-Id: <20230224170118.16766-10-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu This patch adds task switch support for vector. It also supports all lengths of vlen. [guoren@linux.alibaba.com: First available porting to support vector context switching] [nick.knight@sifive.com: Rewrite vector.S to support dynamic vlen, xlen and code refine] [vincent.chen@sifive.com: Fix the might_sleep issue in riscv_v_vstate_save, riscv_v_vstate_restore] [andrew@sifive.com: Optimize task switch codes of vector] [ruinland.tsai@sifive.com: Fix the arch_release_task_struct free wrong datap issue] [vineetg: Fixed lkp warning with W=1 build] [andy.chiu: Use inline asm for task switches] Suggested-by: Andrew Waterman Co-developed-by: Nick Knight Signed-off-by: Nick Knight Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Ruinland Tsai Signed-off-by: Ruinland Tsai Signed-off-by: Greentime Hu Signed-off-by: Vineet Gupta Signed-off-by: Andy Chiu --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/switch_to.h | 3 ++ arch/riscv/include/asm/thread_info.h | 3 ++ arch/riscv/include/asm/vector.h | 43 ++++++++++++++++++++++++++-- arch/riscv/kernel/process.c | 18 ++++++++++++ 5 files changed, 66 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 94a0590c6971..f0ddf691ac5e 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -39,6 +39,7 @@ struct thread_struct { unsigned long s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; unsigned long bad_cause; + struct __riscv_v_ext_state vstate; }; /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 4b96b13dee27..a727be723c56 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -78,6 +79,8 @@ do { \ struct task_struct *__next = (next); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ + if (has_vector()) \ + __switch_to_vector(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h index f704c8dd57e0..9e28c0199030 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -80,6 +80,9 @@ struct thread_info { .preempt_count = INIT_PREEMPT_COUNT, \ } +void arch_release_task_struct(struct task_struct *tsk); +int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); + #endif /* !__ASSEMBLY__ */ /* diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 9c025f2efdc3..830f9d3c356b 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -10,6 +10,9 @@ #ifdef CONFIG_RISCV_ISA_V +#include +#include +#include #include #include #include @@ -75,7 +78,8 @@ static __always_inline void __vstate_csr_restore(struct __riscv_v_ext_state *src "r" (src->vcsr) :); } -static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, void *datap) +static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, + void *datap) { riscv_v_enable(); __vstate_csr_save(save_to); @@ -93,7 +97,7 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, vo } static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_from, - void *datap) + void *datap) { riscv_v_enable(); asm volatile ( @@ -110,6 +114,38 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ riscv_v_disable(); } +static inline void riscv_v_vstate_save(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) == SR_VS_DIRTY) { + struct __riscv_v_ext_state *vstate = &task->thread.vstate; + + __riscv_v_vstate_save(vstate, vstate->datap); + __riscv_v_vstate_clean(regs); + } +} + +static inline void riscv_v_vstate_restore(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) != SR_VS_OFF) { + struct __riscv_v_ext_state *vstate = &task->thread.vstate; + + __riscv_v_vstate_restore(vstate, vstate->datap); + __riscv_v_vstate_clean(regs); + } +} + +static inline void __switch_to_vector(struct task_struct *prev, + struct task_struct *next) +{ + struct pt_regs *regs; + + regs = task_pt_regs(prev); + riscv_v_vstate_save(prev, regs); + riscv_v_vstate_restore(next, task_pt_regs(next)); +} + #else /* ! CONFIG_RISCV_ISA_V */ struct pt_regs; @@ -118,6 +154,9 @@ static __always_inline bool has_vector(void) { return false; } static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } #define riscv_v_vsize (0) #define riscv_v_setup_vsize() do {} while (0) +#define riscv_v_vstate_save(task, regs) do {} while (0) +#define riscv_v_vstate_restore(task, regs) do {} while (0) +#define __switch_to_vector(__prev, __next) do {} while (0) #define riscv_v_vstate_off(regs) do {} while (0) #define riscv_v_vstate_on(regs) do {} while (0) diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 8955f2432c2d..5e9506a32fbe 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -24,6 +24,7 @@ #include #include #include +#include register unsigned long gp_in_global __asm__("gp"); @@ -148,12 +149,28 @@ void flush_thread(void) fstate_off(current, task_pt_regs(current)); memset(¤t->thread.fstate, 0, sizeof(current->thread.fstate)); #endif +#ifdef CONFIG_RISCV_ISA_V + /* Reset vector state */ + riscv_v_vstate_off(task_pt_regs(current)); + kfree(current->thread.vstate.datap); + memset(¤t->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); +#endif +} + +void arch_release_task_struct(struct task_struct *tsk) +{ + /* Free the vector context of datap. */ + if (has_vector() && tsk->thread.vstate.datap) + kfree(tsk->thread.vstate.datap); } int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) { fstate_save(src, task_pt_regs(src)); *dst = *src; + /* clear entire V context, including datap for a new task */ + memset(&dst->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); + return 0; } @@ -186,6 +203,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) childregs->a0 = 0; /* Return value of fork() */ p->thread.ra = (unsigned long)ret_from_fork; } + riscv_v_vstate_off(childregs); p->thread.sp = (unsigned long)childregs; /* kernel sp */ return 0; } From patchwork Fri Feb 24 17:01:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151530 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8D1AC7EE23 for ; Fri, 24 Feb 2023 17:02:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230081AbjBXRCy (ORCPT ); Fri, 24 Feb 2023 12:02:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230023AbjBXRCw (ORCPT ); Fri, 24 Feb 2023 12:02:52 -0500 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32A7D6B166 for ; Fri, 24 Feb 2023 09:02:42 -0800 (PST) Received: by mail-pj1-x1029.google.com with SMTP id x34so13667227pjj.0 for ; Fri, 24 Feb 2023 09:02:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=SS8cs34eoeplv/e/P/DsQeAACLLYEFUlQHvyo+fUX8U=; b=iWccYLaoCAU3sGfYapc6H7liLvvc7Exy0HCLNXC8m8DysZxQD6roppOeLjfGgfiZEk HGCu2wwldJ3CbCATd8HcVo8hOB54BlPY3pwnm1tkl6ij4KL2V0MKqj0HR31lGQYwXG+P re4Y/UpoAPrGxYxukn0+0CvPfyAYpZvuVlHEreuRGJTFb6XmCWMM94X3LxF4/YUBT/i4 HDeDcDj/ff4kISFVeDHLHoqDjBX9+dclFHiTqnkJDAdMG2sYMwuLjmUiCkFUWR6Pw74b HObtm7X/21NKAGhH6Zjtc1RPjWHXbt/vH8P92NN/VQ457bt5Wq05+S8KgVB/I7z1DTbe kU4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=SS8cs34eoeplv/e/P/DsQeAACLLYEFUlQHvyo+fUX8U=; b=bYZd3RJrUXslAoNxLr3sjl4GRwKneKkeij+QmkhRwsv3jmkYk7KsdeCfE+GzApq+Yu bG2D5gsZvvZevug2b3dNUzhwgHFXlYiTfIQDCplFoJkTPqVnsyEmmcsWEZqOgHIni60j 7CLcijBdRy4ZTI+ksBtR8CefFSc019PlVnc6nlrU6A0EATBf0rt0n4gL2Yc+ulxlzn0F PrcH35XztK5kSSD3aznpUKC6DmWFW0q8tob8lOt5efCpWFLXxxRbhs6uvCH8jTaXlv8k ytNn4ZXpdXFrwwH5k5PLDpFO0coETHrHqT04h6fubanfKULPZofF9HSDNTxTFgeDhXT1 VG6A== X-Gm-Message-State: AO0yUKU4l68tI0U2VX/pkVgbRsKQPOaCoagt5xdcj2bnhvePBfxcQOn2 JwTeCvN3De0s5UnxTpwXe19N4g== X-Google-Smtp-Source: AK7set8bPOj2fgbw0D9aoNGRvfM1d/GPc41QtnqA4eBys94c6tCinu6q4OyuiQ+zNDmDzUT5RrD0xw== X-Received: by 2002:a17:902:eccc:b0:19a:fdc9:7983 with SMTP id a12-20020a170902eccc00b0019afdc97983mr18039208plh.63.1677258161512; Fri, 24 Feb 2023 09:02:41 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.02.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:02:40 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Andrew Jones , Heiko Stuebner , Conor Dooley , Lad Prabhakar , Liao Chang , Jisheng Zhang , Guo Ren , Vincent Chen , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Xianting Tian , Mattias Nissler , Richard Henderson Subject: [PATCH -next v14 10/19] riscv: Allocate user's vector context in the first-use trap Date: Fri, 24 Feb 2023 17:01:09 +0000 Message-Id: <20230224170118.16766-11-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Vector unit is disabled by default for all user processes. Thus, a process will take a trap (illegal instruction) into kernel at the first time when it uses Vector. Only after then, the kernel allocates V context and starts take care of the context for that user process. Suggested-by: Richard Henderson Link: https://lore.kernel.org/r/3923eeee-e4dc-0911-40bf-84c34aee962d@linaro.org Signed-off-by: Andy Chiu --- arch/riscv/include/asm/insn.h | 29 +++++++++++ arch/riscv/include/asm/vector.h | 2 + arch/riscv/kernel/traps.c | 14 ++++- arch/riscv/kernel/vector.c | 91 +++++++++++++++++++++++++++++++++ 4 files changed, 134 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index 8d5c84f2d5ef..4e1505cef8aa 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -137,6 +137,26 @@ #define RVG_OPCODE_JALR 0x67 #define RVG_OPCODE_JAL 0x6f #define RVG_OPCODE_SYSTEM 0x73 +#define RVG_SYSTEM_CSR_OFF 20 +#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0) + +/* parts of opcode for RVF, RVD and RVQ */ +#define RVFDQ_FL_FS_WIDTH_OFF 12 +#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(3, 0) +#define RVFDQ_FL_FS_WIDTH_W 2 +#define RVFDQ_FL_FS_WIDTH_D 3 +#define RVFDQ_LS_FS_WIDTH_Q 4 +#define RVFDQ_OPCODE_FL 0x07 +#define RVFDQ_OPCODE_FS 0x27 + +/* parts of opcode for RVV */ +#define RVV_OPCODE_VECTOR 0x57 +#define RVV_VL_VS_WIDTH_8 0 +#define RVV_VL_VS_WIDTH_16 5 +#define RVV_VL_VS_WIDTH_32 6 +#define RVV_VL_VS_WIDTH_64 7 +#define RVV_OPCODE_VL RVFDQ_OPCODE_FL +#define RVV_OPCODE_VS RVFDQ_OPCODE_FS /* parts of opcode for RVC*/ #define RVC_OPCODE_C0 0x0 @@ -304,6 +324,15 @@ static __always_inline bool riscv_insn_is_branch(u32 code) (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \ (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); }) +#define RVG_EXTRACT_SYSTEM_CSR(x) \ + ({typeof(x) x_ = (x); RV_X(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); }) + +#define RVFDQ_EXTRACT_FL_FS_WIDTH(x) \ + ({typeof(x) x_ = (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \ + RVFDQ_FL_FS_WIDTH_MASK); }) + +#define RVV_EXRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x) + /* * Get the immediate from a J-type instruction. * diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 830f9d3c356b..9aeab4074ca8 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -21,6 +21,7 @@ extern unsigned long riscv_v_vsize; void riscv_v_setup_vsize(void); +bool riscv_v_first_use_handler(struct pt_regs *regs); static __always_inline bool has_vector(void) { @@ -151,6 +152,7 @@ static inline void __switch_to_vector(struct task_struct *prev, struct pt_regs; static __always_inline bool has_vector(void) { return false; } +static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { return false; } static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } #define riscv_v_vsize (0) #define riscv_v_setup_vsize() do {} while (0) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index f6fda94e8e59..2a98fe74274e 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -24,6 +24,7 @@ #include #include #include +#include int show_unhandled_signals = 1; @@ -135,8 +136,17 @@ DO_ERROR_INFO(do_trap_insn_misaligned, SIGBUS, BUS_ADRALN, "instruction address misaligned"); DO_ERROR_INFO(do_trap_insn_fault, SIGSEGV, SEGV_ACCERR, "instruction access fault"); -DO_ERROR_INFO(do_trap_insn_illegal, - SIGILL, ILL_ILLOPC, "illegal instruction"); + +asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_regs *regs) +{ + if (has_vector() && user_mode(regs)) { + if (riscv_v_first_use_handler(regs)) + return; + } + do_trap_error(regs, SIGILL, ILL_ILLOPC, regs->epc, + "Oops - illegal instruction"); +} + DO_ERROR_INFO(do_trap_load_fault, SIGSEGV, SEGV_ACCERR, "load access fault"); #ifndef CONFIG_RISCV_M_MODE diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 082baf2a061f..585e2c51b28e 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -4,9 +4,19 @@ * Author: Andy Chiu */ #include +#include +#include +#include +#include +#include +#include +#include +#include #include #include +#include +#include unsigned long riscv_v_vsize __read_mostly; EXPORT_SYMBOL_GPL(riscv_v_vsize); @@ -19,3 +29,84 @@ void riscv_v_setup_vsize(void) riscv_v_disable(); } +static bool insn_is_vector(u32 insn_buf) +{ + u32 opcode = insn_buf & __INSN_OPCODE_MASK; + bool is_vector = false; + + /* + * All V-related instructions, including CSR operations are 4-Byte. So, + * do not handle if the instruction length is not 4-Byte. + */ + if (unlikely(GET_INSN_LENGTH(insn_buf) != 4)) + return false; + + switch (opcode) { + case RVV_OPCODE_VECTOR: + is_vector = true; + break; + case RVV_OPCODE_VL: + case RVV_OPCODE_VS: + u32 width = RVV_EXRACT_VL_VS_WIDTH(insn_buf); + + if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 || + width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64) + is_vector = true; + break; + case RVG_OPCODE_SYSTEM: + u32 csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf); + + if ((csr >= CSR_VSTART && csr <= CSR_VCSR) || + (csr >= CSR_VL && csr <= CSR_VLENB)) + is_vector = true; + break; + } + return is_vector; +} + +int riscv_v_thread_zalloc(void) +{ + void *datap; + + datap = kzalloc(riscv_v_vsize, GFP_KERNEL); + if (!datap) + return -ENOMEM; + current->thread.vstate.datap = datap; + memset(¤t->thread.vstate, 0, offsetof(struct __riscv_v_ext_state, + datap)); + return 0; +} + +bool riscv_v_first_use_handler(struct pt_regs *regs) +{ + __user u32 *epc = (u32 *)regs->epc; + u32 insn = (u32)regs->badaddr; + + /* If V has been enabled then it is not the first-use trap */ + if (riscv_v_vstate_query(regs)) + return false; + + /* Get the instruction */ + if (!insn) { + if (__get_user(insn, epc)) + return false; + } + /* Filter out non-V instructions */ + if (!insn_is_vector(insn)) + return false; + + /* Sanity check. datap should be null by the time of the first-use trap */ + WARN_ON(current->thread.vstate.datap); + /* + * Now we sure that this is a V instruction. And it executes in the + * context where VS has been off. So, try to allocate the user's V + * context and resume execution. + */ + if (riscv_v_thread_zalloc()) { + force_sig(SIGKILL); + return true; + } + riscv_v_vstate_on(regs); + return true; +} + From patchwork Fri Feb 24 17:01:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAC4CC7EE2E for ; Fri, 24 Feb 2023 17:03:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230023AbjBXRDA (ORCPT ); Fri, 24 Feb 2023 12:03:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229681AbjBXRC7 (ORCPT ); Fri, 24 Feb 2023 12:02:59 -0500 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D812210C for ; Fri, 24 Feb 2023 09:02:49 -0800 (PST) Received: by mail-pl1-x62f.google.com with SMTP id ky4so152387plb.3 for ; Fri, 24 Feb 2023 09:02:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=7+ktzSBzWBlJTBXe2t4kNMhyRTMebke2LjylJDfEW1M=; b=U7ArKcI8EA64iuMsRfvLdvN899TQbUeBPIONmH5TPfZP9eZhFusFSCuXi3sGWNGEd4 5SQEOSK5T3dtrWuqhEDWlv5pPj55I2dQ5h+S5a5rQ5aKhF/zOfVXoqmFOmdEG2WSAA5R EZGh99cnd4AVkrX0yVvMTDI+xKwJ4KfyWJdWIAjbWlIyGmbONmyo50yivZX5wU0coeX2 CEjGhIsqpb5UNiX6CQw6rdbI5JIDqv+OkUaaYl3exTVXCepfaEUFdF+2E/4avrEUfBp9 6+fB7AyGP1yAUW2cqCWswTRp97K2mZyx3wOxAnv+QnvkOOjr6ktKkLzdso7cvFqQINCX H84Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=7+ktzSBzWBlJTBXe2t4kNMhyRTMebke2LjylJDfEW1M=; b=y1q8QR4YiNcFLXACvefgSXzkFBIMrrTJ1zdkZ70UlNpsp9CEtDM85qrlIHPofH44TN P7+VxT2D2mo7n+ENcgksQD3VvSv/H2+F2o/M72ZOQkiQsTalhSuJfeLDjrie1YwlTfuC WE6XnZfp2i10ajZ+XDZrSDI4cJvf753zsVNHTLZIC4zRBqQtGdsjRY41pQhfyLXUGetC 0m18UlpwD5uIsgV92hriqXpHkIn9g7+F2QzOerrAuBuUDQPbLj98vqG/jZ3lSl/A51BS JJdD5YPswS7QsXIsj0lCNSamw+W91K1B/O8QLjetNnBFnDePkQabCJ7L4xLr9URoWxbX T/ZA== X-Gm-Message-State: AO0yUKXp/kJjnwBHIutUt97fprLqY4sWlOYEkRXAPM1/407r5SI4n/qU WdZkxysob+ARsg3Eo7hr9sUwAA== X-Google-Smtp-Source: AK7set80zewt/ZysWjYp5vJhVBdEJ7dqiJCs+0d/Q5Lxos6RBTiwinrLKF85McCYiokK8i4Uls+JQw== X-Received: by 2002:a17:902:d488:b0:19c:1433:5fae with SMTP id c8-20020a170902d48800b0019c14335faemr19716479plg.2.1677258168503; Fri, 24 Feb 2023 09:02:48 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.02.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:02:47 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Oleg Nesterov , Eric Biederman , Kees Cook , Richard Henderson , Catalin Marinas , Mark Brown , Jiaxun Yang , Janosch Frank , Rolf Eike Beer , Huacai Chen , Alexey Dobriyan Subject: [PATCH -next v14 11/19] riscv: Add ptrace vector support Date: Fri, 24 Feb 2023 17:01:10 +0000 Message-Id: <20230224170118.16766-12-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu This patch adds ptrace support for riscv vector. The vector registers will be saved in datap pointer of __riscv_v_ext_state. This pointer will be set right after the __riscv_v_ext_state data structure then it will be put in ubuf for ptrace system call to get or set. It will check if the datap got from ubuf is set to the correct address or not when the ptrace system call is trying to set the vector registers. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- arch/riscv/include/uapi/asm/ptrace.h | 7 +++ arch/riscv/kernel/ptrace.c | 71 ++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 3 files changed, 79 insertions(+) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 586786d023c4..e8d127ec5cf7 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -94,6 +94,13 @@ struct __riscv_v_ext_state { */ }; +/* + * According to spec: The number of bits in a single vector register, + * VLEN >= ELEN, which must be a power of 2, and must be no greater than + * 2^16 = 65536bits = 8192bytes + */ +#define RISCV_MAX_VLENB (8192) + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 2ae8280ae475..3c0e01d7f8fb 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -7,6 +7,7 @@ * Copied from arch/tile/kernel/ptrace.c */ +#include #include #include #include @@ -27,6 +28,9 @@ enum riscv_regset { #ifdef CONFIG_FPU REGSET_F, #endif +#ifdef CONFIG_RISCV_ISA_V + REGSET_V, +#endif }; static int riscv_gpr_get(struct task_struct *target, @@ -83,6 +87,62 @@ static int riscv_fpr_set(struct task_struct *target, } #endif +#ifdef CONFIG_RISCV_ISA_V +static int riscv_vr_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + struct __riscv_v_ext_state *vstate = &target->thread.vstate; + + if (!riscv_v_vstate_query(task_pt_regs(target))) + return -EINVAL; + /* + * Ensure the vector registers have been saved to the memory before + * copying them to membuf. + */ + if (target == current) + riscv_v_vstate_save(current, task_pt_regs(current)); + + /* Copy vector header from vstate. */ + membuf_write(&to, vstate, offsetof(struct __riscv_v_ext_state, datap)); + membuf_zero(&to, sizeof(void *)); +#if __riscv_xlen == 32 + membuf_zero(&to, sizeof(__u32)); +#endif + + /* Copy all the vector registers from vstate. */ + return membuf_write(&to, vstate->datap, riscv_v_vsize); +} + +static int riscv_vr_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret, size; + struct __riscv_v_ext_state *vstate = &target->thread.vstate; + + if (!riscv_v_vstate_query(task_pt_regs(target))) + return -EINVAL; + /* Copy rest of the vstate except datap */ + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0, + offsetof(struct __riscv_v_ext_state, datap)); + if (unlikely(ret)) + return ret; + + /* Skip copy datap. */ + size = sizeof(vstate->datap); + count -= size; + ubuf += size; + + /* Copy all the vector registers. */ + pos = 0; + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap, + 0, riscv_v_vsize); + return ret; +} +#endif + static const struct user_regset riscv_user_regset[] = { [REGSET_X] = { .core_note_type = NT_PRSTATUS, @@ -102,6 +162,17 @@ static const struct user_regset riscv_user_regset[] = { .set = riscv_fpr_set, }, #endif +#ifdef CONFIG_RISCV_ISA_V + [REGSET_V] = { + .core_note_type = NT_RISCV_VECTOR, + .align = 16, + .n = ((32 * RISCV_MAX_VLENB) + + sizeof(struct __riscv_v_ext_state)) / sizeof(__u32), + .size = sizeof(__u32), + .regset_get = riscv_vr_get, + .set = riscv_vr_set, + }, +#endif }; static const struct user_regset_view riscv_user_native_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 4c6a8fa5e7ed..eeb65ccb5550 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -439,6 +439,7 @@ typedef struct elf64_shdr { #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */ #define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */ #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ +#define NT_RISCV_VECTOR 0x900 /* RISC-V vector registers */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */ From patchwork Fri Feb 24 17:01:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151532 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3C27C7EE2D for ; Fri, 24 Feb 2023 17:03:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230087AbjBXRDE (ORCPT ); Fri, 24 Feb 2023 12:03:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230085AbjBXRDB (ORCPT ); Fri, 24 Feb 2023 12:03:01 -0500 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 392CE5FF4 for ; Fri, 24 Feb 2023 09:02:53 -0800 (PST) Received: by mail-pl1-x633.google.com with SMTP id s5so198230plg.0 for ; Fri, 24 Feb 2023 09:02:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=4OIOt+i2FPUUG761vxHsPnTGTmnqKlqPflyjCyvck2Q=; b=OU8AF9tNo8cvjdesztUh7J2bMGT7DF8pw6VT470S4w3FkgPvmNzP7WoNrTFpalVkqx R08fYG2J6ka7bROxWlaNqMoUVxQse5knzCBUBxM4b+O2FyZXY0xDt8pVOr7i0KTygF56 cvczdiCMZuXqv9lSNqgcb2aktfsAiMaawArq37VH/fYK/NYMuuQXAtWNsXzNkiTTqIoH kDaEY7y8skSSSz/x3WvmexLxsHYa0TOaqZ1vnkQWnRIhD4tZuGRJo3oLf1awCzhLT+om XeDv3bJZEHmRXG1PE3asgUkA6FyC1sDTlpiDEQ6lPTM7hUL3wNSaPn/GbkuMzYsZTby0 cgHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=4OIOt+i2FPUUG761vxHsPnTGTmnqKlqPflyjCyvck2Q=; b=8R8KmpOP7lXdOXhWIMzFIuRquhjTuzzD9WoZ9g7IWWDAGy4cHkZqI7IkkkOIyJHE0a bGfTgwheClC7wxpxb7d2JNswfsnoFEf7hiAEwmxWmsWoOQqRUDczf+ZlL/4bdO0aZ07c SuMDWSnIsTODhxJ6uZKY3RyPEloI0QreJqlX2ag9za6FpBzDNKjJrMqVcPyNDJPUM6kS D9XyyGGnm8bxLciVoucRjpZkxRHm/Cp6ofZ4vT/FCfKbsCIn7G6Zm9BunN3mfRyi5SAL AyuwijQOUPhGXzxxb2EfWYfSc9NfkSsqApPVSpMoj0Vg9VuJ+UqSQ5nQT8pMweaN2V6v IIyg== X-Gm-Message-State: AO0yUKWIkQkTaNMmauWkq05h7O+cZxOgMYTK56ftihvmQmFeejXgGDrX IyEGo6aOBM/Y+D/BAwT/2XkWKw== X-Google-Smtp-Source: AK7set/8c1sk0d5VHRUyvH1XHmF4lUGcCLfNDTtBkpMV8VbJNSL04MQoKY19udSmkzrwEBAnlypk/A== X-Received: by 2002:a17:902:cece:b0:19a:973b:b615 with SMTP id d14-20020a170902cece00b0019a973bb615mr21981971plg.36.1677258172670; Fri, 24 Feb 2023 09:02:52 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.02.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:02:52 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Vincent Chen , Guo Ren , Conor Dooley , Andrew Bresticker Subject: [PATCH -next v14 12/19] riscv: signal: check fp-reserved words unconditionally Date: Fri, 24 Feb 2023 17:01:11 +0000 Message-Id: <20230224170118.16766-13-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org In order to let kernel/user locate and identify an extension context on the existing sigframe, we are going to utilize reserved space of fp and encode the information there. And since the sigcontext has already preserved a space for fp context w or w/o CONFIG_FPU, we move those reserved words checking/setting routine back into generic code. This commit also undone an additional logical change carried by the refactor commit 007f5c3589578 ("Refactor FPU code in signal setup/return procedures"). Originally we did not restore fp context if restoring of gpr have failed. And it was fine on the other side. In such way the kernel could keep the regfiles intact, and potentially react at the failing point of restore. Signed-off-by: Andy Chiu Acked-by: Conor Dooley --- arch/riscv/kernel/signal.c | 53 +++++++++++++++++++------------------- 1 file changed, 26 insertions(+), 27 deletions(-) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index bfb2afa4135f..0c8be5404a73 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -38,26 +38,13 @@ static long restore_fp_state(struct pt_regs *regs, { long err; struct __riscv_d_ext_state __user *state = &sc_fpregs->d; - size_t i; err = __copy_from_user(¤t->thread.fstate, state, sizeof(*state)); if (unlikely(err)) return err; fstate_restore(current, regs); - - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc_fpregs->q.reserved); i++) { - u32 value; - - err = __get_user(value, &sc_fpregs->q.reserved[i]); - if (unlikely(err)) - break; - if (value != 0) - return -EINVAL; - } - - return err; + return 0; } static long save_fp_state(struct pt_regs *regs, @@ -65,20 +52,9 @@ static long save_fp_state(struct pt_regs *regs, { long err; struct __riscv_d_ext_state __user *state = &sc_fpregs->d; - size_t i; fstate_save(current, regs); err = __copy_to_user(state, ¤t->thread.fstate, sizeof(*state)); - if (unlikely(err)) - return err; - - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc_fpregs->q.reserved); i++) { - err = __put_user(0, &sc_fpregs->q.reserved[i]); - if (unlikely(err)) - break; - } - return err; } #else @@ -90,11 +66,29 @@ static long restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { long err; + size_t i; + /* sc_regs is structured the same as the start of pt_regs */ err = __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs)); + if (unlikely(err)) + return err; /* Restore the floating-point state. */ - if (has_fpu()) - err |= restore_fp_state(regs, &sc->sc_fpregs); + if (has_fpu()) { + err = restore_fp_state(regs, &sc->sc_fpregs); + if (unlikely(err)) + return err; + } + + /* We support no other extension state at this time. */ + for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) { + u32 value; + + err = __get_user(value, &sc->sc_fpregs.q.reserved[i]); + if (unlikely(err)) + break; + if (value != 0) + return -EINVAL; + } return err; } @@ -145,11 +139,16 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, { struct sigcontext __user *sc = &frame->uc.uc_mcontext; long err; + size_t i; + /* sc_regs is structured the same as the start of pt_regs */ err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs)); /* Save the floating-point state. */ if (has_fpu()) err |= save_fp_state(regs, &sc->sc_fpregs); + /* We support no other extension state at this time. */ + for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) + err |= __put_user(0, &sc->sc_fpregs.q.reserved[i]); return err; } From patchwork Fri Feb 24 17:01:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75963C7EE23 for ; Fri, 24 Feb 2023 17:03:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230016AbjBXRDI (ORCPT ); Fri, 24 Feb 2023 12:03:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230083AbjBXRDH (ORCPT ); Fri, 24 Feb 2023 12:03:07 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D165B40F7 for ; Fri, 24 Feb 2023 09:03:01 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id kb15so226890pjb.1 for ; Fri, 24 Feb 2023 09:03:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=75Miv22SHBi8JrhnNBDl8uvRiMa4XJY5yqvFgU4WUC0=; b=VvGYaFWMwqLlAwIn3k7+lGC6lLGEoDkAlSwFmQ9kPQb7mJMrD7ItwzsmTbyRiAwU7Q OtNBWdqBQNjAX91b29aBj2HwBpbRSYl4vBDd62GmtjynSeV2SBlE/naW/DxUGVcaF2p5 a65f51UcOauPdRg5jvo4/A6FEE9nqJgDwn8j1aM4ejUapDi+hto8R8AY0XCF9VEEiDTw snJsmb+fwpBZR+9AZ5pnvXf4Dpi8crU2l9TFuguIjno3oaZQ5MebJsI+p2S9oPQX3BmD shuVkSIjjT91elc7mjC9+XT6vl5xRDQulQJstfDM0PSThu++uNt+bwDwBaSkdeuhR6jB iCRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=75Miv22SHBi8JrhnNBDl8uvRiMa4XJY5yqvFgU4WUC0=; b=FOX/pBdDeNpgzUDg9su749Rf/ZCp+Q58TmqL66WqnheFu6qvrTVRvDsHLanmyu+eYf 8aX5+I35QOwtEDb1TTHJUEP0hbTgnpGGhqrcg5hNsQVGtt+mGiy4aRoQLyPpGhuydb2k 2a4WryxBsEr7IafKlXTE9lC/yWAFUk7tKTFsYrOiAi6j8hhbH56cpVu9AtaafkQ2aPyN mIco95g0v7TCvkvXLZjtZXnZR0yEeY+cSEeX/ka39obnB03uh7lf1mJP4XIIaYRp9zmK QT340IRc92ZSeo/l6tOWzGY09ntsrk3sieGiKFdST9cempZaUzCfz6OtHov3I9wBiNNG g3HQ== X-Gm-Message-State: AO0yUKVQbDy3nin28nfV85j9v9zsMyxhAEGubb3WIr4xVHuYTwhUCJi3 bdZ2BvSwFnzN48BCeQ+TIJjc1w== X-Google-Smtp-Source: AK7set/smceFxzDkhVFwpYJq3XJGP6EDnexj0baDUX1a8YvKzWfu7LJFypAQnX5Brh/dAd9iuprYyw== X-Received: by 2002:a17:902:e54f:b0:19a:89d4:802f with SMTP id n15-20020a170902e54f00b0019a89d4802fmr19683539plf.57.1677258181082; Fri, 24 Feb 2023 09:03:01 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.02.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:03:00 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Richard Henderson , Conor Dooley , Heiko Stuebner , Guo Ren , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Wenting Zhang , Jisheng Zhang , Xianting Tian , David Hildenbrand , Al Viro , Andrew Bresticker Subject: [PATCH -next v14 13/19] riscv: signal: Add sigcontext save/restore for vector Date: Fri, 24 Feb 2023 17:01:12 +0000 Message-Id: <20230224170118.16766-14-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu This patch facilitates the existing fp-reserved words for placement of the first extension's context header on the user's sigframe. A context header consists of a distinct magic word and the size, including the header itself, of an extension on the stack. Then, the frame is followed by the context of that extension, and then a header + context body for another extension if exists. If there is no more extension to come, then the frame must be ended with a null context header. A special case is rv64gc, where the kernel support no extensions requiring to expose additional regfile to the user. In such case the kernel would place the null context header right after the first reserved word of __riscv_q_ext_state when saving sigframe. And the kernel would check if all reserved words are zeros when a signal handler returns. __riscv_q_ext_state---->| |<-__riscv_extra_ext_header ~ ~ .reserved[0]--->|0 |<- .reserved <-------|magic |<- .hdr | |size |_______ end of sc_fpregs | |ext-bdy| | ~ ~ +)size ------->|magic |<- another context header |size | |ext-bdy| ~ ~ |magic:0|<- null context header |size:0 | The vector registers will be saved in datap pointer. The datap pointer will be allocated dynamically when the task needs in kernel space. On the other hand, datap pointer on the sigframe will be set right after the __riscv_v_ext_state data structure. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Suggested-by: Vineet Gupta Suggested-by: Richard Henderson Signed-off-by: Andy Chiu --- arch/riscv/include/uapi/asm/ptrace.h | 15 ++ arch/riscv/include/uapi/asm/sigcontext.h | 16 +- arch/riscv/kernel/setup.c | 3 + arch/riscv/kernel/signal.c | 186 ++++++++++++++++++++--- 4 files changed, 200 insertions(+), 20 deletions(-) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index e8d127ec5cf7..e17c550986a6 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -71,6 +71,21 @@ struct __riscv_q_ext_state { __u32 reserved[3]; }; +struct __riscv_ctx_hdr { + __u32 magic; + __u32 size; +}; + +struct __riscv_extra_ext_header { + __u32 __padding[129] __attribute__((aligned(16))); + /* + * Reserved for expansion of sigcontext structure. Currently zeroed + * upon signal, and must be zero upon sigreturn. + */ + __u32 reserved; + struct __riscv_ctx_hdr hdr; +}; + union __riscv_fp_state { struct __riscv_f_ext_state f; struct __riscv_d_ext_state d; diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/uapi/asm/sigcontext.h index 84f2dfcfdbce..8b8a8541673a 100644 --- a/arch/riscv/include/uapi/asm/sigcontext.h +++ b/arch/riscv/include/uapi/asm/sigcontext.h @@ -8,6 +8,17 @@ #include +/* The Magic number for signal context frame header. */ +#define RISCV_V_MAGIC 0x53465457 +#define END_MAGIC 0x0 + +/* The size of END signal context header. */ +#define END_HDR_SIZE 0x0 + +struct __sc_riscv_v_state { + struct __riscv_v_ext_state v_state; +} __attribute__((aligned(16))); + /* * Signal context structure * @@ -16,7 +27,10 @@ */ struct sigcontext { struct user_regs_struct sc_regs; - union __riscv_fp_state sc_fpregs; + union { + union __riscv_fp_state sc_fpregs; + struct __riscv_extra_ext_header sc_extdesc; + }; }; #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */ diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 376d2827e736..b9b3e03b2564 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -262,6 +262,8 @@ static void __init parse_dtb(void) #endif } +extern void __init init_rt_signal_env(void); + void __init setup_arch(char **cmdline_p) { parse_dtb(); @@ -299,6 +301,7 @@ void __init setup_arch(char **cmdline_p) riscv_init_cbom_blocksize(); riscv_fill_hwcap(); + init_rt_signal_env(); apply_boot_alternatives(); if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && riscv_isa_extension_available(NULL, ZICBOM)) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 0c8be5404a73..76c0480ee4cd 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -18,9 +18,11 @@ #include #include #include +#include #include extern u32 __user_rt_sigreturn[2]; +static size_t riscv_v_sc_size; #define DEBUG_SIG 0 @@ -62,34 +64,159 @@ static long save_fp_state(struct pt_regs *regs, #define restore_fp_state(task, regs) (0) #endif +#ifdef CONFIG_RISCV_ISA_V + +static long save_v_state(struct pt_regs *regs, void **sc_vec) +{ + /* + * Put __sc_riscv_v_state to the user's signal context space pointed + * by sc_vec and the datap point the address right + * after __sc_riscv_v_state. + */ + struct __riscv_ctx_hdr __user *hdr = (struct __riscv_ctx_hdr *)(*sc_vec); + struct __sc_riscv_v_state __user *state = (struct __sc_riscv_v_state *)(hdr + 1); + void __user *datap = state + 1; + long err; + + /* datap is designed to be 16 byte aligned for better performance */ + WARN_ON(unlikely(!IS_ALIGNED((unsigned long)datap, 16))); + + riscv_v_vstate_save(current, regs); + /* Copy everything of vstate but datap. */ + err = __copy_to_user(&state->v_state, ¤t->thread.vstate, + offsetof(struct __riscv_v_ext_state, datap)); + /* Copy the pointer datap itself. */ + err |= __put_user(datap, &state->v_state.datap); + /* Copy the whole vector content to user space datap. */ + err |= __copy_to_user(datap, current->thread.vstate.datap, riscv_v_vsize); + /* Copy magic to the user space after saving all vector conetext */ + err |= __put_user(RISCV_V_MAGIC, &hdr->magic); + err |= __put_user(riscv_v_sc_size, &hdr->size); + if (unlikely(err)) + return err; + + /* Only progress the sv_vec if everything has done successfully */ + *sc_vec += riscv_v_sc_size; + return 0; +} + +/* + * Restore Vector extension context from the user's signal frame. This function + * assumes a valid extension header. So magic and size checking must be done by + * the caller. + */ +static long __restore_v_state(struct pt_regs *regs, void *sc_vec) +{ + long err; + struct __sc_riscv_v_state __user *state = (struct __sc_riscv_v_state *)(sc_vec); + void __user *datap; + + /* Copy everything of __sc_riscv_v_state except datap. */ + err = __copy_from_user(¤t->thread.vstate, &state->v_state, + offsetof(struct __riscv_v_ext_state, datap)); + if (unlikely(err)) + return err; + + /* Copy the pointer datap itself. */ + err = __get_user(datap, &state->v_state.datap); + if (unlikely(err)) + return err; + /* + * Copy the whole vector content from user space datap. Use + * copy_from_user to prevent information leak. + */ + err = copy_from_user(current->thread.vstate.datap, datap, riscv_v_vsize); + if (unlikely(err)) + return err; + + riscv_v_vstate_restore(current, regs); + + return err; +} +#else +#define save_v_state(task, regs) (0) +#define __restore_v_state(task, regs) (0) +#endif + static long restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { + void *sc_ext_ptr = &sc->sc_extdesc.hdr; + __u32 rsvd; long err; - size_t i; - /* sc_regs is structured the same as the start of pt_regs */ err = __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs)); if (unlikely(err)) - return err; + goto done; /* Restore the floating-point state. */ if (has_fpu()) { err = restore_fp_state(regs, &sc->sc_fpregs); if (unlikely(err)) - return err; + goto done; } - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) { - u32 value; - - err = __get_user(value, &sc->sc_fpregs.q.reserved[i]); - if (unlikely(err)) + /* Check the reserved word before extensions parsing */ + err = __get_user(rsvd, &sc->sc_extdesc.reserved); + if (unlikely(err)) + goto done; + if (unlikely(rsvd)) + goto invalid; + + while (1 && !err) { + __u32 magic, size; + struct __riscv_ctx_hdr *head = (struct __riscv_ctx_hdr *)sc_ext_ptr; + + err |= __get_user(magic, &head->magic); + err |= __get_user(size, &head->size); + if (err) + goto done; + + sc_ext_ptr += sizeof(struct __riscv_ctx_hdr); + switch (magic) { + case END_MAGIC: + if (size != END_HDR_SIZE) + goto invalid; + goto done; + case RISCV_V_MAGIC: + if (!has_vector() || !riscv_v_vstate_query(regs)) + goto invalid; + if (size != riscv_v_sc_size) + goto invalid; + err = __restore_v_state(regs, sc_ext_ptr); break; - if (value != 0) - return -EINVAL; + default: + goto invalid; + } + sc_ext_ptr = ((void *)(head) + size); } +done: return err; +invalid: + return -EINVAL; +} + +static size_t cal_rt_frame_size(void) +{ + struct rt_sigframe __user *frame; + size_t frame_size; + size_t total_context_size = 0; + + frame_size = sizeof(*frame); + + if (has_vector() && riscv_v_vstate_query(task_pt_regs(current))) + total_context_size += riscv_v_sc_size; + /* + * Preserved a __riscv_ctx_hdr for END signal context header if an + * extension uses __riscv_extra_ext_header + */ + if (total_context_size) + total_context_size += sizeof(struct __riscv_ctx_hdr); + + frame_size += (total_context_size); + + frame_size = round_up(frame_size, 16); + return frame_size; + } SYSCALL_DEFINE0(rt_sigreturn) @@ -98,13 +225,14 @@ SYSCALL_DEFINE0(rt_sigreturn) struct rt_sigframe __user *frame; struct task_struct *task; sigset_t set; + size_t frame_size = cal_rt_frame_size(); /* Always make any pending restarted system calls return -EINTR */ current->restart_block.fn = do_no_restart_syscall; frame = (struct rt_sigframe __user *)regs->sp; - if (!access_ok(frame, sizeof(*frame))) + if (!access_ok(frame, frame_size)) goto badframe; if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) @@ -138,17 +266,22 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, struct pt_regs *regs) { struct sigcontext __user *sc = &frame->uc.uc_mcontext; + void *sc_ext_ptr = &sc->sc_extdesc.hdr; long err; - size_t i; /* sc_regs is structured the same as the start of pt_regs */ err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs)); /* Save the floating-point state. */ if (has_fpu()) err |= save_fp_state(regs, &sc->sc_fpregs); - /* We support no other extension state at this time. */ - for (i = 0; i < ARRAY_SIZE(sc->sc_fpregs.q.reserved); i++) - err |= __put_user(0, &sc->sc_fpregs.q.reserved[i]); + /* Save the vector state. */ + if (has_vector() && riscv_v_vstate_query(regs)) + err |= save_v_state(regs, &sc_ext_ptr); + /* Write zero to fp-reserved space and check it on restore_sigcontext */ + err |= __put_user(0, &sc->sc_extdesc.reserved); + /* And put END __riscv_ctx_hdr at the end. */ + err |= __put_user(END_MAGIC, &((struct __riscv_ctx_hdr *)sc_ext_ptr)->magic); + err |= __put_user(END_HDR_SIZE, &((struct __riscv_ctx_hdr *)sc_ext_ptr)->size); return err; } @@ -172,6 +305,13 @@ static inline void __user *get_sigframe(struct ksignal *ksig, /* Align the stack frame. */ sp &= ~0xfUL; + /* + * Fail if the size of the altstack is not large enough for the + * sigframe construction. + */ + if (current->sas_ss_size && sp < current->sas_ss_sp) + return (void __user __force *)(-1UL); + return (void __user *)sp; } @@ -180,9 +320,10 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, { struct rt_sigframe __user *frame; long err = 0; + size_t frame_size = cal_rt_frame_size(); - frame = get_sigframe(ksig, regs, sizeof(*frame)); - if (!access_ok(frame, sizeof(*frame))) + frame = get_sigframe(ksig, regs, frame_size); + if (!access_ok(frame, frame_size)) return -EFAULT; err |= copy_siginfo_to_user(&frame->info, &ksig->info); @@ -336,3 +477,10 @@ asmlinkage __visible void do_work_pending(struct pt_regs *regs, thread_info_flags = read_thread_flags(); } while (thread_info_flags & _TIF_WORK_MASK); } + +void init_rt_signal_env(void); +void __init init_rt_signal_env(void) +{ + riscv_v_sc_size = sizeof(struct __riscv_ctx_hdr) + + sizeof(struct __sc_riscv_v_state) + riscv_v_vsize; +} From patchwork Fri Feb 24 17:01:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E051EC7EE2D for ; Fri, 24 Feb 2023 17:03:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230083AbjBXRDQ (ORCPT ); Fri, 24 Feb 2023 12:03:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229532AbjBXRDO (ORCPT ); Fri, 24 Feb 2023 12:03:14 -0500 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64F46A5D2 for ; Fri, 24 Feb 2023 09:03:09 -0800 (PST) Received: by mail-pj1-x102a.google.com with SMTP id y2so12819612pjg.3 for ; Fri, 24 Feb 2023 09:03:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=AlKKel+cEzUa4nWulxqzQ6V6S4zBsnEjdcY3a0TOoBk=; b=PFkVseWH6FYDa2QPWImXVwfI6wbxmjaZhktQRlb5siMyemaCYGewGR989TRUVx9Nrf ZwUmEbPlA77eMOEnn0vSv7867SRLP2mpv5NxOgWu3oGja/szg9NTHy+7b6WoL3WNemLT ShazTTf/SYmncboXMu1h55Cs5iFosxdwprx/HHutV4Hh+/Z923km2ncgeeBb2qVZ3Uc6 bytRzD3cQX5CqmGZ5rnMoPWzijAWdDpnoC0FLVcx96y6McA/cRSo8YAb9e7LsPnNGV9+ XVQrYfSTbaXxYu6sV0OD4xhI234l9vPuEN3dV9JwgOsC+GqFHxv6d9eAwory042ZgMYJ DqYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=AlKKel+cEzUa4nWulxqzQ6V6S4zBsnEjdcY3a0TOoBk=; b=CYxohqlJWrwH/vE/kMSjtZYl35W09NsdaMe/bukI7fz9JHOEkg8qxTTGi7hlgooQaC chyYlQP2QR38rjq0lmaE4htttbc/W5GZ9HeD50bJHRMCj6VWWgEDkfV+rWIg2K5RY1nV ZLSMm6wrlDmKzQvjdSZYft5NjJZK1V61pXJNGjdZg5RLttEqJ1kIFyX2LsSrLsPaae9V s3I7Lq0yVQUKvNMaOuig9bTWDnlRnpxujZTGB2KC3ml8Ybr8TZnHicdXmMS56bmOYW5i 1wdB5HSY/LiayRTIhcZd4e7dZIDS2jHjjngLZ8aVMAcIjb6TS+wbQaV0XNYcqd/z/DtF Xs0A== X-Gm-Message-State: AO0yUKVohozx1uXO2jcZOzOhUSQ4EpIxvoGhv1A3D/S/WTAnLySo5lBU oqGphuCyGNAi9sv1n8xwGILE8g== X-Google-Smtp-Source: AK7set9uimFJXh/iOMry0tS54oA8/EwH5nN2iSDih6nh3Z8BSKitt4coCFXsd5HOnF67hJpXpp+rZg== X-Received: by 2002:a17:903:1208:b0:19a:eb93:6165 with SMTP id l8-20020a170903120800b0019aeb936165mr19452666plh.22.1677258188637; Fri, 24 Feb 2023 09:03:08 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.03.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:03:08 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Eric Biederman , Kees Cook , Guo Ren , Heiko Stuebner , Conor Dooley , Nick Knight , Sunil V L , Kefeng Wang , Zong Li , Andrew Bresticker , Al Viro Subject: [PATCH -next v14 14/19] riscv: signal: Report signal frame size to userspace via auxv Date: Fri, 24 Feb 2023 17:01:13 +0000 Message-Id: <20230224170118.16766-15-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Vincent Chen The vector register belongs to the signal context. They need to be stored and restored as entering and leaving the signal handler. According to the V-extension specification, the maximum length of the vector registers can be 2^(XLEN-1). Hence, if userspace refers to the MINSIGSTKSZ to create a sigframe, it may not be enough. To resolve this problem, this patch refers to the commit 94b07c1f8c39c ("arm64: signal: Report signal frame size to userspace via auxv") to enable userspace to know the minimum required sigframe size through the auxiliary vector and use it to allocate enough memory for signal context. Note that auxv always reports size of the sigframe as if V exists for all starting processes, whenever the kernel has CONFIG_RISCV_ISA_V. The reason is that users usually reference this value to allocate an alternative signal stack, and the user may use V anytime. So the user must reserve a space for V-context in sigframe in case that the signal handler invokes after the kernel allocating V. Signed-off-by: Greentime Hu Signed-off-by: Vincent Chen Signed-off-by: Andy Chiu Acked-by: Conor Dooley --- arch/riscv/include/asm/elf.h | 9 +++++++++ arch/riscv/include/asm/processor.h | 2 ++ arch/riscv/include/uapi/asm/auxvec.h | 1 + arch/riscv/kernel/signal.c | 20 +++++++++++++++----- 4 files changed, 27 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index 30e7d2455960..ca23c4f6c440 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -105,6 +105,15 @@ do { \ get_cache_size(3, CACHE_TYPE_UNIFIED)); \ NEW_AUX_ENT(AT_L3_CACHEGEOMETRY, \ get_cache_geometry(3, CACHE_TYPE_UNIFIED)); \ + /* \ + * Should always be nonzero unless there's a kernel bug. \ + * If we haven't determined a sensible value to give to \ + * userspace, omit the entry: \ + */ \ + if (likely(signal_minsigstksz)) \ + NEW_AUX_ENT(AT_MINSIGSTKSZ, signal_minsigstksz); \ + else \ + NEW_AUX_ENT(AT_IGNORE, 0); \ } while (0) #define ARCH_HAS_SETUP_ADDITIONAL_PAGES struct linux_binprm; diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index f0ddf691ac5e..38ded8c5f207 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -7,6 +7,7 @@ #define _ASM_RISCV_PROCESSOR_H #include +#include #include @@ -81,6 +82,7 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); +extern unsigned long signal_minsigstksz __ro_after_init; #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h index fb187a33ce58..2c50d9ca30e0 100644 --- a/arch/riscv/include/uapi/asm/auxvec.h +++ b/arch/riscv/include/uapi/asm/auxvec.h @@ -35,5 +35,6 @@ /* entries in ARCH_DLINFO */ #define AT_VECTOR_SIZE_ARCH 9 +#define AT_MINSIGSTKSZ 51 #endif /* _UAPI_ASM_RISCV_AUXVEC_H */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 76c0480ee4cd..aa8ee95dee2d 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -21,6 +21,8 @@ #include #include +unsigned long __ro_after_init signal_minsigstksz; + extern u32 __user_rt_sigreturn[2]; static size_t riscv_v_sc_size; @@ -195,7 +197,7 @@ static long restore_sigcontext(struct pt_regs *regs, return -EINVAL; } -static size_t cal_rt_frame_size(void) +static size_t cal_rt_frame_size(bool cal_all) { struct rt_sigframe __user *frame; size_t frame_size; @@ -203,8 +205,10 @@ static size_t cal_rt_frame_size(void) frame_size = sizeof(*frame); - if (has_vector() && riscv_v_vstate_query(task_pt_regs(current))) - total_context_size += riscv_v_sc_size; + if (has_vector()) { + if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) + total_context_size += riscv_v_sc_size; + } /* * Preserved a __riscv_ctx_hdr for END signal context header if an * extension uses __riscv_extra_ext_header @@ -225,7 +229,7 @@ SYSCALL_DEFINE0(rt_sigreturn) struct rt_sigframe __user *frame; struct task_struct *task; sigset_t set; - size_t frame_size = cal_rt_frame_size(); + size_t frame_size = cal_rt_frame_size(false); /* Always make any pending restarted system calls return -EINTR */ current->restart_block.fn = do_no_restart_syscall; @@ -320,7 +324,7 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, { struct rt_sigframe __user *frame; long err = 0; - size_t frame_size = cal_rt_frame_size(); + size_t frame_size = cal_rt_frame_size(false); frame = get_sigframe(ksig, regs, frame_size); if (!access_ok(frame, frame_size)) @@ -483,4 +487,10 @@ void __init init_rt_signal_env(void) { riscv_v_sc_size = sizeof(struct __riscv_ctx_hdr) + sizeof(struct __sc_riscv_v_state) + riscv_v_vsize; + /* + * Determine the stack space required for guaranteed signal delivery. + * The signal_minsigstksz will be populated into the AT_MINSIGSTKSZ entry + * in the auxiliary array at process startup. + */ + signal_minsigstksz = cal_rt_frame_size(true); } From patchwork Fri Feb 24 17:01:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 627B0C7EE23 for ; Fri, 24 Feb 2023 17:03:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230088AbjBXRDY (ORCPT ); Fri, 24 Feb 2023 12:03:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229532AbjBXRDX (ORCPT ); Fri, 24 Feb 2023 12:03:23 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B828C46A2 for ; Fri, 24 Feb 2023 09:03:13 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id ky4so153501plb.3 for ; Fri, 24 Feb 2023 09:03:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=gGZWEGHhXqO9OeXhoDxEGsON6GC4YBeiRX5XbYj9IGA=; b=ghKPeKR0G7uqNkPIH1npSQFQIWcsGSKvYwwCyhwQTOj1TK5WP1/aNJ87vT0C1mdcnO ht5/8+RtBaKIBxaPDYvuzQsOxqiMvI534Qu4gaxQ+XfWL9g2HKUXKKWh1ey/XkDk9aE4 uOginkp7cstMsnvp873wEwWYntVED1Z4ero00tYFcx5ZsZFedEvwzeLBaW2pWlE7ZkvX SRYhb5BU8VVVN5y4d3J1ryOd+P61zO/X+cx91jMeI/8uHICjlll5wYhewyKdfmnsTgxM 4UtNUvfkSRXbex1Rs90s99OR/M3QkP960CJkZZXziXCoNG/Qs9eq5X/jSB4btL/i3pcv y8KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=gGZWEGHhXqO9OeXhoDxEGsON6GC4YBeiRX5XbYj9IGA=; b=Yf5OU1h718QI9mHYEHqlxbvfc26ycAtmIrvSUl7dww8vcQA5FbiCTDwElbAVfhkFF2 E1NOmXqCB3s76mdLupQ+uN+j8GSytZWeAj3RPCI0h8GInZDl0Cf6164XFOsX54nqyu+h JWUUSQaQFp5va2tQQSRbD5p3CtDiJ9g83d96TMQPJ8zmeGCPTMxMbYm7hD77fjzoKJBL JZed33TWcgeFNxZeFyNDyeFB12R2a0aznrdZv7yZpLGnb5UEWH3EZs1NR1GUZkdZRFrc B5czWmga5DITvDvPEvKQqDIgHSvya6C1x/vcz5E6o5751uade04i31kIPHDx673vyAos 9PBg== X-Gm-Message-State: AO0yUKUtPVNiij5q5sY+8uAWOrFU3aoYJCBdxuhtapmp0QKHGpURD/f8 KSP1mUUsXUOvyVK/cuNuO3jzZw== X-Google-Smtp-Source: AK7set/PDa9oZC/tYXZAV4EbClHLZdMbVmxGR97qkvUkEEVLbHU3vmzGKHxKFJkEDjHgyyUthiP+iw== X-Received: by 2002:a17:903:1ce:b0:19a:c65d:f97 with SMTP id e14-20020a17090301ce00b0019ac65d0f97mr24637061plh.41.1677258193134; Fri, 24 Feb 2023 09:03:13 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.03.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:03:12 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou , Vincent Chen , Guo Ren , Al Viro , Andrew Bresticker Subject: [PATCH -next v14 15/19] riscv: signal: validate altstack to reflect Vector Date: Fri, 24 Feb 2023 17:01:14 +0000 Message-Id: <20230224170118.16766-16-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org MINSIGSTKSZ alone have become less informative by the time an user calls sigaltstack(), as the kernel starts to support extensions that dynamically introduce footprint on a signal frame. For example, an RV64V implementation with vlen = 512 may occupy 2K + 40 + 12 Bytes of a signal frame with the upcoming Vector support. And there is no need for reserving the extra sigframe for some processes that do not execute any V-instructions. Thus, provide the function sigaltstack_size_valid() to validate its size based on current allocation status of supported extensions. Signed-off-by: Andy Chiu --- arch/riscv/kernel/signal.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index aa8ee95dee2d..aff441e83a98 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -494,3 +494,11 @@ void __init init_rt_signal_env(void) */ signal_minsigstksz = cal_rt_frame_size(true); } + +#ifdef CONFIG_DYNAMIC_SIGFRAME +bool sigaltstack_size_valid(size_t ss_size) +{ + return ss_size > cal_rt_frame_size(false); +} +#endif /* CONFIG_DYNAMIC_SIGFRAME */ + From patchwork Fri Feb 24 17:01:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67BC6C7EE2D for ; Fri, 24 Feb 2023 17:03:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230091AbjBXRD2 (ORCPT ); Fri, 24 Feb 2023 12:03:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229532AbjBXRD1 (ORCPT ); Fri, 24 Feb 2023 12:03:27 -0500 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E27383CE3F for ; Fri, 24 Feb 2023 09:03:17 -0800 (PST) Received: by mail-pj1-x102a.google.com with SMTP id y2so12820150pjg.3 for ; Fri, 24 Feb 2023 09:03:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=W4ANpghfk7OqklmmNR8esM/3NMZ7VY2gRTQHqD92eU4=; b=dMohg4moPmm6cCczEKC8E/zvUDd4dGMuiAb9JR5LsDjbQ6sjcvvNPACcDJS+vQZreH s1+d5ZzZVMsBHsXtMphSfqrS6HHGLzYJYVZ6x4DSGXsf8s6LrvXzG3WEo5vzjXnkelql Qo1DKU7Xcws0HahmUhV3tZbIqK/0sWTJ2mLv802azlhr34ksVsnDm608sLmrN+P5XmQI Hkcva7btRprCmaHI42qzeH/Ixq9t+pwcJH9D9tViYyfO+jsOivEIDYzDNVGs+csjc+AG 5pBUCCRL6x7J9QzPvgASmSj31o6IFS/IEifv9+pcvHsuyvoaaJd9JfQqPzNTc5Qk/G/o IUIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=W4ANpghfk7OqklmmNR8esM/3NMZ7VY2gRTQHqD92eU4=; b=xOdNO1uXxmTEIOUqnPPB/X2dwDZVysHFMc8WFYIFNNDY55bmQAIZLj5FhkPPE3PSTJ KZoGIRNPXbG23x+6t0E8FqtlOyELHz60FXdHKTKPM8TijoaC26xvMDjkQaRg1V1zX63g fH6/G/ZbtZsLVxN2CScC8Rf8qecAc/7pYOqQoNw6GEsvkCE/8Ol23yxpF0G7zutVyT6b zVWwqs2/OaIn/6QVHCBYJZHi4fjg9/8tzSaGwZUPbcq5toXrb6B3TFo1DxJvnmT/Cz/7 2UcMJu1soZT+iH0d2mCTGkj7r2TllJKZY2eFjBGITknHyQ8U1WhfHwzZPSFPb9p+fyLU pJkw== X-Gm-Message-State: AO0yUKWY/yhmrBEizLOEUiDsWYVsE6CGXlx0yODLIXy5+pc8AKGRGwJx 6Q7ei6Cne+T9O9DsKRbVBvzCaw== X-Google-Smtp-Source: AK7set84M3dR0yl25NPofcni6EwMg6Eo19N35Lc/dXah3YwoY7M9ZpumK8/yDiYHactEzCMuxhMa0Q== X-Received: by 2002:a17:90b:1b10:b0:237:9896:3989 with SMTP id nu16-20020a17090b1b1000b0023798963989mr2425819pjb.34.1677258197522; Fri, 24 Feb 2023 09:03:17 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:03:16 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, ShihPo Hung , Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Guo Ren , Masahiro Yamada Subject: [PATCH -next v14 16/19] riscv: prevent stack corruption by reserving task_pt_regs(p) early Date: Fri, 24 Feb 2023 17:01:15 +0000 Message-Id: <20230224170118.16766-17-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Greentime Hu Early function calls, such as setup_vm, relocate_enable_mmu, soc_early_init etc, are free to operate on stack. However, PT_SIZE_ON_STACK bytes at the head of the kernel stack are purposedly reserved for the placement of per-task register context pointed by task_pt_regs(p). Those functions may corrupt task_pt_regs if we overlap the $sp with it. In fact, we had accidentally corrupted sstatus.VS in some tests, treating the kernel to save V context before V was actually allocated, resulting in a kernel panic. Thus, we should skip PT_SIZE_ON_STACK for $sp before making C function calls from the top-level assembly. Co-developed-by: ShihPo Hung Signed-off-by: ShihPo Hung Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- arch/riscv/kernel/head.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index e16bb2185d55..11c3b94c4534 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -301,6 +301,7 @@ clear_bss_done: la tp, init_task la sp, init_thread_union + THREAD_SIZE XIP_FIXUP_OFFSET sp + addi sp, sp, -PT_SIZE_ON_STACK #ifdef CONFIG_BUILTIN_DTB la a0, __dtb_start XIP_FIXUP_OFFSET a0 @@ -318,6 +319,7 @@ clear_bss_done: /* Restore C environment */ la tp, init_task la sp, init_thread_union + THREAD_SIZE + addi sp, sp, -PT_SIZE_ON_STACK #ifdef CONFIG_KASAN call kasan_early_init From patchwork Fri Feb 24 17:01:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9C27C7EE2D for ; Fri, 24 Feb 2023 17:03:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230095AbjBXRDf (ORCPT ); Fri, 24 Feb 2023 12:03:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230022AbjBXRDe (ORCPT ); Fri, 24 Feb 2023 12:03:34 -0500 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E22839CF0 for ; Fri, 24 Feb 2023 09:03:22 -0800 (PST) Received: by mail-pl1-x62b.google.com with SMTP id bh1so106442plb.11 for ; Fri, 24 Feb 2023 09:03:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=YhtBb89nOsK8vMV5FLn5GLV4Y9PvKk5nrBq2eua1ZQQ=; b=e9tp0eUH0VpJXlp6I8slYqRmoD66QhY2GidzFBryqo0fmqNGhXvEpg5Awm9vMT6aSM ETKYkFU9m+PE5kz5q0CxIjpWn2PkLTs0SOmQ1dLBupc/EUbPBf9SVbLq6yskE4AsDtop kWKs2jOmIy9RcWDxFqYaxAL/CpK+es7RihysURnKQK2wPhftkINFlC+SnbgeCrFYLGiN Sh3QsA5BotnYOpwWNPxZcm4duNYmxWx4pBbdqu8DRHdKCuLyhReKwm3HlKmhoAyOYjjP EsGwf56ARuyQuwkV6rzmiu4zaIs20bA79KvUls+bUHUy/JqJV5BqIKN+hsNvNu7g1nrn qxXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YhtBb89nOsK8vMV5FLn5GLV4Y9PvKk5nrBq2eua1ZQQ=; b=12TDRqQeaPPZEzbNED5VYR5mMjO+aGL4rVQLKSG/33NYFNRuAvtiufh4hiRpDCSEcX MrMNkVSXy9K/OPDAn4PW5p+oIl5O1SMB0d15OCXqdDtJieDmRNn1jd4Atx/A+AlSVj7Q I3H7SnuIRDz594hpxSmk02SfpuZfuh05C+WI0XNp4MfalijzkhxwYeZeuES6HC6PoQep Oyu22rEfjAUvXa5eBZAmU+8aNCVdh9JNiesTCVvgULC19BlE5OMIoiWQIQZg6mlRqhdj zc+anxm/nRrcFkIhEJ58Sv7tD+lVbaIYIMmfr90t4AqKbkr/K7yWJou0dfbbXoRi3vJI MrIA== X-Gm-Message-State: AO0yUKVkMbH6iTvFH5+jgykkVY0HE9vON/Q/JNiKc5NR08rwtYH1zVp2 TULZaoXHRcjDdq7XDbY1PfIpmA== X-Google-Smtp-Source: AK7set8hYBn6Bl6fkiAJavukNy4SdPO2tgwvfzCYBpoAWBin6Lr2TtJ8a0nudLP6vMHi4qPMB1dBEg== X-Received: by 2002:a17:903:32cf:b0:19a:b092:b31a with SMTP id i15-20020a17090332cf00b0019ab092b31amr17326037plr.8.1677258201509; Fri, 24 Feb 2023 09:03:21 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:03:20 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou Subject: [PATCH -next v14 17/19] riscv: kvm: Add V extension to KVM ISA Date: Fri, 24 Feb 2023 17:01:16 +0000 Message-Id: <20230224170118.16766-18-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Vincent Chen Add V extension to KVM isa extension list to enable supporting of V extension on VCPUs. Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Andy Chiu Reviewed-by: Conor Dooley --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 92af6f3f057c..3e3de7d486e1 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -105,6 +105,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_SVINVAL, KVM_RISCV_ISA_EXT_ZIHINTPAUSE, KVM_RISCV_ISA_EXT_ZICBOM, + KVM_RISCV_ISA_EXT_V, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 7c08567097f0..b060d26ab783 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -57,6 +57,7 @@ static const unsigned long kvm_isa_ext_arr[] = { [KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h, [KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i, [KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m, + [KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v, KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), From patchwork Fri Feb 24 17:01:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151538 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56899C7EE2D for ; Fri, 24 Feb 2023 17:03:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230101AbjBXRDl (ORCPT ); Fri, 24 Feb 2023 12:03:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230104AbjBXRDj (ORCPT ); Fri, 24 Feb 2023 12:03:39 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C18B18A5C for ; Fri, 24 Feb 2023 09:03:26 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id h14so111422plf.10 for ; Fri, 24 Feb 2023 09:03:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=X3MkKxTtH8sEXZX8feLpoFOu0c9GU2RA9cYjHPd/7hw=; b=Bg43datoA2cgA998jVLblZtOW5cERhvM38D7my2aghj36G/lcN5ShYQXQOIu7BzXTB M/sb5+2ydiLQ7t4VgUSbBKgS9KZ2d2PHWWVcYNrwbkwOiNLTzF42B32hBEBC8GeQEV4t 5rxXghogr+utnvxo+fU9aqPnDCR8lWFB1iXN7mNpAgnbS9u3fdG2nOZkGW3f2+N01BmI /PZcI3mfaZmm2fE44NdHB6CExeR4S/txlh1O6engbExA5k6cn49oxMJSdJAu1B2AdS1k mn/8fIyhE9KTta6L2xT6sq/1mUWqXe6CnJd9oEQaKYMhB3JN9OE4Q5B128P0ugqZ8/8e 34Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=X3MkKxTtH8sEXZX8feLpoFOu0c9GU2RA9cYjHPd/7hw=; b=BCOX0TTkqRjWN7Vv1UDzGf0BVeXW20i453c7tLmP0cTCTPKcZn3nWOun0QYsjtIW28 iKIOT44aJaclmp15kJCYgkkfR5aO/BVxXNSTVWG65KWggE/1iVoS6yUQvqZvabre9Lik fwpwaYTgk1iiozeVf2dgjZI90mdJ/4tnn2uGrlQCH58cyZik2wgiD3Yqoiw+7V9vbqlm DvbVN2AHMFE4GQnQ7isocYzhGBKEX+5+sxuA3VZAhPYJ4mfNGnniVaCmG0PnpVaJbSMz /mVC2/27ItGFzxxYD7TlVMZ9/uOkuKp1kiknljCtCt5BlFQ967JBGLSEpQfZ3H+u4JAG hJgQ== X-Gm-Message-State: AO0yUKVG+6yocEGE8wUWRXPbNn0P6oc2zbX+urAK72J+4gyWET0SVh5O DKQ3ihIdTzbRStZ2iBNy/hlJSg== X-Google-Smtp-Source: AK7set+863/F2Dp7uatapWKFz0IcESh4AKj4CFEbBw4SrbN4EN21XCbHMFs5PFBOEM5xUaBZrrKzvQ== X-Received: by 2002:a17:903:74b:b0:198:f36b:7dfa with SMTP id kl11-20020a170903074b00b00198f36b7dfamr12993620plb.12.1677258206100; Fri, 24 Feb 2023 09:03:26 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.03.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:03:25 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou Subject: [PATCH -next v14 18/19] riscv: KVM: Add vector lazy save/restore support Date: Fri, 24 Feb 2023 17:01:17 +0000 Message-Id: <20230224170118.16766-19-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Vincent Chen This patch adds vector context save/restore for guest VCPUs. To reduce the impact on KVM performance, the implementation imitates the FP context switch mechanism to lazily store and restore the vector context only when the kernel enters/exits the in-kernel run loop and not during the KVM world switch. Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Signed-off-by: Andy Chiu --- arch/riscv/include/asm/kvm_host.h | 2 + arch/riscv/include/asm/kvm_vcpu_vector.h | 77 ++++++++++ arch/riscv/include/uapi/asm/kvm.h | 7 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu.c | 30 ++++ arch/riscv/kvm/vcpu_vector.c | 177 +++++++++++++++++++++++ 6 files changed, 294 insertions(+) create mode 100644 arch/riscv/include/asm/kvm_vcpu_vector.h create mode 100644 arch/riscv/kvm/vcpu_vector.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 93f43a3e7886..58d660995f22 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -140,6 +141,7 @@ struct kvm_cpu_context { unsigned long sstatus; unsigned long hstatus; union __riscv_fp_state fp; + struct __riscv_v_ext_state vector; }; struct kvm_vcpu_csr { diff --git a/arch/riscv/include/asm/kvm_vcpu_vector.h b/arch/riscv/include/asm/kvm_vcpu_vector.h new file mode 100644 index 000000000000..a6dae7e2859d --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_vector.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 SiFive + * + * Authors: + * Atish Patra + * Anup Patel + * Vincent Chen + * Greentime Hu + */ + +#ifndef __KVM_VCPU_RISCV_VECTOR_H +#define __KVM_VCPU_RISCV_VECTOR_H + +#include + +#ifdef CONFIG_RISCV_ISA_V +#include +#include + +static __always_inline void __kvm_riscv_vector_save(struct kvm_cpu_context *context) +{ + __riscv_v_vstate_save(&context->vector, context->vector.datap); +} + +static __always_inline void __kvm_riscv_vector_restore(struct kvm_cpu_context *context) +{ + __riscv_v_vstate_restore(&context->vector, context->vector.datap); +} + +void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context *cntx, + unsigned long *isa); +void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx, + unsigned long *isa); +void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx); +void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx); +void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu); +#else + +struct kvm_cpu_context; + +static inline void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu) +{ +} + +static inline void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context *cntx, + unsigned long *isa) +{ +} + +static inline void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx, + unsigned long *isa) +{ +} + +static inline void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx) +{ +} + +static inline void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx) +{ +} + +static inline void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu) +{ +} +#endif + +int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype); +int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype); +#endif diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 3e3de7d486e1..b6d7f96d57ab 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -153,6 +153,13 @@ enum KVM_RISCV_ISA_EXT_ID { /* ISA Extension registers are mapped as type 7 */ #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) +/* V extension registers are mapped as type 8 */ +#define KVM_REG_RISCV_VECTOR (0x08 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_VECTOR_CSR_REG(name) \ + (offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_VECTOR_REG(n) \ + ((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long)) + #endif #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index 019df9208bdd..b26bc605a267 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -17,6 +17,7 @@ kvm-y += mmu.o kvm-y += vcpu.o kvm-y += vcpu_exit.o kvm-y += vcpu_fp.o +kvm-y += vcpu_vector.o kvm-y += vcpu_insn.o kvm-y += vcpu_switch.o kvm-y += vcpu_sbi.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index b060d26ab783..ab21ef25e314 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { KVM_GENERIC_VCPU_STATS(), @@ -134,6 +136,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) kvm_riscv_vcpu_fp_reset(vcpu); + kvm_riscv_vcpu_vector_reset(vcpu); + kvm_riscv_vcpu_timer_reset(vcpu); WRITE_ONCE(vcpu->arch.irqs_pending, 0); @@ -189,6 +193,15 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) cntx->hstatus |= HSTATUS_SPVP; cntx->hstatus |= HSTATUS_SPV; + if (has_vector()) { + cntx->vector.datap = kmalloc(riscv_v_vsize, GFP_KERNEL); + if (!cntx->vector.datap) + return -ENOMEM; + vcpu->arch.host_context.vector.datap = kzalloc(riscv_v_vsize, GFP_KERNEL); + if (!vcpu->arch.host_context.vector.datap) + return -ENOMEM; + } + /* By default, make CY, TM, and IR counters accessible in VU mode */ reset_csr->scounteren = 0x7; @@ -219,6 +232,9 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) /* Free unused pages pre-allocated for G-stage page table mappings */ kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); + + /* Free vector context space for host and guest kernel */ + kvm_riscv_vcpu_free_vector_context(vcpu); } int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) @@ -595,6 +611,9 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, KVM_REG_RISCV_FP_D); case KVM_REG_RISCV_ISA_EXT: return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg); + case KVM_REG_RISCV_VECTOR: + return kvm_riscv_vcpu_set_reg_vector(vcpu, reg, + KVM_REG_RISCV_VECTOR); default: break; } @@ -622,6 +641,9 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, KVM_REG_RISCV_FP_D); case KVM_REG_RISCV_ISA_EXT: return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg); + case KVM_REG_RISCV_VECTOR: + return kvm_riscv_vcpu_get_reg_vector(vcpu, reg, + KVM_REG_RISCV_VECTOR); default: break; } @@ -888,6 +910,9 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context); kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context, vcpu->arch.isa); + kvm_riscv_vcpu_host_vector_save(&vcpu->arch.host_context); + kvm_riscv_vcpu_guest_vector_restore(&vcpu->arch.guest_context, + vcpu->arch.isa); vcpu->cpu = cpu; } @@ -903,6 +928,11 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); kvm_riscv_vcpu_timer_save(vcpu); + kvm_riscv_vcpu_guest_vector_save(&vcpu->arch.guest_context, + vcpu->arch.isa); + kvm_riscv_vcpu_host_vector_restore(&vcpu->arch.host_context); + + csr_write(CSR_HGATP, 0); csr->vsstatus = csr_read(CSR_VSSTATUS); csr->vsie = csr_read(CSR_VSIE); diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c new file mode 100644 index 000000000000..68f194771794 --- /dev/null +++ b/arch/riscv/kvm/vcpu_vector.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 SiFive + * + * Authors: + * Atish Patra + * Anup Patel + * Vincent Chen + * Greentime Hu + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_RISCV_ISA_V +extern unsigned long riscv_v_vsize; +void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu) +{ + unsigned long *isa = vcpu->arch.isa; + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + + cntx->sstatus &= ~SR_VS; + if (riscv_isa_extension_available(isa, v)) { + cntx->sstatus |= SR_VS_INITIAL; + WARN_ON(!cntx->vector.datap); + memset(cntx->vector.datap, 0, riscv_v_vsize); + } else { + cntx->sstatus |= SR_VS_OFF; + } +} + +static void kvm_riscv_vcpu_vector_clean(struct kvm_cpu_context *cntx) +{ + cntx->sstatus &= ~SR_VS; + cntx->sstatus |= SR_VS_CLEAN; +} + +void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context *cntx, + unsigned long *isa) +{ + if ((cntx->sstatus & SR_VS) == SR_VS_DIRTY) { + if (riscv_isa_extension_available(isa, v)) + __kvm_riscv_vector_save(cntx); + kvm_riscv_vcpu_vector_clean(cntx); + } +} + +void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx, + unsigned long *isa) +{ + if ((cntx->sstatus & SR_VS) != SR_VS_OFF) { + if (riscv_isa_extension_available(isa, v)) + __kvm_riscv_vector_restore(cntx); + kvm_riscv_vcpu_vector_clean(cntx); + } +} + +void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx) +{ + /* No need to check host sstatus as it can be modified outside */ + if (riscv_isa_extension_available(NULL, v)) + __kvm_riscv_vector_save(cntx); +} + +void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx) +{ + if (riscv_isa_extension_available(NULL, v)) + __kvm_riscv_vector_restore(cntx); +} + +void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu) +{ + kfree(vcpu->arch.guest_reset_context.vector.datap); + kfree(vcpu->arch.host_context.vector.datap); +} +#else +#define riscv_v_vsize (0) +#endif + +static void *kvm_riscv_vcpu_vreg_addr(struct kvm_vcpu *vcpu, + unsigned long reg_num, + size_t reg_size) +{ + struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; + void *reg_val; + size_t vlenb = riscv_v_vsize / 32; + + if (reg_num < KVM_REG_RISCV_VECTOR_REG(0)) { + if (reg_size != sizeof(unsigned long)) + return NULL; + switch (reg_num) { + case KVM_REG_RISCV_VECTOR_CSR_REG(vstart): + reg_val = &cntx->vector.vstart; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(vl): + reg_val = &cntx->vector.vl; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(vtype): + reg_val = &cntx->vector.vtype; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr): + reg_val = &cntx->vector.vcsr; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(datap): + default: + return NULL; + } + } else if (reg_num <= KVM_REG_RISCV_VECTOR_REG(31)) { + if (reg_size != vlenb) + return NULL; + reg_val = cntx->vector.datap + + (reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb; + } else { + return NULL; + } + + return reg_val; +} + +int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + unsigned long *isa = vcpu->arch.isa; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val = NULL; + size_t reg_size = KVM_REG_SIZE(reg->id); + + if (rtype == KVM_REG_RISCV_VECTOR && + riscv_isa_extension_available(isa, v)) { + reg_val = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size); + } + + if (!reg_val) + return -EINVAL; + + if (copy_to_user(uaddr, reg_val, reg_size)) + return -EFAULT; + + return 0; +} + +int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + unsigned long *isa = vcpu->arch.isa; + unsigned long __user *uaddr = + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val = NULL; + size_t reg_size = KVM_REG_SIZE(reg->id); + + if (rtype == KVM_REG_RISCV_VECTOR && + riscv_isa_extension_available(isa, v)) { + reg_val = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size); + } + + if (!reg_val) + return -EINVAL; + + if (copy_from_user(reg_val, uaddr, reg_size)) + return -EFAULT; + + return 0; +} From patchwork Fri Feb 24 17:01:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13151539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F05BC7EE2D for ; Fri, 24 Feb 2023 17:03:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230108AbjBXRDo (ORCPT ); Fri, 24 Feb 2023 12:03:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230024AbjBXRDl (ORCPT ); Fri, 24 Feb 2023 12:03:41 -0500 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D35F35454C for ; Fri, 24 Feb 2023 09:03:29 -0800 (PST) Received: by mail-pl1-x633.google.com with SMTP id s5so199760plg.0 for ; Fri, 24 Feb 2023 09:03:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=sQCYkWxghjLS7BAQiZptP45payXWmeGjuFJjmEJEuNw=; b=iG7u46voWoCSXsiGC6Ysj4m1pbjjUvB2vqFL7cTXHrPGbkWtDLDalWuivRKZXBTTfe kD1u/0FERjeGskarnybYskbOvXn6AYKDq09mEejyQ2Ve9fGuHqHgEiHSBck53ZOXpI4g 6v1qPCxZ3IWdn3xjhhkeiqlW+L8Vnnd0dkkqylyO0ZYXjZmheTHjZtbxC4gmXx3ZzUHL fOw6b0msdExdSij/iTwNJBulPwJTbau1hxc3xCPlJ7FPzno08MfUSbODByVjxMbAVZz+ KG3+8ra9cffVbtio4BTEJqA0sfeqN7gdTX0yz4a3naXCwKWMFUOkO4Ax9+EvwVC9ON3C LErQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=sQCYkWxghjLS7BAQiZptP45payXWmeGjuFJjmEJEuNw=; b=ig5++42UyPOudATu1SXpNIi44JUMpIFC2+pm7bhqfgnUj9VB8RYK9zNDzO6HV/ma64 F1fmJgxbXe+sdPts3HTiadXWrNWy1m8m6rb6jTPi8HZmdPMWfBfG1OxQjxD+X4oXuNbN l6Ir3ZFy4A1xaJxJROhTdJV2he7UBQQjHTF60gyATOuF+dsOwx4W5O47RkYCga1Yd+Hw QhNdaw5pCF49fdKWAoubbCCFKeiZLJ3eT7mrzJgcZehvxNpQ8W+kcP18qMYkXMHZ0Sx9 5+wzEryCBCg5G6Sk2tCaa/sBN8LlHop/bToW80KU4y9TzToiUcm3R1FFFWMyEey+5n2b cFqQ== X-Gm-Message-State: AO0yUKWcGoT5RQdSkwqhwFJZnnX2gMMk7XDEwOYAsLNDUKg2T7fCSfa4 17Yfvjmn34BGdEntEBgzAJVbqQ== X-Google-Smtp-Source: AK7set9Ndd7cIxsBi8HJx0vn2lfPItJRZuCTbx6BWLEvEmJFMQ8OEZOrWu57xNwWs55af4DUU19VCw== X-Received: by 2002:a17:902:b286:b0:19c:a9b8:4349 with SMTP id u6-20020a170902b28600b0019ca9b84349mr9480458plr.32.1677258209313; Fri, 24 Feb 2023 09:03:29 -0800 (PST) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b12-20020a170902b60c00b0019472226769sm9234731pls.251.2023.02.24.09.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Feb 2023 09:03:28 -0800 (PST) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu , Paul Walmsley , Albert Ou Subject: [PATCH -next v14 19/19] riscv: Enable Vector code to be built Date: Fri, 24 Feb 2023 17:01:18 +0000 Message-Id: <20230224170118.16766-20-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230224170118.16766-1-andy.chiu@sifive.com> References: <20230224170118.16766-1-andy.chiu@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Guo Ren This patch adds a config which enables vector feature from the kernel space. Signed-off-by: Guo Ren Co-developed-by: Greentime Hu Signed-off-by: Greentime Hu Suggested-by: Vineet Gupta Suggested-by: Atish Patra Signed-off-by: Andy Chiu --- arch/riscv/Kconfig | 18 ++++++++++++++++++ arch/riscv/Makefile | 3 ++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 81eb031887d2..19deeb3bb36b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -418,6 +418,24 @@ config RISCV_ISA_SVPBMT If you don't know what to do here, say Y. +config TOOLCHAIN_HAS_V + bool + default y + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64iv) + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32iv) + depends on LLD_VERSION >= 140000 || LD_VERSION >= 23800 + +config RISCV_ISA_V + bool "VECTOR extension support" + depends on TOOLCHAIN_HAS_V + select DYNAMIC_SIGFRAME + default y + help + Say N here if you want to disable all vector related procedure + in the kernel. + + If you don't know what to do here, say Y. + config TOOLCHAIN_HAS_ZBB bool default y diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 76989561566b..375a048b11cb 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -56,6 +56,7 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c +riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v # Newer binutils versions default to ISA spec version 20191213 which moves some # instructions from the I extension to the Zicsr and Zifencei extensions. @@ -65,7 +66,7 @@ riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei # Check if the toolchain supports Zihintpause extension riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause -KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) +KBUILD_CFLAGS += -march=$(subst fdv,,$(riscv-march-y)) KBUILD_AFLAGS += -march=$(riscv-march-y) KBUILD_CFLAGS += -mno-save-restore