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Marchesi" To: bpf Cc: Alexei Starovoitov , bpf@ietf.org, David Vernet Subject: [PATCH V3] bpf, docs: Document BPF insn encoding in term of stored bytes Date: Mon, 27 Feb 2023 22:05:51 +0100 Message-ID: <877cw295u8.fsf@oracle.com> User-Agent: Gnus/5.13 (Gnus v5.13) X-ClientProxiedBy: LO4P123CA0493.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1ab::12) To BYAPR10MB2888.namprd10.prod.outlook.com (2603:10b6:a03:88::32) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR10MB2888:EE_|IA0PR10MB6913:EE_ X-MS-Office365-Filtering-Correlation-Id: f09c474b-6a54-4436-715f-08db19066c15 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Xt2WhGGFnvWkJqjY9fKUGtLBFi2fi7PjP+s5vD4pawGwtLGcoRdsQaSr9NcgRmPffhObuk+T4RZKAZkyzDrBHJFtdbpQaAAAeVa4wQce6zssQFUF8tbdwn3OzYy1bMO0VfwcbZ/nTJWHhqK99Q3K6/Se85pvBA3qKsT1WK880CwTj8afZsZ7aJzza+JSnEhotPgRYDBh02rAbnJsvBJwsBpLrS3ytNuYU2nmoWb/pxShDyGJJsWhI1QCjeRgQGhGQnFuZfWTvn7IvIJzjdUWchyZMNOyZFxfq09+ZOweCXUeEp/vEcuAK7PDgLfj0wfDDpiUHSTxlV5ne0KF+yvS7iBW34dSEPod8MbnOBNdupv+uujgYY781IAevrJIvJt98VDw1lKbNyX0ZpUro4LfXZx3+ZHKrUF1L6J1Cd4DBF1gBXE8k4kRGlQhLKuzRMhfiLzJ4UVqfkcB6wDHY84k3QZZk5AylnqoY76t2l6KDC65okMOfyNKpySDO352uhskBak3UvT0Bcs7egCBjrdvQtSAXvBr83HDiBiPQykX7xhABViiayXoYh9BKmZ0ohIjRmthq9m7UvCO8Wv8Vig64/gST8q8H4UZSqnfDlIwNPf+uc7YEnPDTh0M/CxTEpXjPuUyodLFYZ7fD2KYqANYiQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BYAPR10MB2888.namprd10.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230025)(366004)(396003)(136003)(346002)(39860400002)(376002)(451199018)(36756003)(83380400001)(316002)(54906003)(4326008)(66476007)(8676002)(6916009)(38100700002)(6512007)(6506007)(2616005)(478600001)(186003)(26005)(6666004)(6486002)(5660300002)(66946007)(66556008)(2906002)(8936002)(86362001)(41300700001);DIR:OUT;SFP:1101; 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This is hopefully easier to understand by implementors looking to generate and/or consume bytes conforming BPF instructions. The patch also clarifies that the unused bytes in a pseudo-instruction shall be cleared with zeros. Signed-off-by: Jose E. Marchesi Acked-by: David Vernet --- Documentation/bpf/instruction-set.rst | 63 ++++++++++++++------------- 1 file changed, 33 insertions(+), 30 deletions(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 01802ed9b29b..fae2e48d6a0b 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -38,15 +38,11 @@ eBPF has two instruction encodings: * the wide instruction encoding, which appends a second 64-bit immediate (i.e., constant) value after the basic instruction for a total of 128 bits. -The basic instruction encoding looks as follows for a little-endian processor, -where MSB and LSB mean the most significant bits and least significant bits, -respectively: +The fields conforming an encoded basic instruction are stored in the +following order:: -============= ======= ======= ======= ============ -32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB) -============= ======= ======= ======= ============ -imm offset src_reg dst_reg opcode -============= ======= ======= ======= ============ + opcode:8 src:4 dst:4 offset:16 imm:32 // In little-endian BPF. + opcode:8 dst:4 src:4 offset:16 imm:32 // In big-endian BPF. **imm** signed integer immediate value @@ -54,48 +50,55 @@ imm offset src_reg dst_reg opcode **offset** signed integer offset used with pointer arithmetic -**src_reg** +**src** the source register number (0-10), except where otherwise specified (`64-bit immediate instructions`_ reuse this field for other purposes) -**dst_reg** +**dst** destination register number (0-10) **opcode** operation to perform -and as follows for a big-endian processor: +Note that the contents of multi-byte fields ('imm' and 'offset') are +stored using big-endian byte ordering in big-endian BPF and +little-endian byte ordering in little-endian BPF. -============= ======= ======= ======= ============ -32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB) -============= ======= ======= ======= ============ -imm offset dst_reg src_reg opcode -============= ======= ======= ======= ============ +For example:: -Multi-byte fields ('imm' and 'offset') are similarly stored in -the byte order of the processor. + opcode offset imm assembly + src dst + 07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little + dst src + 07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big Note that most instructions do not use all of the fields. Unused fields shall be cleared to zero. -As discussed below in `64-bit immediate instructions`_, a 64-bit immediate -instruction uses a 64-bit immediate value that is constructed as follows. -The 64 bits following the basic instruction contain a pseudo instruction -using the same format but with opcode, dst_reg, src_reg, and offset all set to zero, -and imm containing the high 32 bits of the immediate value. +As discussed below in `64-bit immediate instructions`_, a 64-bit +immediate instruction uses a 64-bit immediate value that is +constructed as follows. The 64 bits following the basic instruction +contain a pseudo instruction using the same format but with opcode, +dst, src, and offset all set to zero, and imm containing the high 32 +bits of the immediate value. -================= ================== -64 bits (MSB) 64 bits (LSB) -================= ================== -basic instruction pseudo instruction -================= ================== +This is depicted in the following figure:: + + basic_instruction + .-----------------------------. + | | + code:8 regs:16 offset:16 imm:32 unused:32 imm:32 + | | + '--------------' + pseudo instruction Thus the 64-bit immediate value is constructed as follows: imm64 = (next_imm << 32) | imm where 'next_imm' refers to the imm value of the pseudo instruction -following the basic instruction. +following the basic instruction. The unused bytes in the pseudo +instruction are reserved and shall be cleared to zero. Instruction classes ------------------- @@ -137,7 +140,7 @@ code source instruction class source value description ====== ===== ============================================== BPF_K 0x00 use 32-bit 'imm' value as source operand - BPF_X 0x08 use 'src_reg' register value as source operand + BPF_X 0x08 use 'src' register value as source operand ====== ===== ============================================== **instruction class**