From patchwork Mon Jan 28 23:06:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785043 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB57313B4 for ; Mon, 28 Jan 2019 23:07:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DB17E2B26C for ; Mon, 28 Jan 2019 23:07:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF5522B505; Mon, 28 Jan 2019 23:07:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4842A2B4D5 for ; Mon, 28 Jan 2019 23:07:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726678AbfA1XHF (ORCPT ); Mon, 28 Jan 2019 18:07:05 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:36621 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726937AbfA1XHF (ORCPT ); Mon, 28 Jan 2019 18:07:05 -0500 Received: by mail-wr1-f68.google.com with SMTP id u4so20021100wrp.3 for ; Mon, 28 Jan 2019 15:07:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mathembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=LnhuCvA6OBCsc6Z3TyYYS/ECd+d6SFx0/EIU5NWss9Y=; b=MJxexMlC/kk4jtZXRXsP8Mf+uHKo/2Oj0UoMDuRrdB0EN41BZo5UGWfzOz0vKBKu6F GSUUY+0/yJtAjnUEu/piprlmSNXnvsNazQh6kwLkFmyJMIoKs8FA1IP91FMQcYUHVJU/ zQ21RSf/HdA2AhpyUKHhFJz9DqsimPwvdGIuXk76F2mi5WGsJiQz0NRkhb9k4Z/G+jAX 8IrwpzhRvGTtJfDmsR4DXWvlU55Ob+6YPrEVzYJ61soW3UcH+CuER2D33PJ4kF2X6snA LsBDHjZGB+MKibEtpI0hotritOWauk/8RNO3ILvO6WK5N3zwSMM3x2h6oFvCSkzwf077 /Z5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=LnhuCvA6OBCsc6Z3TyYYS/ECd+d6SFx0/EIU5NWss9Y=; b=MZ0MwZ3AdWhLR+jndzi1ApdwkkTSbuNHMM/P7XqWx7IwWsbC7ighp4W4aJ8NIMai0K WVIJh8frCwBvcXfzkZUucYr4pOwhzOSVy20XR6FyFr0seS5BM3vu6V1xWlbRwUg8wSa2 LK+WFLFKgB6KU9g5ylnvJtEGLRLoGRl5FNPNhIk/t/audXm5/Pp2QcLTf3vitTj1Duvd F3kW7g3/drj3A9MNKIeLXEMkuAFDdYPPEXgyR4Evn7SJkiQhyIyvqXvrTgl5YCD5IFuv 8pJUo2PUmxFxo0GuUlEYNHFXNZ6NcnMFmJGhLWRWCB7gBRHu/EEdUyqy9Odm8RkjMU/a Ps4w== X-Gm-Message-State: AJcUukdVFYj0pSfcX0/F/e3P8flaUxEb0z/lvA/o1sds5dn1uhROd87o iNr4jHRTIh0tlwmRImsj9Zde+8OQzz6hvw== X-Google-Smtp-Source: ALg8bN6iLoftyqASt6rwtOWuAlBBHY6zob/DK0D24baBpfu1IIngmBSrN6Z9iwpodNlNXg3wPzf9vQ== X-Received: by 2002:adf:8b83:: with SMTP id o3mr24287502wra.81.1548716823649; Mon, 28 Jan 2019 15:07:03 -0800 (PST) Received: from diamond.mathembedded.com (host86-176-243-190.range86-176.btcentralplus.com. [86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.02 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:02 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 01/17] clocksource: exynos_mct: Clear timer interrupt when stopping Date: Mon, 28 Jan 2019 23:06:44 +0000 Message-Id: <20190128230700.7325-2-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Ensure that after we have stopped the timer any pending interrupts are cleared. This fixes a problem when suspending, as interrupts are disabled before the timer is stopped, so the timer interrupt may still be asserted, preventing the system entering a low power state when the wfi is executed. Signed-off-by: Stuart Menefy --- drivers/clocksource/exynos_mct.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 7a244b681876..c99d0b6e8b5f 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -398,12 +398,15 @@ static int exynos4_tick_set_next_event(unsigned long cycles, return 0; } +static void exynos4_mct_tick_clear(struct mct_clock_event_device *mevt); + static int set_state_shutdown(struct clock_event_device *evt) { struct mct_clock_event_device *mevt; mevt = container_of(evt, struct mct_clock_event_device, evt); exynos4_mct_tick_stop(mevt); + exynos4_mct_tick_clear(mevt); return 0; } From patchwork Mon Jan 28 23:06:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785047 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 86B7491E for ; Mon, 28 Jan 2019 23:07:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 76AEA2B26C for ; Mon, 28 Jan 2019 23:07:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6B47C2B4D5; Mon, 28 Jan 2019 23:07:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 227AA2B4D0 for ; Mon, 28 Jan 2019 23:07:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726937AbfA1XHG (ORCPT ); Mon, 28 Jan 2019 18:07:06 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:37226 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726954AbfA1XHG (ORCPT ); Mon, 28 Jan 2019 18:07:06 -0500 Received: by mail-wr1-f65.google.com with SMTP id s12so19997170wrt.4 for ; Mon, 28 Jan 2019 15:07:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mathembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=PiHkZ/5jaqPnV3WBhCp06Z6bYFbrn9HV5SsnU88DseI=; b=OuVTUL++4WG5WVqEvmM93hvvWXpdm9O0q8YYqHhgOy3I5VxAtUkqDIb3VyoVaH9MSV 2aOCTbZ4Nl+hmilJcmoP5nL+e5nFzyxkWqI322suaMXKcPCSKX6W1OhKDJ1M6CO3a23n kZEzKjsqUNLCjcblg9Dj7NxtbefgVtwzpXfY5++FEqcIhONTEZPpoWLbV0D8AMX0/7NX wLw99rK8m+L63crFgv7ljSlDLj1YjikbN1zjK8fhfSWpJtURoTb/3YDfkoFfkfCVtE/c bj57vQcZU1v2U04jE50jxboShdh/ojRpwieadgTT0sQz1JILTJvCvtP5+tTdV1bpRwwE M/hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=PiHkZ/5jaqPnV3WBhCp06Z6bYFbrn9HV5SsnU88DseI=; b=cKrtUj39OB3ZJydQ1WLQAdkXB5jY5Izjw/IAWAkzd+d+AqqtDfqv6ndvHZsNftI68g ecDCmbWAb68wSKGCJeT0K44PpKoTfuQH7qtU0p4tXs1NmtcLnnixEYH5fwTp/yKOp139 qZEt3SsTssSnr2Ki5wGfAp/5KbmIVo6pRl7MN2RM6mDWIvZUJmV2+Q/+UgyFTfj8PtMZ kNiuRsbUZ6QL/F8XvmJKhLgBHIbR7I31LCXxt1RyO1KBbh1GDEM67c5FTp0MFwqNDVN/ CX+FCo6UI/67uWQeSIJh8B/nv2n8brRPdN5SB5M9TamUQZtl5J7ortzV+/iUbx3ClBks Md/g== X-Gm-Message-State: AJcUukcnenwMNCNWsX+6DfXRpwgGCTi/Y0OcyyOtfZ/EqADM//GXbHa7 fI5lJ2QRNqhLpt06pEX/95rc+y6B29q0UQ== X-Google-Smtp-Source: ALg8bN42Yj7a+dFVCgUAxXPmLXejqLUTw1RyNVCmbZ/TSITniwKRABQb9gmFGdBdNy1h5l7Xly0n1w== X-Received: by 2002:adf:fdc2:: with SMTP id i2mr24341001wrs.117.1548716824774; Mon, 28 Jan 2019 15:07:04 -0800 (PST) Received: from diamond.mathembedded.com (host86-176-243-190.range86-176.btcentralplus.com. [86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:03 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 02/17] ARM: EXYNOS: Fix timeout booting secondary CPUs Date: Mon, 28 Jan 2019 23:06:45 +0000 Message-Id: <20190128230700.7325-3-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Without this fix the loop waiting for the timeout exits, but the subsequent test to see if the timeout occurred fails. Signed-off-by: Stuart Menefy --- arch/arm/mach-exynos/platsmp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index c39ffd2e2fe6..b6da7edbbd2f 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -336,9 +336,9 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) /* wait max 10 ms until cpu1 is on */ while (exynos_cpu_power_state(core_id) != S5P_CORE_LOCAL_PWR_EN) { - if (timeout-- == 0) + if (timeout == 0) break; - + timeout--; mdelay(1); } From patchwork Mon Jan 28 23:06:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785051 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 058E7184E for ; Mon, 28 Jan 2019 23:07:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E8E8A2B26C for ; Mon, 28 Jan 2019 23:07:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DCF412B510; Mon, 28 Jan 2019 23:07:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4B19A2B26C for ; Mon, 28 Jan 2019 23:07:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727032AbfA1XHJ (ORCPT ); Mon, 28 Jan 2019 18:07:09 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:42908 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726954AbfA1XHI (ORCPT ); Mon, 28 Jan 2019 18:07:08 -0500 Received: by mail-wr1-f68.google.com with SMTP id q18so19992851wrx.9 for ; Mon, 28 Jan 2019 15:07:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mathembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=jsBHs2CK3nLuHA2I3owN1Z6eytC91gTcHVh1xEoYkKA=; b=LjsMhqNdKxW3oEeSf+7U3Seo90PHd/T4L8kifMyvVu5gl3b4Ox++/zsh28qaW7uWuq n1QLgbk8q3iq+J0Xrb/iwfTNLl+GDRcBb3JoUU8qJ/PVyhePucxUQNbWt2DmE02aptOz EM3HdMf+p2m1oHNOevHKFSmLekCcppwteDzu7yYz27wkRYCy5qklagcnjdDVSxB+cfbp yIbxj16KbNLUsuRo30evKsP+3Tgm8DyI70CCoyIYLNt8lmgURx++w7tKQUev342q0jTL AF7gmDuESUpMT/rGabWJqAhrEfD2rFok2VVhUg0go5idRnOx9qdrq4GwA9ymOqssTqhI CrSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=jsBHs2CK3nLuHA2I3owN1Z6eytC91gTcHVh1xEoYkKA=; b=MIZk6DYGw+S8ty+l+fypuvdnERJZCJmSV+OvnVYI8xHP6op88PU87luVsFepA5punP fgL1XakCohLpA98WeRq7mvigw20A9RpbwoaEKqOlBvUMYxihsn7IWWVOqTJl4M0DSvM7 34xsI053WFmmhdG/ljjG8xD6OWX9wsUwuYqGWezZXM+X6rQUZyDSQlSAdwM9tM3C8M8s 8VsfXugRRoO21UHoVQEx8MzyF4bz2pIyZYH9g+sDm1+WRF9jHbo9GAkN/O4JbmQOaQ29 vIs+M4uMujNpEBdDbZFagC0CSjX9TLctpMRlKWzP31avdFZkBXykndnAKs3lwLAOSxBi iGiw== X-Gm-Message-State: AHQUAub2xWVnlAIasiLKtFbablrq7TiR9Lhu47ADxg+PH5Ym7b0wDZ8W uG6G8wgeU3YJsV5VtfpER4dXfP5f8duNPg== X-Google-Smtp-Source: AHgI3IbbOI45T7/VnhKkUmpzzUAZPfsUy+xW+WtClgRTx2ztL/udaRnzabLuSnUaAK6PE+YtiQ35WA== X-Received: by 2002:adf:8484:: with SMTP id 4mr17129172wrg.249.1548716825659; Mon, 28 Jan 2019 15:07:05 -0800 (PST) Received: from diamond.mathembedded.com (host86-176-243-190.range86-176.btcentralplus.com. [86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:05 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 03/17] mfd: sec: Add support for the RTC on S2MPA01 Date: Mon, 28 Jan 2019 23:06:46 +0000 Message-Id: <20190128230700.7325-4-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The RTC on the S2MPA01 is largely the same as that on other Samsung PMIC devices, so adding support for it just involves configuring it and describing the interrupt registers. Signed-off-by: Stuart Menefy --- drivers/mfd/sec-core.c | 2 ++ drivers/mfd/sec-irq.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/rtc/rtc-s5m.c | 15 ++++++++ 3 files changed, 114 insertions(+) diff --git a/drivers/mfd/sec-core.c b/drivers/mfd/sec-core.c index e0835c9df7a1..911381414334 100644 --- a/drivers/mfd/sec-core.c +++ b/drivers/mfd/sec-core.c @@ -103,6 +103,8 @@ static const struct mfd_cell s2mps15_devs[] = { static const struct mfd_cell s2mpa01_devs[] = { { .name = "s2mpa01-pmic", + }, { + .name = "s2mpa01-rtc", }, }; diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c index ad0099077e7e..7cc863b07384 100644 --- a/drivers/mfd/sec-irq.c +++ b/drivers/mfd/sec-irq.c @@ -11,12 +11,96 @@ #include #include +#include #include #include #include #include #include +static struct regmap_irq s2mpa01_irqs[] = { + [S2MPA01_IRQ_PWRONF] = { + .reg_offset = 0, + .mask = S2MPA01_IRQ_PWRONF_MASK, + }, + [S2MPA01_IRQ_PWRONR] = { + .reg_offset = 0, + .mask = S2MPA01_IRQ_PWRONR_MASK, + }, + [S2MPA01_IRQ_JIGONBF] = { + .reg_offset = 0, + .mask = S2MPA01_IRQ_JIGONBF_MASK, + }, + [S2MPA01_IRQ_JIGONBR] = { + .reg_offset = 0, + .mask = S2MPA01_IRQ_JIGONBR_MASK, + }, + [S2MPA01_IRQ_ACOKBF] = { + .reg_offset = 0, + .mask = S2MPA01_IRQ_ACOKBF_MASK, + }, + [S2MPA01_IRQ_ACOKBR] = { + .reg_offset = 0, + .mask = S2MPA01_IRQ_ACOKBR_MASK, + }, + [S2MPA01_IRQ_PWRON1S] = { + .reg_offset = 0, + .mask = S2MPA01_IRQ_PWRON1S_MASK, + }, + [S2MPA01_IRQ_MRB] = { + .reg_offset = 0, + .mask = S2MPA01_IRQ_MRB_MASK, + }, + [S2MPA01_IRQ_RTC60S] = { + .reg_offset = 1, + .mask = S2MPA01_IRQ_RTC60S_MASK, + }, + [S2MPA01_IRQ_RTCA1] = { + .reg_offset = 1, + .mask = S2MPA01_IRQ_RTCA1_MASK, + }, + [S2MPA01_IRQ_RTCA0] = { + .reg_offset = 1, + .mask = S2MPA01_IRQ_RTCA0_MASK, + }, + [S2MPA01_IRQ_SMPL] = { + .reg_offset = 1, + .mask = S2MPA01_IRQ_SMPL_MASK, + }, + [S2MPA01_IRQ_RTC1S] = { + .reg_offset = 1, + .mask = S2MPA01_IRQ_RTC1S_MASK, + }, + [S2MPA01_IRQ_WTSR] = { + .reg_offset = 1, + .mask = S2MPA01_IRQ_WTSR_MASK, + }, + [S2MPA01_IRQ_INT120C] = { + .reg_offset = 2, + .mask = S2MPA01_IRQ_INT120C_MASK, + }, + [S2MPA01_IRQ_INT140C] = { + .reg_offset = 2, + .mask = S2MPA01_IRQ_INT140C_MASK, + }, + [S2MPA01_IRQ_LDO3_TSD] = { + .reg_offset = 2, + .mask = S2MPA01_IRQ_LDO3_TSD_MASK, + }, + [S2MPA01_IRQ_B16_TSD] = { + .reg_offset = 2, + .mask = S2MPA01_IRQ_B16_TSD_MASK, + }, + [S2MPA01_IRQ_B24_TSD] = { + .reg_offset = 2, + .mask = S2MPA01_IRQ_B24_TSD_MASK, + }, + [S2MPA01_IRQ_B35_TSD] = { + .reg_offset = 2, + .mask = S2MPA01_IRQ_B35_TSD_MASK, + }, +}; + static const struct regmap_irq s2mps11_irqs[] = { [S2MPS11_IRQ_PWRONF] = { .reg_offset = 0, @@ -372,6 +456,16 @@ static const struct regmap_irq s5m8763_irqs[] = { }, }; +static struct regmap_irq_chip s2mpa01_irq_chip = { + .name = "s2mpa01", + .irqs = s2mpa01_irqs, + .num_irqs = ARRAY_SIZE(s2mpa01_irqs), + .num_regs = 3, + .status_base = S2MPA01_REG_INT1, + .mask_base = S2MPA01_REG_INT1M, + .ack_base = S2MPA01_REG_INT1, +}; + static const struct regmap_irq_chip s2mps11_irq_chip = { .name = "s2mps11", .irqs = s2mps11_irqs, @@ -455,6 +549,9 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic) case S5M8767X: sec_irq_chip = &s5m8767_irq_chip; break; + case S2MPA01: + sec_irq_chip = &s2mpa01_irq_chip; + break; case S2MPS11X: sec_irq_chip = &s2mps11_irq_chip; break; diff --git a/drivers/rtc/rtc-s5m.c b/drivers/rtc/rtc-s5m.c index c7f1bf823ea0..0f7623a57e74 100644 --- a/drivers/rtc/rtc-s5m.c +++ b/drivers/rtc/rtc-s5m.c @@ -246,6 +246,7 @@ static int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info *info, ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val); val &= S5M_ALARM0_STATUS; break; + case S2MPA01: case S2MPS15X: case S2MPS14X: case S2MPS13X: @@ -309,6 +310,7 @@ static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info) case S5M8767X: data &= ~S5M_RTC_TIME_EN_MASK; break; + case S2MPA01: case S2MPS15X: case S2MPS14X: case S2MPS13X: @@ -396,6 +398,7 @@ static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm) break; case S5M8767X: + case S2MPA01: case S2MPS15X: case S2MPS14X: case S2MPS13X: @@ -422,6 +425,7 @@ static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm) s5m8763_tm_to_data(tm, data); break; case S5M8767X: + case S2MPA01: case S2MPS15X: case S2MPS14X: case S2MPS13X: @@ -469,6 +473,7 @@ static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) break; case S5M8767X: + case S2MPA01: case S2MPS15X: case S2MPS14X: case S2MPS13X: @@ -513,6 +518,7 @@ static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info) break; case S5M8767X: + case S2MPA01: case S2MPS15X: case S2MPS14X: case S2MPS13X: @@ -557,6 +563,7 @@ static int s5m_rtc_start_alarm(struct s5m_rtc_info *info) break; case S5M8767X: + case S2MPA01: case S2MPS15X: case S2MPS14X: case S2MPS13X: @@ -598,6 +605,7 @@ static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) break; case S5M8767X: + case S2MPA01: case S2MPS15X: case S2MPS14X: case S2MPS13X: @@ -679,6 +687,7 @@ static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info) ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2); break; + case S2MPA01: case S2MPS15X: case S2MPS14X: case S2MPS13X: @@ -728,6 +737,11 @@ static int s5m_rtc_probe(struct platform_device *pdev) return -ENOMEM; switch (platform_get_device_id(pdev)->driver_data) { + case S2MPA01: + regmap_cfg = &s2mps14_rtc_regmap_config; + info->regs = &s2mps14_rtc_regs; + alarm_irq = S2MPA01_IRQ_RTCA0; + break; case S2MPS15X: regmap_cfg = &s2mps14_rtc_regmap_config; info->regs = &s2mps15_rtc_regs; @@ -861,6 +875,7 @@ static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume); static const struct platform_device_id s5m_rtc_id[] = { { "s5m-rtc", S5M8767X }, + { "s2mpa01-rtc", S2MPA01 }, { "s2mps13-rtc", S2MPS13X }, { "s2mps14-rtc", S2MPS14X }, { "s2mps15-rtc", S2MPS15X }, From patchwork Mon Jan 28 23:06:47 2019 Content-Type: text/plain; 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[86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.05 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:05 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 04/17] regulator: s2mpa01: Fix step values for some LDOs Date: Mon, 28 Jan 2019 23:06:47 +0000 Message-Id: <20190128230700.7325-5-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The step values for some of the LDOs appears to be incorrect, resulting in incorrect voltages (or at least, ones which are different from the Samsung 3.4 kernel). Signed-off-by: Stuart Menefy Reviewed-by: Krzysztof Kozlowski --- drivers/regulator/s2mpa01.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/regulator/s2mpa01.c b/drivers/regulator/s2mpa01.c index 095d25f3d2ea..58a1fe583a6c 100644 --- a/drivers/regulator/s2mpa01.c +++ b/drivers/regulator/s2mpa01.c @@ -298,13 +298,13 @@ static const struct regulator_desc regulators[] = { regulator_desc_ldo(2, STEP_50_MV), regulator_desc_ldo(3, STEP_50_MV), regulator_desc_ldo(4, STEP_50_MV), - regulator_desc_ldo(5, STEP_50_MV), + regulator_desc_ldo(5, STEP_25_MV), regulator_desc_ldo(6, STEP_25_MV), regulator_desc_ldo(7, STEP_50_MV), regulator_desc_ldo(8, STEP_50_MV), regulator_desc_ldo(9, STEP_50_MV), regulator_desc_ldo(10, STEP_50_MV), - regulator_desc_ldo(11, STEP_25_MV), + regulator_desc_ldo(11, STEP_50_MV), regulator_desc_ldo(12, STEP_50_MV), regulator_desc_ldo(13, STEP_50_MV), regulator_desc_ldo(14, STEP_50_MV), @@ -315,11 +315,11 @@ static const struct regulator_desc regulators[] = { regulator_desc_ldo(19, STEP_50_MV), regulator_desc_ldo(20, STEP_50_MV), regulator_desc_ldo(21, STEP_50_MV), - regulator_desc_ldo(22, STEP_25_MV), - regulator_desc_ldo(23, STEP_25_MV), + regulator_desc_ldo(22, STEP_50_MV), + regulator_desc_ldo(23, STEP_50_MV), regulator_desc_ldo(24, STEP_50_MV), regulator_desc_ldo(25, STEP_50_MV), - regulator_desc_ldo(26, STEP_50_MV), + regulator_desc_ldo(26, STEP_25_MV), regulator_desc_buck1_4(1), regulator_desc_buck1_4(2), regulator_desc_buck1_4(3), From patchwork Mon Jan 28 23:06:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785053 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D2AF891E for ; Mon, 28 Jan 2019 23:07:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C2D412B26C for ; Mon, 28 Jan 2019 23:07:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B75CD2B4D0; Mon, 28 Jan 2019 23:07:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 60E542B26C for ; Mon, 28 Jan 2019 23:07:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727034AbfA1XHK (ORCPT ); Mon, 28 Jan 2019 18:07:10 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:40333 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727006AbfA1XHJ (ORCPT ); Mon, 28 Jan 2019 18:07:09 -0500 Received: by mail-wm1-f66.google.com with SMTP id f188so15700476wmf.5 for ; Mon, 28 Jan 2019 15:07:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mathembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=P8mllz0KMgQrspybiLoEzeCMuG9uaqyD0z9whkWfzKE=; b=jfQRkV5F5Ir+c0YGbfb9M+4lA0QGZ3x4TGH4RqTPk4B/qoMD90ypdMBrpUwV6DVW2y 8JO1RRehTq14DYTr+ccmt/a8FkAFuBbiBZPEIKWzUzgj8ViYIIfu4WGd2Y8UdEIX7R3V rqH58zdcNdig0EdP1ZxcyXicnC8OEM5zRH1HJC+pzlLx7tD+2dsnIHSOaM2J6jD+8cQ5 v/zvvFzQHnztmQLgtf502ABatbqFpWsbiIV92pEDJ+zd+wGgq2w/6G4M8BGFUAuh2/Sb YQxusttllnBtIaYmfjwo2CzNzaVjgcE0ymGEEuBra0hngWIsdNWypqV02Whs6NRHj8w/ nhag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=P8mllz0KMgQrspybiLoEzeCMuG9uaqyD0z9whkWfzKE=; b=jRl2h1T3rc38foCRoFH8R9vykYOjSJQwjR4mT5bYSxd2MStHR35lRWiwrDFNLyvAhH MiofX4sFM+c3jJZCn5yonKBH6nPHpj7WnC862mNxRmyZwtF0g7A8SUMWFxhIPi+E9jdn XzcWF3xKSXG83UJfbEWn1+qTNGpf2bmzAknPIn7Dta8GBySz8LPcUPxJUMvtEcxf1n95 LkEYzew7UgdBbJUAPaHQvggi/6VoUr1AP238sr3Lm1JAn3j8FN1cI1No+DXYv8ScfPVX F/vVmV9axNmRKuId2pEnePe1SG0jLIlISBy0P3ZQm6DlQ+n1n4Fh9l5vxlE64ILZDw/2 oMsg== X-Gm-Message-State: AJcUukdyA8afBUbq9yVaXA32Y3YcznbsHXdv8A6xRygDxCPWKPZpWbkz o72TjD9y/udHOynbiq0LGNtgLyucqHy3hQ== X-Google-Smtp-Source: ALg8bN7OU88FhnN1JMqLpwgVf9WjztvYjOcowWC2tZUsYoqfxb/38abdDOFRJbaFi66+Kt3AYAyNgw== X-Received: by 2002:a1c:e910:: with SMTP id q16mr17617929wmc.68.1548716827685; Mon, 28 Jan 2019 15:07:07 -0800 (PST) Received: from diamond.mathembedded.com (host86-176-243-190.range86-176.btcentralplus.com. [86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.06 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:06 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 05/17] ARM: dts: exynos: Use bustop PLL as the source for MMC clocks on Exynos5260 Date: Mon, 28 Jan 2019 23:06:48 +0000 Message-Id: <20190128230700.7325-6-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP By default the MMC clock will be derived from mediatop PLL, which usually runs at 666MHz. However as most SD and MMC clocks are multiples or fractions of 100MHz, it makes more sense to use the bustop PLL which runs at 800MHz. Signed-off-by: Stuart Menefy --- arch/arm/boot/dts/exynos5260.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 55167850619c..14b423de9137 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -288,6 +288,14 @@ #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>; clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC0>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; fifo-depth = <64>; status = "disabled"; }; @@ -300,6 +308,14 @@ #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>; clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC1>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; fifo-depth = <64>; status = "disabled"; }; @@ -312,6 +328,14 @@ #size-cells = <0>; clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>; clock-names = "biu", "ciu"; + assigned-clocks = + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B>, + <&clock_top TOP_SCLK_MMC2>; + assigned-clock-parents = + <&clock_top TOP_MOUT_BUSTOP_PLL_USER>, + <&clock_top TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A>; + assigned-clock-rates = <0>, <0>, <800000000>; fifo-depth = <64>; status = "disabled"; }; From patchwork Mon Jan 28 23:06:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A93FC13B4 for ; Mon, 28 Jan 2019 23:07:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 99D752B26C for ; Mon, 28 Jan 2019 23:07:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8EA492B4D0; Mon, 28 Jan 2019 23:07:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 350A62B26C for ; Mon, 28 Jan 2019 23:07:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727043AbfA1XHK (ORCPT ); Mon, 28 Jan 2019 18:07:10 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:32887 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727000AbfA1XHK (ORCPT ); Mon, 28 Jan 2019 18:07:10 -0500 Received: by mail-wm1-f66.google.com with SMTP id r24so11596302wmh.0 for ; Mon, 28 Jan 2019 15:07:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mathembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=FL9IzS4epoUJIGvWIEmwGM4W9GvbMIhGZGs0QVmYhdQ=; b=0YLS/Irx+5UkInTDzRxYwBhJ0apGIDjMxHi2kossT2mkK3Zr+DqMS+BrsPY+RjwVR/ +qYBFwZE9WaDZwgUkCqdqpwkCQaKkdXyOHGSKBUhSryXnAUK8pNFDAzitFyL31DtPMqZ uo+C3TfI2Kt/XedVYeHxyYBmK++C+nibFR9QjZ6MM31MP97nDSvz4kIOzsB/4HHLo6Pp C8LIEXiEUVS1LcU4Yktz+tErvhXwylAoHp5FN1DxHWmcgaIXSCts4OxHvwaynyAlAWx5 QAtKKDXEVIsOd9Iu7xLq4mSgI2WAIzeVl4eem+KWhzD/YqQRWadnpuPHbgp5KTcY1NjY x8ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=FL9IzS4epoUJIGvWIEmwGM4W9GvbMIhGZGs0QVmYhdQ=; b=NmmdXlKk4UWlwPDeaqO3Jov63Wi+8C6XNt05EvC2taYiHOX/zktx0IDgLF9aoTJI5t gWhBJUZ/teP5REq7lA4tcSDZsvLLC42A1oCNCl5XDZ7o16+ci0VueVrlnlpKo0FSyyVL vW6m6GJov0apoaPw2UUWStrbs/uWpe649tYh6OS+5QWC6TkBCZmuYcJu6JM5j1Bx5nAM pD4M/AJbMQ7TXI5IQEnfMkU4kw5WbxFH8pZWF5f2FNHCdSoIbrCMJVTZWnOZAoLG486q rXOJgYojc2c+yRdqJj2Who0DfB3KMbELctEhQ2bIVzRgR/ROzQAkvuMh6KU7qA9eHHii /I3w== X-Gm-Message-State: AJcUukcDCSGsk1oJlbYysnM0N7KUrFGZzzW8dAXfNdXPnVJciZLSGcmU tj37d1THnfFJoThyvTgBaQTAKyjbm2o+Lw== X-Google-Smtp-Source: ALg8bN4qJEJUu2uiDmA08Cj/k5aqnaXl4/WZYHd3Cin4kVHbS8hyQGMKpuR41HIPBtIkDvZANHzLgw== X-Received: by 2002:a1c:20cb:: with SMTP id g194mr18248556wmg.77.1548716828765; Mon, 28 Jan 2019 15:07:08 -0800 (PST) Received: from diamond.mathembedded.com (host86-176-243-190.range86-176.btcentralplus.com. [86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:07 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 06/17] ARM: dts: exynos: Add high speed I2C ports for exynos5260 Date: Mon, 28 Jan 2019 23:06:49 +0000 Message-Id: <20190128230700.7325-7-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the missing high speed I2C ports. Signed-off-by: Stuart Menefy --- arch/arm/boot/dts/exynos5260.dtsi | 57 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 14b423de9137..5f75ff422043 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -17,6 +17,10 @@ #size-cells = <1>; aliases { + i2c0 = &hsi2c_0; + i2c1 = &hsi2c_1; + i2c2 = &hsi2c_2; + i2c3 = &hsi2c_3; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; @@ -176,6 +180,59 @@ reg = <0x10000000 0x100>; }; + hsi2c_0: hsi2c@12DA0000 { + compatible = "samsung,exynos5260-hsi2c"; + reg = <0x12DA0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC0>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_1: hsi2c@12DB0000 { + compatible = "samsung,exynos5260-hsi2c"; + reg = <0x12DB0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC1>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_2: hsi2c@12DC0000 { + compatible = "samsung,exynos5260-hsi2c"; + reg = <0x12DC0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC2>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_3: hsi2c@12DD0000 { + compatible = "samsung,exynos5260-hsi2c"; + samsung,check-transdone-int; + reg = <0x12DD0000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_hs_bus>; + clocks = <&clock_peri PERI_CLK_HSIC3>; + clock-names = "hsi2c"; + status = "disabled"; + }; + mct: mct@100b0000 { compatible = "samsung,exynos4210-mct"; reg = <0x100B0000 0x1000>; From patchwork Mon Jan 28 23:06:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785057 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AFC9213B4 for ; Mon, 28 Jan 2019 23:07:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9F5B72B26C for ; Mon, 28 Jan 2019 23:07:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 93CBB2B4D0; Mon, 28 Jan 2019 23:07:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 443A42B26C for ; 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[86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.08 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:09 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 07/17] ARM: dts: exynos: Add interrupts for dedicated EINTs on Exynos5260 Date: Mon, 28 Jan 2019 23:06:50 +0000 Message-Id: <20190128230700.7325-8-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the missing interrupt information for the GPIO lines with dedicated EINT interrupts. Signed-off-by: Stuart Menefy --- arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi index b1edb20b789e..17e2f3e0d71e 100644 --- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -153,6 +153,14 @@ #gpio-cells = <2>; interrupt-controller; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; @@ -161,6 +169,14 @@ #gpio-cells = <2>; interrupt-controller; + interrupts = , + , + , + , + , + , + , + ; #interrupt-cells = <2>; }; From patchwork Mon Jan 28 23:06:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785059 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D54BC91E for ; Mon, 28 Jan 2019 23:07:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C578D2B26C for ; Mon, 28 Jan 2019 23:07:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B9FC62B4D0; Mon, 28 Jan 2019 23:07:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5DC322B26C for ; Mon, 28 Jan 2019 23:07:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727048AbfA1XHN (ORCPT ); Mon, 28 Jan 2019 18:07:13 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:39697 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727000AbfA1XHM (ORCPT ); Mon, 28 Jan 2019 18:07:12 -0500 Received: by mail-wm1-f66.google.com with SMTP id y8so15720090wmi.4 for ; Mon, 28 Jan 2019 15:07:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mathembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=P8fADFJfsdGKMuxKeeoBkO7l6Gq5ey8OIxyJOauZT5Y=; b=c271NLVNLmArD8YIrY2wbwZfNQ3xppBEL6/mSmSkU3O8SvRLenYDauseckJAO81LLs uf11KEdEeQePRRUh2qq0R5AgABvSNQ2vzznC0Y3rlujceLkhRL6VM8uw2DAznR+UZ8wX kcHPWn0Z2ykKq6Xf9j+qAJOEpIkbC0XHY/AQWkHtIAH/g7yDJP+oYV1SQVsfiVRH0YVv jynEw9u0aH5/fPv3BUjpt/wSQ2cabqL5FlJLTqd1XtlB2LTZtkjx5hpY+is+w9e+bdlk 2xAfG+95TkBpYgwdaFyGVkEgGabuyaefZ/AjYzQ0cXdOSkmzWeSZ0sIWudIy5s7HvWLz DX6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=P8fADFJfsdGKMuxKeeoBkO7l6Gq5ey8OIxyJOauZT5Y=; b=FedIjpc22cqmdHRh8VLji5unrwguRiQKKbagO1A/2HUJ60Wh9dkEUpNECtCmjEbvOq oO600U1HKvdE/Pp5/lyvd6EzfFU63mDMgkzovItTXdkzxSqTwWVpP95oKLOsmEbt/X0i s6x1zdhpTevMitQlWq66etfEbX3SJ1BlG6tFoiIsttkmbr6SWSQ/k2bgB3jAi5ubWjPM p0/FDxgFpz0qF2fbJ30BYzsJcRTn/NO2G46w/5I6KgVGRp73MSIpRxjHyF62GD333TOt Ta5r0HbudwMWotjeh8DfVVbk+e0dsT/ORP14BwdDpZ28VWaKL2jZ11G5W/rLR2kaxgbJ XefA== X-Gm-Message-State: AJcUukc//wj3rOM4EIBNNoWmRd06hBa0UtTQ7M6Ef12qM+Z/S2N85OaV gukb5kff5u0FzS3JdxFCAfAyLliTjk06XA== X-Google-Smtp-Source: ALg8bN6ha15ZbGAij4/jPkjBe0PWpYOL1tddyyXkGgnkRvMl849pCeB5fOlgmmgjk28y26iast8PPw== X-Received: by 2002:a1c:5604:: with SMTP id k4mr18091564wmb.107.1548716830820; Mon, 28 Jan 2019 15:07:10 -0800 (PST) Received: from diamond.mathembedded.com (host86-176-243-190.range86-176.btcentralplus.com. [86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.09 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:10 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 08/17] ARM: dts: exynos: Fix interrupt for shared EINTs on Exynos5260 Date: Mon, 28 Jan 2019 23:06:51 +0000 Message-Id: <20190128230700.7325-9-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fix the interrupt information for the GPIO lines with a shared EINT interrupt. Signed-off-by: Stuart Menefy --- arch/arm/boot/dts/exynos5260.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 5f75ff422043..84c9b4443dc6 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -280,7 +280,7 @@ wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; - interrupts = ; + interrupts = ; }; }; From patchwork Mon Jan 28 23:06:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785065 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4CCA7184E for ; Mon, 28 Jan 2019 23:07:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A5C62B26C for ; Mon, 28 Jan 2019 23:07:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2E8512B4D0; Mon, 28 Jan 2019 23:07:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 17CCE2B26C for ; Mon, 28 Jan 2019 23:07:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727000AbfA1XHP (ORCPT ); Mon, 28 Jan 2019 18:07:15 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:44507 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727006AbfA1XHP (ORCPT ); Mon, 28 Jan 2019 18:07:15 -0500 Received: by mail-wr1-f67.google.com with SMTP id z5so19973242wrt.11 for ; Mon, 28 Jan 2019 15:07:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mathembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=5eESpU8TRdwPoosN34EY/5EHNp0K6UWIjr74/39yaOQ=; b=dQuSi+IvWbKahXWHixY4qMLH0+XRUSLOlI1YJVh/UGlVQIN2jYtmazTMyu66uc0afm oqRb7hgMvH8OSf1e+9AK7ZwTVYRNDNt69Zb0qvTK8uXSfI3OLhZndL/5wZN0iYVN02tq fj5c7YMW6mvBG8hotombEWIDQht5PRy72sWLkiGTZEj5VrbRmafP/1FFJTwNna/MZ716 U3/RZvRhzBNDgGrnYW/rZNgIPo7YMmjd0WPsG/5vWvuMy3+aK+8BttzVK1qwBgN6AVbd vYsdmDF4L8VmC6K3aKnHhdYj+w8TuaGtPJ1FMEJ4ZLpNtDuSD2sZKbSzCMGKuAyXWjli z/Ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=5eESpU8TRdwPoosN34EY/5EHNp0K6UWIjr74/39yaOQ=; b=J7xXVvAZ6byqzqkwRzI/aGqhRst5VUz+cnPggeRYFd4Pl6ME+EPk61S//9EZ05v7Dc KZJQidV3tnmEYcdiVNlnIFkJ1zwnJ2k97kf2H1wfNeRZhjwVVoWD6o6uT0Lbh+u2Kd0q Z7ECVcfZtfhUJEUOMs2N+VaSeNkaht48rDZM6+S7SX8BJ7a4jWIrYRD6HTKZC12s0wrM Kfrg2jbeoFrFucDCFli18KAZm7Zsh3dH5+PhhxWtZLM4GYjfwLMrBsd5Ph5+MnDix1ki uG7jJkjVrCX7vI7mIZ5up6eCyRIaxvTxPiVhbNdom710xWXnkxG1kVhJJeL1r0WV7yPa nrCQ== X-Gm-Message-State: AJcUukdZTtw7RpgUyexQ0YeQwAneCA/zHSEUCfObh3EfcwdANltMuNZL pEqlcD3injHUod+nizOtrMIPiAnrcMYNRw== X-Google-Smtp-Source: ALg8bN7C1s7hz5Jtd/1RaI8p6CDBiVKxi8DbgmCRIjooEyx096YH59l2oU02bSACgYIhlYOk4rkmfA== X-Received: by 2002:adf:fe43:: with SMTP id m3mr22858890wrs.290.1548716831828; Mon, 28 Jan 2019 15:07:11 -0800 (PST) Received: from diamond.mathembedded.com (host86-176-243-190.range86-176.btcentralplus.com. [86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.10 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:11 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 09/17] soc: samsung: pmu: Add initial support for Exynos5260 Date: Mon, 28 Jan 2019 23:06:52 +0000 Message-Id: <20190128230700.7325-10-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Initial support for the PMU on the Exynos5260, largely derived from the Samsung 3.4 kernel. Signed-off-by: Stuart Menefy --- drivers/soc/samsung/Makefile | 2 +- drivers/soc/samsung/exynos-pmu.c | 3 + drivers/soc/samsung/exynos-pmu.h | 1 + drivers/soc/samsung/exynos5260-pmu.c | 178 ++++++++++++++++++++++++++++ include/linux/soc/samsung/exynos-regs-pmu.h | 126 ++++++++++++++++++++ 5 files changed, 309 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/samsung/exynos5260-pmu.c diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile index 29f294baac6e..5b6bf33e8b39 100644 --- a/drivers/soc/samsung/Makefile +++ b/drivers/soc/samsung/Makefile @@ -2,5 +2,5 @@ obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \ - exynos5250-pmu.o exynos5420-pmu.o + exynos5250-pmu.o exynos5260-pmu.o exynos5420-pmu.o obj-$(CONFIG_EXYNOS_PM_DOMAINS) += pm_domains.o diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index d34ca201b8b7..dafdc0d1288b 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -85,6 +85,9 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { .compatible = "samsung,exynos5250-pmu", .data = exynos_pmu_data_arm_ptr(exynos5250_pmu_data), }, { + .compatible = "samsung,exynos5260-pmu", + .data = exynos_pmu_data_arm_ptr(exynos5260_pmu_data), + }, { .compatible = "samsung,exynos5410-pmu", }, { .compatible = "samsung,exynos5420-pmu", diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h index 977e4daf5a0f..bfd30b6f3093 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -34,6 +34,7 @@ extern const struct exynos_pmu_data exynos3250_pmu_data; extern const struct exynos_pmu_data exynos4210_pmu_data; extern const struct exynos_pmu_data exynos4412_pmu_data; extern const struct exynos_pmu_data exynos5250_pmu_data; +extern const struct exynos_pmu_data exynos5260_pmu_data; extern const struct exynos_pmu_data exynos5420_pmu_data; #endif diff --git a/drivers/soc/samsung/exynos5260-pmu.c b/drivers/soc/samsung/exynos5260-pmu.c new file mode 100644 index 000000000000..c121e3288dea --- /dev/null +++ b/drivers/soc/samsung/exynos5260-pmu.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2018 Garrison Technology Limited +// derived from exynos5250-pmu.c which was: +// Copyright (c) 2011-2015 Samsung Electronics Co., Ltd. +// +// EXYNOS5260 - CPU PMU (Power Management Unit) support + +#include +#include + +#include "exynos-pmu.h" + +static const struct exynos_pmu_conf exynos5260_pmu_config[] = { + /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ + { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x8} }, + { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x8} }, + { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5260_KFC_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x8} }, + { EXYNOS5260_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5260_KFC_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x8} }, + { EXYNOS5260_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5260_KFC_CORE2_SYS_PWR_REG, { 0x0, 0x0, 0x8} }, + { EXYNOS5260_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5260_KFC_CORE3_SYS_PWR_REG, { 0x0, 0x0, 0x8} }, + { EXYNOS5260_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5260_EAGLE_NONCPU_SYS_PWR_REG, { 0x0, 0x0, 0x8} }, + { EXYNOS5260_KFC_NONCPU_SYS_PWR_REG, { 0x0, 0x0, 0x8} }, + { EXYNOS5260_A5IS_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5260_DIS_IRQ_A5IS_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5260_DIS_IRQ_A5IS_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x7} }, + { EXYNOS5260_KFC_L2_SYS_PWR_REG, { 0x0, 0x0, 0x7} }, + { EXYNOS5260_CLKSTOP_CMU_TOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5260_CLKRUN_CMU_TOP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_RESET_CMU_TOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5260_RESET_CPUCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5260_CLKSTOP_CMU_MIF_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5260_CLKRUN_CMU_MIF_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_RESET_CMU_MIF_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5260_DISABLE_PLL_CMU_TOP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_DISABLE_PLL_AUD_PLL_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5260_DISABLE_PLL_MIF_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, + { EXYNOS5260_TOP_BUS_MIF_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, + { EXYNOS5260_TOP_RETENTION_MIF_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5260_TOP_PWR_MIF_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, + { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5260_SLEEP_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5260_LOGIC_RESET_MIF_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_OSCCLK_GATE_MIF_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, + { EXYNOS5260_SLEEP_RESET_MIF_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5260_MEMORY_TOP_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, + { EXYNOS5260_MEMORY_MIF_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, + { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, + { EXYNOS5260_PAD_RETENTION_AUD_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5260_PAD_RETENTION_JTAG_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_PAD_RETENTION_TOP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_PAD_RETENTION_MIF_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_PAD_RETENTION_BOOTLDO_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_PAD_ISOLATION_MIF_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, + { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_GPIO_MODE_MIF_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, + { EXYNOS5260_GPIO_MODE_AUD_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, + { EXYNOS5260_GSCL_SYS_PWR_REG, { 0xF, 0x0, 0x0} }, + { EXYNOS5260_G3D_SYS_PWR_REG, { 0xF, 0x0, 0x0} }, + { EXYNOS5260_DISP_SYS_PWR_REG, { 0xF, 0x0, 0x0} }, + { EXYNOS5260_AUD_SYS_PWR_REG, { 0xF, 0xF, 0x0} }, + { EXYNOS5260_G2D_SYS_PWR_REG, { 0xF, 0x0, 0x0} }, + { EXYNOS5260_ISP_SYS_PWR_REG, { 0xF, 0x0, 0x0} }, + { EXYNOS5260_MFC_SYS_PWR_REG, { 0xF, 0x0, 0x0} }, + { EXYNOS5260_MEMORY_G2D_SYS_PWR_REG, { 0x0, 0x0, 0xF} }, + { PMU_TABLE_END,}, +}; + +static unsigned int const exynos5260_list_feed[] = { + EXYNOS5_ARM_CORE0_OPTION, + EXYNOS5_ARM_CORE1_OPTION, + EXYNOS5260_KFC_CORE0_OPTION, + EXYNOS5260_KFC_CORE1_OPTION, + EXYNOS5260_KFC_CORE2_OPTION, + EXYNOS5260_KFC_CORE3_OPTION, + EXYNOS5260_EAGLE_NONCPU_OPTION, + EXYNOS5260_KFC_NONCPU_OPTION, + EXYNOS5260_TOP_PWR_OPTION, + EXYNOS5260_TOP_PWR_MIF_OPTION, + EXYNOS5260_GSCL_OPTION, + EXYNOS5260_G3D_OPTION, + EXYNOS5260_DISP_OPTION, + EXYNOS5260_AUD_OPTION, + EXYNOS5260_G2D_OPTION, + EXYNOS5260_ISP_OPTION, + EXYNOS5260_MFC_OPTION, +}; + +static void exynos5260_powerdown_conf_extra(enum sys_powerdown mode) +{ + if (!(pmu_raw_readl(EXYNOS5260_PMU_DEBUG) & 0x1)) + pmu_raw_writel(1, EXYNOS5_XXTI_SYS_PWR_REG); +} + +static void exynos5260_pmu_init(void) +{ + unsigned int value; + int i; + + /* Enable USE_STANDBY_WFI for all CORE */ + pmu_raw_writel(EXYNOS5260_USE_STANDBY_WFI_ALL | + EXYNOS5260_USE_PROLOGNED_LOGIC_RESET, + S5P_CENTRAL_SEQ_OPTION); + + /* Set PSHOLD port for output high */ + value = pmu_raw_readl(S5P_PS_HOLD_CONTROL); + value |= EXYNOS5260_PS_HOLD_OUTPUT_HIGH; + pmu_raw_writel(value, S5P_PS_HOLD_CONTROL); + + /* Enable signal for PSHOLD port */ + value = pmu_raw_readl(S5P_PS_HOLD_CONTROL); + value |= EXYNOS5260_PS_HOLD_EN; + pmu_raw_writel(value, S5P_PS_HOLD_CONTROL); + + /* Init core interface reg */ + value = pmu_raw_readl(EXYNOS5260_EAGLE_NONCPU_OPTION); + value &= ~(0xF << 16); + pmu_raw_writel(value, EXYNOS5260_EAGLE_NONCPU_OPTION); + value = pmu_raw_readl(EXYNOS5260_KFC_NONCPU_OPTION); + value &= ~(0xF << 16); + pmu_raw_writel(value, EXYNOS5260_KFC_NONCPU_OPTION); + + /* Init L2 option */ + pmu_raw_writel(0, EXYNOS5260_EAGLE_L2_OPTION); + pmu_raw_writel(0, EXYNOS5260_KFC_L2_OPTION); + + /* Procedure of central sequencer needs to be changed */ + pmu_raw_writel((1<<31 | 0x3a<<16 | 0x3e), EXYNOS5260_SEQ_TRANSITION0); + pmu_raw_writel((1<<31 | 0x3e<<16 | 0x3b), EXYNOS5260_SEQ_TRANSITION1); + pmu_raw_writel((1<<31 | 0x3d<<16 | 0x3f), EXYNOS5260_SEQ_TRANSITION2); + + /* Reset assert ctrl */ + for (i = 0; i < 2; i++) { + value = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(i)); + value |= S5P_USE_DELAYED_RESET_ASSERTION; + pmu_raw_writel(value, EXYNOS_ARM_CORE_OPTION(i)); + } + + /* + * Set power on/off notification method + * Enable only SC_FEEDBACK + */ + for (i = 0; i < ARRAY_SIZE(exynos5260_list_feed); i++) { + value = pmu_raw_readl(exynos5260_list_feed[i]); + value &= ~EXYNOS5_USE_SC_COUNTER; + value |= EXYNOS5_USE_SC_FEEDBACK; + pmu_raw_writel(value, exynos5260_list_feed[i]); + } + + pmu_raw_writel(0x3, EXYNOS5260_UP_SCHEDULER); +} + +const struct exynos_pmu_data exynos5260_pmu_data = { + .pmu_config = exynos5260_pmu_config, + .pmu_init = exynos5260_pmu_init, + .powerdown_conf_extra = exynos5260_powerdown_conf_extra, +}; diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h index 5addaf5ccbce..e35861aa08bc 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -138,6 +138,8 @@ (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) #define EXYNOS_ARM_CORE_OPTION(_nr) \ (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x8) +#define EXYNOS_ARM_CORE_RESET(_nr) \ + (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0xc) #define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500 #define EXYNOS_COMMON_CONFIGURATION(_nr) \ @@ -170,6 +172,8 @@ #define S5P_PS_HOLD_CONTROL 0x330C #define S5P_PS_HOLD_EN (1 << 31) #define S5P_PS_HOLD_OUTPUT_HIGH (3 << 8) +#define EXYNOS5260_PS_HOLD_EN (1 << 9) +#define EXYNOS5260_PS_HOLD_OUTPUT_HIGH (1 << 8) #define S5P_CAM_OPTION 0x3C08 #define S5P_MFC_OPTION 0x3C48 @@ -482,6 +486,128 @@ #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) +/* Only for EXYNOS5260 */ +#define EXYNOS5260_CONFIGURATION_LOCAL_POWER_CFG 0xf +#define EXYNOS5260_CONFIGURATION_INITIATE_WAKEUP_FROM_LOWPOWER 0xf0000 +#define EXYNOS5260_STATUS_WAKEUP_FROM_LOCAL_CFG (0xf << 8) +#define EXYNOS5260_STATUS_STATES 0xf0000 +#define EXYNOS5260_STATUS_STATES_NORMAL 0x40000 +#define EXYNOS5260_SWRESET_PORESET BIT(1) + +#define EXYNOS5260_UP_SCHEDULER 0x0120 +#define EXYNOS5260_SEQ_TRANSITION0 0x0220 +#define EXYNOS5260_SEQ_TRANSITION1 0x0224 +#define EXYNOS5260_SEQ_TRANSITION2 0x0228 +#define EXYNOS5260_EINT_WAKEUP_MASK 0x060C +#define EXYNOS5260_WAKEUP_MASK1 0x0610 +#define EXYNOS5260_PMU_DEBUG 0x0A00 +#define EXYNOS5260_KFC_CORE0_SYS_PWR_REG 0x1040 +#define EXYNOS5260_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG 0x1048 +#define EXYNOS5260_KFC_CORE1_SYS_PWR_REG 0x1050 +#define EXYNOS5260_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG 0x1058 +#define EXYNOS5260_KFC_CORE2_SYS_PWR_REG 0x1060 +#define EXYNOS5260_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG 0x1068 +#define EXYNOS5260_KFC_CORE3_SYS_PWR_REG 0x1070 +#define EXYNOS5260_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG 0x1078 +#define EXYNOS5260_EAGLE_NONCPU_SYS_PWR_REG 0x1080 +#define EXYNOS5260_KFC_NONCPU_SYS_PWR_REG 0x1084 +#define EXYNOS5260_A5IS_SYS_PWR_REG 0x10B0 +#define EXYNOS5260_DIS_IRQ_A5IS_LOCAL_SYS_PWR_REG 0x10B4 +#define EXYNOS5260_DIS_IRQ_A5IS_CENTRAL_SYS_PWR_REG 0x10B8 +#define EXYNOS5260_KFC_L2_SYS_PWR_REG 0x10C4 +#define EXYNOS5260_CLKSTOP_CMU_TOP_SYS_PWR_REG 0x1100 +#define EXYNOS5260_CLKRUN_CMU_TOP_SYS_PWR_REG 0x1104 +#define EXYNOS5260_RESET_CMU_TOP_SYS_PWR_REG 0x110C +#define EXYNOS5260_RESET_CPUCLKSTOP_SYS_PWR_REG 0x111C +#define EXYNOS5260_CLKSTOP_CMU_MIF_SYS_PWR_REG 0x1120 +#define EXYNOS5260_CLKRUN_CMU_MIF_SYS_PWR_REG 0x1124 +#define EXYNOS5260_RESET_CMU_MIF_SYS_PWR_REG 0x112C +#define EXYNOS5260_DISABLE_PLL_CMU_TOP_SYS_PWR_REG 0x1140 +#define EXYNOS5260_DISABLE_PLL_AUD_PLL_SYS_PWR_REG 0x1144 +#define EXYNOS5260_DISABLE_PLL_MIF_SYS_PWR_REG 0x1160 +#define EXYNOS5260_TOP_BUS_MIF_SYS_PWR_REG 0x1190 +#define EXYNOS5260_TOP_RETENTION_MIF_SYS_PWR_REG 0x1194 +#define EXYNOS5260_TOP_PWR_MIF_SYS_PWR_REG 0x1198 +#define EXYNOS5260_SLEEP_RESET_SYS_PWR_REG 0x11A8 +#define EXYNOS5260_LOGIC_RESET_MIF_SYS_PWR_REG 0x11B0 +#define EXYNOS5260_OSCCLK_GATE_MIF_SYS_PWR_REG 0x11B4 +#define EXYNOS5260_SLEEP_RESET_MIF_SYS_PWR_REG 0x11B8 +#define EXYNOS5260_MEMORY_TOP_SYS_PWR_REG 0x11C0 +#define EXYNOS5260_MEMORY_MIF_SYS_PWR_REG 0x11E0 +#define EXYNOS5260_PAD_RETENTION_AUD_SYS_PWR_REG 0x1204 +#define EXYNOS5260_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1208 +#define EXYNOS5260_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1218 +#define EXYNOS5260_PAD_RETENTION_TOP_SYS_PWR_REG 0x1220 +#define EXYNOS5260_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 +#define EXYNOS5260_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1228 +#define EXYNOS5260_PAD_RETENTION_MMC1_SYS_PWR_REG 0x122C +#define EXYNOS5260_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238 +#define EXYNOS5260_PAD_RETENTION_MIF_SYS_PWR_REG 0x123C +#define EXYNOS5260_PAD_RETENTION_BOOTLDO_SYS_PWR_REG 0x1248 +#define EXYNOS5260_PAD_ISOLATION_MIF_SYS_PWR_REG 0x1250 +#define EXYNOS5260_GPIO_MODE_MIF_SYS_PWR_REG 0x1320 +#define EXYNOS5260_GPIO_MODE_AUD_SYS_PWR_REG 0x1340 +#define EXYNOS5260_GSCL_SYS_PWR_REG 0x1400 +#define EXYNOS5260_G3D_SYS_PWR_REG 0x140C +#define EXYNOS5260_DISP_SYS_PWR_REG 0x1410 +#define EXYNOS5260_AUD_SYS_PWR_REG 0x1418 +#define EXYNOS5260_G2D_SYS_PWR_REG 0x1424 +#define EXYNOS5260_ISP_SYS_PWR_REG 0x1428 +#define EXYNOS5260_MFC_SYS_PWR_REG 0x1430 +#define EXYNOS5260_MEMORY_G2D_SYS_PWR_REG 0x1564 +#define EXYNOS5260_KFC_CORE0_OPTION 0x2208 +#define EXYNOS5260_KFC_CORE1_OPTION 0x2288 +#define EXYNOS5260_KFC_CORE2_OPTION 0x2308 +#define EXYNOS5260_KFC_CORE3_OPTION 0x2388 + +#define EXYNOS5260_EAGLE_NONCPU_OPTION 0x2408 +#define EXYNOS5260_KFC_NONCPU_OPTION 0x2428 +#define EXYNOS5260_EAGLE_L2_OPTION 0x2608 +#define EXYNOS5260_KFC_L2_OPTION 0x2628 +#define EXYNOS5260_TOP_PWR_OPTION 0x2C48 +#define EXYNOS5260_TOP_PWR_MIF_OPTION 0x2CC8 +#define EXYNOS5260_PAD_RETENTION_LPDDR3_OPTION 0x3008 +#define EXYNOS5260_PAD_RETENTION_AUD_OPTION 0x3028 +#define EXYNOS5260_PAD_RETENTION_JTAG_OPTION 0x3048 +#define EXYNOS5260_PAD_RETENTION_MMC2_OPTION 0x30C8 +#define EXYNOS5260_PAD_RETENTION_TOP_OPTION 0x3108 +#define EXYNOS5260_PAD_RETENTION_UART_OPTION 0x3128 +#define EXYNOS5260_PAD_RETENTION_MMC0_OPTION 0x3148 +#define EXYNOS5260_PAD_RETENTION_MMC1_OPTION 0x3168 +#define EXYNOS5260_PAD_RETENTION_SPI_OPTION 0x31C8 +#define EXYNOS5260_PAD_RETENTION_MIF_OPTION 0x31E8 +#define EXYNOS5260_PAD_RETENTION_BOOTLDO_OPTION 0x3248 +#define EXYNOS5260_GSCL_OPTION 0x4008 +#define EXYNOS5260_G3D_OPTION 0x4068 +#define EXYNOS5260_DISP_OPTION 0x4088 +#define EXYNOS5260_AUD_OPTION 0x40C8 +#define EXYNOS5260_G2D_OPTION 0x4128 +#define EXYNOS5260_ISP_OPTION 0x4148 +#define EXYNOS5260_MFC_OPTION 0x4188 + +#define EXYNOS5260_USE_PROLOGNED_LOGIC_RESET (1 << 12) + +#define EXYNOS5260_USE_STANDBYWFI_ARM_CORE0 (1 << 16) +#define EXYNOS5260_USE_STANDBYWFI_ARM_CORE1 (1 << 17) +#define EXYNOS5260_USE_STANDBYWFI_KFC_CORE0 (1 << 20) +#define EXYNOS5260_USE_STANDBYWFI_KFC_CORE1 (1 << 21) +#define EXYNOS5260_USE_STANDBYWFI_KFC_CORE2 (1 << 22) +#define EXYNOS5260_USE_STANDBYWFI_KFC_CORE3 (1 << 23) +#define EXYNOS5260_USE_STANDBYWFE_ARM_CORE0 (1 << 24) +#define EXYNOS5260_USE_STANDBYWFE_ARM_CORE1 (1 << 25) +#define EXYNOS5260_USE_STANDBYWFE_KFC_CORE0 (1 << 28) +#define EXYNOS5260_USE_STANDBYWFE_KFC_CORE1 (1 << 29) +#define EXYNOS5260_USE_STANDBYWFE_KFC_CORE2 (1 << 30) +#define EXYNOS5260_USE_STANDBYWFE_KFC_CORE3 (1 << 31) + +#define EXYNOS5260_USE_STANDBY_WFI_ALL \ + (EXYNOS5260_USE_STANDBYWFI_ARM_CORE0 | \ + EXYNOS5260_USE_STANDBYWFI_ARM_CORE1 | \ + EXYNOS5260_USE_STANDBYWFI_KFC_CORE0 | \ + EXYNOS5260_USE_STANDBYWFI_KFC_CORE1 | \ + EXYNOS5260_USE_STANDBYWFI_KFC_CORE2 | \ + EXYNOS5260_USE_STANDBYWFI_KFC_CORE3) + #define EXYNOS5420_SWRESET_KFC_SEL 0x3 /* Only for EXYNOS5420 */ From patchwork Mon Jan 28 23:06:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785061 Return-Path: Received: from mail.wl.linuxfoundation.org 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[86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.11 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:12 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 10/17] clk: samsung: exynos5260: Remove security related clocks Date: Mon, 28 Jan 2019 23:06:53 +0000 Message-Id: <20190128230700.7325-11-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When running in secure mode, accessing many of the clock registers related to security features raises an exception. Signed-off-by: Stuart Menefy --- drivers/clk/samsung/clk-exynos5260.c | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c index 2cc2583abd87..9a0024866a36 100644 --- a/drivers/clk/samsung/clk-exynos5260.c +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -1055,17 +1055,8 @@ static const unsigned long mif_clk_regs[] __initconst = { EN_ACLK_MIF_SECURE_DREX0_TZ, EN_ACLK_MIF_SECURE_INTMEM, EN_PCLK_MIF, - EN_PCLK_MIF_SECURE_MONOCNT, - EN_PCLK_MIF_SECURE_RTC_APBIF, - EN_PCLK_MIF_SECURE_DREX1_TZ, - EN_PCLK_MIF_SECURE_DREX0_TZ, EN_SCLK_MIF, EN_IP_MIF, - EN_IP_MIF_SECURE_MONOCNT, - EN_IP_MIF_SECURE_RTC_APBIF, - EN_IP_MIF_SECURE_DREX1_TZ, - EN_IP_MIF_SECURE_DREX0_TZ, - EN_IP_MIF_SECURE_INTEMEM, }; PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"}; @@ -1192,21 +1183,10 @@ static const unsigned long peri_clk_regs[] __initconst = { EN_PCLK_PERI2, EN_PCLK_PERI3, EN_PCLK_PERI_SECURE_CHIPID, - EN_PCLK_PERI_SECURE_PROVKEY0, - EN_PCLK_PERI_SECURE_PROVKEY1, - EN_PCLK_PERI_SECURE_SECKEY, - EN_PCLK_PERI_SECURE_ANTIRBKCNT, - EN_PCLK_PERI_SECURE_TOP_RTC, - EN_PCLK_PERI_SECURE_TZPC, - EN_SCLK_PERI, - EN_SCLK_PERI_SECURE_TOP_RTC, EN_IP_PERI0, EN_IP_PERI1, EN_IP_PERI2, EN_IP_PERI_SECURE_CHIPID, - EN_IP_PERI_SECURE_PROVKEY0, - EN_IP_PERI_SECURE_PROVKEY1, - EN_IP_PERI_SECURE_SECKEY, EN_IP_PERI_SECURE_ANTIRBKCNT, EN_IP_PERI_SECURE_TOP_RTC, EN_IP_PERI_SECURE_TZPC, @@ -1330,15 +1310,6 @@ static const struct samsung_gate_clock peri_gate_clks[] __initconst = { GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66", EN_IP_PERI_SECURE_CHIPID, 2, 0, 0), - GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0), - - GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0), - - GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_SECKEY, 5, 0, 0), - GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66", EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0), From patchwork Mon Jan 28 23:06:54 2019 Content-Type: text/plain; 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[86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.12 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:13 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 11/17] ARM: MCPM: Add provision for platform specific wfi alternative Date: Mon, 28 Jan 2019 23:06:54 +0000 Message-Id: <20190128230700.7325-12-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On some platforms (in particular the Exynos5260) the wfi is not executed directly by the operating system but by trapping into the secure monitor. Signed-off-by: Stuart Menefy --- arch/arm/common/mcpm_entry.c | 8 ++++++-- arch/arm/include/asm/mcpm.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c index ad574d20415c..524be627c87e 100644 --- a/arch/arm/common/mcpm_entry.c +++ b/arch/arm/common/mcpm_entry.c @@ -289,8 +289,12 @@ void mcpm_cpu_power_down(void) __mcpm_cpu_down(cpu, cluster); /* Now we are prepared for power-down, do it: */ - if (cpu_going_down) - wfi(); + if (cpu_going_down) { + if (platform_ops->wfi_alternative) + platform_ops->wfi_alternative(last_man); + else + wfi(); + } /* * It is possible for a power_up request to happen concurrently diff --git a/arch/arm/include/asm/mcpm.h b/arch/arm/include/asm/mcpm.h index acd4983d9b1f..96fdb41ac626 100644 --- a/arch/arm/include/asm/mcpm.h +++ b/arch/arm/include/asm/mcpm.h @@ -223,6 +223,7 @@ struct mcpm_platform_ops { int (*cluster_powerup)(unsigned int cluster); void (*cpu_suspend_prepare)(unsigned int cpu, unsigned int cluster); void (*cpu_powerdown_prepare)(unsigned int cpu, unsigned int cluster); + void (*wfi_alternative)(bool last_man); void (*cluster_powerdown_prepare)(unsigned int cluster); void (*cpu_cache_disable)(void); void (*cluster_cache_disable)(void); From patchwork Mon Jan 28 23:06:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785067 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C394291E for ; Mon, 28 Jan 2019 23:07:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B2F322B26C for ; Mon, 28 Jan 2019 23:07:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A77F52B4D0; Mon, 28 Jan 2019 23:07:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5666D2B26C for ; Mon, 28 Jan 2019 23:07:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727051AbfA1XHR (ORCPT ); Mon, 28 Jan 2019 18:07:17 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:36631 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727069AbfA1XHQ (ORCPT ); Mon, 28 Jan 2019 18:07:16 -0500 Received: by mail-wr1-f65.google.com with SMTP id u4so20021454wrp.3 for ; Mon, 28 Jan 2019 15:07:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mathembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=TyO226Fh7cGGVe6YTHIuYsif68/tJCa7YHRDcFWoOcU=; b=J4TSWwALGIY8RIZiMXWQQLpm4FBBFtx/j50gKUTwzKt8aBpglI84Z74UVDuLycs6IA L+XkH6dSvspsPsMKJxB4LtoQNNc2An+PuWpjdCoqHgxtZ30uTSHtD0IBMziLrmf9DJ7/ mQL5/Fq/ueQy9gFTFxQEgESyuTiFHfErrCdFZQmrJcrrsskbCeqNekJLtlXnexalhLKO TWroB31KZ7cqqeJ8TylVT208/8S2f+5OoK+BwqMioQ5maUhSKaQIMh4oC4UL41Wa5rIr LOcjhi3I3l8frL8twwgtK0LY3Xml5wj8l/CJ5br8ZEhJYUqSaqz4W9zzYRLc8dJDHv5B bG+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=TyO226Fh7cGGVe6YTHIuYsif68/tJCa7YHRDcFWoOcU=; b=s85rQRZdZy36eNPNH+e9IFCPkgSPhUY1fEqkLBIT0Yzxb1VB1zqnbGQhoIc7ZlLeip OyKVomh/7uKGZcJEpFb8CmXwT+E8ECnuA8jtUvE0KkKNYAmOmR/Ml+7GR77a+QfFQ2Hn ztavYINBCEUUAHx6NwXCCv9WOPNL3XgTWkqXI3HsnTFkGJCEhvZsjfVMlm/Lwup5j62Y +qa0ploh9nB9qNh/2reRu3rpDS+BWVP0kOY3o+ikqNF7YeJGSosxf/Zc4HY0F7NAVPh+ uWy15Fa11DgzDj1ObYLTZwbbNqqRzIYHi4gcd03ReEUwxswkYNIgcz6MH1vd/itRZzRr TUYA== X-Gm-Message-State: AJcUukfgKorKPxANQDnnVQT4jgnjTcFb4xbuPwU50pIgMKOy2HasdEjg 5BXsYoe8z5HETyO086mYweJjCeuoVERi1g== X-Google-Smtp-Source: ALg8bN57Osnee1m9fZ/lbMfKteL6rHMKWUDuhUVvP9XOMoodL//AazlOW7HRSrsOf4G+bOdD3X+Y2Q== X-Received: by 2002:a5d:694d:: with SMTP id r13mr22621666wrw.323.1548716834884; Mon, 28 Jan 2019 15:07:14 -0800 (PST) Received: from diamond.mathembedded.com (host86-176-243-190.range86-176.btcentralplus.com. [86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.13 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:14 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 12/17] ARM: EXYNOS: Add basic infrastructure for Exynos5260 Date: Mon, 28 Jan 2019 23:06:55 +0000 Message-Id: <20190128230700.7325-13-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Extend runtime checks so is_samsung_exynos5260() and soc_is_exynos5260() work. Signed-off-by: Stuart Menefy --- arch/arm/mach-exynos/common.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 1b8699e94098..58e6014e3578 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -19,6 +19,7 @@ #define EXYNOS4_CPU_MASK 0xFFFE0000 #define EXYNOS5250_SOC_ID 0x43520000 +#define EXYNOS5260_SOC_ID 0xE5260000 #define EXYNOS5410_SOC_ID 0xE5410000 #define EXYNOS5420_SOC_ID 0xE5420000 #define EXYNOS5800_SOC_ID 0xE5422000 @@ -36,6 +37,7 @@ IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK) IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) +IS_SAMSUNG_CPU(exynos5260, EXYNOS5260_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) @@ -68,6 +70,12 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos5250() 0 #endif +#if defined(CONFIG_SOC_EXYNOS5260) +# define soc_is_exynos5260() is_samsung_exynos5260() +#else +# define soc_is_exynos5260() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS5410) # define soc_is_exynos5410() is_samsung_exynos5410() #else From patchwork Mon Jan 28 23:06:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785069 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7C6B613B4 for ; Mon, 28 Jan 2019 23:07:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6A3AE2B26C for ; Mon, 28 Jan 2019 23:07:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5E9272B4D0; Mon, 28 Jan 2019 23:07:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 50E402B26C for ; Mon, 28 Jan 2019 23:07:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727082AbfA1XHT (ORCPT ); Mon, 28 Jan 2019 18:07:19 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:35735 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727069AbfA1XHS (ORCPT ); Mon, 28 Jan 2019 18:07:18 -0500 Received: by mail-wm1-f67.google.com with SMTP id t200so15872646wmt.0 for ; Mon, 28 Jan 2019 15:07:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mathembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:in-reply-to:references; bh=Kb9pQ+h79DbIhkBlEZdRWcfEn3U4hspFZty4GNqWHX8=; b=sN+g+sglUFOx1rv5FnkyGc6b+3TVUirLEFZbKtwd6xi3gNIZOebnUzVQA80VR08WCH Jg8jg6OdeaSje3rkqhL+ilH1BXSeSOarIonmB+5/Q14sKa5QcP37Kt8Qg+S27uqqLlaX zwFDwjPno6Bi2hLUsGsdAclBNaXAuAGE7BGp/EdNySXglDZORFXnw3cFmdg91PVKmX0U iRrZYuOaS5vxhmzqU8sjn6fZBRlrln6X5oqq7JdLcgCh/+jTfk1FMEslaBsvbbx7ieGk bKOhBtqN1dK8zi7UiezrdqfURtXyU1saKNLT6Djk1L/0L0PycqVaT7gInQKQ6WXgLmVy 7mqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Kb9pQ+h79DbIhkBlEZdRWcfEn3U4hspFZty4GNqWHX8=; b=DX0leNlKpzupPC/1C+F9wc8mm8QrxGEW0um95Q36NkrI0Y+FwXZg+pBIKFUZiTdonO /8jKDqfkK3OkBt84RKLRPXtYX8tileGaQU9ETTkchNJeaJNTQ+FwgORoYm3Ao5oYEIxX YM6s6S1VavOoOM1z1EniCRd+ba9WyVPSGf+Ww28IcxQmLcHQFS8Cl1D8inQpYBWvQH8D o2k4x9iartBx7Hbx63M4LFlYPaATvJtrkys5FduiRt9dbAVD4tA/TpFhDtLcYfs0fPxc 0dyuEa6QSD++xTIfeOIpWvRFXUEFFVldTxL3wWtvNlLv8L/fkKYwwVdqPsXaJOXhW6rZ TZuQ== X-Gm-Message-State: AJcUukd/uLgGLHT0VjFjXbAGTbUYvaHjAvE8tUd7i4TwcWbCIXWD6NrO TXHcHf14nij5jSBLeY4/CVJCV1Cg5V4CpA== X-Google-Smtp-Source: ALg8bN4DpEEepEpkyzcB2RdcazO7A05+esIsZLjDbE5bdiETRdEYzToHeNoAJpl8bTDc6ZB0xppRZg== X-Received: by 2002:a1c:38c4:: with SMTP id f187mr18241860wma.90.1548716835967; Mon, 28 Jan 2019 15:07:15 -0800 (PST) Received: from diamond.mathembedded.com (host86-176-243-190.range86-176.btcentralplus.com. [86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.14 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:15 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 13/17] ARM: EXYNOS: Move cpunr calculation to a function Date: Mon, 28 Jan 2019 23:06:56 +0000 Message-Id: <20190128230700.7325-14-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The generic MCPM code uses a [cpu,cluster] tuple to identify each core, so the Exynos specific code converts this into a single integer cpunr, which is then used as an offset to registers. Move the current 5420 specific calculations to a new function so we can change this for other devices. Signed-off-by: Stuart Menefy --- arch/arm/mach-exynos/mcpm-exynos.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index 72bc035bedbe..571349e1e02e 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -55,13 +55,21 @@ static void __iomem *ns_sram_base_addr __ro_after_init; : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ "r9", "r10", "lr", "memory") +static int exynos_cpunr(unsigned int cpu, unsigned int cluster) +{ + if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER || + cluster >= EXYNOS5420_NR_CLUSTERS) + return -EINVAL; + return cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); +} + static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) { - unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); + unsigned int cpunr; pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER || - cluster >= EXYNOS5420_NR_CLUSTERS) + cpunr = exynos_cpunr(cpu, cluster); + if (cpunr < 0) return -EINVAL; if (!exynos_cpu_power_state(cpunr)) { @@ -104,11 +112,10 @@ static int exynos_cluster_powerup(unsigned int cluster) static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) { - unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); + unsigned int cpunr = exynos_cpunr(cpu, cluster); pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER || - cluster >= EXYNOS5420_NR_CLUSTERS); + BUG_ON(cpunr < 0); exynos_cpu_power_down(cpunr); } @@ -152,11 +159,10 @@ static void exynos_cluster_cache_disable(void) static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster) { unsigned int tries = 100; - unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); + unsigned int cpunr = exynos_cpunr(cpu, cluster); pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER || - cluster >= EXYNOS5420_NR_CLUSTERS); + BUG_ON(cpunr < 0); /* Wait for the core state to be OFF */ while (tries--) { From patchwork Mon Jan 28 23:06:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785075 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E4B53184E for ; Mon, 28 Jan 2019 23:07:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D27862B47D for ; Mon, 28 Jan 2019 23:07:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C6AFD2B505; Mon, 28 Jan 2019 23:07:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B6D982B4D5 for ; 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[86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.15 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:16 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 14/17] ARM: EXYNOS: Switch SMP support for Exynos5260 to use MCPM Date: Mon, 28 Jan 2019 23:06:57 +0000 Message-Id: <20190128230700.7325-15-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Switch the SMP support for the Exynos5260 to use the MCPM infrastructure, including support for suspend/resume. As far as possible this replicates the operations performed by the last 3.4 kernel released by Samsung. Signed-off-by: Stuart Menefy --- arch/arm/boot/dts/exynos5260.dtsi | 21 +++++++ arch/arm/mach-exynos/common.h | 1 + arch/arm/mach-exynos/exynos.c | 1 - arch/arm/mach-exynos/mcpm-exynos.c | 118 +++++++++++++++++++++++++++++-------- arch/arm/mach-exynos/platsmp.c | 37 ++++++++++-- arch/arm/mach-exynos/suspend.c | 86 ++++++++++++++++++++++++--- 6 files changed, 227 insertions(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 84c9b4443dc6..e8a5c8715b94 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -233,6 +233,24 @@ status = "disabled"; }; + sysram@2020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x54000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x54000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@53000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x53000 0x1000>; + }; + }; + mct: mct@100b0000 { compatible = "samsung,exynos4210-mct"; reg = <0x100B0000 0x1000>; @@ -299,6 +317,9 @@ pmu_system_controller: system-controller@10d50000 { compatible = "samsung,exynos5260-pmu", "syscon"; reg = <0x10D50000 0x10000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; }; uart0: serial@12c00000 { diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 58e6014e3578..ede449bc73f1 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -110,6 +110,7 @@ enum { void exynos_firmware_init(void); /* CPU BOOT mode flag for Exynos3250 SoC bootloader */ +#define HOTPLUG (1 << 2) /* 5260 */ #define C2_STATE (1 << 3) /* * Magic values for bootloader indicating chosen low power mode. diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 865dcc4c3181..2866cb0ff51a 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -119,7 +119,6 @@ void exynos_set_delayed_reset_assertion(bool enable) * feat, the matches below should be moved to suspend.c. */ static const struct of_device_id exynos_dt_pmu_match[] = { - { .compatible = "samsung,exynos5260-pmu" }, { .compatible = "samsung,exynos5410-pmu" }, { /*sentinel*/ }, }; diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index 571349e1e02e..e5e8d1f27995 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -17,10 +17,15 @@ #include #include "common.h" +#include "smc.h" #define EXYNOS5420_CPUS_PER_CLUSTER 4 #define EXYNOS5420_NR_CLUSTERS 2 +#define EXYNOS5260_CPUS_PER_BIG_CLUSTER 2 +#define EXYNOS5260_CPUS_PER_LITTLE_CLUSTER 4 +#define EXYNOS5260_NR_CLUSTERS 2 + #define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9) #define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29) #define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30) @@ -57,6 +62,17 @@ static void __iomem *ns_sram_base_addr __ro_after_init; static int exynos_cpunr(unsigned int cpu, unsigned int cluster) { + if (soc_is_exynos5260()) { + static const int cpus_per_cluster[EXYNOS5260_NR_CLUSTERS] = { + EXYNOS5260_CPUS_PER_BIG_CLUSTER, + EXYNOS5260_CPUS_PER_LITTLE_CLUSTER + }; + if (cluster >= EXYNOS5260_NR_CLUSTERS || + cpu >= cpus_per_cluster[cluster]) + return -EINVAL; + return cpu + (cluster * 4); + } + if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER || cluster >= EXYNOS5420_NR_CLUSTERS) return -EINVAL; @@ -92,8 +108,20 @@ static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) while (!pmu_raw_readl(S5P_PMU_SPARE2)) udelay(10); - pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu), - EXYNOS_SWRESET); + if (soc_is_exynos5260()) { + u32 val, offset; + + offset = EXYNOS_ARM_CORE_STATUS(cpunr); + val = pmu_raw_readl(offset); + val |= EXYNOS5260_STATUS_WAKEUP_FROM_LOCAL_CFG; + pmu_raw_writel(val, offset); + + pmu_raw_writel(EXYNOS5260_SWRESET_PORESET, + EXYNOS_ARM_CORE_RESET(cpunr)); + } else { + pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu), + EXYNOS_SWRESET); + } } } @@ -106,6 +134,9 @@ static int exynos_cluster_powerup(unsigned int cluster) if (cluster >= EXYNOS5420_NR_CLUSTERS) return -EINVAL; + if (soc_is_exynos5260()) + return 0; + exynos_cluster_power_up(cluster); return 0; } @@ -119,21 +150,44 @@ static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) exynos_cpu_power_down(cpunr); } +static void exynos_wfi_alternative(bool last_man) +{ + if (soc_is_exynos5260()) { + exynos_smc(SMC_CMD_SHUTDOWN, + last_man ? OP_TYPE_CLUSTER : OP_TYPE_CORE, + SMC_POWERSTATE_IDLE, + 0); + return; + } + + wfi(); +} + static void exynos_cluster_powerdown_prepare(unsigned int cluster) { pr_debug("%s: cluster %u\n", __func__, cluster); BUG_ON(cluster >= EXYNOS5420_NR_CLUSTERS); + + if (soc_is_exynos5260()) + return; + exynos_cluster_power_down(cluster); } static void exynos_cpu_cache_disable(void) { + if (soc_is_exynos5260()) + return; + /* Disable and flush the local CPU cache. */ exynos_v7_exit_coherency_flush(louis); } static void exynos_cluster_cache_disable(void) { + if (soc_is_exynos5260()) + return; + if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { /* * On the Cortex-A15 we need to disable @@ -180,12 +234,20 @@ static void exynos_cpu_is_up(unsigned int cpu, unsigned int cluster) { /* especially when resuming: make sure power control is set */ exynos_cpu_powerup(cpu, cluster); + + if (soc_is_exynos5260()) { + /* Note this is different to exynos_cpunr() */ + int cpunr = cpu + (cluster ? 0 : 4); + + exynos_clear_boot_flag(cpunr, HOTPLUG); + } } static const struct mcpm_platform_ops exynos_power_ops = { .cpu_powerup = exynos_cpu_powerup, .cluster_powerup = exynos_cluster_powerup, .cpu_powerdown_prepare = exynos_cpu_powerdown_prepare, + .wfi_alternative = exynos_wfi_alternative, .cluster_powerdown_prepare = exynos_cluster_powerdown_prepare, .cpu_cache_disable = exynos_cpu_cache_disable, .cluster_cache_disable = exynos_cluster_cache_disable, @@ -205,6 +267,7 @@ static void __naked exynos_pm_power_up_setup(unsigned int affinity_level) } static const struct of_device_id exynos_dt_mcpm_match[] = { + { .compatible = "samsung,exynos5260" }, { .compatible = "samsung,exynos5420" }, { .compatible = "samsung,exynos5800" }, {}, @@ -253,11 +316,13 @@ static int __init exynos_mcpm_init(void) return -ENOMEM; } - /* - * To increase the stability of KFC reset we need to program - * the PMU SPARE3 register - */ - pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3); + if (soc_is_exynos5420() || soc_is_exynos5800()) { + /* + * To increase the stability of KFC reset we need to program + * the PMU SPARE3 register. + */ + pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3); + } ret = mcpm_platform_register(&exynos_power_ops); if (!ret) @@ -273,24 +338,27 @@ static int __init exynos_mcpm_init(void) pr_info("Exynos MCPM support installed\n"); - /* - * On Exynos5420/5800 for the A15 and A7 clusters: - * - * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores - * in a cluster are turned off before turning off the cluster L2. - * - * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered - * off before waking it up. - * - * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be - * turned on before the first man is powered up. - */ - for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) { - value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i)); - value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN | - EXYNOS5420_USE_ARM_CORE_DOWN_STATE | - EXYNOS5420_USE_L2_COMMON_UP_STATE; - pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i)); + if (soc_is_exynos5420() || soc_is_exynos5800()) { + /* + * On Exynos5420/5800 for the A15 and A7 clusters: + * + * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the + * cores in a cluster are turned off before turning off the + * cluster L2. + * + * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is + * powered off before waking it up. + * + * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 + * will be turned on before the first man is powered up. + */ + for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) { + value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i)); + value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN | + EXYNOS5420_USE_ARM_CORE_DOWN_STATE | + EXYNOS5420_USE_L2_COMMON_UP_STATE; + pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i)); + } } exynos_mcpm_setup_entry_point(); diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index b6da7edbbd2f..07c21b2afc11 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -100,6 +100,23 @@ void exynos_cpu_power_down(int cpu) return; } + if (cpu == 4 && (soc_is_exynos5260())) { + /* + * Bypass power down for CPU4 (KFC0) during suspend. Check for + * the SYS_PWR_REG value to decide if we are suspending + * the system. + */ + int val = pmu_raw_readl(EXYNOS5260_KFC_CORE0_SYS_PWR_REG); + + if ((val & 0xf) == 8) + return; + } + + if (soc_is_exynos5260()) { + pmu_raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); + return; + } + core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu)); core_conf &= ~S5P_CORE_LOCAL_PWR_EN; pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); @@ -117,6 +134,9 @@ void exynos_cpu_power_up(int cpu) if (soc_is_exynos3250()) core_conf |= S5P_CORE_AUTOWAKEUP_EN; + else if (soc_is_exynos5260()) + core_conf = EXYNOS5260_CONFIGURATION_LOCAL_POWER_CFG | + EXYNOS5260_CONFIGURATION_INITIATE_WAKEUP_FROM_LOWPOWER; pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); @@ -129,8 +149,17 @@ void exynos_cpu_power_up(int cpu) */ int exynos_cpu_power_state(int cpu) { - return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & - S5P_CORE_LOCAL_PWR_EN); + u32 status = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)); + + if (soc_is_exynos5260()) { + if ((status & EXYNOS5260_STATUS_STATES) == + EXYNOS5260_STATUS_STATES_NORMAL) + return S5P_CORE_LOCAL_PWR_EN; + else + return 0; + } + + return status & S5P_CORE_LOCAL_PWR_EN; } /** @@ -197,7 +226,7 @@ static inline void __iomem *cpu_boot_reg(int cpu) boot_reg = cpu_boot_reg_base(); if (!boot_reg) return IOMEM_ERR_PTR(-ENODEV); - if (soc_is_exynos4412()) + if (soc_is_exynos4412() || soc_is_exynos5260()) boot_reg += 4*cpu; else if (soc_is_exynos5420() || soc_is_exynos5800()) boot_reg += 4; @@ -371,7 +400,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) call_firmware_op(cpu_boot, core_id); - if (soc_is_exynos3250()) + if (soc_is_exynos3250() /* || soc_is_exynos5260() */) dsb_sev(); else arch_send_wakeup_ipi_mask(cpumask_of(cpu)); diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index 0850505ac78b..174b8064a655 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -230,6 +230,7 @@ EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu"); EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu"); EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu"); EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu"); +EXYNOS_PMU_IRQ(exynos5260_pmu_irq, "samsung,exynos5260-pmu"); EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu"); static int exynos_cpu_do_idle(void) @@ -258,6 +259,24 @@ static int exynos3250_cpu_suspend(unsigned long arg) return exynos_cpu_do_idle(); } +static int exynos5260_cpu_suspend(unsigned long arg) +{ + /* MCPM works with HW CPU identifiers */ + unsigned int mpidr = read_cpuid_mpidr(); + unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + + if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) { + mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume); + mcpm_cpu_suspend(); + } + + pr_info("Failed to suspend the system\n"); + + /* return value != 0 means failure */ + return 1; +} + static int exynos5420_cpu_suspend(unsigned long arg) { /* MCPM works with HW CPU identifiers */ @@ -324,6 +343,17 @@ static void exynos3250_pm_prepare(void) pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0); } +static void exynos5260_pm_prepare(void) +{ + /* Set wake-up mask registers */ + pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), + EXYNOS5260_WAKEUP_MASK1); + /* EXYNOS5260_EINT_WAKEUP_MASK is set by pinctrl */ + + /* Set value of power down register for sleep mode */ + exynos_sys_powerdown_conf(SYS_SLEEP); +} + static void exynos5420_pm_prepare(void) { unsigned int tmp; @@ -369,14 +399,18 @@ static void exynos5420_pm_prepare(void) pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION); } - static int exynos_pm_suspend(void) { + int val; exynos_pm_central_suspend(); /* Setting SEQ_OPTION register */ - pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, - S5P_CENTRAL_SEQ_OPTION); + if (soc_is_exynos5260()) + val = EXYNOS5260_USE_STANDBYWFI_KFC_CORE0 | + EXYNOS5260_USE_PROLOGNED_LOGIC_RESET; + else + val = S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0; + pmu_raw_writel(val, S5P_CENTRAL_SEQ_OPTION); if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) exynos_cpu_save_register(); @@ -384,6 +418,17 @@ static int exynos_pm_suspend(void) return 0; } +static int exynos5260_pm_suspend(void) +{ + pmu_raw_writel(EXYNOS5260_USE_STANDBYWFI_KFC_CORE0 | + EXYNOS5260_USE_PROLOGNED_LOGIC_RESET, + S5P_CENTRAL_SEQ_OPTION); + + exynos_pm_central_suspend(); + + return 0; +} + static int exynos5420_pm_suspend(void) { u32 this_cluster; @@ -442,6 +487,19 @@ static void exynos3250_pm_resume(void) pmu_raw_writel(0x0, S5P_INFORM1); } +static void exynos5260_pm_resume(void) +{ + pmu_raw_writel(EXYNOS5260_USE_STANDBY_WFI_ALL | + EXYNOS5260_USE_PROLOGNED_LOGIC_RESET, + S5P_CENTRAL_SEQ_OPTION); + + if (exynos_pm_central_resume()) + goto early_wakeup; + +early_wakeup: + return; +} + static void exynos5420_prepare_pm_resume(void) { if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) @@ -593,6 +651,15 @@ static const struct exynos_pm_data exynos5250_pm_data = { .cpu_suspend = exynos_cpu_suspend, }; +static const struct exynos_pm_data exynos5260_pm_data = { + .wkup_irq = exynos3250_wkup_irq, + .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), + .pm_suspend = exynos5260_pm_suspend, + .pm_resume = exynos5260_pm_resume, + .pm_prepare = exynos5260_pm_prepare, + .cpu_suspend = exynos5260_cpu_suspend, +}; + static const struct exynos_pm_data exynos5420_pm_data = { .wkup_irq = exynos5250_wkup_irq, .wake_disable_mask = (0x7F << 7) | (0x1F << 1), @@ -617,6 +684,9 @@ static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { .compatible = "samsung,exynos5250-pmu", .data = &exynos5250_pm_data, }, { + .compatible = "samsung,exynos5260-pmu", + .data = &exynos5260_pm_data, + }, { .compatible = "samsung,exynos5420-pmu", .data = &exynos5420_pm_data, }, @@ -644,10 +714,12 @@ void __init exynos_pm_init(void) pm_data = (const struct exynos_pm_data *) match->data; - /* All wakeup disable */ - tmp = pmu_raw_readl(S5P_WAKEUP_MASK); - tmp |= pm_data->wake_disable_mask; - pmu_raw_writel(tmp, S5P_WAKEUP_MASK); + if (!soc_is_exynos5260()) { + /* All wakeup disable */ + tmp = pmu_raw_readl(S5P_WAKEUP_MASK); + tmp |= pm_data->wake_disable_mask; + pmu_raw_writel(tmp, S5P_WAKEUP_MASK); + } exynos_pm_syscore_ops.suspend = pm_data->pm_suspend; exynos_pm_syscore_ops.resume = pm_data->pm_resume; From patchwork Mon Jan 28 23:06:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stuart Menefy X-Patchwork-Id: 10785071 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 03BC413B4 for ; Mon, 28 Jan 2019 23:07:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E730B2B47D for ; Mon, 28 Jan 2019 23:07:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D93332B510; Mon, 28 Jan 2019 23:07:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 598282B47D for ; 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[86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.17 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:17 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 15/17] pinctrl: samsung: Add support for pad retention control for Exynos5260 Date: Mon, 28 Jan 2019 23:06:58 +0000 Message-Id: <20190128230700.7325-16-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for retention control for Exynos5260 SoC. Signed-off-by: Stuart Menefy --- .../bindings/pinctrl/samsung-pinctrl.txt | 2 ++ arch/arm/boot/dts/exynos5260.dtsi | 2 +- drivers/pinctrl/samsung/pinctrl-exynos-arm.c | 25 ++++++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.c | 21 ++++++++++++++++++ 4 files changed, 49 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 70659c917bdc..548d5786c400 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -163,6 +163,8 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a found on Samsung S5Pv210 SoCs, - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs. + - samsung,exynos5260-wakeup-eint: represents wakeup interrupt controller + found on Samsung Exynos5260 SoCs. - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller found on Samsung Exynos7 SoC. - interrupts: interrupt used by multiplexed wakeup interrupts. diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index e8a5c8715b94..8b46f7078d5d 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -296,7 +296,7 @@ interrupts = ; wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; + compatible = "samsung,exynos5260-wakeup-eint"; interrupt-parent = <&gic>; interrupts = ; }; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c index 44c6b753f692..997b938eecb2 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c @@ -605,6 +605,28 @@ static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), }; +/* PMU pad retention groups registers for Exynos5260 */ +static const u32 exynos5260_retention_regs[] = { + EXYNOS5260_PAD_RETENTION_LPDDR3_OPTION, + EXYNOS5260_PAD_RETENTION_JTAG_OPTION, + EXYNOS5260_PAD_RETENTION_MMC2_OPTION, + EXYNOS5260_PAD_RETENTION_TOP_OPTION, + EXYNOS5260_PAD_RETENTION_UART_OPTION, + EXYNOS5260_PAD_RETENTION_MMC0_OPTION, + EXYNOS5260_PAD_RETENTION_MMC1_OPTION, + EXYNOS5260_PAD_RETENTION_SPI_OPTION, + EXYNOS5260_PAD_RETENTION_MIF_OPTION, + EXYNOS5260_PAD_RETENTION_BOOTLDO_OPTION, +}; + +static const struct samsung_retention_data exynos5260_retention_data __initconst = { + .regs = exynos5260_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5260_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + /* * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes * three gpio/pin-mux/pinconfig controllers. @@ -618,6 +640,7 @@ static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos5260_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos5260_pin_banks1, @@ -625,6 +648,7 @@ static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos5260_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos5260_pin_banks2, @@ -632,6 +656,7 @@ static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos5260_retention_data, }, }; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index f49ea3d92aa1..c11343967632 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -372,6 +372,25 @@ static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = { .eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK, }; +static const struct exynos_irq_chip exynos5260_wkup_irq_chip __initconst = { + .chip = { + .name = "exynos5260_wkup_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + .irq_set_wake = exynos_wkup_irq_set_wake, + .irq_request_resources = exynos_irq_request_resources, + .irq_release_resources = exynos_irq_release_resources, + }, + .eint_con = EXYNOS_WKUP_ECON_OFFSET, + .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, + .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, + .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, + /* Only difference with exynos4210_wkup_irq_chip: */ + .eint_wake_mask_reg = EXYNOS5260_EINT_WAKEUP_MASK, +}; + static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { .chip = { .name = "exynos4210_wkup_irq_chip", @@ -412,6 +431,8 @@ static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { static const struct of_device_id exynos_wkup_irq_ids[] = { { .compatible = "samsung,s5pv210-wakeup-eint", .data = &s5pv210_wkup_irq_chip }, + { .compatible = "samsung,exynos5260-wakeup-eint", + .data = &exynos5260_wkup_irq_chip }, { .compatible = "samsung,exynos4210-wakeup-eint", .data = &exynos4210_wkup_irq_chip }, { .compatible = "samsung,exynos7-wakeup-eint", From patchwork Mon Jan 28 23:06:59 2019 Content-Type: text/plain; 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[86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.18 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:18 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 16/17] clk: samsung: exynos5260: Add CLK_IGNORE_UNUSED flag to fix suspend Date: Mon, 28 Jan 2019 23:06:59 +0000 Message-Id: <20190128230700.7325-17-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the CLK_IGNORE_UNUSED flag to a number of clocks, to fix problems seen with suspend/resume: - AUD UART: if the UART isn't configured (in s3c24xx_serial_set_termios) then the baudclk isn't set up, and so s3c24xx_serial_resume doesn't enable the clock prior to accessing the registers, causing an external abort. - FIMD1: no idea, but suspend doesn't work if this is off - TZPCn: on a secure part suspend doesn't work if the TrustZone clocks are disabled. Signed-off-by: Stuart Menefy --- drivers/clk/samsung/clk-exynos5260.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c index 9a0024866a36..9635c462f030 100644 --- a/drivers/clk/samsung/clk-exynos5260.c +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -119,7 +119,8 @@ static const struct samsung_gate_clock aud_gate_clks[] __initconst = { GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm", EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0), GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart", - EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0), + EN_SCLK_AUD, 2, + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD, 0, 0, 0), @@ -298,7 +299,7 @@ static const struct samsung_gate_clock disp_gate_clks[] __initconst = { GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user", EN_IP_DISP, 6, 0, 0), GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user", - EN_IP_DISP, 7, 0, 0), + EN_IP_DISP, 7, CLK_IGNORE_UNUSED, 0), GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user", EN_IP_DISP, 8, 0, 0), GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user", @@ -1314,27 +1315,27 @@ static const struct samsung_gate_clock peri_gate_clks[] __initconst = { EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0), GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_TZPC, 10, 0, 0), + EN_IP_PERI_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0), GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_TZPC, 11, 0, 0), + EN_IP_PERI_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0), GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_TZPC, 12, 0, 0), + EN_IP_PERI_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0), GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_TZPC, 13, 0, 0), + EN_IP_PERI_SECURE_TZPC, 13, CLK_IGNORE_UNUSED, 0), GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_TZPC, 14, 0, 0), + EN_IP_PERI_SECURE_TZPC, 14, CLK_IGNORE_UNUSED, 0), GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_TZPC, 15, 0, 0), + EN_IP_PERI_SECURE_TZPC, 15, CLK_IGNORE_UNUSED, 0), GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_TZPC, 16, 0, 0), + EN_IP_PERI_SECURE_TZPC, 16, CLK_IGNORE_UNUSED, 0), GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_TZPC, 17, 0, 0), + EN_IP_PERI_SECURE_TZPC, 17, CLK_IGNORE_UNUSED, 0), GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_TZPC, 18, 0, 0), + EN_IP_PERI_SECURE_TZPC, 18, CLK_IGNORE_UNUSED, 0), GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_TZPC, 19, 0, 0), + EN_IP_PERI_SECURE_TZPC, 19, CLK_IGNORE_UNUSED, 0), GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66", - EN_IP_PERI_SECURE_TZPC, 20, 0, 0), + EN_IP_PERI_SECURE_TZPC, 20, CLK_IGNORE_UNUSED, 0), }; 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[86.176.243.190]) by smtp.gmail.com with ESMTPSA id o64sm506765wmo.47.2019.01.28.15.07.19 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Jan 2019 15:07:19 -0800 (PST) From: Stuart Menefy To: linux-samsung-soc@vger.kernel.org Subject: [PATCH 17/17] ARM: dts: exynos: Add DTS file for exynos5260-rexred Date: Mon, 28 Jan 2019 23:07:00 +0000 Message-Id: <20190128230700.7325-18-stuart.menefy@mathembedded.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190128230700.7325-1-stuart.menefy@mathembedded.com> References: <20190128230700.7325-1-stuart.menefy@mathembedded.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for the RexNos REX-RED board which is based on the Exynos5260. Signed-off-by: Stuart Menefy --- .../bindings/arm/samsung/samsung-boards.txt | 2 + .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5260-rexred.dts | 396 +++++++++++++++++++++ 4 files changed, 400 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5260-rexred.dts diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index 56021bf2a916..f7dc2f9e3e57 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -70,6 +70,8 @@ Required root node properties: Octa board. - "insignal,origen" - for Exynos4210-based Insignal Origen board. - "insignal,origen4412" - for Exynos4412-based Insignal Origen board. + * Rexnos + - "rexnos,rexred" - for Exynos5260-based Rexnos RexRed board. Optional nodes: diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 389508584f48..0666385ec11e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -328,6 +328,7 @@ raydium Raydium Semiconductor Corp. rda Unisoc Communications, Inc. realtek Realtek Semiconductor Corp. renesas Renesas Electronics Corporation +rexnos REXNOS Co., Ltd richtek Richtek Technology Corporation ricoh Ricoh Co. Ltd. rikomagic Rikomagic Tech Corp. Ltd diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148a15b2..2c6190e0834b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -191,6 +191,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5250-snow.dtb \ exynos5250-snow-rev5.dtb \ exynos5250-spring.dtb \ + exynos5260-rexred.dtb \ exynos5260-xyref5260.dtb \ exynos5410-odroidxu.dtb \ exynos5410-smdk5410.dtb \ diff --git a/arch/arm/boot/dts/exynos5260-rexred.dts b/arch/arm/boot/dts/exynos5260-rexred.dts new file mode 100644 index 000000000000..46187ad0c696 --- /dev/null +++ b/arch/arm/boot/dts/exynos5260-rexred.dts @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RexNos REX-RED Exynos5260 board device tree source + * + * Copyright (c) 2018 Garrison Technology Limited + * derived from exynos5260-xyref5260.dts which was: + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + */ + +/dts-v1/; +#include +#include +#include "exynos5260.dtsi" + +/ { + model = "Rexnos RexRed board based on EXYNOS5260"; + compatible = "rexnos,rexred", "samsung,exynos5260", "samsung,exynos5"; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x80000000>; + }; + + chosen { + bootargs = "console=ttySAC2,115200"; + }; + + gpio_keys { + compatible = "gpio-keys"; + + wakeup { + label = "SW1"; + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + home { + label = "S1"; + gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + back { + label = "S2"; + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + menu { + label = "S3"; + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + up { + label = "S4"; + gpios = <&gpx2 4 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + down { + label = "S5"; + gpios = <&gpx2 5 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + fin_pll: xxti { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + firmware@02073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + xrtcxti: xrtcxti { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xrtcxti"; + #clock-cells = <0>; + }; +}; + +&pinctrl_0 { + s2mpa01_irq: s2mpa01-irq { + samsung,pins = "gpx0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samaung,pin-drv = ; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&hsi2c_0 { + status = "okay"; + samsung,polling-mode; + clock-frequency = <100000>; + + s2mpa01_pmic@66 { + compatible = "samsung,s2mpa01-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx0>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mpa01_irq>; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "vdd_mif range"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12000>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_eagle"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12000>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int range"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12000>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d range"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12000>; + }; + + buck5_reg: BUCK5 { + regulator-name = "must-be-on-buck5"; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12000>; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12000>; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_disp range"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <1000>; + }; + + buck8_reg: BUCK8 { + regulator-name = "must-be-on-buck8"; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12000>; + }; + + buck9_reg: BUCK9 { + regulator-name = "must-be-on-buck9"; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12000>; + }; + + ldo1_reg: LDO1 { + regulator-name = "must-be-on-ldo1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "vddq_mmc2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "vcc_1.8v_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "must-be-on-ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "must-be-on-ldo5"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vcc_1.0v_MIPI"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vcc_1.8v_MIPI"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vddq_mmc01"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vcc_3.3v_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vmmc2"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "Main Camera IO (1.8V)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "Camera Sensor (2.8V)"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "Main Camera AF (2.8V)"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "VT Camera Core (1.8V)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo18_reg: LDO18 { + regulator-name = "tsp_avdd_3.3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "usb_vdd_3.0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo22_reg: LDO22 { + regulator-name = "usb_vdd_3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo19_reg: LDO19 { + regulator-name = "vcc_3.0_evt1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo20_reg: LDO20 { + regulator-name = "vcc_1.8_evt1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "tsp_io range"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo25_reg: LDO25 { + regulator-name = "vcc_1.2v_cam"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo26_reg: LDO26 { + regulator-name = "vcc_1.2v_usb range"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&mmc_0 { + status = "okay"; + non-removable; + cap-mmc-highspeed; + supports-hs200-mode; /* 200 MHz */ + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + vqmmc-supply = <&ldo10_reg>; +}; + +/* mmc1 is connected to J1 for the SDIO WiFi */ + +&mmc_2 { + status = "okay"; + cap-sd-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; + disable-wp; + vmmc-supply = <&ldo13_reg>; + vqmmc-supply = <&ldo2_reg>; +};