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Wed, 1 Mar 2023 01:52:02 +0000 From: "Peng Fan (OSS)" To: herbert@gondor.apana.org.au, davem@davemloft.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, horia.geanta@nxp.com, pankaj.gupta@nxp.com, gaurav.jain@nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, stefan@agner.ch, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan Subject: [PATCH 1/9] ARM: dts: vfxxx: drop the number after jr Date: Wed, 1 Mar 2023 09:56:54 +0800 Message-Id: <20230301015702.3388458-2-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230301015702.3388458-1-peng.fan@oss.nxp.com> References: <20230301015702.3388458-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0022.apcprd02.prod.outlook.com (2603:1096:4:1f4::16) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|DBBPR04MB7546:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e3de60c-e14f-468f-9b5c-08db19f78d40 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Use jr@xxxx, instead jr[0,1]@xxxx, and the DT schema will reflect it. Signed-off-by: Peng Fan --- arch/arm/boot/dts/vfxxx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index ff4479994b60..61ab76c43a11 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -735,13 +735,13 @@ crypto: crypto@400f0000 { clocks = <&clks VF610_CLK_CAAM>; clock-names = "ipg"; - sec_jr0: jr0@1000 { + sec_jr0: jr@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; }; - sec_jr1: jr1@2000 { + sec_jr1: jr@2000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x2000 0x1000>; interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; From patchwork Wed Mar 1 01:56:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13155422 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26B15C7EE30 for ; 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DPAA Queue Interface (HW interface between Queue Manager & SEC 4). + 2. Job Rings (HW interface between cores & SEC 4 registers). + + High Speed Data Path Configuration, + + HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts + such as the P4080. The number of simultaneous dequeues the QI can make is + equal to the number of Descriptor Controller (DECO) engines in a particular + SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus + dequeue from 5 subportals simultaneously. + + Job Ring Data Path Configuration, + + Each JR is located on a separate 4k page, they may (or may not) be made visible + in the memory partition devoted to a particular core. The P4080 has 4 JRs, so + up to 4 JRs can be configured; and all 4 JRs process requests in parallel. + +maintainers: + - Peng Fan + +properties: + compatible: + enum: + - fsl,sec-v4.0 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + reg: + maxItems: 1 + + ranges: + description: + A standard property. Specifies the physical address range of the SEC + 4.0 register space (-SNVS not included). A triplet that includes the + child address, parent address, & length. + + interrupts: + description: + Specifies the interrupts generated by this device. The value of the + interrupts property consists of one interrupt specifier. The format + of the specifier is defined by the binding document describing the + node's interrupt parent. + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + oneOf: + - items: + - const: mem + - const: aclk + - const: ipg + - const: emi_slow + - items: + - const: aclk + - const: ipg + - items: + - const: ipg + - const: aclk + - const: mem + + fsl,sec-era: + description: + Optional. A standard property. Define the 'ERA' of the SEC device. + $ref: /schemas/types.yaml#/definitions/uint32 + +patternProperties: + "jr@[0-9a-f]+$": + type: object + description: + Child of the crypto node defines data processing interface to SEC 4 + across the peripheral bus for purposes of processing + cryptographic descriptors. The specified address + range can be made visible to one (or more) cores. + The interrupt defined for this node is controlled within + the address range of this node. + + properties: + compatible: + enum: + - fsl,sec-v4.0-job-ring + + reg: + maxItems: 1 + + interrupts: + description: + Specifies the interrupts generated by this device. The value of the + interrupts property consists of one interrupt specifier. The format + of the specifier is defined by the binding document describing the + node's interrupt parent. + maxItems: 1 + + fsl,liodn: + description: + Specifies the LIODN to be used in conjunction with the ppid-to-liodn + table that specifies the PPID to LIODN mapping. Needed if the PAMU + is used. Value is a 12 bit value where value is a LIODN ID for this + JR. This property is normally set by boot firmware. + $ref: /schemas/types.yaml#/definitions/uint32-array + maximum: 0x1 + + required: + - compatible + - reg + - interrupts + + "rtic@[0-9a-f]+$": + type: object + description: + Run Time Integrity Check (RTIC) Node. Child node of the crypto node. + Defines a register space that contains up to 5 sets of addresses and + their lengths (sizes) that will be checked at run time. After an + initial hash result is calculated, these addresses are checked by HW + to monitor any change. If any memory is modified, a Security Violation + is triggered (see SNVS definition). + + properties: + compatible: + enum: + - fsl,sec-v4.0-rtic + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + reg: + minItems: 1 + maxItems: 2 + + ranges: + description: + A standard property. Specifies the physical address range of the + SEC 4 register space (-SNVS not included). A triplet that includes + the child address, parent address, & length. + + required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + + patternProperties: + "rtic-[a-f]@[0-9]+$": + type: object + description: + Run Time Integrity Check (RTIC) Memory Node. A child node that + defines individual RTIC memory regions that are used to perform + run-time integrity check of memory areas that should not modified. + The node defines a register that contains the memory address & + length (combined) and a second register that contains the hash + result in big endian format. + + properties: + compatible: + enum: + - fsl,sec-v4.0-rtic-memory + + reg: + minItems: 1 + maxItems: 2 + + fsl,rtic-region: + description: + Specifies the HW address (36 bit address) for this region + followed by the length of the HW partition to be checked; + the address is represented as a 64 bit quantity followed + by a 32 bit length. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 3 + + fsl,liodn: + description: + Specifies the LIODN to be used in conjunction with + the ppid-to-liodn table that specifies the PPID to LIODN + mapping. Needed if the PAMU is used. Value is a 12 bit value + where value is a LIODN ID for this RTIC memory region. This + property is normally set by boot firmware. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 3 + + required: + - compatible + - reg + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + # iMX6QDL/SX requires four clocks + - | + #include + #include + + crypto@300000 { + compatible = "fsl,sec-v4.0"; + fsl,sec-era = <2>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x300000 0x10000>; + ranges = <0 0x300000 0x10000>; + interrupt-parent = <&mpic>; + interrupts = <92 2>; + clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, + <&clks IMX6QDL_CLK_CAAM_ACLK>, + <&clks IMX6QDL_CLK_CAAM_IPG>, + <&clks IMX6QDL_CLK_EIM_SLOW>; + clock-names = "mem", "aclk", "ipg", "emi_slow"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <88 2>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <89 2>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <90 2>; + }; + + sec_jr3: jr@4000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x4000 0x1000>; + interrupt-parent = <&mpic>; + interrupts = <91 2>; + }; + + rtic@6000 { + compatible = "fsl,sec-v4.0-rtic"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x6000 0x100>; + ranges = <0x0 0x6100 0xe00>; + + rtic_a: rtic-a@0 { + compatible = "fsl,sec-v4.0-rtic-memory"; + reg = <0x00 0x20 0x100 0x80>; + }; + + rtic_b: rtic-b@20 { + compatible = "fsl,sec-v4.0-rtic-memory"; + reg = <0x20 0x20 0x200 0x80>; + }; + + rtic_c: rtic-c@40 { + compatible = "fsl,sec-v4.0-rtic-memory"; + reg = <0x40 0x20 0x300 0x80>; + }; + + rtic_d: rtic-d@60 { + compatible = "fsl,sec-v4.0-rtic-memory"; + reg = <0x60 0x20 0x500 0x80>; + }; + }; + }; + + # iMX6UL does only require three clocks + - | + #include + #include + + crypto: crypto@2140000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2140000 0x3c000>; + ranges = <0 0x2140000 0x3c000>; + interrupts = ; + + clocks = <&clks IMX6UL_CLK_CAAM_IPG>, + <&clks IMX6UL_CLK_CAAM_ACLK>, + <&clks IMX6UL_CLK_CAAM_MEM>; + clock-names = "ipg", "aclk", "mem"; + }; +... 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Wed, 1 Mar 2023 01:52:11 +0000 From: "Peng Fan (OSS)" To: herbert@gondor.apana.org.au, davem@davemloft.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, horia.geanta@nxp.com, pankaj.gupta@nxp.com, gaurav.jain@nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, stefan@agner.ch, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan Subject: [PATCH 3/9] dt-bindings: crypto: fsl-sec4: support sec5.4/0 and i.MX6UL Date: Wed, 1 Mar 2023 09:56:56 +0800 Message-Id: <20230301015702.3388458-4-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230301015702.3388458-1-peng.fan@oss.nxp.com> References: <20230301015702.3388458-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0022.apcprd02.prod.outlook.com (2603:1096:4:1f4::16) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|DBBPR04MB7546:EE_ X-MS-Office365-Filtering-Correlation-Id: 353e6c94-94a7-4ecb-8d0d-08db19f79301 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Peng Fan --- .../devicetree/bindings/crypto/fsl-sec4.yaml | 58 ++++++++++++++++--- 1 file changed, 50 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml index 678c8389ef49..1b801ae5ab51 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.yaml @@ -45,8 +45,18 @@ maintainers: properties: compatible: - enum: - - fsl,sec-v4.0 + oneOf: + - enum: + - fsl,sec-v4.0 + - items: + - enum: + - fsl,imx6ul-caam + - fsl,sec-v5.0 + - const: fsl,sec-v4.0 + - items: + - const: fsl,sec-v5.4 + - const: fsl,sec-v5.0 + - const: fsl,sec-v4.0 "#address-cells": const: 1 @@ -77,6 +87,8 @@ properties: clock-names: oneOf: + - items: + - const: ipg - items: - const: mem - const: aclk @@ -85,11 +97,17 @@ properties: - items: - const: aclk - const: ipg + - items: + - const: ipg + - const: aclk - items: - const: ipg - const: aclk - const: mem + dma-coherent: + type: boolean + fsl,sec-era: description: Optional. A standard property. Define the 'ERA' of the SEC device. @@ -108,8 +126,16 @@ patternProperties: properties: compatible: - enum: - - fsl,sec-v4.0-job-ring + oneOf: + - enum: + - fsl,sec-v4.0-job-ring + - items: + - const: fsl,sec-v5.0-job-ring + - const: fsl,sec-v4.0-job-ring + - items: + - const: fsl,sec-v5.4-job-ring + - const: fsl,sec-v5.0-job-ring + - const: fsl,sec-v4.0-job-ring reg: maxItems: 1 @@ -148,8 +174,16 @@ patternProperties: properties: compatible: - enum: - - fsl,sec-v4.0-rtic + oneOf: + - enum: + - fsl,sec-v4.0-rtic + - items: + - const: fsl,sec-v5.0-rtic + - const: fsl,sec-v4.0-rtic + - items: + - const: fsl,sec-v5.4-rtic + - const: fsl,sec-v5.0-rtic + - const: fsl,sec-v4.0-rtic "#address-cells": const: 1 @@ -187,8 +221,16 @@ patternProperties: properties: compatible: - enum: - - fsl,sec-v4.0-rtic-memory + oneOf: + - enum: + - fsl,sec-v4.0-rtic-memory + - items: + - const: fsl,sec-v5.0-rtic-memory + - const: fsl,sec-v4.0-rtic-memory + - items: + - const: fsl,sec-v5.4-rtic-memory + - const: fsl,sec-v5.0-rtic-memory + - const: fsl,sec-v4.0-rtic-memory reg: minItems: 1 From patchwork Wed Mar 1 01:56:57 2023 Content-Type: text/plain; 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Wed, 1 Mar 2023 01:52:16 +0000 From: "Peng Fan (OSS)" To: herbert@gondor.apana.org.au, davem@davemloft.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, horia.geanta@nxp.com, pankaj.gupta@nxp.com, gaurav.jain@nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, stefan@agner.ch, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan Subject: [PATCH 4/9] dt-bindings: crypto: add fsl-sec4-snvs DT schema Date: Wed, 1 Mar 2023 09:56:57 +0800 Message-Id: <20230301015702.3388458-5-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230301015702.3388458-1-peng.fan@oss.nxp.com> References: <20230301015702.3388458-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0022.apcprd02.prod.outlook.com (2603:1096:4:1f4::16) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|DBBPR04MB7546:EE_ X-MS-Office365-Filtering-Correlation-Id: 9e135365-3ce7-4fb2-10dc-08db19f795ce X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This function monitors security state information & reports + security violations. This also included rtc, system power off and ON/OFF + key. + + For more information on SEC4, ref fsl-sec4-crypto.yaml + +maintainers: + - Peng Fan + +properties: + compatible: + oneOf: + - items: + - const: fsl,sec-v4.0-mon + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + description: + A standard property. Specifies the physical address range of the SNVS + register space. A triplet that includes the child address, parent + address, & length. + + interrupts: + description: + Specifies the interrupts generated by this device. The value of the + interrupts property consists of one interrupt specifier. The format + of the specifier is defined by the binding document describing the + node's interrupt parent. + minItems: 1 + maxItems: 2 + + snvs-rtc-lp: + type: object + description: + Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node. A SNVS + child node that defines SNVS LP RTC. + + properties: + compatible: + enum: + - fsl,sec-v4.0-mon-rtc-lp + + interrupts: + minItems: 1 + maxItems: 2 + + regmap: + description: This is phandle to the register map node. + $ref: /schemas/types.yaml#/definitions/phandle + + offset: + description: LP register offset. default it is 0x34. + $ref: /schemas/types.yaml#/definitions/uint32 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: snvs-rtc + + required: + - compatible + - interrupts + - regmap + + snvs-powerkey: + type: object + description: + The snvs-pwrkey is designed to enable POWER key function which + controlled by SNVS ONOFF, the driver can report the status of POWER + key and wakeup system if pressed after system suspend. + + properties: + compatible: + enum: + - fsl,sec-v4.0-pwrkey + + interrupts: + description: The SNVS ON/OFF interrupt number to the CPU(s). + maxItems: 1 + + linux,keycode: + description: Keycode to emit, KEY_POWER by default. + $ref: /schemas/types.yaml#/definitions/int32 + + regmap: + description: This is phandle to the register map node. + $ref: /schemas/types.yaml#/definitions/phandle + + wakeup-source: + description: Button can wake-up the system. + type: boolean + + required: + - compatible + - interrupts + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + sec_mon: sec_mon@314000 { + compatible = "fsl,sec-v4.0-mon", "syscon"; + reg = <0x314000 0x1000>; + + snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&sec_mon>; + offset = <0x34>; + interrupts = , + ; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs-rtc"; + }; + + snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&sec_mon>; + interrupts = ; + linux,keycode = <116>; /* KEY_POWER */ + wakeup-source; + }; + }; From patchwork Wed Mar 1 01:56:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13155424 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DC8DC64EC7 for ; Wed, 1 Mar 2023 01:53:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229756AbjCABx0 (ORCPT ); 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Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by DBBPR04MB7546.eurprd04.prod.outlook.com (2603:10a6:10:1f7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6134.30; Wed, 1 Mar 2023 01:52:21 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::f55a:cf12:da08:6d2a]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::f55a:cf12:da08:6d2a%3]) with mapi id 15.20.6134.027; Wed, 1 Mar 2023 01:52:21 +0000 From: "Peng Fan (OSS)" To: herbert@gondor.apana.org.au, davem@davemloft.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, horia.geanta@nxp.com, pankaj.gupta@nxp.com, gaurav.jain@nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, stefan@agner.ch, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan Subject: [PATCH 5/9] dt-bindings: crypto: fsl-sec4-snvs: add simple-mfd compatible Date: Wed, 1 Mar 2023 09:56:58 +0800 Message-Id: <20230301015702.3388458-6-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230301015702.3388458-1-peng.fan@oss.nxp.com> References: <20230301015702.3388458-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0022.apcprd02.prod.outlook.com (2603:1096:4:1f4::16) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|DBBPR04MB7546:EE_ X-MS-Office365-Filtering-Correlation-Id: 6dbe2e6f-265f-4ae9-fcd7-08db19f798a9 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Peng Fan --- Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml index 633e70f9b303..6878ae8127ec 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml @@ -27,6 +27,7 @@ properties: - items: - const: fsl,sec-v4.0-mon - const: syscon + - const: simple-mfd reg: maxItems: 1 From patchwork Wed Mar 1 01:56:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13155430 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEBE5C64EC4 for ; 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Signed-off-by: Peng Fan --- Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml index 6878ae8127ec..1a4b4975e1d9 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4-snvs.yaml @@ -24,6 +24,10 @@ maintainers: properties: compatible: oneOf: + - items: + - const: fsl,sec-v5.4-mon + - const: fsl,sec-v5.0-mon + - const: fsl,sec-v4.0-mon - items: - const: fsl,sec-v4.0-mon - const: syscon From patchwork Wed Mar 1 01:57:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13155431 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82A4EC7EE30 for ; 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Signed-off-by: Peng Fan --- .../devicetree/bindings/crypto/fsl-sec4.txt | 553 ------------------ 1 file changed, 553 deletions(-) delete mode 100644 Documentation/devicetree/bindings/crypto/fsl-sec4.txt diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt deleted file mode 100644 index 8f359f473ada..000000000000 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ /dev/null @@ -1,553 +0,0 @@ -===================================================================== -SEC 4 Device Tree Binding -Copyright (C) 2008-2011 Freescale Semiconductor Inc. - - CONTENTS - -Overview - -SEC 4 Node - -Job Ring Node - -Run Time Integrity Check (RTIC) Node - -Run Time Integrity Check (RTIC) Memory Node - -Secure Non-Volatile Storage (SNVS) Node - -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node - -Full Example - -NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator -Accelerator and Assurance Module (CAAM). - -===================================================================== -Overview - -DESCRIPTION - -SEC 4 h/w can process requests from 2 types of sources. -1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4). -2. Job Rings (HW interface between cores & SEC 4 registers). - -High Speed Data Path Configuration: - -HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts -such as the P4080. The number of simultaneous dequeues the QI can make is -equal to the number of Descriptor Controller (DECO) engines in a particular -SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus -dequeue from 5 subportals simultaneously. - -Job Ring Data Path Configuration: - -Each JR is located on a separate 4k page, they may (or may not) be made visible -in the memory partition devoted to a particular core. The P4080 has 4 JRs, so -up to 4 JRs can be configured; and all 4 JRs process requests in parallel. - -===================================================================== -SEC 4 Node - -Description - - Node defines the base address of the SEC 4 block. - This block specifies the address range of all global - configuration registers for the SEC 4 block. It - also receives interrupts from the Run Time Integrity Check - (RTIC) function within the SEC 4 block. - -PROPERTIES - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0" - - - fsl,sec-era - Usage: optional - Value type: - Definition: A standard property. Define the 'ERA' of the SEC - device. - - - #address-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing physical addresses in child nodes. - - - #size-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing the size of physical addresses in - child nodes. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical - address and length of the SEC4 configuration registers. - registers - - - ranges - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - range of the SEC 4.0 register space (-SNVS not included). A - triplet that includes the child address, parent address, & - length. - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by this - device. The value of the interrupts property - consists of one interrupt specifier. The format - of the specifier is defined by the binding document - describing the node's interrupt parent. - - - clocks - Usage: required if SEC 4.0 requires explicit enablement of clocks - Value type: - Definition: A list of phandle and clock specifier pairs describing - the clocks required for enabling and disabling SEC 4.0. - - - clock-names - Usage: required if SEC 4.0 requires explicit enablement of clocks - Value type: - Definition: A list of clock name strings in the same order as the - clocks property. - - Note: All other standard properties (see the Devicetree Specification) - are allowed but are optional. - - -EXAMPLE - -iMX6QDL/SX requires four clocks - - crypto@300000 { - compatible = "fsl,sec-v4.0"; - fsl,sec-era = <2>; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x300000 0x10000>; - ranges = <0 0x300000 0x10000>; - interrupt-parent = <&mpic>; - interrupts = <92 2>; - clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, - <&clks IMX6QDL_CLK_CAAM_ACLK>, - <&clks IMX6QDL_CLK_CAAM_IPG>, - <&clks IMX6QDL_CLK_EIM_SLOW>; - clock-names = "mem", "aclk", "ipg", "emi_slow"; - }; - - -iMX6UL does only require three clocks - - crypto: crypto@2140000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2140000 0x3c000>; - ranges = <0 0x2140000 0x3c000>; - interrupts = ; - - clocks = <&clks IMX6UL_CLK_CAAM_MEM>, - <&clks IMX6UL_CLK_CAAM_ACLK>, - <&clks IMX6UL_CLK_CAAM_IPG>; - clock-names = "mem", "aclk", "ipg"; - }; - -===================================================================== -Job Ring (JR) Node - - Child of the crypto node defines data processing interface to SEC 4 - across the peripheral bus for purposes of processing - cryptographic descriptors. The specified address - range can be made visible to one (or more) cores. - The interrupt defined for this node is controlled within - the address range of this node. - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0-job-ring" - - - reg - Usage: required - Value type: - Definition: Specifies a two JR parameters: an offset from - the parent physical address and the length the JR registers. - - - fsl,liodn - Usage: optional-but-recommended - Value type: - Definition: - Specifies the LIODN to be used in conjunction with - the ppid-to-liodn table that specifies the PPID to LIODN mapping. - Needed if the PAMU is used. Value is a 12 bit value - where value is a LIODN ID for this JR. This property is - normally set by boot firmware. - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by this - device. The value of the interrupts property - consists of one interrupt specifier. The format - of the specifier is defined by the binding document - describing the node's interrupt parent. - -EXAMPLE - jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - fsl,liodn = <0x081>; - interrupt-parent = <&mpic>; - interrupts = <88 2>; - }; - - -===================================================================== -Run Time Integrity Check (RTIC) Node - - Child node of the crypto node. Defines a register space that - contains up to 5 sets of addresses and their lengths (sizes) that - will be checked at run time. After an initial hash result is - calculated, these addresses are checked by HW to monitor any - change. If any memory is modified, a Security Violation is - triggered (see SNVS definition). - - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0-rtic". - - - #address-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing physical addresses in child nodes. Must - have a value of 1. - - - #size-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing the size of physical addresses in - child nodes. Must have a value of 1. - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies a two parameters: - an offset from the parent physical address and the length - the SEC4 registers. - - - ranges - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - range of the SEC 4 register space (-SNVS not included). A - triplet that includes the child address, parent address, & - length. - -EXAMPLE - rtic@6000 { - compatible = "fsl,sec-v4.0-rtic"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x6000 0x100>; - ranges = <0x0 0x6100 0xe00>; - }; - -===================================================================== -Run Time Integrity Check (RTIC) Memory Node - A child node that defines individual RTIC memory regions that are used to - perform run-time integrity check of memory areas that should not modified. - The node defines a register that contains the memory address & - length (combined) and a second register that contains the hash result - in big endian format. - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0-rtic-memory". - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies two parameters: - an offset from the parent physical address and the length: - - 1. The location of the RTIC memory address & length registers. - 2. The location RTIC hash result. - - - fsl,rtic-region - Usage: optional-but-recommended - Value type: - Definition: - Specifies the HW address (36 bit address) for this region - followed by the length of the HW partition to be checked; - the address is represented as a 64 bit quantity followed - by a 32 bit length. - - - fsl,liodn - Usage: optional-but-recommended - Value type: - Definition: - Specifies the LIODN to be used in conjunction with - the ppid-to-liodn table that specifies the PPID to LIODN - mapping. Needed if the PAMU is used. Value is a 12 bit value - where value is a LIODN ID for this RTIC memory region. This - property is normally set by boot firmware. - -EXAMPLE - rtic-a@0 { - compatible = "fsl,sec-v4.0-rtic-memory"; - reg = <0x00 0x20 0x100 0x80>; - fsl,liodn = <0x03c>; - fsl,rtic-region = <0x12345678 0x12345678 0x12345678>; - }; - -===================================================================== -Secure Non-Volatile Storage (SNVS) Node - - Node defines address range and the associated - interrupt for the SNVS function. This function - monitors security state information & reports - security violations. This also included rtc, - system power off and ON/OFF key. - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0-mon" and "syscon". - - - reg - Usage: required - Value type: - Definition: A standard property. Specifies the physical - address and length of the SEC4 configuration - registers. - - - #address-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing physical addresses in child nodes. Must - have a value of 1. - - - #size-cells - Usage: required - Value type: - Definition: A standard property. Defines the number of cells - for representing the size of physical addresses in - child nodes. Must have a value of 1. - - - ranges - Usage: required - Value type: - Definition: A standard property. Specifies the physical address - range of the SNVS register space. A triplet that includes - the child address, parent address, & length. - - - interrupts - Usage: optional - Value type: - Definition: Specifies the interrupts generated by this - device. The value of the interrupts property - consists of one interrupt specifier. The format - of the specifier is defined by the binding document - describing the node's interrupt parent. - -EXAMPLE - sec_mon@314000 { - compatible = "fsl,sec-v4.0-mon", "syscon"; - reg = <0x314000 0x1000>; - ranges = <0 0x314000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <93 2>; - }; - -===================================================================== -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node - - A SNVS child node that defines SNVS LP RTC. - - - compatible - Usage: required - Value type: - Definition: Must include "fsl,sec-v4.0-mon-rtc-lp". - - - interrupts - Usage: required - Value type: - Definition: Specifies the interrupts generated by this - device. The value of the interrupts property - consists of one interrupt specifier. The format - of the specifier is defined by the binding document - describing the node's interrupt parent. - - - regmap - Usage: required - Value type: - Definition: this is phandle to the register map node. - - - offset - Usage: option - value type: - Definition: LP register offset. default it is 0x34. - - - clocks - Usage: optional, required if SNVS LP RTC requires explicit - enablement of clocks - Value type: - Definition: a clock specifier describing the clock required for - enabling and disabling SNVS LP RTC. - - - clock-names - Usage: optional, required if SNVS LP RTC requires explicit - enablement of clocks - Value type: - Definition: clock name string should be "snvs-rtc". - -EXAMPLE - sec_mon_rtc_lp@1 { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - interrupts = <93 2>; - regmap = <&snvs>; - offset = <0x34>; - clocks = <&clks IMX7D_SNVS_CLK>; - clock-names = "snvs-rtc"; - }; - -===================================================================== -System ON/OFF key driver - - The snvs-pwrkey is designed to enable POWER key function which controlled - by SNVS ONOFF, the driver can report the status of POWER key and wakeup - system if pressed after system suspend. - - - compatible: - Usage: required - Value type: - Definition: Mush include "fsl,sec-v4.0-pwrkey". - - - interrupts: - Usage: required - Value type: - Definition: The SNVS ON/OFF interrupt number to the CPU(s). - - - linux,keycode: - Usage: option - Value type: - Definition: Keycode to emit, KEY_POWER by default. - - - wakeup-source: - Usage: option - Value type: - Definition: Button can wake-up the system. - - - regmap: - Usage: required: - Value type: - Definition: this is phandle to the register map node. - -EXAMPLE: - snvs-pwrkey@020cc000 { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = <0 4 0x4> - linux,keycode = <116>; /* KEY_POWER */ - wakeup-source; - }; - -===================================================================== -FULL EXAMPLE - - crypto: crypto@300000 { - compatible = "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x300000 0x10000>; - ranges = <0 0x300000 0x10000>; - interrupt-parent = <&mpic>; - interrupts = <92 2>; - - sec_jr0: jr@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <88 2>; - }; - - sec_jr1: jr@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <89 2>; - }; - - sec_jr2: jr@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <90 2>; - }; - - sec_jr3: jr@4000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x4000 0x1000>; - interrupt-parent = <&mpic>; - interrupts = <91 2>; - }; - - rtic@6000 { - compatible = "fsl,sec-v4.0-rtic"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x6000 0x100>; - ranges = <0x0 0x6100 0xe00>; - - rtic_a: rtic-a@0 { - compatible = "fsl,sec-v4.0-rtic-memory"; - reg = <0x00 0x20 0x100 0x80>; - }; - - rtic_b: rtic-b@20 { - compatible = "fsl,sec-v4.0-rtic-memory"; - reg = <0x20 0x20 0x200 0x80>; - }; - - rtic_c: rtic-c@40 { - compatible = "fsl,sec-v4.0-rtic-memory"; - reg = <0x40 0x20 0x300 0x80>; - }; - - rtic_d: rtic-d@60 { - compatible = "fsl,sec-v4.0-rtic-memory"; - reg = <0x60 0x20 0x500 0x80>; - }; - }; - }; - - sec_mon: sec_mon@314000 { - compatible = "fsl,sec-v4.0-mon"; - reg = <0x314000 0x1000>; - ranges = <0 0x314000 0x1000>; - - sec_mon_rtc_lp@34 { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&sec_mon>; - offset = <0x34>; - interrupts = <93 2>; - clocks = <&clks IMX7D_SNVS_CLK>; - clock-names = "snvs-rtc"; - }; - - snvs-pwrkey@020cc000 { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&sec_mon>; - interrupts = <0 4 0x4>; - linux,keycode = <116>; /* KEY_POWER */ - wakeup-source; - }; - }; - -===================================================================== From patchwork Wed Mar 1 01:57:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13155432 X-Patchwork-Delegate: herbert@gondor.apana.org.au Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 070B4C7EE30 for ; Wed, 1 Mar 2023 01:54:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229781AbjCAByb (ORCPT ); Tue, 28 Feb 2023 20:54:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229789AbjCABy3 (ORCPT ); Tue, 28 Feb 2023 20:54:29 -0500 Received: from EUR01-VE1-obe.outbound.protection.outlook.com (mail-ve1eur01on2051.outbound.protection.outlook.com [40.107.14.51]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29E532E0C9; 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Wed, 1 Mar 2023 01:52:36 +0000 From: "Peng Fan (OSS)" To: herbert@gondor.apana.org.au, davem@davemloft.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, horia.geanta@nxp.com, pankaj.gupta@nxp.com, gaurav.jain@nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, stefan@agner.ch, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan Subject: [PATCH 8/9] dt-bindings: crypto: fsl-sec4-snvs: add snvs-lpgpr support Date: Wed, 1 Mar 2023 09:57:01 +0800 Message-Id: <20230301015702.3388458-9-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230301015702.3388458-1-peng.fan@oss.nxp.com> References: <20230301015702.3388458-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0022.apcprd02.prod.outlook.com (2603:1096:4:1f4::16) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|DBBPR04MB7546:EE_ X-MS-Office365-Filtering-Correlation-Id: 090c9973-1710-4421-a0e3-08db19f7a185 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Wed, 1 Mar 2023 01:52:41 +0000 From: "Peng Fan (OSS)" To: herbert@gondor.apana.org.au, davem@davemloft.net, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, horia.geanta@nxp.com, pankaj.gupta@nxp.com, gaurav.jain@nxp.com, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, stefan@agner.ch, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan Subject: [PATCH 9/9] dt-bindings: crypto: fsl-sec4-snvs: add poweroff support Date: Wed, 1 Mar 2023 09:57:02 +0800 Message-Id: <20230301015702.3388458-10-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230301015702.3388458-1-peng.fan@oss.nxp.com> References: <20230301015702.3388458-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI1PR02CA0022.apcprd02.prod.outlook.com (2603:1096:4:1f4::16) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|DBBPR04MB7546:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a278638-f018-41e5-52ad-08db19f7a466 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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