From patchwork Wed Mar 1 20:10:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13156411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E383C7EE23 for ; Wed, 1 Mar 2023 20:11:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0737110E241; Wed, 1 Mar 2023 20:11:49 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5B25A10E241 for ; Wed, 1 Mar 2023 20:11:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677701507; x=1709237507; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oxP7y9nxIsVXhDSJYI88qNHTJ24iNgXRzGb0wlKSQ98=; b=d1onNfEAr982ycVoHhq3H0ICpWAfNumexZLbxfHmwf2LHkcRKgOBofUY SwROrSAPSuPDVlSpOJp6qPx9Z6qne1R8CTK76leKRGV8WkX3k8I7EJ85Q 9BfmFLA/LgO6VmCGFFEMcYbb6wwPrMvBTf4X5Hecsn/lR+ZjQl4e+rF+M s99XHA8jgVMBIclhUQks5WV6rp0kSqgePuqseP14yBRnyghB7YogLGRUs O8AbjfJ4a/e78bEc7qvjna5Z5WpFKM14hvpYdgzxLW3tz6zIZ/Ko/uMWz YlDxGfCeJGExNWkIAxMW5i4tvOJ6L0ZXoZtYyBagD56nuujbdAKvybBrE w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="314933480" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="314933480" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 12:11:46 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="674691935" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="674691935" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 12:11:45 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Mar 2023 12:10:49 -0800 Message-Id: <20230301201053.928709-2-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230301201053.928709-1-radhakrishna.sripada@intel.com> References: <20230301201053.928709-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 1/5] drm/i915/mtl: Fix Wa_16015201720 implementation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The commit 2357f2b271ad ("drm/i915/mtl: Initial display workarounds") extended the workaround Wa_16015201720 to MTL. However the registers that the original WA implemented moved for MTL. Implement the workaround with the correct register. v3: Skip clock gating for pipe C, D DMC's and fix the title Fixes: 2357f2b271ad ("drm/i915/mtl: Initial display workarounds") Cc: Matt Atwood Cc: Lucas De Marchi Signed-off-by: Radhakrishna Sripada Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_dmc.c | 26 +++++++++++++++++++----- drivers/gpu/drm/i915/i915_reg.h | 10 ++++++--- 2 files changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index f70ada2357dc..b4283cf319f2 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -389,15 +389,12 @@ static void disable_all_event_handlers(struct drm_i915_private *i915) } } -static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) +static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) { enum pipe pipe; - if (DISPLAY_VER(i915) < 13) - return; - /* - * Wa_16015201720:adl-p,dg2, mtl + * Wa_16015201720:adl-p,dg2 * The WA requires clock gating to be disabled all the time * for pipe A and B. * For pipe C and D clock gating needs to be disabled only @@ -413,6 +410,25 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) PIPEDMC_GATING_DIS, 0); } +static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915) +{ + /* + * Wa_16015201720 + * The WA requires clock gating to be disabled all the time + * for pipe A and B. + */ + intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, + MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); +} + +static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) +{ + if (DISPLAY_VER(i915) >= 14 && enable) + return mtl_pipedmc_clock_gating_wa(i915); + else if (DISPLAY_VER(i915) == 13) + return adlp_pipedmc_clock_gating_wa(i915, enable); +} + void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe) { enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c1efa655fb68..7c9ac5b43831 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1794,9 +1794,13 @@ * GEN9 clock gating regs */ #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) -#define DARBF_GATING_DIS (1 << 27) -#define PWM2_GATING_DIS (1 << 14) -#define PWM1_GATING_DIS (1 << 13) +#define DARBF_GATING_DIS REG_BIT(27) +#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15) +#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14) +#define PWM2_GATING_DIS REG_BIT(14) +#define MTL_PIPEDMC_GATING_DIS_C REG_BIT(13) +#define PWM1_GATING_DIS REG_BIT(13) +#define MTL_PIPEDMC_GATING_DIS_D REG_BIT(12) #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) #define TGL_VRH_GATING_DIS REG_BIT(31) From patchwork Wed Mar 1 20:10:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13156414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7448C7EE33 for ; Wed, 1 Mar 2023 20:11:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0766710E256; Wed, 1 Mar 2023 20:11:53 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id AFA2A10E24B for ; Wed, 1 Mar 2023 20:11:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677701507; x=1709237507; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XZv71f37ibq5Slxyc6vT/ttFkZq4IJYO/iB3Gp33b9k=; b=R+Zquy4BFaGLd17mUi7KqdrNA9eTEZCSSq9YbI5kGTsGES1TJ5/wojti XqHXPZES0+rwdIq6uWtV87NtRcqhwYqx1eRgpbovKovNlaV+UU7LOQyzs YgEYJMH8S5xfy5vXBIuLIfL9ZBtQ3rwPXeQ6zLFVXl8OvS0670RQ8HavO Dk4m4AsyGdhFpBWlGhVeONRteNcLgH7frEBqKdTbFaxohWb2ZXtv9jZnn TPGjVfuk109cT8ln+LfX+TyjNYYIuIFoRkDnjO2E/fi3fkf6N9Qo543rH wce5lvrivke19btDpQsa5siG0ag/+SscYuPlJSXcIjhIIqLWchKGHo7Lb w==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="314933485" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="314933485" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 12:11:47 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="674691937" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="674691937" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 12:11:45 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Mar 2023 12:10:50 -0800 Message-Id: <20230301201053.928709-3-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230301201053.928709-1-radhakrishna.sripada@intel.com> References: <20230301201053.928709-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 2/5] drm/i915/gt: generate per tile debugfs files X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andi Shyti Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Andi Shyti In the view of multi-gt we want independent per gt debug files. In debugfs create gt0/ gt1/ ... gtN/ for tile related files. In 4 tiles, the debugfs would be structured as follows: /sys/kernel/debug/dri └── 0    ├── gt0    │   ├── drpc    │   ├── engines    │   ├── forcewake    │   ├── frequency    │   └── rps_boost    ├── gt1    │   ├── drpc    │   ├── engines    │   ├── forcewake    │   ├── frequency    │   └── rps_boost    ├── gt2    │   ├── drpc    │   ├── engines    │   ├── forcewake    │   ├── frequency    │   └── rps_boost    └─- gt3    :   ├── drpc    :   ├── engines    :   ├── forcewake       ├── frequency       └── rps_boost v2: Fix the missed assignment dbgfs_node Cc: Tvrtko Ursulin Signed-off-by: Andi Shyti Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 4 +++- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 5 ++++- drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c | 2 ++ 4 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c index 5fc2df01aa0d..4dc23b8d3aa2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c @@ -83,11 +83,13 @@ static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root) void intel_gt_debugfs_register(struct intel_gt *gt) { struct dentry *root; + char gtname[4]; if (!gt->i915->drm.primary->debugfs_root) return; - root = debugfs_create_dir("gt", gt->i915->drm.primary->debugfs_root); + snprintf(gtname, sizeof(gtname), "gt%u", gt->info.id); + root = debugfs_create_dir(gtname, gt->i915->drm.primary->debugfs_root); if (IS_ERR(root)) return; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index bb4dfe707a7d..e46aac1a41e6 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -42,6 +42,8 @@ struct intel_guc { /** @capture: the error-state-capture module's data and objects */ struct intel_guc_state_capture *capture; + struct dentry *dbgfs_node; + /** @sched_engine: Global engine used to submit requests to GuC */ struct i915_sched_engine *sched_engine; /** diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c index 195db8c9d420..55bc8b55fbc0 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c @@ -542,8 +542,11 @@ static int guc_log_relay_create(struct intel_guc_log *log) */ n_subbufs = 8; + if (!guc->dbgfs_node) + return -ENOENT; + guc_log_relay_chan = relay_open("guc_log", - i915->drm.primary->debugfs_root, + guc->dbgfs_node, subbuf_size, n_subbufs, &relay_callbacks, i915); if (!guc_log_relay_chan) { diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c index 284d6fbc2d08..2f93cc4e408a 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.c @@ -54,6 +54,8 @@ void intel_uc_debugfs_register(struct intel_uc *uc, struct dentry *gt_root) if (IS_ERR(root)) return; + uc->guc.dbgfs_node = root; + intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), uc); intel_guc_debugfs_register(&uc->guc, root); From patchwork Wed Mar 1 20:10:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13156415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39943C7EE30 for ; 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a="314933484" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="314933484" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 12:11:46 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="674691940" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="674691940" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 12:11:45 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Mar 2023 12:10:51 -0800 Message-Id: <20230301201053.928709-4-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230301201053.928709-1-radhakrishna.sripada@intel.com> References: <20230301201053.928709-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 3/5] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi , Paulo Zanoni Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Irq reset and post install are to be made multi-gt aware for the interrupts to work for the media tile on Meteorlake. Iterate through all the gts to process irq reset for each gt. Based on original version by Paulo and Tvrtko Cc: Paulo Zanoni Cc: Tvrtko Ursulin Reviewed-by: Lucas De Marchi Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 417c981e4968..9377f59c1ac2 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2759,16 +2759,19 @@ static void gen11_irq_reset(struct drm_i915_private *dev_priv) static void dg1_irq_reset(struct drm_i915_private *dev_priv) { - struct intel_gt *gt = to_gt(dev_priv); - struct intel_uncore *uncore = gt->uncore; + struct intel_gt *gt; + unsigned int i; dg1_master_intr_disable(dev_priv->uncore.regs); - gen11_gt_irq_reset(gt); - gen11_display_irq_reset(dev_priv); + for_each_gt(gt, dev_priv, i) { + gen11_gt_irq_reset(gt); - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); - GEN3_IRQ_RESET(uncore, GEN8_PCU_); + GEN3_IRQ_RESET(gt->uncore, GEN11_GU_MISC_); + GEN3_IRQ_RESET(gt->uncore, GEN8_PCU_); + } + + gen11_display_irq_reset(dev_priv); } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, @@ -3422,13 +3425,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) { - struct intel_gt *gt = to_gt(dev_priv); - struct intel_uncore *uncore = gt->uncore; u32 gu_misc_masked = GEN11_GU_MISC_GSE; + struct intel_gt *gt; + unsigned int i; - gen11_gt_irq_postinstall(gt); + for_each_gt(gt, dev_priv, i) { + gen11_gt_irq_postinstall(gt); - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked, + gu_misc_masked); + } if (HAS_DISPLAY(dev_priv)) { icp_irq_postinstall(dev_priv); @@ -3437,8 +3443,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) GEN11_DISPLAY_IRQ_ENABLE); } - dg1_master_intr_enable(uncore->regs); - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs); + intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR); } static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) From patchwork Wed Mar 1 20:10:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13156413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 54BFEC7EE23 for ; Wed, 1 Mar 2023 20:11:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0247D10E252; Wed, 1 Mar 2023 20:11:51 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 04BFF10E241 for ; Wed, 1 Mar 2023 20:11:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677701508; x=1709237508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VHn3ezUP4HIvkoPTlcuCHpjcJtDFKgQqgZPT278CkqQ=; b=HcFVus31lIDzyhKg6tNlP+FTlmplft+7yHQ/NUygRu8fVAFEovX4YJLi XwA9VnbSzobRl4PBufwq0/gzUiAWPFLfL2lO52JWI2K53j4WEHxaiH2u+ sJlj+Md2RPXUV1TJ2m4F59RGzDQodWnl5orbGw0uJMp8QxKy08n8KJO+w wE1v0Lr8yL/ZwiuBGStOYt1aNVeH+BJCA9dw6bBUudL2DbPevEKUpSAlG Pd44hPZWDryRU26Os70rQjiZeEoydSDYui5vw9UkvDJPx6RD+6MmkD46r pe+I4ABCKr5mSElyYhbY7XMaVFpWZl6rU0TFf6mrt0J4W5T/IUm3q9B5g Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="314933486" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="314933486" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 12:11:47 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="674691943" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="674691943" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 12:11:45 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Mar 2023 12:10:52 -0800 Message-Id: <20230301201053.928709-5-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230301201053.928709-1-radhakrishna.sripada@intel.com> References: <20230301201053.928709-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 4/5] drm/i915/fbdev: lock the fbdev obj before vma pin X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matthew Auld , Chris Wilson Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Tejas Upadhyay lock the fbdev obj before calling into i915_vma_pin_iomap(). This helps to solve below : <7>[ 93.563308] i915 0000:00:02.0: [drm:intelfb_create [i915]] no BIOS fb, allocating a new one <4>[ 93.581844] ------------[ cut here ]------------ <4>[ 93.581855] WARNING: CPU: 12 PID: 625 at drivers/gpu/drm/i915/gem/i915_gem_pages.c:424 i915_gem_object_pin_map+0x152/0x1c0 [i915] Fixes: f0b6b01b3efe ("drm/i915: Add ww context to intel_dpt_pin, v2.") Cc: Chris Wilson Cc: Matthew Auld Cc: Maarten Lankhorst Signed-off-by: Tejas Upadhyay Signed-off-by: Radhakrishna Sripada Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/display/intel_fbdev.c | 24 ++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 3659350061a7..2766d7ef0128 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -210,6 +210,7 @@ static int intelfb_create(struct drm_fb_helper *helper, bool prealloc = false; void __iomem *vaddr; struct drm_i915_gem_object *obj; + struct i915_gem_ww_ctx ww; int ret; mutex_lock(&ifbdev->hpd_lock); @@ -283,13 +284,24 @@ static int intelfb_create(struct drm_fb_helper *helper, info->fix.smem_len = vma->size; } - vaddr = i915_vma_pin_iomap(vma); - if (IS_ERR(vaddr)) { - drm_err(&dev_priv->drm, - "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr); - ret = PTR_ERR(vaddr); - goto out_unpin; + for_i915_gem_ww(&ww, ret, false) { + ret = i915_gem_object_lock(vma->obj, &ww); + + if (ret) + continue; + + vaddr = i915_vma_pin_iomap(vma); + if (IS_ERR(vaddr)) { + drm_err(&dev_priv->drm, + "Failed to remap framebuffer into virtual memory (%pe)\n", vaddr); + ret = PTR_ERR(vaddr); + continue; + } } + + if (ret) + goto out_unpin; + info->screen_base = vaddr; info->screen_size = vma->size; From patchwork Wed Mar 1 20:10:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13156412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B2BA7C7EE30 for ; Wed, 1 Mar 2023 20:11:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2BD2910E24D; Wed, 1 Mar 2023 20:11:50 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 12E7510E24B for ; Wed, 1 Mar 2023 20:11:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677701508; x=1709237508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Gn6zGOnEfxlc6H1QFJNZZ1b/nc79QxLXeNUqRpagSzA=; b=ETxzxo1D5KdbvYXNtgg6+1BdSXwL+PwzptTIZqfrt2F/QhWI43wfLclK ee7m4VgGTy4GSIk901M/BlDBlZMn3KMrbGOpobjChaIhWXyUkSp7itR+g ncaVT67nX7Tg2PG2iGB0W9X4EvwhFtAxoMXx+RJ8GuiW4mJrCzSsTSx3H EW2HsoKqATEz9dOV7oOZN0IlkkLQ5xtN/iHiKCOiEKycjRf9DFwoV0YyT 6iMbC4MsBBLW+TZf/UftjvQm1dOKeXry9uHUSxyIYeRsvGdWvwGQ6G7me 6c8ZipNwT0tK/Ay19srMJJkjL5ZzFjIQbHNBaeBGwxV8jPaAYQGJYtTUl g==; X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="314933487" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="314933487" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 12:11:47 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10636"; a="674691946" X-IronPort-AV: E=Sophos;i="5.98,225,1673942400"; d="scan'208";a="674691946" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2023 12:11:45 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 1 Mar 2023 12:10:53 -0800 Message-Id: <20230301201053.928709-6-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230301201053.928709-1-radhakrishna.sripada@intel.com> References: <20230301201053.928709-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 5/5] drm/i915/display/mtl: Program latch to phy reset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matt Roper Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: José Roberto de Souza Latch reset of phys during DC9 and when driver is unloaded to avoid phy reset. Specification ask us to program it closer to the step that enables DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy latch during driver load. BSpec: 49197 Reviewed-by: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Radhakrishna Sripada Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 743b919bb2cf..50098c77e3be 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1624,6 +1624,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, intel_power_well_enable(dev_priv, well); mutex_unlock(&power_domains->lock); + if (DISPLAY_VER(dev_priv) == 14) + intel_de_rmw(dev_priv, DC_STATE_EN, + HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); + /* 4. Enable CDCLK. */ intel_cdclk_init_hw(dev_priv); @@ -1677,6 +1681,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) /* 3. Disable CD clock */ intel_cdclk_uninit_hw(dev_priv); + if (DISPLAY_VER(dev_priv) == 14) + intel_de_rmw(dev_priv, DC_STATE_EN, 0, + HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH); + /* * 4. Disable Power Well 1 (PG1). * The AUX IO power wells are toggled on demand, so they are already diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7c9ac5b43831..fa1905cc5a99 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7360,6 +7360,8 @@ enum skl_power_gate { #define DC_STATE_DISABLE 0 #define DC_STATE_EN_DC3CO REG_BIT(30) #define DC_STATE_DC3CO_STATUS REG_BIT(29) +#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21) +#define HOLD_PHY_PG1_LATCH REG_BIT(20) #define DC_STATE_EN_UPTO_DC5 (1 << 0) #define DC_STATE_EN_DC9 (1 << 3) #define DC_STATE_EN_UPTO_DC6 (2 << 0)