From patchwork Thu Mar 2 15:26:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felix Moessbauer X-Patchwork-Id: 13157410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E867C678D4 for ; Thu, 2 Mar 2023 15:30:50 +0000 (UTC) Received: from mta-65-225.siemens.flowmailer.net (mta-65-225.siemens.flowmailer.net [185.136.65.225]) by mx.groups.io with SMTP id smtpd.web11.18897.1677770843620646369 for ; Thu, 02 Mar 2023 07:27:25 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=felix.moessbauer@siemens.com header.s=fm1 header.b=Pbbs0xuO; spf=pass (domain: rts-flowmailer.siemens.com, ip: 185.136.65.225, mailfrom: fm-72506-20230302152721110eb89704e9561fd8-0vwb3d@rts-flowmailer.siemens.com) Received: by mta-65-225.siemens.flowmailer.net with ESMTPSA id 20230302152721110eb89704e9561fd8 for ; Thu, 02 Mar 2023 16:27:21 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=felix.moessbauer@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=upKed2U3no8AR0DzZU+PVcqh8pShiAeTurXE57Rfag0=; b=Pbbs0xuO4MtldyDMFANsCkEaVWgCPlyzNY0oUTpY1DlNqCyuOJIgMsL7Z0SZGFuF4qURN0 Rg0TH/qt/sSh/lT+IcsfMAXyAe0Fn6kvw0+xfAyhHARh6KWpvlCE417oMHspXXDD5qdWgp09 0xYpMCHhzIAu5JcH0fUcON1q5mQGE=; From: Felix Moessbauer To: cip-dev@lists.cip-project.org Cc: daniel.bovensiepen@siemens.com, jan.kiszka@siemens.com, quirin.gylstorff@siemens.com, Felix Moessbauer Subject: [isar-cip-core][PATCH v3 1/9] fix efibootguard for riscv64 Date: Thu, 2 Mar 2023 15:26:51 +0000 Message-Id: <20230302152659.2096307-2-felix.moessbauer@siemens.com> In-Reply-To: <20230302152659.2096307-1-felix.moessbauer@siemens.com> References: <20230302152659.2096307-1-felix.moessbauer@siemens.com> MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-72506:519-21489:flowmailer List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 02 Mar 2023 15:30:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/10876 This commit backports an upstream patch for efibootguard that fixes the riscv64 install location. As it is not yet in an EBG release, we add it as a patch here. No internal logic of EBG is changed, hence no dedicated release is needed. Signed-off-by: Felix Moessbauer --- recipes-bsp/efibootguard/efibootguard_0.13.bb | 3 ++ ...01-add-machine-type-name-for-riscv64.patch | 39 +++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch diff --git a/recipes-bsp/efibootguard/efibootguard_0.13.bb b/recipes-bsp/efibootguard/efibootguard_0.13.bb index 3279854..dd76198 100644 --- a/recipes-bsp/efibootguard/efibootguard_0.13.bb +++ b/recipes-bsp/efibootguard/efibootguard_0.13.bb @@ -21,6 +21,9 @@ SRC_URI = " \ file://debian \ " SRC_URI[sha256sum] = "639a6d8f687cb099b2e9b01eb08ad1494267fe26b5d903b4d405d0737feb989b" +# add riscv64 support +SRC_URI += "file://0001-add-machine-type-name-for-riscv64.patch" +CHANGELOG_V = "${PV}+cip" PROVIDES = "${PN}" PROVIDES += "${PN}-dev" diff --git a/recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch b/recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch new file mode 100644 index 0000000..adc7962 --- /dev/null +++ b/recipes-bsp/efibootguard/files/0001-add-machine-type-name-for-riscv64.patch @@ -0,0 +1,39 @@ +From 391dd5e04b17be6f5184afb2de4853795f1d5620 Mon Sep 17 00:00:00 2001 +From: Felix Moessbauer +Date: Tue, 31 Jan 2023 09:27:31 +0100 +Subject: [PATCH 1/1] add machine type name for riscv64 + +By adding the machine type name, the generated efi binary for +riscv64 is suffixed with the corresponding efi machine name. + +Signed-off-by: Felix Moessbauer +Signed-off-by: Jan Kiszka +--- + configure.ac | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/configure.ac b/configure.ac +index d8f9d3a..90d70b0 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -87,6 +87,7 @@ SET_ARCH(X86_64, x86_64*) + SET_ARCH(IA64, ia64*) + SET_ARCH(AARCH64, aarch64*) + SET_ARCH(ARM, arm*) ++SET_ARCH(RISCV64, riscv64*) + + ARCH=$(echo $host | sed "s/\(-\).*$//") + +@@ -103,6 +104,9 @@ AM_COND_IF(ARCH_AARCH64, [ + AM_COND_IF(ARCH_ARM, [ + MACHINE_TYPE_NAME=arm]) + ++AM_COND_IF(ARCH_RISCV64, [ ++ MACHINE_TYPE_NAME=riscv64]) ++ + AC_SUBST([ARCH]) + AC_SUBST([MACHINE_TYPE_NAME]) + AM_CONDITIONAL([ARCH_IS_X86], [test "$ARCH" = "ia32" -o "$ARCH" = "x86_64"]) +-- +2.30.2 + From patchwork Thu Mar 2 15:26:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felix Moessbauer X-Patchwork-Id: 13157409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51551C7EE2F for ; Thu, 2 Mar 2023 15:30:50 +0000 (UTC) Received: from mta-64-225.siemens.flowmailer.net (mta-64-225.siemens.flowmailer.net [185.136.64.225]) by mx.groups.io with SMTP id smtpd.web10.18834.1677770846576666441 for ; Thu, 02 Mar 2023 07:27:26 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=felix.moessbauer@siemens.com header.s=fm1 header.b=nEtMEum/; spf=pass (domain: rts-flowmailer.siemens.com, ip: 185.136.64.225, mailfrom: fm-72506-20230302152724fd9893325caeb33e89-acec1h@rts-flowmailer.siemens.com) Received: by mta-64-225.siemens.flowmailer.net with ESMTPSA id 20230302152724fd9893325caeb33e89 for ; Thu, 02 Mar 2023 16:27:24 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=felix.moessbauer@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=goUYLnCbE+z6Wgayx9Ahsq+uNzH0fly5PgAojaCCLes=; b=nEtMEum/qD6CkSNp6cgSCvUJl2I4uf2tBPe6+Z0C1gPLOfkQEBKm11vchp9fvHwJUwAcZb OLHFXsXAPQb97Zii6SCYkTChA8TSqE8YlL0v4bbsGyaFqn9SHgyaimQfR9kFU4dULbhsUSYY e6KTlqdrDnqAI2SRwgEWbd2jLswKI=; From: Felix Moessbauer To: cip-dev@lists.cip-project.org Cc: daniel.bovensiepen@siemens.com, jan.kiszka@siemens.com, quirin.gylstorff@siemens.com, Felix Moessbauer Subject: [isar-cip-core][PATCH v3 2/9] update cip-kernel-config Date: Thu, 2 Mar 2023 15:26:52 +0000 Message-Id: <20230302152659.2096307-3-felix.moessbauer@siemens.com> In-Reply-To: <20230302152659.2096307-1-felix.moessbauer@siemens.com> References: <20230302152659.2096307-1-felix.moessbauer@siemens.com> MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-72506:519-21489:flowmailer List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 02 Mar 2023 15:30:50 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/10877 This patch updates the cip-kernel-config revision to 3515389 to get support for qemu-riscv64. Signed-off-by: Felix Moessbauer --- recipes-kernel/linux/linux-cip-common.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/recipes-kernel/linux/linux-cip-common.inc b/recipes-kernel/linux/linux-cip-common.inc index 7148a98..6dda973 100644 --- a/recipes-kernel/linux/linux-cip-common.inc +++ b/recipes-kernel/linux/linux-cip-common.inc @@ -23,6 +23,6 @@ SRC_URI:append = " ${@ "git://gitlab.com/cip-project/cip-kernel/cip-kernel-confi if d.getVar('USE_CIP_KERNEL_CONFIG') == '1' else '' \ }" -SRCREV_cip-kernel-config ?= "ce52837418aea714e780e0cbc8afb9515c12cc1b" +SRCREV_cip-kernel-config ?= "351538952cfa7c6336e83bf66ca4f3bbdc06f89b" S = "${WORKDIR}/linux-cip-${PV}" From patchwork Thu Mar 2 15:26:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felix Moessbauer X-Patchwork-Id: 13157412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F872C7EE2F for ; Thu, 2 Mar 2023 15:31:00 +0000 (UTC) Received: from mta-64-227.siemens.flowmailer.net (mta-64-227.siemens.flowmailer.net [185.136.64.227]) by mx.groups.io with SMTP id smtpd.web11.18904.1677770861139122093 for ; Thu, 02 Mar 2023 07:27:41 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=felix.moessbauer@siemens.com header.s=fm1 header.b=M+oPK4Vj; spf=pass (domain: rts-flowmailer.siemens.com, ip: 185.136.64.227, mailfrom: fm-72506-202303021527393f98e5635d05ad2f47-xrfjsr@rts-flowmailer.siemens.com) Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 202303021527393f98e5635d05ad2f47 for ; Thu, 02 Mar 2023 16:27:39 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=felix.moessbauer@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=UMbJw3JZm4RUlfBTJ4DUQX0QLgYY8C2FV9u1vcuwSWw=; b=M+oPK4VjlVbhuCIWEpcjIxWTOcPIBHlvP48UwWlq0t/cLY1b4wdJELMKYqhjSiUa9S+sgL 0FgheFLKEHckYVV9qHuSXr7dg10LMRREIqacRVsgA6TyQk9MmDCCfoDZjLSV5lztGWV+Wi4Q T44FiYW+TnkKfMed2sYb/YWKs0rck=; From: Felix Moessbauer To: cip-dev@lists.cip-project.org Cc: daniel.bovensiepen@siemens.com, jan.kiszka@siemens.com, quirin.gylstorff@siemens.com, Felix Moessbauer Subject: [isar-cip-core][PATCH v3 3/9] refactor(u-boot): deploy via sstate-cache Date: Thu, 2 Mar 2023 15:26:53 +0000 Message-Id: <20230302152659.2096307-4-felix.moessbauer@siemens.com> In-Reply-To: <20230302152659.2096307-1-felix.moessbauer@siemens.com> References: <20230302152659.2096307-1-felix.moessbauer@siemens.com> MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-72506:519-21489:flowmailer List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 02 Mar 2023 15:31:00 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/10878 This patch refactors how the firmware.bin is deployed to the DEPLOY_DIR_IMAGE. Instead of directly copying, we now deploy via the sstate cache. By that, the cleanup is automatically handled and potential conflicts on the filename are reported. Signed-off-by: Felix Moessbauer --- recipes-bsp/u-boot/u-boot-qemu-common.inc | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/recipes-bsp/u-boot/u-boot-qemu-common.inc b/recipes-bsp/u-boot/u-boot-qemu-common.inc index 0a9a15a..4d8b240 100644 --- a/recipes-bsp/u-boot/u-boot-qemu-common.inc +++ b/recipes-bsp/u-boot/u-boot-qemu-common.inc @@ -13,11 +13,21 @@ require recipes-bsp/u-boot/u-boot-common.inc U_BOOT_BIN = "u-boot.bin" -do_deploy[dirs] = "${DEPLOY_DIR_IMAGE}" +DEPLOYDIR_U_BOOT = "${WORKDIR}/deploy-u-boot" +SSTATETASKS += "do_deploy" + +do_deploy[cleandirs] += "${DEPLOYDIR_U_BOOT}" +do_deploy[sstate-inputdirs] = "${DEPLOYDIR_U_BOOT}" +do_deploy[sstate-outputdirs] = "${DEPLOY_DIR_IMAGE}" do_deploy() { dpkg --fsys-tarfile "${WORKDIR}/u-boot-${MACHINE}_${PV}_${DISTRO_ARCH}.deb" | \ tar xOf - "./usr/lib/u-boot/${MACHINE}/${U_BOOT_BIN}" \ - > "${DEPLOY_DIR_IMAGE}/firmware.bin" + > "${DEPLOYDIR_U_BOOT}/firmware.bin" +} + +python do_deploy_setscene () { + sstate_setscene(d) } +addtask do_deploy_setscene addtask deploy after do_dpkg_build before do_deploy_deb From patchwork Thu Mar 2 15:26:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felix Moessbauer X-Patchwork-Id: 13157413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F446C678D4 for ; Thu, 2 Mar 2023 15:31:00 +0000 (UTC) Received: from mta-64-227.siemens.flowmailer.net (mta-64-227.siemens.flowmailer.net [185.136.64.227]) by mx.groups.io with SMTP id smtpd.web10.18841.1677770863423877111 for ; Thu, 02 Mar 2023 07:27:43 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=felix.moessbauer@siemens.com header.s=fm1 header.b=hSjFqxVz; spf=pass (domain: rts-flowmailer.siemens.com, ip: 185.136.64.227, mailfrom: fm-72506-202303021527411ed7e5c9a983d5b956-8ordox@rts-flowmailer.siemens.com) Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 202303021527411ed7e5c9a983d5b956 for ; Thu, 02 Mar 2023 16:27:41 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=felix.moessbauer@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=LmMPfiOEYL382rOy/Flrt2p72Ug5pHJo838aBYFPltw=; b=hSjFqxVz5jZnbOWn5c1YuKUyba4B66NAE/PpMlW/OK0jItxFSjrVonvANVWUaZyqbq9CK6 5dTP4/1sdJMor2+LEyqUNLoIGLEzss+5iuivXzNNb+OwZqXVVp7YGrkSBA7RD4VnVIwzhRXz ETc02ueA97Pd2f5Ep+YnvJCy+yDac=; From: Felix Moessbauer To: cip-dev@lists.cip-project.org Cc: daniel.bovensiepen@siemens.com, jan.kiszka@siemens.com, quirin.gylstorff@siemens.com, Felix Moessbauer Subject: [isar-cip-core][PATCH v3 4/9] wic(ebg): add support for riscv64 Date: Thu, 2 Mar 2023 15:26:54 +0000 Message-Id: <20230302152659.2096307-5-felix.moessbauer@siemens.com> In-Reply-To: <20230302152659.2096307-1-felix.moessbauer@siemens.com> References: <20230302152659.2096307-1-felix.moessbauer@siemens.com> MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-72506:519-21489:flowmailer List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 02 Mar 2023 15:31:00 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/10879 This patch adds the mapping between the efi architecture and the distro architecture for riscv64. Signed-off-by: Felix Moessbauer --- scripts/lib/wic/plugins/source/efibootguard-boot.py | 6 ++++-- scripts/lib/wic/plugins/source/efibootguard-efi.py | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/scripts/lib/wic/plugins/source/efibootguard-boot.py b/scripts/lib/wic/plugins/source/efibootguard-boot.py index 3d6b2d7..0de28ca 100644 --- a/scripts/lib/wic/plugins/source/efibootguard-boot.py +++ b/scripts/lib/wic/plugins/source/efibootguard-boot.py @@ -185,13 +185,15 @@ class EfibootguardBootPlugin(SourcePlugin): "amd64": "x64", "arm64": "aa64", "armhf": "arm", - "i386": "ia32" + "i386": "ia32", + "riscv64" : "riscv64" } distro_to_lib_arch = { "amd64": "x86_64-linux-gnu", "arm64": "aarch64-linux-gnu", "armhf": "arm-linux-gnueabihf", - "i386": "i386-linux-gnu" + "i386": "i386-linux-gnu", + "riscv64": "riscv64-linux-gnu", } rootfs_path = rootfs_dir.get('ROOTFS_DIR') distro_arch = get_bitbake_var("DISTRO_ARCH") diff --git a/scripts/lib/wic/plugins/source/efibootguard-efi.py b/scripts/lib/wic/plugins/source/efibootguard-efi.py index 2d16fe3..d6cdf0f 100644 --- a/scripts/lib/wic/plugins/source/efibootguard-efi.py +++ b/scripts/lib/wic/plugins/source/efibootguard-efi.py @@ -56,14 +56,16 @@ class EfibootguardEFIPlugin(SourcePlugin): "amd64": "x64", "arm64": "aa64", "armhf": "arm", - "i386": "ia32" + "i386": "ia32", + "riscv64" : "riscv64" } distro_to_lib_arch = { "amd64": "x86_64-linux-gnu", "arm64": "aarch64-linux-gnu", "armhf": "arm-linux-gnueabihf", - "i386": "i386-linux-gnu" + "i386": "i386-linux-gnu", + "riscv64": "riscv64-linux-gnu", } distro_arch = get_bitbake_var("DISTRO_ARCH") From patchwork Thu Mar 2 15:26:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felix Moessbauer X-Patchwork-Id: 13157415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D7E3C7EE2F for ; Thu, 2 Mar 2023 15:31:10 +0000 (UTC) Received: from mta-64-227.siemens.flowmailer.net (mta-64-227.siemens.flowmailer.net [185.136.64.227]) by mx.groups.io with SMTP id smtpd.web11.18904.1677770861139122093 for ; Thu, 02 Mar 2023 07:27:44 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=felix.moessbauer@siemens.com header.s=fm1 header.b=k6LXxsoO; spf=pass (domain: rts-flowmailer.siemens.com, ip: 185.136.64.227, mailfrom: fm-72506-20230302152744790d7dbd0ce9793029-1wywn2@rts-flowmailer.siemens.com) Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 20230302152744790d7dbd0ce9793029 for ; Thu, 02 Mar 2023 16:27:44 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=felix.moessbauer@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=gYPWaRxASQmcxny66E9thj+4ib+loS6je9VTXZzzopg=; b=k6LXxsoO8iE6nv/3PBFwuiaxe6QR6m7gyASNOwCCndHL5hjVpPuYn7uKHIAj0+3YlNnPfH QQanj1ChSmjQ+yGWlCiZ1Nu391q27x2PzsE5zVrRhaiOZLI5GPIWt7qAvYA0M5CN7vEcJ9oB uovadMaKtRI8dWDm00Zi3p/87/ZbA=; From: Felix Moessbauer To: cip-dev@lists.cip-project.org Cc: daniel.bovensiepen@siemens.com, jan.kiszka@siemens.com, quirin.gylstorff@siemens.com, Felix Moessbauer Subject: [isar-cip-core][PATCH v3 5/9] add opensbi with u-boot payload for riscv64 Date: Thu, 2 Mar 2023 15:26:55 +0000 Message-Id: <20230302152659.2096307-6-felix.moessbauer@siemens.com> In-Reply-To: <20230302152659.2096307-1-felix.moessbauer@siemens.com> References: <20230302152659.2096307-1-felix.moessbauer@siemens.com> MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-72506:519-21489:flowmailer List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 02 Mar 2023 15:31:10 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/10880 This patch adds the opensbi firmware with u-boot payload (smode) for the qemu-riscv64 machine. Using that, the generated riscv64 images can be booted on qemu. Signed-off-by: Felix Moessbauer --- recipes-bsp/opensbi/files/qemu-riscv64-rules | 12 +++ .../opensbi/opensbi-qemu-riscv64_1.2.bb | 8 ++ recipes-bsp/opensbi/opensbi.inc | 45 ++++++++++ ...iscv-Fix-build-against-binutils-2.38.patch | 55 ++++++++++++ ...upport-building-double-float-modules.patch | 89 +++++++++++++++++++ .../u-boot/u-boot-qemu-riscv64_2022.07.bb | 23 +++++ 6 files changed, 232 insertions(+) create mode 100644 recipes-bsp/opensbi/files/qemu-riscv64-rules create mode 100644 recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb create mode 100644 recipes-bsp/opensbi/opensbi.inc create mode 100644 recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch create mode 100644 recipes-bsp/u-boot/files/riscv64/0002-riscv-support-building-double-float-modules.patch create mode 100644 recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb diff --git a/recipes-bsp/opensbi/files/qemu-riscv64-rules b/recipes-bsp/opensbi/files/qemu-riscv64-rules new file mode 100644 index 0000000..960e10c --- /dev/null +++ b/recipes-bsp/opensbi/files/qemu-riscv64-rules @@ -0,0 +1,12 @@ +#!/usr/bin/make -f + +ifneq ($(DEB_BUILD_GNU_TYPE),$(DEB_HOST_GNU_TYPE)) +export CROSS_COMPILE=$(DEB_HOST_GNU_TYPE)- +endif + +override_dh_auto_build: + CFLAGS= LDFLAGS= $(MAKE) $(PARALLEL_MAKE) PLATFORM=generic \ + FW_PAYLOAD_PATH=/usr/lib/u-boot/qemu-riscv64/u-boot.bin + +%: + dh $@ diff --git a/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb b/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb new file mode 100644 index 0000000..b503afc --- /dev/null +++ b/recipes-bsp/opensbi/opensbi-qemu-riscv64_1.2.bb @@ -0,0 +1,8 @@ +# +# Copyright (c) Siemens AG, 2023 +# +# SPDX-License-Identifier: MIT + +include opensbi.inc + +SRC_URI[opensbi.sha256sum] = "8fcbce598a73acc2c7f7d5607d46b9d5107d3ecbede8f68f42631dcfc25ef2b2" diff --git a/recipes-bsp/opensbi/opensbi.inc b/recipes-bsp/opensbi/opensbi.inc new file mode 100644 index 0000000..b41a8bb --- /dev/null +++ b/recipes-bsp/opensbi/opensbi.inc @@ -0,0 +1,45 @@ +# +# Copyright (c) Siemens AG, 2023 +# +# SPDX-License-Identifier: MIT + +inherit dpkg + +U_BOOT_PACKAGE ?= "u-boot-${MACHINE}" +PLATFORM ?= "generic" + +DEPLOYDIR_FIRMWARE = "${WORKDIR}/deploy-fw" +SSTATETASKS += "do_deploy" + +SRC_URI = " \ + https://github.com/riscv/opensbi/archive/v${PV}.tar.gz;downloadfilename=opensbi-${PV}.tar.gz;name=opensbi \ + file://${MACHINE}-rules" + +S = "${WORKDIR}/opensbi-${PV}" + +DEPENDS += "${U_BOOT_PACKAGE}" +DEBIAN_BUILD_DEPENDS .= ",${U_BOOT_PACKAGE}" + +do_prepare_build[cleandirs] += "${S}/debian" +do_prepare_build() { + cp ${WORKDIR}/${MACHINE}-rules ${WORKDIR}/rules + deb_debianize + + echo "build/platform/${PLATFORM}/firmware/fw_payload.bin /usr/lib/opensbi/${MACHINE}/" > ${S}/debian/install +} + +do_deploy[cleandirs] += "${DEPLOYDIR_FIRMWARE}" +do_deploy[sstate-inputdirs] = "${DEPLOYDIR_FIRMWARE}" +do_deploy[sstate-outputdirs] = "${DEPLOY_DIR_IMAGE}" +do_deploy() { + dpkg --fsys-tarfile "${WORKDIR}/${PN}_${PV}_${DISTRO_ARCH}.deb" | \ + tar xOf - "./usr/lib/opensbi/${MACHINE}/fw_payload.bin" \ + > "${DEPLOYDIR_FIRMWARE}/fw_payload.bin" +} + +python do_deploy_setscene () { + sstate_setscene(d) +} +addtask do_deploy_setscene + +addtask deploy after do_dpkg_build before do_deploy_deb diff --git a/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch b/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch new file mode 100644 index 0000000..6f8a2ae --- /dev/null +++ b/recipes-bsp/u-boot/files/riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch @@ -0,0 +1,55 @@ +From 5df4b2299f86933fa79aa3bc6a3986fc7e55b7e0 Mon Sep 17 00:00:00 2001 +From: Alexandre Ghiti +Date: Mon, 3 Oct 2022 18:07:54 +0200 +Subject: [PATCH 1/2] riscv: Fix build against binutils 2.38 + +The following description is copied from the equivalent patch for the +Linux Kernel proposed by Aurelien Jarno: + +>From version 2.38, binutils default to ISA spec version 20191213. This +means that the csr read/write (csrr*/csrw*) instructions and fence.i +instruction has separated from the `I` extension, become two standalone +extensions: Zicsr and Zifencei. As the kernel uses those instruction, +this causes the following build failure: + +arch/riscv/cpu/mtrap.S: Assembler messages: +arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' +arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' +arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' +arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' + +Signed-off-by: Alexandre Ghiti +Reviewed-by: Bin Meng +Tested-by: Heinrich Schuchardt +Tested-by: Heiko Stuebner +Tested-by: Christian Stewart +Reviewed-by: Rick Chen +--- + arch/riscv/Makefile | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 0b80eb8d86..53d1194ffb 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) + CMODEL = medany + endif + +-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ ++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) ++ ++# Newer binutils versions default to ISA spec version 20191213 which moves some ++# instructions from the I extension to the Zicsr and Zifencei extensions. ++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) ++ifeq ($(toolchain-need-zicsr-zifencei),y) ++ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei ++endif ++ ++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ + -mcmodel=$(CMODEL) + + PLATFORM_CPPFLAGS += $(ARCH_FLAGS) +-- +2.30.2 + diff --git a/recipes-bsp/u-boot/files/riscv64/0002-riscv-support-building-double-float-modules.patch b/recipes-bsp/u-boot/files/riscv64/0002-riscv-support-building-double-float-modules.patch new file mode 100644 index 0000000..ec7d7d3 --- /dev/null +++ b/recipes-bsp/u-boot/files/riscv64/0002-riscv-support-building-double-float-modules.patch @@ -0,0 +1,89 @@ +From 5aefdcad0950c244d826988a8bd2f90584399849 Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Wed, 12 Oct 2022 14:59:51 +0200 +Subject: [PATCH 2/2] riscv: support building double-float modules + +The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a +compiled for double-float. To link to it we have to adjust how we build +U-Boot. + +As U-Boot actually does not use floating point at all this should not +make a significant difference for the produced binaries. + +Signed-off-by: Heinrich Schuchardt +Reviewed-by: Rick Chen +Reviewed-by: Leo Yu-Chi Liang +--- + arch/riscv/Kconfig | 15 +++++++++++++++ + arch/riscv/Makefile | 15 ++++++++++++--- + 2 files changed, 27 insertions(+), 3 deletions(-) + +diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig +index 0cf51799fe..25ed0ba1cf 100644 +--- a/arch/riscv/Kconfig ++++ b/arch/riscv/Kconfig +@@ -161,6 +161,21 @@ config RISCV_ISA_C + when building U-Boot, which results in compressed instructions in the + U-Boot binary. + ++config RISCV_ISA_F ++ bool "Standard extension for Single-Precision Floating Point" ++ default y ++ help ++ Adds "F" to the ISA string passed to the compiler. ++ ++config RISCV_ISA_D ++ bool "Standard extension for Double-Precision Floating Point" ++ depends on RISCV_ISA_F ++ default y ++ help ++ Adds "D" to the ISA string passed to the compiler and changes the ++ riscv32 ABI from ilp32 to ilp32d and the riscv64 ABI from lp64 to ++ lp64d. ++ + config RISCV_ISA_A + def_bool y + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 53d1194ffb..4963b5109b 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -5,15 +5,22 @@ + + ifeq ($(CONFIG_ARCH_RV64I),y) + ARCH_BASE = rv64im +- ABI = lp64 ++ ABI_BASE = lp64 + endif + ifeq ($(CONFIG_ARCH_RV32I),y) + ARCH_BASE = rv32im +- ABI = ilp32 ++ ABI_BASE = ilp32 + endif + ifeq ($(CONFIG_RISCV_ISA_A),y) + ARCH_A = a + endif ++ifeq ($(CONFIG_RISCV_ISA_F),y) ++ ARCH_F = f ++endif ++ifeq ($(CONFIG_RISCV_ISA_D),y) ++ ARCH_D = d ++ ABI_D = d ++endif + ifeq ($(CONFIG_RISCV_ISA_C),y) + ARCH_C = c + endif +@@ -24,7 +31,9 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) + CMODEL = medany + endif + +-RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) ++ ++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_F)$(ARCH_D)$(ARCH_C) ++ABI = $(ABI_BASE)$(ABI_D) + + # Newer binutils versions default to ISA spec version 20191213 which moves some + # instructions from the I extension to the Zicsr and Zifencei extensions. +-- +2.30.2 + diff --git a/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb b/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb new file mode 100644 index 0000000..6f101c5 --- /dev/null +++ b/recipes-bsp/u-boot/u-boot-qemu-riscv64_2022.07.bb @@ -0,0 +1,23 @@ +# +# CIP Core, generic profile +# +# Copyright (c) Siemens AG, 2022 +# +# Authors: +# Jan Kiszka +# +# SPDX-License-Identifier: MIT +# + +require u-boot-qemu-common.inc + +# we run as OpenSBI payload, hence use smode +U_BOOT_CONFIG = "${MACHINE}_smode_defconfig" + +EFI_ARCH = "riscv64" + +SRC_URI += " \ + file://riscv64/0001-riscv-Fix-build-against-binutils-2.38.patch \ + file://riscv64/0002-riscv-support-building-double-float-modules.patch" + +U_BOOT_BIN = "u-boot.bin" From patchwork Thu Mar 2 15:26:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felix Moessbauer X-Patchwork-Id: 13157414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D7AFC6FA8E for ; Thu, 2 Mar 2023 15:31:10 +0000 (UTC) Received: from mta-65-226.siemens.flowmailer.net (mta-65-226.siemens.flowmailer.net [185.136.65.226]) by mx.groups.io with SMTP id smtpd.web10.18850.1677770882136108523 for ; Thu, 02 Mar 2023 07:28:02 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=felix.moessbauer@siemens.com header.s=fm1 header.b=CV60H3Bs; spf=pass (domain: rts-flowmailer.siemens.com, ip: 185.136.65.226, mailfrom: fm-72506-20230302152759518a772272a4bfeaa2-smxwyf@rts-flowmailer.siemens.com) Received: by mta-65-226.siemens.flowmailer.net with ESMTPSA id 20230302152759518a772272a4bfeaa2 for ; Thu, 02 Mar 2023 16:27:59 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=felix.moessbauer@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=7TFLNRBcj0utWV+RqrC9SVBJ/AtrsUng5/0qya7qxWg=; b=CV60H3BsPtjzr9VIcabUxxAcTNLgyt4MKlzIqB1OUPDKEfWsD0wE1RNP1MgP9q/zfOaFIw /M5YccEtMtCbeZlHY5RWFqVl7mfyekfXdG9f8XUwEBLDKZlg9LwUWlSp/lrjaK2wnQutm1+e 5wYDal7a2YNUWOnnOwi5iTFrY1Ugo=; From: Felix Moessbauer To: cip-dev@lists.cip-project.org Cc: daniel.bovensiepen@siemens.com, jan.kiszka@siemens.com, quirin.gylstorff@siemens.com, Felix Moessbauer Subject: [isar-cip-core][PATCH v3 6/9] enhance qemu-riscv64 machine to be testable Date: Thu, 2 Mar 2023 15:26:56 +0000 Message-Id: <20230302152659.2096307-7-felix.moessbauer@siemens.com> In-Reply-To: <20230302152659.2096307-1-felix.moessbauer@siemens.com> References: <20230302152659.2096307-1-felix.moessbauer@siemens.com> MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-72506:519-21489:flowmailer List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 02 Mar 2023 15:31:10 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/10881 This patch enhances the qemu-riscv64 machine by adding a reference to u-boot. Further, we now use the qemu_riscv64 defconfig from cip-kernel-config. Signed-off-by: Felix Moessbauer --- conf/machine/qemu-riscv64.conf | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/conf/machine/qemu-riscv64.conf b/conf/machine/qemu-riscv64.conf index f1f3e87..8c1764b 100644 --- a/conf/machine/qemu-riscv64.conf +++ b/conf/machine/qemu-riscv64.conf @@ -12,4 +12,11 @@ DISTRO_ARCH = "riscv64" IMAGE_FSTYPES ?= "ext4" -KERNEL_DEFCONFIG ?= "defconfig" +USE_CIP_KERNEL_CONFIG = "1" + +KERNEL_DEFCONFIG ?= "cip-kernel-config/${KERNEL_DEFCONFIG_VERSION}/riscv/qemu_riscv64_defconfig" + +# for SWUpdate setups: watchdog is configured in U-Boot +WDOG_TIMEOUT = "0" + +PREFERRED_PROVIDER_u-boot-${MACHINE} = "u-boot-qemu-riscv64" From patchwork Thu Mar 2 15:26:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felix Moessbauer X-Patchwork-Id: 13157417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55251C678D4 for ; Thu, 2 Mar 2023 15:31:10 +0000 (UTC) Received: from mta-65-226.siemens.flowmailer.net (mta-65-226.siemens.flowmailer.net [185.136.65.226]) by mx.groups.io with SMTP id smtpd.web11.18911.1677770883930396785 for ; Thu, 02 Mar 2023 07:28:04 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=felix.moessbauer@siemens.com header.s=fm1 header.b=AltUa5E7; spf=pass (domain: rts-flowmailer.siemens.com, ip: 185.136.65.226, mailfrom: fm-72506-202303021528026bc37a7078039a74b4-paxrgy@rts-flowmailer.siemens.com) Received: by mta-65-226.siemens.flowmailer.net with ESMTPSA id 202303021528026bc37a7078039a74b4 for ; Thu, 02 Mar 2023 16:28:02 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=felix.moessbauer@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=1GlxZyhiuBNqjIVsD4yPjK8Incrr20EFNyC6X/BT2e0=; b=AltUa5E79U4FuZ8uHUsmd1qBjTQ+ipGdUJwjfDW+cCd5gt6kyEsHq9HIMc4n5mF4rXlSFX kQWRtfZXFaDRlZfabQscwFtrtUOJuVdN/blrxSJuAgTipYd7pRNSwu3s6LhHNopsYmMNHo/R acPSRh9GERQCurhzUrd3d4vF4FL2I=; From: Felix Moessbauer To: cip-dev@lists.cip-project.org Cc: daniel.bovensiepen@siemens.com, jan.kiszka@siemens.com, quirin.gylstorff@siemens.com, Felix Moessbauer Subject: [isar-cip-core][PATCH v3 7/9] add linux 6.1 mainline kernel Date: Thu, 2 Mar 2023 15:26:57 +0000 Message-Id: <20230302152659.2096307-8-felix.moessbauer@siemens.com> In-Reply-To: <20230302152659.2096307-1-felix.moessbauer@siemens.com> References: <20230302152659.2096307-1-felix.moessbauer@siemens.com> MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-72506:519-21489:flowmailer List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 02 Mar 2023 15:31:10 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/10882 This patch adds the vanilla 6.1 linux kernel for testing and for boards which need a more recent kernel than what CIP can offer. The kernel can be selected from the menu, similar to the other kernels. As defconfig, we always use the kernels internal configuration, because there is no cip-kernel-config for that version yet. In addition, the squashfs knob is selected to support the swupdate pattern without any modifications. Signed-off-by: Felix Moessbauer --- Kconfig | 4 ++++ kas/opt/6.1-mainline.yml | 18 ++++++++++++++++++ recipes-kernel/linux/files/squashfs.cfg | 1 + recipes-kernel/linux/linux-mainline_6.1.bb | 18 ++++++++++++++++++ 4 files changed, 41 insertions(+) create mode 100644 kas/opt/6.1-mainline.yml create mode 100644 recipes-kernel/linux/files/squashfs.cfg create mode 100644 recipes-kernel/linux/linux-mainline_6.1.bb diff --git a/Kconfig b/Kconfig index cd24ce2..a932bbe 100644 --- a/Kconfig +++ b/Kconfig @@ -97,6 +97,9 @@ config KERNEL_4_19 config KERNEL_5_10 bool "Kernel 5.10.x-cip" +config KERNEL_6_1_MAINLINE + bool "Kernel 6.1.x-mainline" + endchoice config KAS_INCLUDE_KERNEL @@ -104,6 +107,7 @@ config KAS_INCLUDE_KERNEL default "kas/opt/4.4.yml" if KERNEL_4_4 default "kas/opt/4.19.yml" if KERNEL_4_19 default "kas/opt/5.10.yml" if KERNEL_5_10 + default "kas/opt/6.1-mainline.yml" if KERNEL_6_1_MAINLINE config KERNEL_RT bool "Real-time CIP kernel" diff --git a/kas/opt/6.1-mainline.yml b/kas/opt/6.1-mainline.yml new file mode 100644 index 0000000..84d12b0 --- /dev/null +++ b/kas/opt/6.1-mainline.yml @@ -0,0 +1,18 @@ +# +# CIP Core, generic profile +# +# Copyright (c) Siemens AG, 2023 +# +# Authors: +# Felix Moessbauer +# +# SPDX-License-Identifier: MIT +# + +header: + version: 12 + +local_conf_header: + kernel-version: | + KERNEL_DEFCONFIG = "" + KERNEL_NAME = "mainline" diff --git a/recipes-kernel/linux/files/squashfs.cfg b/recipes-kernel/linux/files/squashfs.cfg new file mode 100644 index 0000000..7a89d00 --- /dev/null +++ b/recipes-kernel/linux/files/squashfs.cfg @@ -0,0 +1 @@ +CONFIG_SQUASHFS=y diff --git a/recipes-kernel/linux/linux-mainline_6.1.bb b/recipes-kernel/linux/linux-mainline_6.1.bb new file mode 100644 index 0000000..8a879a0 --- /dev/null +++ b/recipes-kernel/linux/linux-mainline_6.1.bb @@ -0,0 +1,18 @@ +# Example recipe for building the mainline kernel +# +# This software is a part of ISAR. +# Copyright (c) Siemens AG, 2018-2020 +# +# SPDX-License-Identifier: MIT + +require recipes-kernel/linux/linux-custom.inc + +ARCHIVE_VERSION = "${@ d.getVar('PV')[:-2] if d.getVar('PV').endswith('.0') else d.getVar('PV') }" + +SRC_URI += " \ + https://cdn.kernel.org/pub/linux/kernel/v6.x/linux-${ARCHIVE_VERSION}.tar.xz \ + file://squashfs.cfg" + +SRC_URI[sha256sum] = "2ca1f17051a430f6fed1196e4952717507171acfd97d96577212502703b25deb" + +S = "${WORKDIR}/linux-${ARCHIVE_VERSION}" From patchwork Thu Mar 2 15:26:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felix Moessbauer X-Patchwork-Id: 13157416 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BAEEC7EE32 for ; Thu, 2 Mar 2023 15:31:10 +0000 (UTC) Received: from mta-64-227.siemens.flowmailer.net (mta-64-227.siemens.flowmailer.net [185.136.64.227]) by mx.groups.io with SMTP id smtpd.web11.18914.1677770886514942570 for ; Thu, 02 Mar 2023 07:28:06 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=felix.moessbauer@siemens.com header.s=fm1 header.b=NVV7LoMK; spf=pass (domain: rts-flowmailer.siemens.com, ip: 185.136.64.227, mailfrom: fm-72506-20230302152804965aab79fea1402217-vabmeb@rts-flowmailer.siemens.com) Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 20230302152804965aab79fea1402217 for ; Thu, 02 Mar 2023 16:28:04 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=felix.moessbauer@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=TELIHZsy6JEg2raK+LfsmtaurnSPk0fNmDPxGUX2DEE=; b=NVV7LoMKqhcAEgAtMhyfKdnl7iDNTOvgiJo12evHiPTc2YrrEHSGQfqkOKaUu2jG7fbUP8 q/O33gWpbxcZU8Qj0XYO8ub5vRO1Qx3utd7RZAh8+ndun//a2ECeDMZKwtr637Bo/jrFhCky bjpQL5TXL+szLOOQFdF5zuOuQ4sn8=; From: Felix Moessbauer To: cip-dev@lists.cip-project.org Cc: daniel.bovensiepen@siemens.com, jan.kiszka@siemens.com, quirin.gylstorff@siemens.com, Felix Moessbauer Subject: [isar-cip-core][PATCH v3 8/9] add swupdate support for qemu-riscv64 Date: Thu, 2 Mar 2023 15:26:58 +0000 Message-Id: <20230302152659.2096307-9-felix.moessbauer@siemens.com> In-Reply-To: <20230302152659.2096307-1-felix.moessbauer@siemens.com> References: <20230302152659.2096307-1-felix.moessbauer@siemens.com> MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-72506:519-21489:flowmailer List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 02 Mar 2023 15:31:10 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/10883 This patch enables the swupdate KConfig entry for the qemu-riscv64 board. For that, we also duplicate the qemu-arm64-efibootguard.wks template for qemu-riscv64. As this is the first riscv64 board, we do not symlink but create a copy. Signed-off-by: Felix Moessbauer --- Kconfig | 2 +- kas/opt/ebg-swu.yml | 1 + wic/qemu-riscv64-efibootguard.wks.in | 13 +++++++++++++ 3 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 wic/qemu-riscv64-efibootguard.wks.in diff --git a/Kconfig b/Kconfig index a932bbe..7d72094 100644 --- a/Kconfig +++ b/Kconfig @@ -181,7 +181,7 @@ if IMAGE_FLASH && !KERNEL_4_4 && !KERNEL_4_19 config IMAGE_SWUPDATE bool "SWUpdate support for root partition" - depends on TARGET_QEMU_AMD64 || TARGET_SIMATIC_IPC227E || TARGET_QEMU_ARM64 || TARGET_QEMU_ARM || TARGET_BBB + depends on TARGET_QEMU_AMD64 || TARGET_SIMATIC_IPC227E || TARGET_QEMU_ARM64 || TARGET_QEMU_ARM || TARGET_BBB || ( TARGET_QEMU_RISCV64 && KERNEL_6_1_MAINLINE ) config IMAGE_SECURE_BOOT bool "Secure boot support" diff --git a/kas/opt/ebg-swu.yml b/kas/opt/ebg-swu.yml index 6bc893b..203a6b9 100644 --- a/kas/opt/ebg-swu.yml +++ b/kas/opt/ebg-swu.yml @@ -32,3 +32,4 @@ local_conf_header: # Add U-Boot for qemu IMAGER_BUILD_DEPS:append:qemu-arm64 = " u-boot-qemu-arm64" IMAGER_BUILD_DEPS:append:qemu-arm = " u-boot-qemu-arm" + IMAGER_BUILD_DEPS:append:qemu-riscv64 = " opensbi-qemu-riscv64" diff --git a/wic/qemu-riscv64-efibootguard.wks.in b/wic/qemu-riscv64-efibootguard.wks.in new file mode 100644 index 0000000..d63fc3a --- /dev/null +++ b/wic/qemu-riscv64-efibootguard.wks.in @@ -0,0 +1,13 @@ +# short-description: riscv64 with EFI Boot Guard and SWUpdate +# long-description: Disk image for riscv64 machines with EFI Boot Guard and SWUpdate + +include ebg-sysparts.inc + +part --source rawcopy --sourceparams "file=${IMAGE_FULLNAME}.squashfs" --align 1024 --fixed-size 1G --uuid "${ABROOTFS_PART_UUID_A}" +part --source empty --align 1024 --fixed-size 1G --uuid "${ABROOTFS_PART_UUID_B}" + +# home and var are extra partitions +part /home --source rootfs --rootfs-dir=${IMAGE_ROOTFS}/home --fstype=ext4 --label home --align 1024 --size 1G +part /var --source rootfs --rootfs-dir=${IMAGE_ROOTFS}/var --fstype=ext4 --label var --align 1024 --size 2G + +bootloader --ptable gpt From patchwork Thu Mar 2 15:26:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felix Moessbauer X-Patchwork-Id: 13157408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FA15C678D4 for ; Thu, 2 Mar 2023 15:30:40 +0000 (UTC) Received: from mta-64-228.siemens.flowmailer.net (mta-64-228.siemens.flowmailer.net [185.136.64.228]) by mx.groups.io with SMTP id smtpd.web11.18925.1677770901011149565 for ; Thu, 02 Mar 2023 07:28:21 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=felix.moessbauer@siemens.com header.s=fm1 header.b=N/HzA0ne; spf=pass (domain: rts-flowmailer.siemens.com, ip: 185.136.64.228, mailfrom: fm-72506-20230302152817bc36b2ddf8111d2a91-_6hf6p@rts-flowmailer.siemens.com) Received: by mta-64-228.siemens.flowmailer.net with ESMTPSA id 20230302152817bc36b2ddf8111d2a91 for ; Thu, 02 Mar 2023 16:28:17 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=felix.moessbauer@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=eM9gN3+g+p1B72Elx10b7yBrX/erGHYywBTPJTkOkME=; b=N/HzA0neqbbAE/y9KsFufzWUu6dlgqDTNUAVjbXqnzAtL82Vf7Av2FHFIqxVmmY2XfK6Fk KVwvnTaOnHNFghsbZ3mKjd4oy/aDvA3KYoguBNC5b0aFKI+NX5TvCAuR6FiOIEu48nFtTKro oNZsJcBayCBzGfksGDqbt/WfahhLw=; From: Felix Moessbauer To: cip-dev@lists.cip-project.org Cc: daniel.bovensiepen@siemens.com, jan.kiszka@siemens.com, quirin.gylstorff@siemens.com, Felix Moessbauer Subject: [isar-cip-core][PATCH v3 9/9] start-qemu: add support for swupdate on RISC-V Date: Thu, 2 Mar 2023 15:26:59 +0000 Message-Id: <20230302152659.2096307-10-felix.moessbauer@siemens.com> In-Reply-To: <20230302152659.2096307-1-felix.moessbauer@siemens.com> References: <20230302152659.2096307-1-felix.moessbauer@siemens.com> MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-72506:519-21489:flowmailer List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Thu, 02 Mar 2023 15:30:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/10874 This patch adds support to run swupdate images for RISC-V64 on qemu. As firmware, we use OpenSBI with u-boot payload in s-mode. Signed-off-by: Felix Moessbauer --- start-qemu.sh | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/start-qemu.sh b/start-qemu.sh index dd16aed..c4a8fe9 100755 --- a/start-qemu.sh +++ b/start-qemu.sh @@ -172,6 +172,14 @@ if [ -n "${SECURE_BOOT}${SWUPDATE_BOOT}" ]; then -bios ${u_boot_bin} \ ${QEMU_COMMON_OPTIONS} "$@" ;; + rv64|riscv64) + opensbi_bin=${FIRMWARE_BIN:-./build/tmp/deploy/images/qemu-${QEMU_ARCH}/fw_payload.bin} + + ${QEMU_PATH}${QEMU} \ + -drive file=${IMAGE_PREFIX}.wic,discard=unmap,if=none,id=disk,format=raw \ + -bios ${opensbi_bin} \ + ${QEMU_COMMON_OPTIONS} "$@" + ;; *) echo "Unsupported architecture: ${arch}" exit 1