From patchwork Fri Mar 3 14:51:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5A5EC678D4 for ; Fri, 3 Mar 2023 14:52:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229947AbjCCOwd (ORCPT ); Fri, 3 Mar 2023 09:52:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230042AbjCCOwV (ORCPT ); Fri, 3 Mar 2023 09:52:21 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7413962331 for ; Fri, 3 Mar 2023 06:52:20 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id p6so2970290plf.0 for ; Fri, 03 Mar 2023 06:52:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VXMF7IvJ5lsdZk4pO/zptMJoKK8XksLiBme5rkpOyuQ=; b=hGkxGdF7kmPPJuJpjPc6kHlHiYApnlT+vJHdTwT37NhdzcXWQAn9fHSEQ0TQ/kbmS5 QypfI0Mf2i8O+/SW49124lKK23mSAwlV45XMizDf+a66Xvia4s+AcmL96M5OdvkpZSO5 UyTJ5JoL5M6QwtmTVE+Fy1G4Xhf9HCqph+/h0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VXMF7IvJ5lsdZk4pO/zptMJoKK8XksLiBme5rkpOyuQ=; b=mMJ2jzLsaJBO0WldAaBta/mHEMVOPCqgC4cd3YulPr81dl6D2gcO75bOfg3AWmuhiV l92uFdxoBJk47OE0muBrUNSlHPXi3xVjMo0sVuNLbxFBhISfDWYfqthDlhM6JPCE/a4w RDP2ZxAjbs97wwmGqLD11QupnkQ5FyOlTn59l0ltlYOSmjKOZUVzzpmRScT7ztOVzEwz EuK/IPwKMJiX3jZ7RrRSEVAufrt+iaYOqPxRTbdWoAY6MH9mQJOSrZHXQBmksiYL+7fP sZ0WyEX9dYdHfLZ0U3N9LLWGBB4WwdHciIjLLyc1GETNqaU2AEk0nGm0NuHwwqrwH5uB lEoQ== X-Gm-Message-State: AO0yUKV2JRZKUwWQR5pLIHb4x7u9sBgGF+2cvBnWbM6ySBp2pP7s/quN 4FcqYSWE4xvzV8Usr6uVpUFofQ== X-Google-Smtp-Source: AK7set81p7rwz/HUcdzWmogVP+ug4N0ohDc+9qRzXBre8c4tHgQ1gH/Ofu3GqXOriiZsk89cvsimjg== X-Received: by 2002:a05:6a20:8f0f:b0:cb:7f0d:e25f with SMTP id b15-20020a056a208f0f00b000cb7f0de25fmr2918924pzk.41.1677855139916; Fri, 03 Mar 2023 06:52:19 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.52.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:52:19 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 01/16] drm: exynos: dsi: Drop explicit call to bridge detach Date: Fri, 3 Mar 2023 20:21:23 +0530 Message-Id: <20230303145138.29233-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos DSI already converted into a bridge driver, so bridge detach will suppose happened during bridge chain removal done by the bridge core. Drop the explicit call chain to detach the bridge. Signed-off-by: Jagan Teki Reviewed-by: Marek Vasut --- Changes for v15, v13, v12, v11: - none Changes for v10: - new patch drivers/gpu/drm/exynos/exynos_drm_dsi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 06d6513ddaae..df15501b1075 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -1531,8 +1531,6 @@ static int exynos_dsi_host_detach(struct mipi_dsi_host *host, struct exynos_dsi *dsi = host_to_dsi(host); struct drm_device *drm = dsi->encoder.dev; - if (dsi->out_bridge->funcs->detach) - dsi->out_bridge->funcs->detach(dsi->out_bridge); dsi->out_bridge = NULL; if (drm->mode_config.poll_enabled) From patchwork Fri Mar 3 14:51:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40D4EC7EE37 for ; Fri, 3 Mar 2023 14:52:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229968AbjCCOwd (ORCPT ); Fri, 3 Mar 2023 09:52:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230432AbjCCOw1 (ORCPT ); Fri, 3 Mar 2023 09:52:27 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 077031ADF8 for ; Fri, 3 Mar 2023 06:52:26 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id i10so2875932plr.9 for ; Fri, 03 Mar 2023 06:52:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=75obg6WaKxGAouYp8L8vU99A5I1ZieLyIbshRx9ot/0=; b=nwx3nUHwxYB+MWEpPux9HLvk8V4noZ7L+o+7LujBV5Kj/aMUzpWTVRIoXDVdVIatL8 PxKHmTzFqu8hHKTC1Y9yr6DnGMfO/UldXSuEx6m7RuJioml+wq0PoBBNuEvEzipmdG01 y0qaUqzqQ1tzuVji8CliTx1YYQnKk2zjXQlhU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=75obg6WaKxGAouYp8L8vU99A5I1ZieLyIbshRx9ot/0=; b=7xkWXDmjsekdPcQqQ/ffy/5EOQrcsSh9EA+MlQAlpkiW+cyGRVByFoghX9a4P575hy eJijSAY9YaQXhhTXvjJm98fLrG2oRqI2QebIXZbQboRwHXuNAaso71Yy8EAY2XbV/0eg TIGT76J48kUUJwDqeij+F5rMTBAbFGGW0bxNkddelc67qdGRBKAm4gmCTgYwuq4lSCKI shSsQcmRjT2axMJd4NuCKjTG+vI760OlqdmYd8CYdU1r1o9/WS5fO65qJiTDoiee6Z/s 12KH6YiR/fqz2eP99vKxbS2MKOu6XmefApufa9ew9AnFKLoiK8RGw+Zsu4UN7A5DGQah tWXg== X-Gm-Message-State: AO0yUKVhtGv/IaLi0XkC/QUOzjm14XwguK8OWWlTW+vFWkQ3Kc+3iWKc pFUCOnquP+FR75iTlYR33tz1Qg== X-Google-Smtp-Source: AK7set9ddne/co5GxlXg9Z5y/8Uyd9N9Zo8lSmWtNpR1RY239kYYX6ZIxpoVDg7hxSfEjK9DP+o/yw== X-Received: by 2002:a05:6a20:5487:b0:c6:d37c:2a62 with SMTP id i7-20020a056a20548700b000c6d37c2a62mr2981782pzk.11.1677855145441; Fri, 03 Mar 2023 06:52:25 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.52.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:52:24 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 02/16] drm: exynos: dsi: Lookup OF-graph or Child node devices Date: Fri, 3 Mar 2023 20:21:24 +0530 Message-Id: <20230303145138.29233-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org In general, for MIPI DSI there are three ways to represent the pipeline for an upstream bridge to find the connected downstream panel or bridge. 1. Child panel or bridge as a conventional device tree child node. 2. Child panel or bridge as an OF-graph port node. 3. Child panel or bridge as an OF-graph ports node. There are three different downstream panels or bridges that are possible to connect an upstream DSI host bridge - DSI Panel, DSI Bridge, and I2C-Configured DSI bridge. An example of the downstream panel represented as a child node, &dsi { compatible = "samsung,exynos5433-mipi-dsi"; ports { port@0 { reg = <0>; dsi_to_mic: endpoint { remote-endpoint = <&mic_to_dsi>; }; }; }; panel@0 { reg = <0>; }; }; An example of the downstream bridge represented as a port node, &i2c4 { bridge@2c { compatible = "ti,sn65dsi84"; ports { port@0 { reg = <0>; bridge_in_dsi: endpoint { remote-endpoint = <&dsi_out_bridge>; data-lanes = <1 2>; }; }; port@2 { reg = <2>; bridge_out_panel: endpoint { remote-endpoint = <&panel_out_bridge>; }; }; }; }; }; &dsi { compatible = "fsl,imx8mm-mipi-dsim"; port { dsi_in_lcdif: endpoint@0 { reg = <0>; remote-endpoint = <&lcdif_out_dsi>; }; dsi_out_bridge: endpoint@1 { reg = <1>; remote-endpoint = <&bridge_in_dsi>; }; }; }; An example of the downstream bridge represented as a ports node, &dsi { compatible = "fsl,imx8mm-mipi-dsim"; ports { port@0 { reg = <0>; dsi_in_lcdif: endpoint@0 { reg = <0>; remote-endpoint = <&lcdif_out_dsi>; }; }; port@1 { reg = <1>; dsi_out_bridge: endpoint { remote-endpoint = <&bridge_in_dsi>; }; }; }; In, summary it is possible to represent all three downstream slaves devices using OF-graph port or ports node however only DSI Panel and DSI Bridge are possible but not possible to represent I2C-Configured DSI bridge child nodes since I2C-Configure bridges are child of I2C node, not upstream DSI host bridge and it is must represent them endpoint port linking. This indeed means, the OF-graph port or ports representation is mandatory for I2C-Configured DSI bridges. This patch tries to add an OF-graph port or ports representation detection code on top of existing child node detection. It is possible to replace the entire detection code using existing drm_of helper drm_of_find_panel_or_bridge but it will break the Exynos DSI since the pipeline doesn't support OF-graph port or ports node. Overall, this patch has a combination of child and OF-graph pipeline detections in order to support the backward compatibility of Exynos DSI child node and i.MX8M Mini/Nano/Plus OF-graph port or ports node pipelines. This is the first common DSI host bridge driver that needs to support all possible downstream connection pipeline combinations. Signed-off-by: Jagan Teki Reviewed-by: Marek Vasut --- Changes for v15: - droped from drm_of - added in exynos dsi - updated commit messages Changes for v13, v12: - none Changes for v11: - drop extra line Changes for v10: - new patch drivers/gpu/drm/exynos/exynos_drm_dsi.c | 38 +++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index df15501b1075..f44a5a702ad5 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -1470,18 +1470,52 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host *host, struct device *dev = dsi->dev; struct drm_encoder *encoder = &dsi->encoder; struct drm_device *drm = encoder->dev; + struct device_node *np = dev->of_node; + struct device_node *remote; struct drm_panel *panel; int ret; - panel = of_drm_find_panel(device->dev.of_node); + /** + * Devices can also be child nodes when we also control that device + * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device). + * + * Lookup for a child node of the given parent that isn't either port + * or ports. + */ + for_each_available_child_of_node(np, remote) { + if (of_node_name_eq(remote, "port") || + of_node_name_eq(remote, "ports")) + continue; + + goto of_find_panel_or_bridge; + } + + /* + * of_graph_get_remote_node() produces a noisy error message if port + * node isn't found and the absence of the port is a legit case here, + * so at first we silently check whether graph presents in the + * device-tree node. + */ + if (!of_graph_is_present(np)) + return -ENODEV; + + remote = of_graph_get_remote_node(np, 1, 0); + +of_find_panel_or_bridge: + if (!remote) + return -ENODEV; + + panel = of_drm_find_panel(remote); if (!IS_ERR(panel)) { dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel); } else { - dsi->out_bridge = of_drm_find_bridge(device->dev.of_node); + dsi->out_bridge = of_drm_find_bridge(remote); if (!dsi->out_bridge) dsi->out_bridge = ERR_PTR(-EINVAL); } + of_node_put(remote); + if (IS_ERR(dsi->out_bridge)) { ret = PTR_ERR(dsi->out_bridge); DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret); From patchwork Fri Mar 3 14:51:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D209FC7EE39 for ; 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Fri, 03 Mar 2023 06:52:30 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 03/16] drm: exynos: dsi: Mark PHY as optional Date: Fri, 3 Mar 2023 20:21:25 +0530 Message-Id: <20230303145138.29233-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The same Samsung MIPI DSIM master can also be used in NXP's i.MX8M Mini/Nano/Plus SoC. In i.MX8M Mini/Nano/Plus SoC the DSI Phy requires a MIPI DPHY bit to reset in order to activate the PHY and that can be done via upstream i.MX8M blk-ctrl driver. So, mark the phy get as optional. Reviewed-by: Frieder Schrempf Reviewed-by: Marek Vasut Signed-off-by: Jagan Teki --- Changes for v15, v13, v12: - none Changes for v11: - collect Frieder RB Changes for v10: - add Plus in commit message - collect Marek RB Changes for v9, v8, v7, v6, v5, v4, v3, v2: - none Changes for v1: - new patch drivers/gpu/drm/exynos/exynos_drm_dsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index f44a5a702ad5..af16af404e87 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -1732,7 +1732,7 @@ static int exynos_dsi_probe(struct platform_device *pdev) if (IS_ERR(dsi->reg_base)) return PTR_ERR(dsi->reg_base); - dsi->phy = devm_phy_get(dev, "dsim"); + dsi->phy = devm_phy_optional_get(dev, "dsim"); if (IS_ERR(dsi->phy)) { dev_info(dev, "failed to get dsim phy\n"); return PTR_ERR(dsi->phy); From patchwork Fri Mar 3 14:51:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158907 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A0A3C678D4 for ; Fri, 3 Mar 2023 14:52:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229803AbjCCOwi (ORCPT ); Fri, 3 Mar 2023 09:52:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229586AbjCCOwi (ORCPT ); Fri, 3 Mar 2023 09:52:38 -0500 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2696B62332 for ; Fri, 3 Mar 2023 06:52:37 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id z2so2862271plf.12 for ; Fri, 03 Mar 2023 06:52:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=legzZg2LI260N51ZPIAg5x5sq5D7Y2TMttdY9F/D8O0=; b=qry+BcDjjI9j/3iSpVUSwuAAcQdZ3/38bEkvGt9ahODGRZ6+hZhYRN5scLC9vRqUmK AtAFD6Xgiy0IAgMi6DmxLria05pzD53iVTkzuf2CuAP9AYV6EZd3ZzDBxzYSli+DMfLv U6e2SuPSJhRMtkvQ2U8TaW1ZvvFScc2BugWFU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=legzZg2LI260N51ZPIAg5x5sq5D7Y2TMttdY9F/D8O0=; b=zk+lWeCT7QQbqK/JXM0M8/CGtNzoXEzolRRNULBEwhxZb71qhYSZBBNHq4MfhVNqxL sAWUfR5QWDN7cmMyP/aRJAASSGvyav5A9zIs+Xjbjm9l2+/kkOaJQaGRw9wWC5gyKpnG QolWu8ETv54puNUt4Wcx3VO56l4It5l18/G1N3LbZQt1ptrT0Dkw3Ed7h6ee40By2mT/ gOhUaVZoNAW1ZnWcDDbxUqSV4O6dda29AvYm6QlX0JTg2WMrZIVnmKc5zx/+8ksS4COn jzTwEX9Q060B+nwUaaUUalsj0zsn5tkTs4hK/g8SEJT2h+OV/5CrjFDSdj0Dyglujh6b WqvQ== X-Gm-Message-State: AO0yUKWpZmHMcXYZinfrV+9Za3oIsN7PYO0WCiSuqh/Ktop6VqtOVoSs jfZo678Z5G4ogMApUOqOeBcCkMgFyoCXbqVDu3E= X-Google-Smtp-Source: AK7set+S1OXuuY2OaPy1V3iEpH9ZmCmscIx33DqlUT/zZVnQSunf/YuxzIIVr9nE6PPpJScJqic8gQ== X-Received: by 2002:a05:6a20:8e02:b0:ce:ca9:ab56 with SMTP id y2-20020a056a208e0200b000ce0ca9ab56mr2921382pzj.34.1677855156554; Fri, 03 Mar 2023 06:52:36 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.52.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:52:35 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 04/16] drm: exynos: dsi: Add platform PLL_P (PMS_P) offset Date: Fri, 3 Mar 2023 20:21:26 +0530 Message-Id: <20230303145138.29233-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Look like PLL PMS_P offset value varies between platforms that have Samsung DSIM IP. However, there is no clear evidence for it as both Exynos and i.MX 8M Mini Application Processor Reference Manual is still referring the PMS_P offset as 13. The offset 13 is not working for i.MX8M Mini SoCs but the downstream NXP sec-dsim.c driver is using offset 14 for i.MX8M Mini SoC platforms [1] [2]. PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P() with offset 13 and then an additional offset of one bit added in sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS(). Not sure whether it is reference manual documentation or something else but this patch trusts the downstream code and handle PLL_P offset via platform driver data so-that imx8mm driver data shall use pll_p_offset to 14. Similar to Mini the i.MX8M Nano/Plus also has P=14, unlike Exynos. [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n210 [2] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211 Reviewed-by: Marek Vasut Signed-off-by: Frieder Schrempf Signed-off-by: Jagan Teki --- Changes for v15, v13, v12, v11, v10, v9: - none Changes for v8: - updated commit message for 8M Nano/Plus Changes for v7, v6: - none Changes for v5: - updated clear commit message Changes for v4, v3, v2: - none Changes for v1: - updated commit message - add downstream driver link drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index af16af404e87..603fed107fd1 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -194,7 +194,7 @@ /* DSIM_PLLCTRL */ #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN (1 << 23) -#define DSIM_PLL_P(x) ((x) << 13) +#define DSIM_PLL_P(x, offset) ((x) << (offset)) #define DSIM_PLL_M(x) ((x) << 4) #define DSIM_PLL_S(x) ((x) << 1) @@ -263,6 +263,7 @@ struct exynos_dsi_driver_data { unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol; + unsigned int pll_p_offset; const unsigned int *reg_values; }; @@ -471,6 +472,7 @@ static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -483,6 +485,7 @@ static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -493,6 +496,7 @@ static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -504,6 +508,7 @@ static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 0, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5433_reg_values, }; @@ -515,6 +520,7 @@ static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 1, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5422_reg_values, }; @@ -628,7 +634,8 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, writel(driver_data->reg_values[PLL_TIMER], dsi->reg_base + driver_data->plltmr_reg); - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | + DSIM_PLL_M(m) | DSIM_PLL_S(s); if (driver_data->has_freqband) { static const unsigned long freq_bands[] = { From patchwork Fri Mar 3 14:51:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158908 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D142C64EC4 for ; Fri, 3 Mar 2023 14:53:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229586AbjCCOxG (ORCPT ); Fri, 3 Mar 2023 09:53:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229997AbjCCOwn (ORCPT ); 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Fri, 03 Mar 2023 06:52:40 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 05/16] drm: exynos: dsi: Introduce hw_type platform data Date: Fri, 3 Mar 2023 20:21:27 +0530 Message-Id: <20230303145138.29233-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Samsung MIPI DSIM controller is common DSI IP that can be used in various SoCs like Exynos, i.MX8M Mini/Nano/Plus. Add hw_type enum via platform_data so that accessing the different controller data between various platforms becomes easy and meaningful. Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Suggested-by: Marek Szyprowski Signed-off-by: Jagan Teki --- Changes for v15, v13: - none Changes for v12: - collect RB from Marek Changes for v11: - collect RB from Frieder - drop extra line Changes for v10: - split from previous series patch "drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge" - update enum type names drivers/gpu/drm/exynos/exynos_drm_dsi.c | 83 ++++++++++++++++++++----- 1 file changed, 68 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 603fed107fd1..64cf69995750 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -254,6 +254,15 @@ struct exynos_dsi_transfer { #define DSIM_STATE_CMD_LPM BIT(2) #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) +enum exynos_dsi_type { + DSIM_TYPE_EXYNOS3250, + DSIM_TYPE_EXYNOS4210, + DSIM_TYPE_EXYNOS5410, + DSIM_TYPE_EXYNOS5422, + DSIM_TYPE_EXYNOS5433, + DSIM_TYPE_COUNT, +}; + struct exynos_dsi_driver_data { const unsigned int *reg_ofs; unsigned int plltmr_reg; @@ -267,6 +276,10 @@ struct exynos_dsi_driver_data { const unsigned int *reg_values; }; +struct exynos_dsi_plat_data { + enum exynos_dsi_type hw_type; +}; + struct exynos_dsi { struct drm_encoder encoder; struct mipi_dsi_host dsi_host; @@ -297,6 +310,7 @@ struct exynos_dsi { struct list_head transfer_list; const struct exynos_dsi_driver_data *driver_data; + const struct exynos_dsi_plat_data *plat_data; }; #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) @@ -524,18 +538,13 @@ static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { .reg_values = exynos5422_reg_values, }; -static const struct of_device_id exynos_dsi_of_match[] = { - { .compatible = "samsung,exynos3250-mipi-dsi", - .data = &exynos3_dsi_driver_data }, - { .compatible = "samsung,exynos4210-mipi-dsi", - .data = &exynos4_dsi_driver_data }, - { .compatible = "samsung,exynos5410-mipi-dsi", - .data = &exynos5_dsi_driver_data }, - { .compatible = "samsung,exynos5422-mipi-dsi", - .data = &exynos5422_dsi_driver_data }, - { .compatible = "samsung,exynos5433-mipi-dsi", - .data = &exynos5433_dsi_driver_data }, - { } +static const struct exynos_dsi_driver_data * +exynos_dsi_types[DSIM_TYPE_COUNT] = { + [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data, + [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data, + [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data, + [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, + [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, }; static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) @@ -1468,8 +1477,6 @@ static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { .attach = exynos_dsi_attach, }; -MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); - static int exynos_dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *device) { @@ -1704,7 +1711,8 @@ static int exynos_dsi_probe(struct platform_device *pdev) dsi->dsi_host.dev = dev; dsi->dev = dev; - dsi->driver_data = of_device_get_match_data(dev); + dsi->plat_data = of_device_get_match_data(dev); + dsi->driver_data = exynos_dsi_types[dsi->plat_data->hw_type]; dsi->supplies[0].supply = "vddcore"; dsi->supplies[1].supply = "vddio"; @@ -1862,6 +1870,51 @@ static const struct dev_pm_ops exynos_dsi_pm_ops = { pm_runtime_force_resume) }; +static const struct exynos_dsi_plat_data exynos3250_dsi_pdata = { + .hw_type = DSIM_TYPE_EXYNOS3250, +}; + +static const struct exynos_dsi_plat_data exynos4210_dsi_pdata = { + .hw_type = DSIM_TYPE_EXYNOS4210, +}; + +static const struct exynos_dsi_plat_data exynos5410_dsi_pdata = { + .hw_type = DSIM_TYPE_EXYNOS5410, +}; + +static const struct exynos_dsi_plat_data exynos5422_dsi_pdata = { + .hw_type = DSIM_TYPE_EXYNOS5422, +}; + +static const struct exynos_dsi_plat_data exynos5433_dsi_pdata = { + .hw_type = DSIM_TYPE_EXYNOS5433, +}; + +static const struct of_device_id exynos_dsi_of_match[] = { + { + .compatible = "samsung,exynos3250-mipi-dsi", + .data = &exynos3250_dsi_pdata, + }, + { + .compatible = "samsung,exynos4210-mipi-dsi", + .data = &exynos4210_dsi_pdata, + }, + { + .compatible = "samsung,exynos5410-mipi-dsi", + .data = &exynos5410_dsi_pdata, + }, + { + .compatible = "samsung,exynos5422-mipi-dsi", + .data = &exynos5422_dsi_pdata, + }, + { + .compatible = "samsung,exynos5433-mipi-dsi", + .data = &exynos5433_dsi_pdata, + }, + { /* sentinel. */ } +}; +MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); + struct platform_driver dsi_driver = { .probe = exynos_dsi_probe, .remove = exynos_dsi_remove, From patchwork Fri Mar 3 14:51:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158909 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC2D8C7EE2F for ; Fri, 3 Mar 2023 14:53:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229997AbjCCOxH (ORCPT ); Fri, 3 Mar 2023 09:53:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230481AbjCCOws (ORCPT ); Fri, 3 Mar 2023 09:52:48 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 291901ADF8 for ; Fri, 3 Mar 2023 06:52:47 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id bo22so2745099pjb.4 for ; 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Fri, 03 Mar 2023 06:52:46 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.52.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:52:45 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 06/16] drm: exynos: dsi: Handle proper host initialization Date: Fri, 3 Mar 2023 20:21:28 +0530 Message-Id: <20230303145138.29233-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Marek Szyprowski Host transfer() in the DSI master will invoke only when the DSI commands are sent from DSI devices like DSI Panel or DSI bridges and this host the transfer wouldn't invoke for I2C-based-DSI bridge drivers. Handling DSI host initialization in transfer calls misses the controller setup for I2C configured DSI bridges. This patch updates the DSI host initialization by calling host to init from bridge pre_enable as the bridge pre_enable API is invoked by core as it is common across all classes of DSI device drivers. The host init during pre_enable is conditional and not invoked for Exynos as existing downstream drm panels and bridges in Exynos are expecting the host initialization during DSI transfer. Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Signed-off-by: Marek Szyprowski Signed-off-by: Jagan Teki --- Changes for v15, v13: - none Changes for v12: - collect RB from Marek Changes for v11: - collect RB from Frieder Changes for v10: - update the to simple logic to handle all platforms Changs for v9 - v8: - none Changes for v2: - check initialized state in samsung_dsim_init Changes for v1: - keep DSI init in host transfer drivers/gpu/drm/exynos/exynos_drm_dsi.c | 27 +++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 64cf69995750..fe195d76ce76 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -254,6 +254,9 @@ struct exynos_dsi_transfer { #define DSIM_STATE_CMD_LPM BIT(2) #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) +#define exynos_dsi_hw_is_exynos(hw) \ + ((hw) >= DSIM_TYPE_EXYNOS3250 && (hw) <= DSIM_TYPE_EXYNOS5433) + enum exynos_dsi_type { DSIM_TYPE_EXYNOS3250, DSIM_TYPE_EXYNOS4210, @@ -1343,6 +1346,9 @@ static int exynos_dsi_init(struct exynos_dsi *dsi) { const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; + if (dsi->state & DSIM_STATE_INITIALIZED) + return 0; + exynos_dsi_reset(dsi); exynos_dsi_enable_irq(dsi); @@ -1355,6 +1361,8 @@ static int exynos_dsi_init(struct exynos_dsi *dsi) exynos_dsi_set_phy_ctrl(dsi); exynos_dsi_init_link(dsi); + dsi->state |= DSIM_STATE_INITIALIZED; + return 0; } @@ -1410,6 +1418,16 @@ static void exynos_dsi_atomic_pre_enable(struct drm_bridge *bridge, } dsi->state |= DSIM_STATE_ENABLED; + + /* + * For Exynos-DSIM the downstream bridge, or panel are expecting + * the host initialization during DSI transfer. + */ + if (!exynos_dsi_hw_is_exynos(dsi->plat_data->hw_type)) { + ret = exynos_dsi_init(dsi); + if (ret) + return; + } } static void exynos_dsi_atomic_enable(struct drm_bridge *bridge, @@ -1601,12 +1619,9 @@ static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, if (!(dsi->state & DSIM_STATE_ENABLED)) return -EINVAL; - if (!(dsi->state & DSIM_STATE_INITIALIZED)) { - ret = exynos_dsi_init(dsi); - if (ret) - return ret; - dsi->state |= DSIM_STATE_INITIALIZED; - } + ret = exynos_dsi_init(dsi); + if (ret) + return ret; ret = mipi_dsi_create_packet(&xfer.packet, msg); if (ret < 0) From patchwork Fri Mar 3 14:51:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158912 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66A15C7EE32 for ; Fri, 3 Mar 2023 14:53:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230118AbjCCOxH (ORCPT ); Fri, 3 Mar 2023 09:53:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230499AbjCCOwx (ORCPT ); Fri, 3 Mar 2023 09:52:53 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B02A19B6 for ; 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Fri, 03 Mar 2023 06:52:51 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:52:51 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 07/16] drm: exynos: dsi: Add atomic check Date: Fri, 3 Mar 2023 20:21:29 +0530 Message-Id: <20230303145138.29233-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Look like an explicit fixing up of mode_flags is required for DSIM IP present in i.MX8M Mini/Nano SoCs. At least the LCDIF + DSIM needs active low sync polarities in order to correlate the correct sync flags of the surrounding components in the chain to make sure the whole pipeline can work properly. On the other hand the i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 says. "13.6.3.5.2 RGB interface Vsync, Hsync, and VDEN are active high signals." i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 3.6.3.5.2 RGB interface i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 13.6.2.7.2 RGB interface both claim "Vsync, Hsync, and VDEN are active high signals.", the LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. No clear evidence about whether it can be documentation issues or something, so added proper comments on the code. Comments are suggested by Marek Vasut. Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Signed-off-by: Jagan Teki --- Changes for v15, v13: - none Changes for v12: - collect RB from Marek Changes for v11: - collect RB from Frieder - fix commit message Changes for v10, v9: - none Changes for v8: - update the comments about sync signals polarities - added clear commit message by including i.MX8M Nano details Changes for v7: - fix the hw_type checking logic Changes for v6: - none Changes for v5: - rebase based new bridge changes [mszyprow] - remove DSIM_QUIRK_FIXUP_SYNC_POL - add hw_type check for sync polarities change. Changes for v4: - none Changes for v3: - add DSIM_QUIRK_FIXUP_SYNC_POL to handle mode_flasg fixup Changes for v2: - none Changes for v1: - fix mode flags in atomic_check instead of mode_fixup drivers/gpu/drm/exynos/exynos_drm_dsi.c | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index fe195d76ce76..796480e4a18b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -263,6 +263,7 @@ enum exynos_dsi_type { DSIM_TYPE_EXYNOS5410, DSIM_TYPE_EXYNOS5422, DSIM_TYPE_EXYNOS5433, + DSIM_TYPE_IMX8MM, DSIM_TYPE_COUNT, }; @@ -1465,6 +1466,32 @@ static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, pm_runtime_put_sync(dsi->dev); } +static int exynos_dsi_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct exynos_dsi *dsi = bridge_to_dsi(bridge); + struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; + + /* + * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM + * inverts HS/VS/DE sync signals polarity, therefore, while + * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 + * 13.6.3.5.2 RGB interface + * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 + * 13.6.2.7.2 RGB interface + * both claim "Vsync, Hsync, and VDEN are active high signals.", the + * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. + */ + if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { + adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); + } + + return 0; +} + static void exynos_dsi_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *mode, const struct drm_display_mode *adjusted_mode) @@ -1487,6 +1514,7 @@ static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_check = exynos_dsi_atomic_check, .atomic_pre_enable = exynos_dsi_atomic_pre_enable, .atomic_enable = exynos_dsi_atomic_enable, .atomic_disable = exynos_dsi_atomic_disable, From patchwork Fri Mar 3 14:51:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158910 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D994AC678D4 for ; Fri, 3 Mar 2023 14:53:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230057AbjCCOxI (ORCPT ); Fri, 3 Mar 2023 09:53:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231140AbjCCOw7 (ORCPT ); Fri, 3 Mar 2023 09:52:59 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDCE6D31B for ; Fri, 3 Mar 2023 06:52:57 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id p3-20020a17090ad30300b0023a1cd5065fso2528742pju.0 for ; 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Fri, 03 Mar 2023 06:52:57 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.52.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:52:56 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 08/16] drm: exynos: dsi: Add input_bus_flags Date: Fri, 3 Mar 2023 20:21:30 +0530 Message-Id: <20230303145138.29233-9-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org LCDIF-DSIM glue logic inverts the HS/VS/DE signals and expecting the i.MX8M Mini/Nano DSI host to add additional Data Enable signal active low (DE_LOW). This makes the valid data transfer on each horizontal line. So, add additional bus flags DE_LOW setting via input_bus_flags for i.MX8M Mini/Nano platforms. Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Suggested-by: Marek Vasut Signed-off-by: Jagan Teki --- Changes for v15, v13: - none Changes for v12: - collect RB from Marek Changes for v11: - collect RB from Frieder Changes for v10, v9: - none Changes for v8: - add DE_LOW for i.MX8M Mini/Nano platforms. Changes for v7, v6: - none Changes for v5: - rebased based on updated bridge changes Changes for v4 - v1: - none drivers/gpu/drm/exynos/exynos_drm_dsi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 796480e4a18b..5d971b607e1a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -1736,6 +1736,10 @@ static const struct component_ops exynos_dsi_component_ops = { .unbind = exynos_dsi_unbind, }; +static const struct drm_bridge_timings dsim_bridge_timings_de_low = { + .input_bus_flags = DRM_BUS_FLAG_DE_LOW, +}; + static int exynos_dsi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1822,6 +1826,10 @@ static int exynos_dsi_probe(struct platform_device *pdev) dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; dsi->bridge.pre_enable_prev_first = true; + /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */ + if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) + dsi->bridge.timings = &dsim_bridge_timings_de_low; + ret = component_add(dev, &exynos_dsi_component_ops); if (ret) goto err_disable_runtime; From patchwork Fri Mar 3 14:51:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59AD7C64EC4 for ; Fri, 3 Mar 2023 14:53:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230157AbjCCOxI (ORCPT ); Fri, 3 Mar 2023 09:53:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230042AbjCCOxG (ORCPT ); Fri, 3 Mar 2023 09:53:06 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C75F7125A1 for ; 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Fri, 03 Mar 2023 06:53:02 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:53:01 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 09/16] drm: exynos: dsi: Add atomic_get_input_bus_fmts Date: Fri, 3 Mar 2023 20:21:31 +0530 Message-Id: <20230303145138.29233-10-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Finding the right input bus format throughout the pipeline is hard so add atomic_get_input_bus_fmts callback and initialize with the proper input format from list of supported output formats. This format can be used in pipeline for negotiating bus format between the DSI-end of this bridge and the other component closer to pipeline components. List of Pixel formats are taken from, AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 3.7.4 Pixel formats Table 14. DSI pixel packing formats Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Tested-by: Marek Szyprowski Signed-off-by: Jagan Teki --- Changes for v15: - collect RB from Marek Changes for v12: - update the logic suggested by Marek Changes for v11: - collect RB from Frieder - drop extra line Changes for v10: - none Changes for v9: - added MEDIA_BUS_FMT_FIXED - return MEDIA_BUS_FMT_RGB888_1X24 output_fmt if supported output_fmt list is unsupported. - added MEDIA_BUS_FMT_YUYV10_1X20, MEDIA_BUS_FMT_YUYV12_1X24 Changes for v8: - added pixel formats supported by NXP AN13573 i.MX 8/RT MIPI DSI/CSI-2 Changes for v7 - v4: - none Changes for v3: - include media-bus-format.h Changes for v2: - none Changes for v1: - new patch drivers/gpu/drm/exynos/exynos_drm_dsi.c | 62 +++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 5d971b607e1a..c8829f33f36e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -1466,6 +1467,66 @@ static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, pm_runtime_put_sync(dsi->dev); } +/* + * This pixel output formats list referenced from, + * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 + * 3.7.4 Pixel formats + * Table 14. DSI pixel packing formats + */ +static const u32 exynos_dsi_pixel_output_fmts[] = { + MEDIA_BUS_FMT_YUYV10_1X20, + MEDIA_BUS_FMT_YUYV12_1X24, + MEDIA_BUS_FMT_UYVY8_1X16, + MEDIA_BUS_FMT_RGB101010_1X30, + MEDIA_BUS_FMT_RGB121212_1X36, + MEDIA_BUS_FMT_RGB565_1X16, + MEDIA_BUS_FMT_RGB666_1X18, + MEDIA_BUS_FMT_RGB888_1X24, +}; + +static bool exynos_dsi_pixel_output_fmt_supported(u32 fmt) +{ + int i; + + if (fmt == MEDIA_BUS_FMT_FIXED) + return false; + + for (i = 0; i < ARRAY_SIZE(exynos_dsi_pixel_output_fmts); i++) { + if (exynos_dsi_pixel_output_fmts[i] == fmt) + return true; + } + + return false; +} + +static u32 * +exynos_dsi_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + if (!exynos_dsi_pixel_output_fmt_supported(output_fmt)) + /* + * Some bridge/display drivers are still not able to pass the + * correct format, so handle those pipelines by falling back + * to the default format till the supported formats finalized. + */ + output_fmt = MEDIA_BUS_FMT_RGB888_1X24; + + input_fmts[0] = output_fmt; + *num_input_fmts = 1; + + return input_fmts; +} + static int exynos_dsi_atomic_check(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, struct drm_crtc_state *crtc_state, @@ -1514,6 +1575,7 @@ static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_get_input_bus_fmts = exynos_dsi_atomic_get_input_bus_fmts, .atomic_check = exynos_dsi_atomic_check, .atomic_pre_enable = exynos_dsi_atomic_pre_enable, .atomic_enable = exynos_dsi_atomic_enable, From patchwork Fri Mar 3 14:51:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68D72C678D4 for ; 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Fri, 03 Mar 2023 06:53:07 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.53.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:53:06 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 10/16] drm: exynos: dsi: Consolidate component and bridge Date: Fri, 3 Mar 2023 20:21:32 +0530 Message-Id: <20230303145138.29233-11-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org DSI host registration, attach and detach operations are quite different for the component and bridge-based DRM drivers.  Supporting generic bridge driver to use both component and bridge based DRM drivers can be tricky and would require additional host related operation hooks. Add host operation hooks for registering and unregistering Exynos and generic drivers, where Exynos hooks are used in existing Exynos component based DRM drivers and generic hooks are used in i.MX8M bridge based DRM drivers.  Add host attach and detach operation hooks for Exynos component DRM drivers and those get invoked while DSI core host attach and detach gets called. Reviewed-by: Marek Vasut Signed-off-by: Marek Szyprowski Signed-off-by: Jagan Teki --- Changes for v15: - remove leading underscores in function names Changes for v13: - none Changes for v12: - fix unneeded decleration - collect RB from Marek Changes for v11: - none Changes for v10: - split from previous series patch "drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge" drivers/gpu/drm/exynos/exynos_drm_dsi.c | 169 +++++++++++++++++++----- 1 file changed, 134 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index c8829f33f36e..afe2d293c785 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -283,10 +283,10 @@ struct exynos_dsi_driver_data { struct exynos_dsi_plat_data { enum exynos_dsi_type hw_type; + const struct exynos_dsim_host_ops *host_ops; }; struct exynos_dsi { - struct drm_encoder encoder; struct mipi_dsi_host dsi_host; struct drm_bridge bridge; struct drm_bridge *out_bridge; @@ -316,6 +316,19 @@ struct exynos_dsi { const struct exynos_dsi_driver_data *driver_data; const struct exynos_dsi_plat_data *plat_data; + + void *priv; +}; + +struct exynos_dsim_host_ops { + int (*register_host)(struct exynos_dsi *dsim); + void (*unregister_host)(struct exynos_dsi *dsim); + int (*attach)(struct exynos_dsi *dsim, struct mipi_dsi_device *device); + int (*detach)(struct exynos_dsi *dsim, struct mipi_dsi_device *device); +}; + +struct exynos_dsi_enc { + struct drm_encoder encoder; }; #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) @@ -1320,7 +1333,8 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) { struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; - struct drm_encoder *encoder = &dsi->encoder; + struct exynos_dsi_enc *dsi_enc = dsi->priv; + struct drm_encoder *encoder = &dsi_enc->encoder; if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) exynos_drm_crtc_te_handler(encoder->crtc); @@ -1589,9 +1603,8 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *device) { struct exynos_dsi *dsi = host_to_dsi(host); + const struct exynos_dsi_plat_data *pdata = dsi->plat_data; struct device *dev = dsi->dev; - struct drm_encoder *encoder = &dsi->encoder; - struct drm_device *drm = encoder->dev; struct device_node *np = dev->of_node; struct device_node *remote; struct drm_panel *panel; @@ -1648,35 +1661,15 @@ static int exynos_dsi_host_attach(struct mipi_dsi_host *host, drm_bridge_add(&dsi->bridge); - drm_bridge_attach(encoder, &dsi->bridge, - list_first_entry_or_null(&encoder->bridge_chain, - struct drm_bridge, - chain_node), 0); - - /* - * This is a temporary solution and should be made by more generic way. - * - * If attached panel device is for command mode one, dsi should register - * TE interrupt handler. - */ - if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { - ret = exynos_dsi_register_te_irq(dsi, &device->dev); - if (ret) + if (pdata->host_ops && pdata->host_ops->attach) { + ret = pdata->host_ops->attach(dsi, device); + if (ret < 0) return ret; } - mutex_lock(&drm->mode_config.mutex); - dsi->lanes = device->lanes; dsi->format = device->format; dsi->mode_flags = device->mode_flags; - exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode = - !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO); - - mutex_unlock(&drm->mode_config.mutex); - - if (drm->mode_config.poll_enabled) - drm_kms_helper_hotplug_event(drm); return 0; } @@ -1685,14 +1678,16 @@ static int exynos_dsi_host_detach(struct mipi_dsi_host *host, struct mipi_dsi_device *device) { struct exynos_dsi *dsi = host_to_dsi(host); - struct drm_device *drm = dsi->encoder.dev; + const struct exynos_dsi_plat_data *pdata = dsi->plat_data; + int ret; dsi->out_bridge = NULL; - if (drm->mode_config.poll_enabled) - drm_kms_helper_hotplug_event(drm); - - exynos_dsi_unregister_te_irq(dsi); + if (pdata->host_ops && pdata->host_ops->detach) { + ret = pdata->host_ops->detach(dsi, device); + if (ret < 0) + return ret; + } drm_bridge_remove(&dsi->bridge); @@ -1766,11 +1761,67 @@ static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) return 0; } +static int exynos_dsim_host_attach(struct exynos_dsi *dsim, + struct mipi_dsi_device *device) +{ + struct exynos_dsi_enc *dsi_enc = dsim->priv; + struct drm_encoder *encoder = &dsi_enc->encoder; + struct drm_device *drm = encoder->dev; + int ret; + + drm_bridge_attach(encoder, &dsim->bridge, + list_first_entry_or_null(&encoder->bridge_chain, + struct drm_bridge, + chain_node), 0); + + /* + * This is a temporary solution and should be made by more generic way. + * + * If attached panel device is for command mode one, dsi should register + * TE interrupt handler. + */ + if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { + ret = exynos_dsi_register_te_irq(dsim, &device->dev); + if (ret) + return ret; + } + + mutex_lock(&drm->mode_config.mutex); + + dsim->lanes = device->lanes; + dsim->format = device->format; + dsim->mode_flags = device->mode_flags; + exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode = + !(dsim->mode_flags & MIPI_DSI_MODE_VIDEO); + + mutex_unlock(&drm->mode_config.mutex); + + if (drm->mode_config.poll_enabled) + drm_kms_helper_hotplug_event(drm); + + return 0; +} + +static int exynos_dsim_host_detach(struct exynos_dsi *dsim, + struct mipi_dsi_device *device) +{ + struct exynos_dsi_enc *dsi_enc = dsim->priv; + struct drm_device *drm = dsi_enc->encoder.dev; + + if (drm->mode_config.poll_enabled) + drm_kms_helper_hotplug_event(drm); + + exynos_dsi_unregister_te_irq(dsim); + + return 0; +} + static int exynos_dsi_bind(struct device *dev, struct device *master, void *data) { struct exynos_dsi *dsi = dev_get_drvdata(dev); - struct drm_encoder *encoder = &dsi->encoder; + struct exynos_dsi_enc *dsi_enc = dsi->priv; + struct drm_encoder *encoder = &dsi_enc->encoder; struct drm_device *drm_dev = data; int ret; @@ -1788,7 +1839,7 @@ static void exynos_dsi_unbind(struct device *dev, struct device *master, { struct exynos_dsi *dsi = dev_get_drvdata(dev); - exynos_dsi_atomic_disable(&dsi->bridge, NULL); + dsi->bridge.funcs->atomic_disable(&dsi->bridge, NULL); mipi_dsi_host_unregister(&dsi->dsi_host); } @@ -1798,6 +1849,40 @@ static const struct component_ops exynos_dsi_component_ops = { .unbind = exynos_dsi_unbind, }; +static int exynos_dsi_register_host(struct exynos_dsi *dsim) +{ + struct exynos_dsi_enc *dsi_enc; + + dsi_enc = devm_kzalloc(dsim->dev, sizeof(*dsi_enc), GFP_KERNEL); + if (!dsi_enc) + return -ENOMEM; + + dsim->priv = dsi_enc; + dsim->bridge.pre_enable_prev_first = true; + + return component_add(dsim->dev, &exynos_dsi_component_ops); +} + +static void exynos_dsi_unregister_host(struct exynos_dsi *dsim) +{ + component_del(dsim->dev, &exynos_dsi_component_ops); +} + +static int generic_dsim_register_host(struct exynos_dsi *dsim) +{ + return mipi_dsi_host_register(&dsim->dsi_host); +} + +static void generic_dsim_unregister_host(struct exynos_dsi *dsim) +{ + mipi_dsi_host_unregister(&dsim->dsi_host); +} + +static const struct exynos_dsim_host_ops generic_dsim_host_ops = { + .register_host = generic_dsim_register_host, + .unregister_host = generic_dsim_unregister_host, +}; + static const struct drm_bridge_timings dsim_bridge_timings_de_low = { .input_bus_flags = DRM_BUS_FLAG_DE_LOW, }; @@ -1892,7 +1977,9 @@ static int exynos_dsi_probe(struct platform_device *pdev) if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) dsi->bridge.timings = &dsim_bridge_timings_de_low; - ret = component_add(dev, &exynos_dsi_component_ops); + if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host) + ret = dsi->plat_data->host_ops->register_host(dsi); + if (ret) goto err_disable_runtime; @@ -1983,24 +2070,36 @@ static const struct dev_pm_ops exynos_dsi_pm_ops = { pm_runtime_force_resume) }; +static const struct exynos_dsim_host_ops exynos_dsi_host_ops = { + .register_host = exynos_dsi_register_host, + .unregister_host = exynos_dsi_unregister_host, + .attach = exynos_dsim_host_attach, + .detach = exynos_dsim_host_detach, +}; + static const struct exynos_dsi_plat_data exynos3250_dsi_pdata = { .hw_type = DSIM_TYPE_EXYNOS3250, + .host_ops = &exynos_dsi_host_ops, }; static const struct exynos_dsi_plat_data exynos4210_dsi_pdata = { .hw_type = DSIM_TYPE_EXYNOS4210, + .host_ops = &exynos_dsi_host_ops, }; static const struct exynos_dsi_plat_data exynos5410_dsi_pdata = { .hw_type = DSIM_TYPE_EXYNOS5410, + .host_ops = &exynos_dsi_host_ops, }; static const struct exynos_dsi_plat_data exynos5422_dsi_pdata = { .hw_type = DSIM_TYPE_EXYNOS5422, + .host_ops = &exynos_dsi_host_ops, }; static const struct exynos_dsi_plat_data exynos5433_dsi_pdata = { .hw_type = DSIM_TYPE_EXYNOS5433, + .host_ops = &exynos_dsi_host_ops, }; static const struct of_device_id exynos_dsi_of_match[] = { From patchwork Fri Mar 3 14:51:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24ED3C64EC4 for ; Fri, 3 Mar 2023 14:53:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230511AbjCCOxj (ORCPT ); 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Fri, 03 Mar 2023 06:53:12 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki Subject: [PATCH v15 11/16] drm: exynos: dsi: Add host helper for te_irq_handler Date: Fri, 3 Mar 2023 20:21:33 +0530 Message-Id: <20230303145138.29233-12-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org IRQ handler for te-gpio seems to be common across DSIM host. However, Exynos is handling this via CRTC drivers but there is no clear evidence on how the same has been handled in i.MX8MM. Keeping the handler as-it-is can be a viable option but adding DSIM bridge core in upcoming patches is not possible to call Exynos CRTC handler as DSIM bridge has to be common across DRM bridge core instead of platform specific DRM drivers like Exynos here. So, this patch handles the handler via platform host helper, so-that handling platform specific hook across Exynos and generic can be reasonable till it makes it generic across all platforms. Reviewed-by: Marek Vasut Signed-off-by: Jagan Teki --- Changes for v15: - remove leading underscores in function names - collect RB from Marek Changes for v13: - none Changes for v12: - updated patch - suggested by Marek V Changes for v11: - none Changes for v10: - split from previous series patch "drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge" drivers/gpu/drm/exynos/exynos_drm_dsi.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index afe2d293c785..2fc166ebe3c7 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -325,6 +325,7 @@ struct exynos_dsim_host_ops { void (*unregister_host)(struct exynos_dsi *dsim); int (*attach)(struct exynos_dsi *dsim, struct mipi_dsi_device *device); int (*detach)(struct exynos_dsi *dsim, struct mipi_dsi_device *device); + irqreturn_t (*te_irq_handler)(struct exynos_dsi *dsim); }; struct exynos_dsi_enc { @@ -1333,11 +1334,10 @@ static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) { struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; - struct exynos_dsi_enc *dsi_enc = dsi->priv; - struct drm_encoder *encoder = &dsi_enc->encoder; + const struct exynos_dsi_plat_data *pdata = dsi->plat_data; - if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) - exynos_drm_crtc_te_handler(encoder->crtc); + if (pdata->host_ops && pdata->host_ops->te_irq_handler) + return pdata->host_ops->te_irq_handler(dsi); return IRQ_HANDLED; } @@ -1761,6 +1761,17 @@ static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) return 0; } +static irqreturn_t exynos_dsim_te_irq_handler(struct exynos_dsi *dsim) +{ + struct exynos_dsi_enc *dsi_enc = dsim->priv; + struct drm_encoder *encoder = &dsi_enc->encoder; + + if (dsim->state & DSIM_STATE_VIDOUT_AVAILABLE) + exynos_drm_crtc_te_handler(encoder->crtc); + + return IRQ_HANDLED; +} + static int exynos_dsim_host_attach(struct exynos_dsi *dsim, struct mipi_dsi_device *device) { @@ -2075,6 +2086,7 @@ static const struct exynos_dsim_host_ops exynos_dsi_host_ops = { .unregister_host = exynos_dsi_unregister_host, .attach = exynos_dsim_host_attach, .detach = exynos_dsim_host_detach, + .te_irq_handler = exynos_dsim_te_irq_handler, }; static const struct exynos_dsi_plat_data exynos3250_dsi_pdata = { From patchwork Fri Mar 3 14:51:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 755A9C7EE32 for ; Fri, 3 Mar 2023 14:53:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230349AbjCCOxk (ORCPT ); Fri, 3 Mar 2023 09:53:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230499AbjCCOxZ (ORCPT ); Fri, 3 Mar 2023 09:53:25 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45977166D5 for ; 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Fri, 03 Mar 2023 06:53:23 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.53.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:53:23 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki , Rob Herring Subject: [PATCH v15 13/16] dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support Date: Fri, 3 Mar 2023 20:21:35 +0530 Message-Id: <20230303145138.29233-14-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Samsung MIPI DSIM bridge can also be found in i.MX8M Mini/Nano SoC. Add dt-bingings for it. Reviewed-by: Marek Vasut Acked-by: Rob Herring Signed-off-by: Jagan Teki --- Changes for v15, v13: - none Changes for v12: - collect RB from Marek Changes for v11, v10, v9: - none Changes for v8: - add comment to include i.MX8M Nano. Changes for v7, v6, v5, v4: - none Changes for v3: - collect Rob Acked-by Changes for v2: - updated comments Changes for v1: - new patch Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt index be377786e8cd..5133d4d39190 100644 --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt @@ -7,6 +7,7 @@ Required properties: "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */ "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */ "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */ + "fsl,imx8mm-mipi-dsim" /* for i.MX8M Mini/Nano SoCs */ - reg: physical base address and length of the registers set for the device - interrupts: should contain DSI interrupt - clocks: list of clock specifiers, must contain an entry for each required From patchwork Fri Mar 3 14:51:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25F44C7EE2F for ; Fri, 3 Mar 2023 14:53:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230481AbjCCOxl (ORCPT ); Fri, 3 Mar 2023 09:53:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231127AbjCCOxb (ORCPT ); Fri, 3 Mar 2023 09:53:31 -0500 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 329D8166D5 for ; Fri, 3 Mar 2023 06:53:30 -0800 (PST) Received: by mail-pl1-x62f.google.com with SMTP id v11so2888138plz.8 for ; Fri, 03 Mar 2023 06:53:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LJit/9jx4Jh9SnqcRqHqL0SMNt+O+dxValiE0RggnWc=; b=aGXkDLxUV1bfq/kkxx+OqcxqiLzgJR70cfR8bimUXvIQA9hGW9okDUwKmRzUkiMcBO 2xMOcOeZbefQUUCJCCpxgjdb3q2YifsEQXjZO/zj27q1cg5J79Hay7c8tgazFJes9PQR 62+h+7S1WSFp46pkSMatzthRvxU+rvMIlWhL4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LJit/9jx4Jh9SnqcRqHqL0SMNt+O+dxValiE0RggnWc=; b=ckj0RVd4uTj0acw1z919Ux1U4ugBd+BMeTRo8py9+PD0NpZ2Etq2G07VEO5kdM677g GLAbLu8+pkRELJg8NkeCWJoV4fo4ljy2kmQLGsfAXCBJv1MNyC+Lj+du4GqRWKPBWKd2 Oelr7XbjR4/7dW86JaSzyNWFHE12SdkJ5ksqo9XY/rmvAjNkmDR/rm3CscJYtpsApuB9 0e3sblJwZ+c06PiL8wNKWTiJARRjgW27H97Lovh7SxWhOnMTRv84EUSaJ62Ixc+7RL53 LNF1Yv+erTZiPGdcAUqJiexc3AXUvbOn90xSgUHEFO1r4KdelXdWGya3oorR2eCdd4aC m7og== X-Gm-Message-State: AO0yUKW9rF1za9zMF27i/Pb+cnjOD8BvT+Y8OzuodNBTqXJJFoc9OVC5 LUvPX9DIh6TLOQciPv9svkvpVQ== X-Google-Smtp-Source: AK7set/MWHpeUF41MTekXhkSJuTltaxfvPzLFc941EekQhZmoSyBo8g0sYeFCS6tV/QJH8j9fEohAA== X-Received: by 2002:a05:6a20:29a9:b0:c7:6c26:48b7 with SMTP id f41-20020a056a2029a900b000c76c2648b7mr2027617pzh.15.1677855209626; Fri, 03 Mar 2023 06:53:29 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.53.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:53:29 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki , Robert Foss , Laurent Pinchart Subject: [PATCH v15 14/16] drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano support Date: Fri, 3 Mar 2023 20:21:36 +0530 Message-Id: <20230303145138.29233-15-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Samsung MIPI DSIM master can also be found in i.MX8M Mini/Nano SoC. Add compatible and associated driver_data for it. Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Acked-by: Robert Foss Reviewed-by: Laurent Pinchart Signed-off-by: Marek Szyprowski Signed-off-by: Jagan Teki --- Changes for v15, v13: - none Changes for v12: - collect RB from Marek Changes for v11: - collect RB from Frieder - collect ACK from Robert Changes for v10, v9: - none Changed for v8: - fix and update the comment Changes for v7, v6: - none Changes for v3: - enable DSIM_QUIRK_FIXUP_SYNC_POL quirk Changes for v5: - [mszyprow] rebased and adjusted to the new driver initialization - drop quirk Changes for v4: - none Changes for v3: - enable DSIM_QUIRK_FIXUP_SYNC_POL quirk Changes for v2: - collect Laurent r-b Changes for v1: - none drivers/gpu/drm/bridge/samsung-dsim.c | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 42e3536cb2fc..3ffdaedaa261 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -376,6 +376,24 @@ static const unsigned int exynos5433_reg_values[] = { [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), }; +static const unsigned int imx8mm_dsim_reg_values[] = { + [RESET_TYPE] = DSIM_SWRST, + [PLL_TIMER] = 500, + [STOP_STATE_CNT] = 0xf, + [PHYCTRL_ULPS_EXIT] = 0, + [PHYCTRL_VREG_LP] = 0, + [PHYCTRL_SLEW_UP] = 0, + [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), + [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), + [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), + [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26), + [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), + [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), + [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08), + [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), + [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), +}; + static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { .reg_ofs = exynos_reg_ofs, .plltmr_reg = 0x50, @@ -437,6 +455,22 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { .reg_values = exynos5422_reg_values, }; +static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { + .reg_ofs = exynos5433_reg_ofs, + .plltmr_reg = 0xa0, + .has_clklane_stop = 1, + .num_clks = 2, + .max_freq = 2100, + .wait_for_reset = 0, + .num_bits_resol = 12, + /* + * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus + * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c + */ + .pll_p_offset = 14, + .reg_values = imx8mm_dsim_reg_values, +}; + static const struct samsung_dsim_driver_data * samsung_dsim_types[DSIM_TYPE_COUNT] = { [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data, @@ -444,6 +478,7 @@ samsung_dsim_types[DSIM_TYPE_COUNT] = { [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data, [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, + [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data, }; static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h) @@ -1875,7 +1910,16 @@ const struct dev_pm_ops samsung_dsim_pm_ops = { }; EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops); +static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = { + .hw_type = DSIM_TYPE_IMX8MM, + .host_ops = &generic_dsim_host_ops, +}; + static const struct of_device_id samsung_dsim_of_match[] = { + { + .compatible = "fsl,imx8mm-mipi-dsim", + .data = &samsung_dsim_imx8mm_pdata, + }, { /* sentinel. */ } }; MODULE_DEVICE_TABLE(of, samsung_dsim_of_match); From patchwork Fri Mar 3 14:51:37 2023 Content-Type: text/plain; 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Fri, 03 Mar 2023 06:53:34 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.53.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:53:34 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Jagan Teki , Rob Herring Subject: [PATCH v15 15/16] dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support Date: Fri, 3 Mar 2023 20:21:37 +0530 Message-Id: <20230303145138.29233-16-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Samsung MIPI DSIM bridge can also be found in i.MX8M Plus SoC. Add dt-bingings for it. Reviewed-by: Marek Vasut Acked-by: Rob Herring Signed-off-by: Jagan Teki --- Changes for v15, v13: - none Changes for v12: - collect RB from Marek Changes for v11: - collect ACK from Rob Changes for v10, v9: - none Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt index 5133d4d39190..2a5f0889ec32 100644 --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt @@ -8,6 +8,7 @@ Required properties: "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */ "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */ "fsl,imx8mm-mipi-dsim" /* for i.MX8M Mini/Nano SoCs */ + "fsl,imx8mp-mipi-dsim" /* for i.MX8M Plus SoCs */ - reg: physical base address and length of the registers set for the device - interrupts: should contain DSI interrupt - clocks: list of clock specifiers, must contain an entry for each required From patchwork Fri Mar 3 14:51:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 13158918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FAB2C7EE37 for ; Fri, 3 Mar 2023 14:53:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230326AbjCCOxn (ORCPT ); Fri, 3 Mar 2023 09:53:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229959AbjCCOxm (ORCPT ); Fri, 3 Mar 2023 09:53:42 -0500 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAC0A18156 for ; Fri, 3 Mar 2023 06:53:40 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id a2so2917946plm.4 for ; Fri, 03 Mar 2023 06:53:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aujyWPMFHiJShpD2rYyPMOf2wRQo87mEd8rP+CNjbJo=; b=erNIyvHi5SVgcpvgvhgkRAw/PQH5VhOu+Z14lyz7vZUAaWJ1HBzOryjsmIkohs57Qz Rav/xys05y9WX++UjFcOoEp+ECexwacCVKFAK7PF8wocTVpXrTTu144ZGSSR8I9FRx0j ThdzfthxwFqyf+DdXdEMW0kXZzz3H5TROoPlQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aujyWPMFHiJShpD2rYyPMOf2wRQo87mEd8rP+CNjbJo=; b=UWT0yodbmY1gPb+OniBySqhRcRW9jqIL/KdFZRslIcwcXGh6AKzhlUK6apQiFcyjnh XQOWVoQx16wv2FxM2Mh2WeArAZr96LmCVxFUQZXj/plC+vjQ5blo/+bKCV/B5KE3n2ZW /mPdlNtdlW90bpKAPcGu7eiYaaKK7grN90jR2MffD209tqSCB3a3FYhSUqxrVDsM0H3z gOohcDETMkCOnJgGxNm0x1H2nujzz4OWzDZwJgx/yRYzvlL074MpCLVMly7Srlg/F8VD s1guwhyKBnZoIFXwQvByw/3ixz8ari3lpc/g8vaBJfRxhshNxx8RezF0lW1rv0hbw2wP BC9g== X-Gm-Message-State: AO0yUKUmHJhLEOguhbiDyTUlOhF3Ln4kNkx/1wJkcZZR7M+qLtdanVlO cnllut7sVAMCO3dg2VVQ9R0xzQ== X-Google-Smtp-Source: AK7set//wi6XK3GdnYb/FMtSE9HHuo5wIh991VjF8hWOjdDl95RsK0pfHsfmt1DcTFHGFnPMtEBbsg== X-Received: by 2002:a05:6a21:9998:b0:cc:d514:62ce with SMTP id ve24-20020a056a21999800b000ccd51462cemr2896607pzb.44.1677855220331; Fri, 03 Mar 2023 06:53:40 -0800 (PST) Received: from localhost.localdomain ([183.83.137.89]) by smtp.gmail.com with ESMTPSA id z4-20020a63e544000000b00502fd70b0bdsm1660856pgj.52.2023.03.03.06.53.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 06:53:39 -0800 (PST) From: Jagan Teki To: Andrzej Hajda , Inki Dae , Marek Szyprowski , Neil Armstrong , Marek Vasut , Maxime Ripard Cc: Seung-Woo Kim , Kyungmin Park , Frieder Schrempf , Tim Harvey , Adam Ford , Matteo Lisi , dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula , Robert Foss , Jagan Teki Subject: [PATCH v15 16/16] drm: bridge: samsung-dsim: Add i.MX8M Plus support Date: Fri, 3 Mar 2023 20:21:38 +0530 Message-Id: <20230303145138.29233-17-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> References: <20230303145138.29233-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Marek Vasut Add extras to support i.MX8M Plus. The main change is the removal of HS/VS/DE signal inversion in the LCDIFv3-DSIM glue logic, otherwise the implementation of this IP in i.MX8M Plus is very much compatible with the i.MX8M Mini/Nano one. Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Acked-by: Robert Foss Signed-off-by: Marek Vasut Signed-off-by: Jagan Teki --- Changes for v15, v13: - none Changes for v12: - collect RB from Marek Changes for v11: - collect RB from Frieder - collect ACK from Robert Changes for v10: - none Changes for v9: - added im8mp in DSIM_STATE_REINITIALIZED check - drop previous = NULL check drivers/gpu/drm/bridge/samsung-dsim.c | 23 +++++++++++++++++++++++ include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 3ffdaedaa261..b4a5348b763c 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -479,6 +479,7 @@ samsung_dsim_types[DSIM_TYPE_COUNT] = { [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data, + [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data, }; static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h) @@ -1452,10 +1453,17 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge, * 13.6.2.7.2 RGB interface * both claim "Vsync, Hsync, and VDEN are active high signals.", the * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. + * + * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not + * implement the same behavior, therefore LCDIFv3 must generate + * HS/VS/DE signals active HIGH. */ if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); + } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) { + adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); } return 0; @@ -1721,6 +1729,10 @@ static const struct samsung_dsim_host_ops generic_dsim_host_ops = { .unregister_host = generic_dsim_unregister_host, }; +static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = { + .input_bus_flags = DRM_BUS_FLAG_DE_HIGH, +}; + static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = { .input_bus_flags = DRM_BUS_FLAG_DE_LOW, }; @@ -1810,6 +1822,8 @@ int samsung_dsim_probe(struct platform_device *pdev) /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */ if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low; + else + dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high; if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host) ret = dsi->plat_data->host_ops->register_host(dsi); @@ -1915,11 +1929,20 @@ static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = { .host_ops = &generic_dsim_host_ops, }; +static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = { + .hw_type = DSIM_TYPE_IMX8MP, + .host_ops = &generic_dsim_host_ops, +}; + static const struct of_device_id samsung_dsim_of_match[] = { { .compatible = "fsl,imx8mm-mipi-dsim", .data = &samsung_dsim_imx8mm_pdata, }, + { + .compatible = "fsl,imx8mp-mipi-dsim", + .data = &samsung_dsim_imx8mp_pdata, + }, { /* sentinel. */ } }; MODULE_DEVICE_TABLE(of, samsung_dsim_of_match); diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h index 4ba387c958ae..fb923caf09e1 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -28,6 +28,7 @@ enum samsung_dsim_type { DSIM_TYPE_EXYNOS5422, DSIM_TYPE_EXYNOS5433, DSIM_TYPE_IMX8MM, + DSIM_TYPE_IMX8MP, DSIM_TYPE_COUNT, };