From patchwork Tue Mar 7 08:13:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13163006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F41D3C678D4 for ; Tue, 7 Mar 2023 08:15:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSl-00062T-NK; Tue, 07 Mar 2023 03:14:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZSSh-000603-HP; Tue, 07 Mar 2023 03:14:19 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSc-0007Jl-Vh; Tue, 07 Mar 2023 03:14:19 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowACn0qJN8gZkNe6lDA--.36330S3; Tue, 07 Mar 2023 16:14:06 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v12 01/10] target/riscv: add cfg properties for Zc* extension Date: Tue, 7 Mar 2023 16:13:54 +0800 Message-Id: <20230307081403.61950-2-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230307081403.61950-1-liweiwei@iscas.ac.cn> References: <20230307081403.61950-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowACn0qJN8gZkNe6lDA--.36330S3 X-Coremail-Antispam: 1UD129KBjvJXoW7WryDtw1rtFyfur45JFykGrg_yoW8KF4fpr 48G3yYkrWDJr17C3yfXF1UKFn8Wws2vayxK392q3WxurW7ArW5XFnYkw1UWF45tFs5Xa1a 9F17CF1DCrsrJa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9m14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr 0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUqAp5UUUUU= X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension. Add check for these properties. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 6 ++++++ 2 files changed, 49 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af2..df7eed57af 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -939,6 +939,49 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } + if (cpu->cfg.ext_c) { + cpu->cfg.ext_zca = true; + if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { + cpu->cfg.ext_zcf = true; + } + if (cpu->cfg.ext_d) { + cpu->cfg.ext_zcd = true; + } + } + + if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension is only relevant to RV32"); + return; + } + + if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension requires F extension"); + return; + } + + if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { + error_setg(errp, "Zcd extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " + "extension"); + return; + } + + if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { + error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " + "Zcd extension"); + return; + } + + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { + error_setg(errp, "Zcmt extension requires Zicsr extension"); + return; + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 638e47c75a..a2426ec479 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -438,6 +438,12 @@ struct RISCVCPUConfig { bool ext_zbkc; bool ext_zbkx; bool ext_zbs; + bool ext_zca; + bool ext_zcb; + bool ext_zcd; + bool ext_zcf; + bool ext_zcmp; + bool ext_zcmt; bool ext_zk; bool ext_zkn; bool ext_zknd; From patchwork Tue Mar 7 08:13:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13163008 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43A9DC678D5 for ; Tue, 7 Mar 2023 08:15:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSp-00066G-KX; Tue, 07 Mar 2023 03:14:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZSSh-000606-K0; Tue, 07 Mar 2023 03:14:19 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSc-0007Jn-Vs; Tue, 07 Mar 2023 03:14:19 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowACn0qJN8gZkNe6lDA--.36330S4; Tue, 07 Mar 2023 16:14:07 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li , Wilfred Mallawa Subject: [PATCH v12 02/10] target/riscv: add support for Zca extension Date: Tue, 7 Mar 2023 16:13:55 +0800 Message-Id: <20230307081403.61950-3-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230307081403.61950-1-liweiwei@iscas.ac.cn> References: <20230307081403.61950-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowACn0qJN8gZkNe6lDA--.36330S4 X-Coremail-Antispam: 1UD129KBjvJXoW7Kw18uw43Zr1ftry5Kr1kAFb_yoW8KF4xpr 4Fk3y7KrZ5Jr93Aa95CF4jqr1UJr4Sgr4xJ39Yvws3JFW3XrW5XFsrKry3KryUZFs2qr1Y 9FZ0yFZ8Za18XaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBE14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v2 6r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2 Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_ Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMI IF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUc6pPUUUUU = X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Modify the check for C extension to Zca (C implies Zca). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Wilfred Mallawa --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c | 8 ++++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 4ad54e8a49..c70c495fc5 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); gen_set_pc(ctx, cpu_pc); - if (!has_ext(ctx, RVC)) { + if (!ctx->cfg_ptr->ext_zca) { TCGv t0 = tcg_temp_new(); misaligned = gen_new_label(); @@ -169,7 +169,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) gen_set_label(l); /* branch taken */ - if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { + if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) { /* misaligned */ gen_exception_inst_addr_mis(ctx); } else { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0ee8ee147d..d1fdd0c2d7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -549,7 +549,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) /* check misaligned: */ next_pc = ctx->base.pc_next + imm; - if (!has_ext(ctx, RVC)) { + if (!ctx->cfg_ptr->ext_zca) { if ((next_pc & 0x3) != 0) { gen_exception_inst_addr_mis(ctx); return; @@ -1122,7 +1122,11 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) if (insn_len(opcode) == 2) { ctx->opcode = opcode; ctx->pc_succ_insn = ctx->base.pc_next + 2; - if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) { + /* + * The Zca extension is added as way to refer to instructions in the C + * extension that do not include the floating-point loads and stores + */ + if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) { return; } } else { From patchwork Tue Mar 7 08:13:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13163005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5E1AC678D5 for ; Tue, 7 Mar 2023 08:14:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSk-00061h-6A; Tue, 07 Mar 2023 03:14:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZSSg-0005zp-Aq; Tue, 07 Mar 2023 03:14:18 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSc-0007Jk-Vd; Tue, 07 Mar 2023 03:14:18 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowACn0qJN8gZkNe6lDA--.36330S5; Tue, 07 Mar 2023 16:14:07 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v12 03/10] target/riscv: add support for Zcf extension Date: Tue, 7 Mar 2023 16:13:56 +0800 Message-Id: <20230307081403.61950-4-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230307081403.61950-1-liweiwei@iscas.ac.cn> References: <20230307081403.61950-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowACn0qJN8gZkNe6lDA--.36330S5 X-Coremail-Antispam: 1UD129KBjvJXoW7uF43Jry7Xw47JFyrJF4UXFb_yoW8trW3pr 18Cay7GrWUAryfA3Z3tF45Xr1UJrs2gry8t3sIyw1kGa1UGFs8Zw1qqr13tr4UXFyvqr1Y kF18A39xC3yktrDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9m14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr 0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUd8n5UUUUU= X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 8 ++++---- target/riscv/insn_trans/trans_rvf.c.inc | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index ccfe59f294..f3ea650325 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -109,11 +109,11 @@ sw 110 ... ... .. ... 00 @cs_w # *** RV32C and RV64C specific Standard Extension (Quadrant 0) *** { ld 011 ... ... .. ... 00 @cl_d - flw 011 ... ... .. ... 00 @cl_w + c_flw 011 ... ... .. ... 00 @cl_w } { sd 111 ... ... .. ... 00 @cs_d - fsw 111 ... ... .. ... 00 @cs_w + c_fsw 111 ... ... .. ... 00 @cs_w } # *** RV32/64C Standard Extension (Quadrant 1) *** @@ -174,9 +174,9 @@ sw 110 . ..... ..... 10 @c_swsp { c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0 ld 011 . ..... ..... 10 @c_ldsp - flw 011 . ..... ..... 10 @c_lwsp + c_flw 011 . ..... ..... 10 @c_lwsp } { sd 111 . ..... ..... 10 @c_sdsp - fsw 111 . ..... ..... 10 @c_swsp + c_fsw 111 . ..... ..... 10 @c_swsp } diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 052408f45c..9e9fa2087a 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -30,6 +30,12 @@ } \ } while (0) +#define REQUIRE_ZCF(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcf) { \ + return false; \ + } \ +} while (0) + static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv_i64 dest; @@ -61,6 +67,18 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) return true; } +static bool trans_c_flw(DisasContext *ctx, arg_flw *a) +{ + REQUIRE_ZCF(ctx); + return trans_flw(ctx, a); +} + +static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a) +{ + REQUIRE_ZCF(ctx); + return trans_fsw(ctx, a); +} + static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a) { REQUIRE_FPU; From patchwork Tue Mar 7 08:13:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13163007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2FA5C678D5 for ; Tue, 7 Mar 2023 08:15:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSm-00062d-Gz; Tue, 07 Mar 2023 03:14:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZSSh-00060Q-P9; Tue, 07 Mar 2023 03:14:19 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSd-0007Jx-28; Tue, 07 Mar 2023 03:14:19 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowACn0qJN8gZkNe6lDA--.36330S6; Tue, 07 Mar 2023 16:14:08 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v12 04/10] target/riscv: add support for Zcd extension Date: Tue, 7 Mar 2023 16:13:57 +0800 Message-Id: <20230307081403.61950-5-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230307081403.61950-1-liweiwei@iscas.ac.cn> References: <20230307081403.61950-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowACn0qJN8gZkNe6lDA--.36330S6 X-Coremail-Antispam: 1UD129KBjvJXoW7Aw1UuFW8GF1kWr4fJrW5KFg_yoW8Kr4xpF 18Cw47GFW5GryfZa13tF43JF4UJFs3Gry8t3sIywn5Gay5GF45Zr1UtFy3tr4UXFWkZr1Y kFyDA39xC395trDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9C14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxGrw CFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE 14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2 IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxK x2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI 0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUQSdkUUUUU= X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 8 ++++---- target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index f3ea650325..b62664b6af 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -97,12 +97,12 @@ } { lq 001 ... ... .. ... 00 @cl_q - fld 001 ... ... .. ... 00 @cl_d + c_fld 001 ... ... .. ... 00 @cl_d } lw 010 ... ... .. ... 00 @cl_w { sq 101 ... ... .. ... 00 @cs_q - fsd 101 ... ... .. ... 00 @cs_d + c_fsd 101 ... ... .. ... 00 @cs_d } sw 110 ... ... .. ... 00 @cs_w @@ -148,7 +148,7 @@ addw 100 1 11 ... 01 ... 01 @cs_2 slli 000 . ..... ..... 10 @c_shift2 { lq 001 ... ... .. ... 10 @c_lqsp - fld 001 . ..... ..... 10 @c_ldsp + c_fld 001 . ..... ..... 10 @c_ldsp } { illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0 @@ -166,7 +166,7 @@ slli 000 . ..... ..... 10 @c_shift2 } { sq 101 ... ... .. ... 10 @c_sqsp - fsd 101 ...... ..... 10 @c_sdsp + c_fsd 101 ...... ..... 10 @c_sdsp } sw 110 . ..... ..... 10 @c_swsp diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 1597bf31d8..2c51e01c40 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -31,6 +31,12 @@ } \ } while (0) +#define REQUIRE_ZCD(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcd) { \ + return false; \ + } \ +} while (0) + static bool trans_fld(DisasContext *ctx, arg_fld *a) { TCGv addr; @@ -59,6 +65,18 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) return true; } +static bool trans_c_fld(DisasContext *ctx, arg_fld *a) +{ + REQUIRE_ZCD(ctx); + return trans_fld(ctx, a); +} + +static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a) +{ + REQUIRE_ZCD(ctx); + return trans_fsd(ctx, a); +} + static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a) { REQUIRE_FPU; From patchwork Tue Mar 7 08:13:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13163011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DDA99C678D5 for ; Tue, 7 Mar 2023 08:15:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSl-00062W-UU; Tue, 07 Mar 2023 03:14:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZSSg-0005zt-GF; Tue, 07 Mar 2023 03:14:18 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSc-0007Jt-Vo; Tue, 07 Mar 2023 03:14:18 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowACn0qJN8gZkNe6lDA--.36330S7; Tue, 07 Mar 2023 16:14:08 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v12 05/10] target/riscv: add support for Zcb extension Date: Tue, 7 Mar 2023 16:13:58 +0800 Message-Id: <20230307081403.61950-6-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230307081403.61950-1-liweiwei@iscas.ac.cn> References: <20230307081403.61950-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowACn0qJN8gZkNe6lDA--.36330S7 X-Coremail-Antispam: 1UD129KBjvJXoW3Wry5Wr13uF4kGry7tr1xGrg_yoW7Zw4xpF 1xCryUGFyqgFyxAayfKF13XF13Gr4SqrWUt39xAw1kJay5KFWDJF1DKay3Ka1DXrsrWr4j 93WDA3yUt3y0qa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9E14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1l42xK82IYc2Ij64vIr4 1l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK 67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI 8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20E Y4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267 AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbmZX7UUUUU== X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add encode and trans* functions support for Zcb instructions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 23 +++++ target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++++++++++++++++++++++ target/riscv/translate.c | 2 + 3 files changed, 125 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index b62664b6af..ab780fa46a 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -43,6 +43,8 @@ %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4 %imm_lui 12:s1 2:5 !function=ex_shift_12 +%uimm_cl_b 5:1 6:1 +%uimm_cl_h 5:1 !function=ex_shift_1 # Argument sets imported from insn32.decode: &empty !extern @@ -53,6 +55,7 @@ &b imm rs2 rs1 !extern &u imm rd !extern &shift shamt rs1 rd !extern +&r2 rd rs1 !extern # Formats 16: @@ -89,6 +92,12 @@ @c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3 +@cu ... ... ... .. ... .. &r2 rs1=%rs1_3 rd=%rs1_3 +@cl_b ... . .. ... .. ... .. &i imm=%uimm_cl_b rs1=%rs1_3 rd=%rs2_3 +@cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3 +@cs_b ... . .. ... .. ... .. &s imm=%uimm_cl_b rs1=%rs1_3 rs2=%rs2_3 +@cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3 + # *** RV32/64C Standard Extension (Quadrant 0) *** { # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved. @@ -180,3 +189,17 @@ sw 110 . ..... ..... 10 @c_swsp sd 111 . ..... ..... 10 @c_sdsp c_fsw 111 . ..... ..... 10 @c_swsp } + +# *** RV64 and RV32 Zcb Extension *** +c_zext_b 100 111 ... 11 000 01 @cu +c_sext_b 100 111 ... 11 001 01 @cu +c_zext_h 100 111 ... 11 010 01 @cu +c_sext_h 100 111 ... 11 011 01 @cu +c_zext_w 100 111 ... 11 100 01 @cu +c_not 100 111 ... 11 101 01 @cu +c_mul 100 111 ... 10 ... 01 @cs_2 +c_lbu 100 000 ... .. ... 00 @cl_b +c_lhu 100 001 ... 0. ... 00 @cl_h +c_lh 100 001 ... 1. ... 00 @cl_h +c_sb 100 010 ... .. ... 00 @cs_b +c_sh 100 011 ... 0. ... 00 @cs_h diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc new file mode 100644 index 0000000000..de96c4afaf --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -0,0 +1,100 @@ +/* + * RISC-V translation routines for the Zcb Standard Extension. + * + * Copyright (c) 2021-2022 PLCT Lab + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#define REQUIRE_ZCB(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcb) \ + return false; \ +} while (0) + +static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a) +{ + REQUIRE_ZCB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8u_tl); +} + +static bool trans_c_zext_h(DisasContext *ctx, arg_c_zext_h *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); +} + +static bool trans_c_sext_b(DisasContext *ctx, arg_c_sext_b *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl); +} + +static bool trans_c_sext_h(DisasContext *ctx, arg_c_sext_h *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl); +} + +static bool trans_c_zext_w(DisasContext *ctx, arg_c_zext_w *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZCB(ctx); + REQUIRE_ZBA(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext32u_tl); +} + +static bool trans_c_not(DisasContext *ctx, arg_c_not *a) +{ + REQUIRE_ZCB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_not_tl); +} + +static bool trans_c_mul(DisasContext *ctx, arg_c_mul *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_M_OR_ZMMUL(ctx); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL); +} + +static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a) +{ + REQUIRE_ZCB(ctx); + return gen_load(ctx, a, MO_UB); +} + +static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a) +{ + REQUIRE_ZCB(ctx); + return gen_load(ctx, a, MO_UW); +} + +static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a) +{ + REQUIRE_ZCB(ctx); + return gen_load(ctx, a, MO_SW); +} + +static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a) +{ + REQUIRE_ZCB(ctx); + return gen_store(ctx, a, MO_UB); +} + +static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a) +{ + REQUIRE_ZCB(ctx); + return gen_store(ctx, a, MO_UW); +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d1fdd0c2d7..3634137d85 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1091,6 +1091,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" +#include "insn_trans/trans_rvzce.c.inc" + /* Include decoders for factored-out extensions */ #include "decode-XVentanaCondOps.c.inc" From patchwork Tue Mar 7 08:13:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13163009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92982C678D4 for ; Tue, 7 Mar 2023 08:15:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSq-00066n-9I; Tue, 07 Mar 2023 03:14:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZSSj-00061L-12; Tue, 07 Mar 2023 03:14:21 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSd-0007KS-7G; Tue, 07 Mar 2023 03:14:20 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowACn0qJN8gZkNe6lDA--.36330S8; Tue, 07 Mar 2023 16:14:10 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v12 06/10] target/riscv: add support for Zcmp extension Date: Tue, 7 Mar 2023 16:13:59 +0800 Message-Id: <20230307081403.61950-7-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230307081403.61950-1-liweiwei@iscas.ac.cn> References: <20230307081403.61950-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowACn0qJN8gZkNe6lDA--.36330S8 X-Coremail-Antispam: 1UD129KBjvJXoWxtr1UWw1xZrW3uF4rZw4fXwb_yoW3Jr1xpF 1UC34xGr18XFWSyw48Kr1rCFnIqr1SgrWUt34Skwn5CayfGF4DJr48KrW3tw4rWFWkuFW5 Ca98Cayjv3y5XFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9E14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1l42xK82IYc2Ij64vIr4 1l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK 67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI 8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20E Y4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267 AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbmZX7UUUUU== X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add encode, trans* functions for Zcmp instructions. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 18 +++ target/riscv/insn_trans/trans_rvzce.c.inc | 187 +++++++++++++++++++++- target/riscv/translate.c | 5 + 3 files changed, 209 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index ab780fa46a..55c9574299 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -21,6 +21,8 @@ %rs1_3 7:3 !function=ex_rvc_register %rs2_3 2:3 !function=ex_rvc_register %rs2_5 2:5 +%r1s 7:3 !function=ex_sreg_register +%r2s 2:3 !function=ex_sreg_register # Immediates: %imm_ci 12:s1 2:5 @@ -45,6 +47,8 @@ %uimm_cl_b 5:1 6:1 %uimm_cl_h 5:1 !function=ex_shift_1 +%spimm 2:2 !function=ex_shift_4 +%urlist 4:4 # Argument sets imported from insn32.decode: &empty !extern @@ -56,7 +60,9 @@ &u imm rd !extern &shift shamt rs1 rd !extern &r2 rd rs1 !extern +&r2_s rs1 rs2 !extern +&cmpp urlist spimm # Formats 16: @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd @@ -97,6 +103,8 @@ @cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3 @cs_b ... . .. ... .. ... .. &s imm=%uimm_cl_b rs1=%rs1_3 rs2=%rs2_3 @cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3 +@cm_pp ... ... ........ .. &cmpp %urlist %spimm +@cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s # *** RV32/64C Standard Extension (Quadrant 0) *** { @@ -176,6 +184,16 @@ slli 000 . ..... ..... 10 @c_shift2 { sq 101 ... ... .. ... 10 @c_sqsp c_fsd 101 ...... ..... 10 @c_sdsp + + # *** RV64 and RV32 Zcmp Extension *** + [ + cm_push 101 11000 .... .. 10 @cm_pp + cm_pop 101 11010 .... .. 10 @cm_pp + cm_popret 101 11110 .... .. 10 @cm_pp + cm_popretz 101 11100 .... .. 10 @cm_pp + cm_mva01s 101 011 ... 11 ... 10 @cm_mv + cm_mvsa01 101 011 ... 01 ... 10 @cm_mv + ] } sw 110 . ..... ..... 10 @c_swsp diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc index de96c4afaf..a47959eb67 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the Zcb Standard Extension. + * RISC-V translation routines for the Zc[b,mp] Standard Extensions. * * Copyright (c) 2021-2022 PLCT Lab * @@ -21,6 +21,11 @@ return false; \ } while (0) +#define REQUIRE_ZCMP(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcmp) \ + return false; \ +} while (0) + static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a) { REQUIRE_ZCB(ctx); @@ -98,3 +103,183 @@ static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a) REQUIRE_ZCB(ctx); return gen_store(ctx, a, MO_UW); } + +#define X_S0 8 +#define X_S1 9 +#define X_Sn 16 + +static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist) +{ + uint32_t reg_bitmap = 0; + + if (ctx->cfg_ptr->ext_e && rlist > 6) { + return 0; + } + + switch (rlist) { + case 15: + reg_bitmap |= 1 << (X_Sn + 11) ; + reg_bitmap |= 1 << (X_Sn + 10) ; + /* FALL THROUGH */ + case 14: + reg_bitmap |= 1 << (X_Sn + 9) ; + /* FALL THROUGH */ + case 13: + reg_bitmap |= 1 << (X_Sn + 8) ; + /* FALL THROUGH */ + case 12: + reg_bitmap |= 1 << (X_Sn + 7) ; + /* FALL THROUGH */ + case 11: + reg_bitmap |= 1 << (X_Sn + 6) ; + /* FALL THROUGH */ + case 10: + reg_bitmap |= 1 << (X_Sn + 5) ; + /* FALL THROUGH */ + case 9: + reg_bitmap |= 1 << (X_Sn + 4) ; + /* FALL THROUGH */ + case 8: + reg_bitmap |= 1 << (X_Sn + 3) ; + /* FALL THROUGH */ + case 7: + reg_bitmap |= 1 << (X_Sn + 2) ; + /* FALL THROUGH */ + case 6: + reg_bitmap |= 1 << X_S1 ; + /* FALL THROUGH */ + case 5: + reg_bitmap |= 1 << X_S0; + /* FALL THROUGH */ + case 4: + reg_bitmap |= 1 << xRA; + break; + default: + break; + } + + return reg_bitmap; +} + +static bool gen_pop(DisasContext *ctx, arg_cmpp *a, bool ret, bool ret_val) +{ + REQUIRE_ZCMP(ctx); + + uint32_t reg_bitmap = decode_push_pop_list(ctx, a->urlist); + if (reg_bitmap == 0) { + return false; + } + + MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ; + int reg_size = memop_size(memop); + target_ulong stack_adj = ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16) + + a->spimm; + TCGv sp = dest_gpr(ctx, xSP); + TCGv addr = tcg_temp_new(); + int i; + + tcg_gen_addi_tl(addr, sp, stack_adj - reg_size); + + for (i = X_Sn + 11; i >= 0; i--) { + if (reg_bitmap & (1 << i)) { + TCGv dest = dest_gpr(ctx, i); + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); + gen_set_gpr(ctx, i, dest); + tcg_gen_subi_tl(addr, addr, reg_size); + } + } + + tcg_gen_addi_tl(sp, sp, stack_adj); + gen_set_gpr(ctx, xSP, sp); + + if (ret_val) { + gen_set_gpr(ctx, xA0, ctx->zero); + } + + if (ret) { + TCGv ret_addr = get_gpr(ctx, xRA, EXT_NONE); + gen_set_pc(ctx, ret_addr); + tcg_gen_lookup_and_goto_ptr(); + ctx->base.is_jmp = DISAS_NORETURN; + } + + return true; +} + +static bool trans_cm_push(DisasContext *ctx, arg_cm_push *a) +{ + REQUIRE_ZCMP(ctx); + + uint32_t reg_bitmap = decode_push_pop_list(ctx, a->urlist); + if (reg_bitmap == 0) { + return false; + } + + MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ; + int reg_size = memop_size(memop); + target_ulong stack_adj = ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16) + + a->spimm; + TCGv sp = dest_gpr(ctx, xSP); + TCGv addr = tcg_temp_new(); + int i; + + tcg_gen_subi_tl(addr, sp, reg_size); + + for (i = X_Sn + 11; i >= 0; i--) { + if (reg_bitmap & (1 << i)) { + TCGv val = get_gpr(ctx, i, EXT_NONE); + tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, memop); + tcg_gen_subi_tl(addr, addr, reg_size); + } + } + + tcg_gen_subi_tl(sp, sp, stack_adj); + gen_set_gpr(ctx, xSP, sp); + + return true; +} + +static bool trans_cm_pop(DisasContext *ctx, arg_cm_pop *a) +{ + return gen_pop(ctx, a, false, false); +} + +static bool trans_cm_popret(DisasContext *ctx, arg_cm_popret *a) +{ + return gen_pop(ctx, a, true, false); +} + +static bool trans_cm_popretz(DisasContext *ctx, arg_cm_popret *a) +{ + return gen_pop(ctx, a, true, true); +} + +static bool trans_cm_mva01s(DisasContext *ctx, arg_cm_mva01s *a) +{ + REQUIRE_ZCMP(ctx); + + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + + gen_set_gpr(ctx, xA0, src1); + gen_set_gpr(ctx, xA1, src2); + + return true; +} + +static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_mvsa01 *a) +{ + REQUIRE_ZCMP(ctx); + + if (a->rs1 == a->rs2) { + return false; + } + + TCGv a0 = get_gpr(ctx, xA0, EXT_NONE); + TCGv a1 = get_gpr(ctx, xA1, EXT_NONE); + + gen_set_gpr(ctx, a->rs1, a0); + gen_set_gpr(ctx, a->rs2, a1); + + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3634137d85..6872d17fb9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -757,6 +757,11 @@ static int ex_rvc_register(DisasContext *ctx, int reg) return 8 + reg; } +static int ex_sreg_register(DisasContext *ctx, int reg) +{ + return reg < 2 ? reg + 8 : reg + 16; +} + static int ex_rvc_shiftli(DisasContext *ctx, int imm) { /* For RV128 a shamt of 0 means a shift by 64. */ From patchwork Tue Mar 7 08:14:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13163013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7151C678D4 for ; Tue, 7 Mar 2023 08:16:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSn-00064a-Qk; Tue, 07 Mar 2023 03:14:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZSSj-00061d-UU; Tue, 07 Mar 2023 03:14:22 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSd-0007KO-A2; Tue, 07 Mar 2023 03:14:21 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowACn0qJN8gZkNe6lDA--.36330S9; Tue, 07 Mar 2023 16:14:10 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v12 07/10] target/riscv: add support for Zcmt extension Date: Tue, 7 Mar 2023 16:14:00 +0800 Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230307081403.61950-1-liweiwei@iscas.ac.cn> References: <20230307081403.61950-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowACn0qJN8gZkNe6lDA--.36330S9 X-Coremail-Antispam: 1UD129KBjvJXoW3KrWDZF17Jry3JFyUKF1rWFg_yoWDuryrpF 48C3y7GrWkJFZ7Aa4fKF45tF15Jw4rG3yjkws3Aws5Ja13JFWrJr1DKw13KF4DXFZ5ur1j 93Z0yFy5ArW8ZFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9E14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1l42xK82IYc2Ij64vIr4 1l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK 67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI 8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20E Y4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267 AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbmZX7UUUUU== X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 36 ++++++++++++++- target/riscv/helper.h | 3 ++ target/riscv/insn16.decode | 7 ++- target/riscv/insn_trans/trans_rvzce.c.inc | 28 +++++++++++- target/riscv/machine.c | 19 ++++++++ target/riscv/meson.build | 3 +- target/riscv/zce_helper.c | 55 +++++++++++++++++++++++ 9 files changed, 157 insertions(+), 5 deletions(-) create mode 100644 target/riscv/zce_helper.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a2426ec479..351d5e3e79 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -176,6 +176,8 @@ struct CPUArchState { /* 128-bit helpers upper part return value */ target_ulong retxh; + target_ulong jvt; + #ifdef CONFIG_USER_ONLY uint32_t elf_flags; #endif @@ -619,6 +621,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, target_ulong new_val, target_ulong write_mask), void *rmw_fn_arg); + +RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); #endif void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index fca7ef0cef..a92313a06f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -319,6 +319,7 @@ #define SMSTATEEN_MAX_COUNT 4 #define SMSTATEEN0_CS (1ULL << 0) #define SMSTATEEN0_FCSR (1ULL << 1) +#define SMSTATEEN0_JVT (1ULL << 2) #define SMSTATEEN0_HSCONTXT (1ULL << 57) #define SMSTATEEN0_IMSIC (1ULL << 58) #define SMSTATEEN0_AIA (1ULL << 59) @@ -523,6 +524,9 @@ /* Crypto Extension */ #define CSR_SEED 0x015 +/* Zcmt Extension */ +#define CSR_JVT 0x017 + /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 @@ -898,4 +902,7 @@ typedef enum RISCVException { #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 +/* JVT CSR bits */ +#define JVT_MODE 0x3F +#define JVT_BASE (~0x3F) #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ab566639e5..d7bf83bc8c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -42,8 +42,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) /* Predicates */ #if !defined(CONFIG_USER_ONLY) -static RISCVException smstateen_acc_ok(CPURISCVState *env, int index, - uint64_t bit) +RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) { bool virt = riscv_cpu_virt_enabled(env); @@ -162,6 +161,22 @@ static RISCVException ctr32(CPURISCVState *env, int csrno) return ctr(env, csrno); } +static RISCVException zcmt(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_zcmt) { + return RISCV_EXCP_ILLEGAL_INST; + } + +#if !defined(CONFIG_USER_ONLY) + RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); + if (ret != RISCV_EXCP_NONE) { + return ret; + } +#endif + + return RISCV_EXCP_NONE; +} + #if !defined(CONFIG_USER_ONLY) static RISCVException mctr(CPURISCVState *env, int csrno) { @@ -3990,6 +4005,20 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, return ret; } +static RISCVException read_jvt(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->jvt; + return RISCV_EXCP_NONE; +} + +static RISCVException write_jvt(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->jvt = val; + return RISCV_EXCP_NONE; +} + /* Control and Status Register function table */ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* User Floating-Point CSRs */ @@ -4020,6 +4049,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* Crypto Extension */ [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed }, + /* Zcmt Extension */ + [CSR_JVT] = {"jvt", zcmt, read_jvt, write_jvt}, + #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 37b54e0991..1880e95c50 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1142,3 +1142,6 @@ DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) + +/* Zce helper */ +DEF_HELPER_FLAGS_2(cm_jalt, TCG_CALL_NO_WG, tl, env, i32) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 55c9574299..b96c534e73 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -49,6 +49,7 @@ %uimm_cl_h 5:1 !function=ex_shift_1 %spimm 2:2 !function=ex_shift_4 %urlist 4:4 +%index 2:8 # Argument sets imported from insn32.decode: &empty !extern @@ -63,6 +64,7 @@ &r2_s rs1 rs2 !extern &cmpp urlist spimm +&cmjt index # Formats 16: @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd @@ -105,6 +107,7 @@ @cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3 @cm_pp ... ... ........ .. &cmpp %urlist %spimm @cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s +@cm_jt ... ... ........ .. &cmjt %index # *** RV32/64C Standard Extension (Quadrant 0) *** { @@ -185,7 +188,7 @@ slli 000 . ..... ..... 10 @c_shift2 sq 101 ... ... .. ... 10 @c_sqsp c_fsd 101 ...... ..... 10 @c_sdsp - # *** RV64 and RV32 Zcmp Extension *** + # *** RV64 and RV32 Zcmp/Zcmt Extension *** [ cm_push 101 11000 .... .. 10 @cm_pp cm_pop 101 11010 .... .. 10 @cm_pp @@ -193,6 +196,8 @@ slli 000 . ..... ..... 10 @c_shift2 cm_popretz 101 11100 .... .. 10 @cm_pp cm_mva01s 101 011 ... 11 ... 10 @cm_mv cm_mvsa01 101 011 ... 01 ... 10 @cm_mv + + cm_jalt 101 000 ........ 10 @cm_jt ] } sw 110 . ..... ..... 10 @c_swsp diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc index a47959eb67..d75acbc4a6 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the Zc[b,mp] Standard Extensions. + * RISC-V translation routines for the Zc[b,mp,mt] Standard Extensions. * * Copyright (c) 2021-2022 PLCT Lab * @@ -26,6 +26,11 @@ return false; \ } while (0) +#define REQUIRE_ZCMT(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcmt) \ + return false; \ +} while (0) + static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a) { REQUIRE_ZCB(ctx); @@ -283,3 +288,24 @@ static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_mvsa01 *a) return true; } + +static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a) +{ + REQUIRE_ZCMT(ctx); + + /* + * Update pc to current for the non-unwinding exception + * that might come from cpu_ld*_code() in the helper. + */ + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->index)); + + /* c.jt vs c.jalt depends on the index. */ + if (a->index >= 32) { + gen_set_gpri(ctx, xRA, ctx->pc_succ_insn); + } + + tcg_gen_lookup_and_goto_ptr(); + ctx->base.is_jmp = DISAS_NORETURN; + return true; +} diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 9c455931d8..27f430ad74 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -329,6 +329,24 @@ static const VMStateDescription vmstate_pmu_ctr_state = { } }; +static bool jvt_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + + return cpu->cfg.ext_zcmt; +} + +static const VMStateDescription vmstate_jvt = { + .name = "cpu/jvt", + .version_id = 1, + .minimum_version_id = 1, + .needed = jvt_needed, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(env.jvt, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 7, @@ -395,6 +413,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_envcfg, &vmstate_debug, &vmstate_smstateen, + &vmstate_jvt, NULL } }; diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 5dee37a242..5b7f813a3e 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -19,7 +19,8 @@ riscv_ss.add(files( 'bitmanip_helper.c', 'translate.c', 'm128_helper.c', - 'crypto_helper.c' + 'crypto_helper.c', + 'zce_helper.c' )) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c new file mode 100644 index 0000000000..b433bda16d --- /dev/null +++ b/target/riscv/zce_helper.c @@ -0,0 +1,55 @@ +/* + * RISC-V Zcmt Extension Helper for QEMU. + * + * Copyright (c) 2021-2022 PLCT Lab + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "exec/cpu_ldst.h" + +target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index) +{ + +#if !defined(CONFIG_USER_ONLY) + RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); + if (ret != RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, 0); + } +#endif + + target_ulong target; + target_ulong val = env->jvt; + int xlen = riscv_cpu_xlen(env); + uint8_t mode = get_field(val, JVT_MODE); + target_ulong base = val & JVT_BASE; + target_ulong t0; + + if (mode != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, 0); + } + + if (xlen == 32) { + t0 = base + (index << 2); + target = cpu_ldl_code(env, t0); + } else { + t0 = base + (index << 3); + target = cpu_ldq_code(env, t0); + } + + return target & ~0x1; +} From patchwork Tue Mar 7 08:14:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13163010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8966DC678D4 for ; Tue, 7 Mar 2023 08:15:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSp-00066H-LQ; Tue, 07 Mar 2023 03:14:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZSSh-00060F-Lo; Tue, 07 Mar 2023 03:14:19 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSd-0007KP-AD; Tue, 07 Mar 2023 03:14:19 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowACn0qJN8gZkNe6lDA--.36330S10; Tue, 07 Mar 2023 16:14:11 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v12 08/10] target/riscv: expose properties for Zc* extension Date: Tue, 7 Mar 2023 16:14:01 +0800 Message-Id: <20230307081403.61950-9-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230307081403.61950-1-liweiwei@iscas.ac.cn> References: <20230307081403.61950-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowACn0qJN8gZkNe6lDA--.36330S10 X-Coremail-Antispam: 1UD129KBjvJXoW7KFy7CF4rWw4xAF4xJFyxZrb_yoW8tr43pr W5Ga47Kw15Jr13Gwsxtr1DJw4rCw4rA3s7K3ySv3Z7JrZ7KrZrXFnrG39rW3yrtF4rZw4S gF13Zr1xurs5ta7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBj14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1l42xK82IYc2Ij64vIr4 1l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK 67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI 8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20E Y4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267 AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUQSdkUUUUU= X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Expose zca,zcb,zcf,zcd,zcmp,zcmt properties. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index df7eed57af..d17ae942bd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -87,6 +87,12 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), + ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca), + ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb), + ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf), + ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd), + ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp), + ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt), ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), @@ -1491,6 +1497,14 @@ static Property riscv_cpu_extensions[] = { /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), + + DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), + DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), + DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), + DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), + DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), + DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), + /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), From patchwork Tue Mar 7 08:14:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13163028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E6CDC678D4 for ; Tue, 7 Mar 2023 08:23:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSar-00068k-W5; Tue, 07 Mar 2023 03:22:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZSap-000684-QP; Tue, 07 Mar 2023 03:22:43 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSam-0000AR-A6; Tue, 07 Mar 2023 03:22:43 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowACn0qJN8gZkNe6lDA--.36330S11; Tue, 07 Mar 2023 16:14:12 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v12 09/10] disas/riscv.c: add disasm support for Zc* Date: Tue, 7 Mar 2023 16:14:02 +0800 Message-Id: <20230307081403.61950-10-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230307081403.61950-1-liweiwei@iscas.ac.cn> References: <20230307081403.61950-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowACn0qJN8gZkNe6lDA--.36330S11 X-Coremail-Antispam: 1UD129KBjvJXoW3AF4DGw47WrWDXFyUuFW7Arb_yoWfZF1DpF 1rG343trWUKa4Sq3WfAFWUAas8trWUXr4xJaySy3Z3Casru343CF1jq3yavFykG3yrKr47 uFsxWa1jg3Z7JwUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBj14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1l42xK82IYc2Ij64vIr4 1l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK 67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI 8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20E Y4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267 AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUQSdkUUUUU= X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- disas/riscv.c | 228 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 227 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 54455aaaa8..189214c41f 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -163,6 +163,13 @@ typedef enum { rv_codec_v_i, rv_codec_vsetvli, rv_codec_vsetivli, + rv_codec_zcb_ext, + rv_codec_zcb_mul, + rv_codec_zcb_lb, + rv_codec_zcb_lh, + rv_codec_zcmp_cm_pushpop, + rv_codec_zcmp_cm_mv, + rv_codec_zcmt_jt, } rv_codec; typedef enum { @@ -935,6 +942,26 @@ typedef enum { rv_op_vsetvli = 766, rv_op_vsetivli = 767, rv_op_vsetvl = 768, + rv_op_c_zext_b = 769, + rv_op_c_sext_b = 770, + rv_op_c_zext_h = 771, + rv_op_c_sext_h = 772, + rv_op_c_zext_w = 773, + rv_op_c_not = 774, + rv_op_c_mul = 775, + rv_op_c_lbu = 776, + rv_op_c_lhu = 777, + rv_op_c_lh = 778, + rv_op_c_sb = 779, + rv_op_c_sh = 780, + rv_op_cm_push = 781, + rv_op_cm_pop = 782, + rv_op_cm_popret = 783, + rv_op_cm_popretz = 784, + rv_op_cm_mva01s = 785, + rv_op_cm_mvsa01 = 786, + rv_op_cm_jt = 787, + rv_op_cm_jalt = 788, } rv_op; /* structures */ @@ -958,6 +985,7 @@ typedef struct { uint8_t rnum; uint8_t vm; uint32_t vzimm; + uint8_t rlist; } rv_decode; typedef struct { @@ -1070,6 +1098,10 @@ static const char rv_vreg_name_sym[32][4] = { #define rv_fmt_vd_vm "O\tDm" #define rv_fmt_vsetvli "O\t0,1,v" #define rv_fmt_vsetivli "O\t0,u,v" +#define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)" +#define rv_fmt_push_rlist "O\tx,-i" +#define rv_fmt_pop_rlist "O\tx,i" +#define rv_fmt_zcmt_index "O\ti" /* pseudo-instruction constraints */ @@ -2065,7 +2097,27 @@ const rv_opcode_data opcode_data[] = { { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 }, { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 }, { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 }, - { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 } + { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }, + { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 }, + { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 }, + { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, + { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 }, + { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, + { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, + { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, + { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, + { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, }; /* CSR names */ @@ -2084,6 +2136,7 @@ static const char *csr_name(int csrno) case 0x000a: return "vxrm"; case 0x000f: return "vcsr"; case 0x0015: return "seed"; + case 0x0017: return "jvt"; case 0x0040: return "uscratch"; case 0x0041: return "uepc"; case 0x0042: return "ucause"; @@ -2306,6 +2359,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) op = rv_op_c_ld; } break; + case 4: + switch ((inst >> 10) & 0b111) { + case 0: op = rv_op_c_lbu; break; + case 1: + if (((inst >> 6) & 1) == 0) { + op = rv_op_c_lhu; + } else { + op = rv_op_c_lh; + } + break; + case 2: op = rv_op_c_sb; break; + case 3: + if (((inst >> 6) & 1) == 0) { + op = rv_op_c_sh; + } + break; + } + break; case 5: if (isa == rv128) { op = rv_op_c_sq; @@ -2362,6 +2433,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 3: op = rv_op_c_and; break; case 4: op = rv_op_c_subw; break; case 5: op = rv_op_c_addw; break; + case 6: op = rv_op_c_mul; break; + case 7: + switch ((inst >> 2) & 0b111) { + case 0: op = rv_op_c_zext_b; break; + case 1: op = rv_op_c_sext_b; break; + case 2: op = rv_op_c_zext_h; break; + case 3: op = rv_op_c_sext_h; break; + case 4: op = rv_op_c_zext_w; break; + case 5: op = rv_op_c_not; break; + } + break; } break; } @@ -2417,6 +2499,46 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) op = rv_op_c_sqsp; } else { op = rv_op_c_fsdsp; + if (((inst >> 12) & 0b01)) { + switch ((inst >> 8) & 0b01111) { + case 8: + if (((inst >> 4) & 0b01111) >= 4) { + op = rv_op_cm_push; + } + break; + case 10: + if (((inst >> 4) & 0b01111) >= 4) { + op = rv_op_cm_pop; + } + break; + case 12: + if (((inst >> 4) & 0b01111) >= 4) { + op = rv_op_cm_popretz; + } + break; + case 14: + if (((inst >> 4) & 0b01111) >= 4) { + op = rv_op_cm_popret; + } + break; + } + } else { + switch ((inst >> 10) & 0b011) { + case 0: + if (((inst >> 2) & 0xFF) >= 32) { + op = rv_op_cm_jalt; + } else { + op = rv_op_cm_jt; + } + break; + case 3: + switch ((inst >> 5) & 0b011) { + case 1: op = rv_op_cm_mvsa01; break; + case 3: op = rv_op_cm_mva01s; break; + } + break; + } + } } break; case 6: op = rv_op_c_swsp; break; @@ -3661,6 +3783,21 @@ static uint32_t operand_crs2q(rv_inst inst) return (inst << 59) >> 61; } +static uint32_t calculate_xreg(uint32_t sreg) +{ + return sreg < 2 ? sreg + 8 : sreg + 16; +} + +static uint32_t operand_sreg1(rv_inst inst) +{ + return calculate_xreg((inst << 54) >> 61); +} + +static uint32_t operand_sreg2(rv_inst inst) +{ + return calculate_xreg((inst << 59) >> 61); +} + static uint32_t operand_crd(rv_inst inst) { return (inst << 52) >> 59; @@ -3883,6 +4020,46 @@ static uint32_t operand_vm(rv_inst inst) return (inst << 38) >> 63; } +static uint32_t operand_uimm_c_lb(rv_inst inst) +{ + return (((inst << 58) >> 63) << 1) | + ((inst << 57) >> 63); +} + +static uint32_t operand_uimm_c_lh(rv_inst inst) +{ + return (((inst << 58) >> 63) << 1); +} + +static uint32_t operand_zcmp_spimm(rv_inst inst) +{ + return ((inst << 60) >> 62) << 4; +} + +static uint32_t operand_zcmp_rlist(rv_inst inst) +{ + return ((inst << 56) >> 60); +} + +static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm) +{ + int xlen_bytes_log2 = isa == rv64 ? 3 : 2; + int regs = rlist == 15 ? 13 : rlist - 3; + uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16); + return stack_adj_base + spimm; +} + +static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa) +{ + return calculate_stack_adj(isa, operand_zcmp_rlist(inst), + operand_zcmp_spimm(inst)); +} + +static uint32_t operand_tbl_index(rv_inst inst) +{ + return ((inst << 54) >> 56); +} + /* decode operands */ static void decode_inst_operands(rv_decode *dec, rv_isa isa) @@ -4199,6 +4376,34 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa) dec->imm = operand_vimm(inst); dec->vzimm = operand_vzimm10(inst); break; + case rv_codec_zcb_lb: + dec->rs1 = operand_crs1q(inst) + 8; + dec->rs2 = operand_crs2q(inst) + 8; + dec->imm = operand_uimm_c_lb(inst); + break; + case rv_codec_zcb_lh: + dec->rs1 = operand_crs1q(inst) + 8; + dec->rs2 = operand_crs2q(inst) + 8; + dec->imm = operand_uimm_c_lh(inst); + break; + case rv_codec_zcb_ext: + dec->rd = operand_crs1q(inst) + 8; + break; + case rv_codec_zcb_mul: + dec->rd = operand_crs1rdq(inst) + 8; + dec->rs2 = operand_crs2q(inst) + 8; + break; + case rv_codec_zcmp_cm_pushpop: + dec->imm = operand_zcmp_stack_adj(inst, isa); + dec->rlist = operand_zcmp_rlist(inst); + break; + case rv_codec_zcmp_cm_mv: + dec->rd = operand_sreg1(inst); + dec->rs2 = operand_sreg2(inst); + break; + case rv_codec_zcmt_jt: + dec->imm = operand_tbl_index(inst); + break; }; } @@ -4358,6 +4563,9 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) case ')': append(buf, ")", buflen); break; + case '-': + append(buf, "-", buflen); + break; case 'b': snprintf(tmp, sizeof(tmp), "%d", dec->bs); append(buf, tmp, buflen); @@ -4541,6 +4749,24 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) append(buf, vma, buflen); break; } + case 'x': { + switch (dec->rlist) { + case 4: + snprintf(tmp, sizeof(tmp), "{ra}"); + break; + case 5: + snprintf(tmp, sizeof(tmp), "{ra, s0}"); + break; + case 15: + snprintf(tmp, sizeof(tmp), "{ra, s0-s11}"); + break; + default: + snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5); + break; + } + append(buf, tmp, buflen); + break; + } default: break; } From patchwork Tue Mar 7 08:14:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13163014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6B2AC6FD1B for ; Tue, 7 Mar 2023 08:16:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSm-00062f-La; Tue, 07 Mar 2023 03:14:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZSSi-00061H-RY; Tue, 07 Mar 2023 03:14:20 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZSSe-0007Kr-Qf; Tue, 07 Mar 2023 03:14:20 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowACn0qJN8gZkNe6lDA--.36330S12; Tue, 07 Mar 2023 16:14:12 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v12 10/10] target/riscv: Add support for Zce Date: Tue, 7 Mar 2023 16:14:03 +0800 Message-Id: <20230307081403.61950-11-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230307081403.61950-1-liweiwei@iscas.ac.cn> References: <20230307081403.61950-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowACn0qJN8gZkNe6lDA--.36330S12 X-Coremail-Antispam: 1UD129KBjvJXoW7KFy7CF1kXFyrCr4DKr47CFg_yoW8KFy5pr 4rGa4jkws8Jr13G3yftr1DJr4rGw4fA3s7K3ySv3Z7XrWfKrW3XF1DCwsruw45JFWrZr1S 9F15uF1UArs5ta7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBj14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1l42xK82IYc2Ij64vIr4 1l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK 67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI 8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20E Y4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267 AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUQSdkUUUUU= X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add and expose property for Zce: * Specifying Zce without F includes Zca, Zcb, Zcmp, Zcmt. * Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 12 ++++++++++++ target/riscv/cpu.h | 1 + 2 files changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d17ae942bd..3502d1e749 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -91,6 +91,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb), ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf), ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd), + ISA_EXT_DATA_ENTRY(zce, true, PRIV_VERSION_1_12_0, ext_zce), ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp), ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt), ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), @@ -945,6 +946,16 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } + if (cpu->cfg.ext_zce) { + cpu->cfg.ext_zca = true; + cpu->cfg.ext_zcb = true; + cpu->cfg.ext_zcmp = true; + cpu->cfg.ext_zcmt = true; + if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { + cpu->cfg.ext_zcf = true; + } + } + if (cpu->cfg.ext_c) { cpu->cfg.ext_zca = true; if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { @@ -1501,6 +1512,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), + DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 351d5e3e79..9b76885166 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -443,6 +443,7 @@ struct RISCVCPUConfig { bool ext_zca; bool ext_zcb; bool ext_zcd; + bool ext_zce; bool ext_zcf; bool ext_zcmp; bool ext_zcmt;