From patchwork Wed Mar 8 13:07:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13165708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18C97C64EC4 for ; Wed, 8 Mar 2023 13:12:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=NdFXlTRfwUKeTUluY0n82subEhbFPKLfCNm2Bp82Nu4=; b=iMkSw/4GNHMxhJ SGQDUnEgAnSlytKD/Uf9i8kfb8SJ+Qnr0uTeE74reGg1XxBMzp/pgYhXpnsm+UTp7qAxoFpPg3xq1 gC2lujUjLtm8B/0sBlU066Qd8fTOqmUFNyFThV284K9ywEaMulTdLx2CZxC7QnApsnyeeEwQCKTSK G8xBGSn1hI8faJXZnEebWATYGPQn8QgXT9mYFqfj9LmWFGxN4poiE+4CKvFw+jwO3giM9ZjcRuppz odsMMRkmBkPnOP2LJIijrGkNQJT3t+H8cuxctkdmSnDH/X//8fLpmgl5xhHBls0itWGTZ96SDKi8I Og/n/TzAMgMDwFWgszOA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pZtZ6-0055Gp-Pw; Wed, 08 Mar 2023 13:10:46 +0000 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pZtVu-0053QP-2l; Wed, 08 Mar 2023 13:07:27 +0000 Received: by mail-wr1-x42f.google.com with SMTP id bx12so15278454wrb.11; Wed, 08 Mar 2023 05:07:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678280844; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=JuDmDmY4IV0QLoJ1ArzJ4ijcazQ7ZD0u2S2wBUytaV4=; b=Dkuy4VDXieLUfg8wLyjcvVyTG3cxdXmVVcyqAjQzY2ESFnznZGMWvTKoAogOrf1tZO 7xFIAbyFOk3M03a449PZz9nPzsMnohAks1WHPKOutMHa6yvON9XXqpZkhtj4mhjSDvHT qGr9G2v6GtndN9sStm89LaOEeRN8glr2KZYlqUVRc8DjKLZa1zJ5g0dZtwMq4vZ3aHaV tNSz8ouiBbvLnReajtgAptfEXBDdlO3tj46vruxT+vCOb/mu5wwLW29zEdvmVRTdd3kZ MGBHUv0ZH1sPVkbN+1wH0xCoPsT7v52aAFl9QHEMPSUWsnAq1Ooz0/j7KlSuLQucpvjM EWow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678280844; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=JuDmDmY4IV0QLoJ1ArzJ4ijcazQ7ZD0u2S2wBUytaV4=; b=5IZ7og8A6JsDAS0P5fWWHirVHajUcV+IOa36TQe3BjfKq4yRsfjq0rEFxa6OJ0xB8H ZT4Yr435EkNFzgNHZTMwvlq7mWR5NOXASwrKwJQdv+/yaNBeVsjJYKXcJ/LKEJlk6lGi /Y6YS7wPxzDbYxtlz/Pa0Ngz+lxpd9SSCRyZhubeiC3OjyuydB4V66PniXtR8LFCN8PW 6RLEm+B6klC5PCssSvFUk9wMntFfbIPaP8vZRFDj7+6iCcgbssrEFE31kxd7Fsil7U09 rkt5yFY4fJBWze6GJ0ln9jdoiNHsrlNiH7MMKkBvgx7UJ/pN/U3X+tfvRSQkHRF9E5yU JuBQ== X-Gm-Message-State: AO0yUKWQAhrE//R2PHCRAHK4+ql69cnPVgExdjCrNztwFiyX9BgnVegZ 8nSHPvDkH1sdN5upCL2BzH8= X-Google-Smtp-Source: AK7set/96yytF4lJdh5dq0MUq0uqJPsADOci+FXLCWrgSJ+F8EsYh8DcDuDj9WyArHHVFVjqlneYOA== X-Received: by 2002:adf:eac7:0:b0:2c7:161e:702f with SMTP id o7-20020adfeac7000000b002c7161e702fmr12307060wrn.47.1678280843674; Wed, 08 Mar 2023 05:07:23 -0800 (PST) Received: from arinc9-PC.lan ([212.68.60.226]) by smtp.gmail.com with ESMTPSA id b3-20020a5d40c3000000b002ce37d2464csm11461328wrq.83.2023.03.08.05.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 05:07:23 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?utf-8?q?Ren=C3=A9_van_Dorst?= Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 net 1/2] net: dsa: mt7530: remove now incorrect comment regarding port 5 Date: Wed, 8 Mar 2023 16:07:14 +0300 Message-Id: <20230308130714.77397-1-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230308_050726_165634_D0CC48B8 X-CRM114-Status: GOOD ( 11.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL Remove now incorrect comment regarding port 5 as GMAC5. This is supposed to be supported since commit 38f790a80560 ("net: dsa: mt7530: Add support for port 5") under mt7530_setup_port5(). Fixes: 38f790a80560 ("net: dsa: mt7530: Add support for port 5") Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index a508402c4ecb..b1a79460df0e 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2201,7 +2201,7 @@ mt7530_setup(struct dsa_switch *ds) mt7530_pll_setup(priv); - /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ + /* Enable port 6 */ val = mt7530_read(priv, MT7530_MHWTRAP); val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; val |= MHWTRAP_MANUAL; From patchwork Wed Mar 8 13:07:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13165709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB423C678D5 for ; Wed, 8 Mar 2023 13:12:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XRZq4TLCs/TJ1gg9acL7/zID9tjSOpU/TuWnqUAk6bM=; b=odS8F6gstXEGCu SZ5tT+8bs7N2A2w0avOrOXUeN6mRaluAoCCfhd/jGZyveB3OyAPsY0EZaPOJ35LIxxuZcATcKABL6 BaeqyyPn/lVlbkbEvevsUzxM0PoJTF+z3JLNm98KaGuE0mXWQ7JsfabXvtSwR/yjjXhgYBrSdj+ng ZPbL58/fe4TzhmAw7sYv+QKZzqiWmBmrukGB/qAD0DHMA6/jDoEPP/clYw1qQpC0R0qEMRTtGhTV6 I9Jy7LD0bCwsoztOqTCqvfv+ZwZInl1lNvfnXveCdAU2Jxg3U6AzDBOxUt+ZNw9cUZfMMyVBdeRfp GJcOPOkblkL2TRbdXKqw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1pZtZy-0055iC-Ug; Wed, 08 Mar 2023 13:11:40 +0000 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1pZtVx-0053SP-Pi; Wed, 08 Mar 2023 13:07:31 +0000 Received: by mail-wr1-x42d.google.com with SMTP id l1so15258111wry.12; Wed, 08 Mar 2023 05:07:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678280846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w1qQOPUYZltp62usDX13u0lfSl6bY/5+CW4Brvbfffs=; b=LoOmc33r6hDYRPAbUIc7PLTQTmw1nd1Yu1JjIRp7tohLlnWvHQuQCbrLVsYxnwhoAf 7VAG8+bxYrXzKq7/ZvkKKQaAzMUUmJZIv36GBOP2aOmn9aLjsKnMVBeidiPun1jUfnAu xpV9uTVIs4cdbz0bmyRk12AxbOUz80jMj9C7KVzL2WdVbEwwOj2l5dkkcWnWLZJVT99W EKbq0sEzdSCv6kVAJ2AqPWtCQC8j5ocjlB1nfwwNOBUE9IpXxUm1OYnpTuRMufAUweQU FuOHJQOcV776gVr4QYPigLCgBUdJxaFpYbwEDAZs46B9QkzfG/aYe2ZnunJfFjCfWTkY f8Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678280846; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w1qQOPUYZltp62usDX13u0lfSl6bY/5+CW4Brvbfffs=; b=SARtTeKIIDHFlcrqe0OnNpimQWfI5y1fXBFTh0RjRBfOca3baSYRe9NhFtebzMAHuR 7tx4Ofq7wdH00lgWdLTnbQlBITlecR29igkW4V65gvsbnmU4n3Eqr81wOsRGX40yGexA Mosuhkv61qDyZTPf6i2InewtyjzUfxEj8oPVDf0HM3p+Djb5sJR71RAS4waOF7jd/Jpc X8bmSw1Ace/FM2QPwnX8PTHp2A7OCxhMZoqv+JB/P3KVnA6bMA9JJ4xfHHprxWi2HbXH et1B0ZtMT1zPmNlNSnEpxNO5oeZ1X1d78LWUTpravsc95/PJjPCJyWX1fhOSe7DQTi0+ YmrA== X-Gm-Message-State: AO0yUKVzoeZ2lsKPPKd58GBltOgB89bPrVPKNoSujNdWXU6niFCJxIVH vyVn9fW/XX41OOTGLLANx+s= X-Google-Smtp-Source: AK7set+chCvVyMu/Alk9YMPkc6M1D5hQo3UquQkcmNKdIEeu879ufUQb+Tt+MiE42KL0vZoz6/4HBQ== X-Received: by 2002:adf:e606:0:b0:2c5:587e:75ba with SMTP id p6-20020adfe606000000b002c5587e75bamr10918723wrm.55.1678280845802; Wed, 08 Mar 2023 05:07:25 -0800 (PST) Received: from arinc9-PC.lan ([212.68.60.226]) by smtp.gmail.com with ESMTPSA id b3-20020a5d40c3000000b002ce37d2464csm11461328wrq.83.2023.03.08.05.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 05:07:25 -0800 (PST) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?utf-8?q?Ren=C3=A9_van_Dorst?= Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 net 2/2] net: dsa: mt7530: set PLL frequency and trgmii only when trgmii is used Date: Wed, 8 Mar 2023 16:07:15 +0300 Message-Id: <20230308130714.77397-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230308130714.77397-1-arinc.unal@arinc9.com> References: <20230308130714.77397-1-arinc.unal@arinc9.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230308_050729_928535_C6183D56 X-CRM114-Status: GOOD ( 17.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Arınç ÜNAL As my testing on the MCM MT7530 switch on MT7621 SoC shows, setting the PLL frequency does not affect MII modes other than trgmii on port 5 and port 6. So the assumption is that the operation here called "setting the PLL frequency" actually sets the frequency of the TRGMII TX clock. Make it so that it and the rest of the trgmii setup run only when the trgmii mode is used. Tested rgmii and trgmii modes of port 6 on MCM MT7530 on MT7621AT Unielec U7621-06 and standalone MT7530 on MT7623NI Bananapi BPI-R2. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch") Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 62 ++++++++++++++++++++-------------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index b1a79460df0e..c2d81b7a429d 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -430,8 +430,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) switch (interface) { case PHY_INTERFACE_MODE_RGMII: trgint = 0; - /* PLL frequency: 125MHz */ - ncpo1 = 0x0c80; break; case PHY_INTERFACE_MODE_TRGMII: trgint = 1; @@ -462,38 +460,40 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(trgint)); - /* Lower Tx Driving for TRGMII path */ - for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) - mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), - TD_DM_DRVP(8) | TD_DM_DRVN(8)); - - /* Disable MT7530 core and TRGMII Tx clocks */ - core_clear(priv, CORE_TRGMII_GSW_CLK_CG, - REG_GSWCK_EN | REG_TRGMIICK_EN); - - /* Setup the MT7530 TRGMII Tx Clock */ - core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); - core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); - core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); - core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); - core_write(priv, CORE_PLL_GROUP4, - RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | - RG_SYSPLL_BIAS_LPF_EN); - core_write(priv, CORE_PLL_GROUP2, - RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | - RG_SYSPLL_POSDIV(1)); - core_write(priv, CORE_PLL_GROUP7, - RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | - RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); - - /* Enable MT7530 core and TRGMII Tx clocks */ - core_set(priv, CORE_TRGMII_GSW_CLK_CG, - REG_GSWCK_EN | REG_TRGMIICK_EN); - - if (!trgint) + if (trgint) { + /* Lower Tx Driving for TRGMII path */ + for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) + mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), + TD_DM_DRVP(8) | TD_DM_DRVN(8)); + + /* Disable MT7530 core and TRGMII Tx clocks */ + core_clear(priv, CORE_TRGMII_GSW_CLK_CG, + REG_GSWCK_EN | REG_TRGMIICK_EN); + + /* Setup the MT7530 TRGMII Tx Clock */ + core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); + core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); + core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); + core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); + core_write(priv, CORE_PLL_GROUP4, + RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | + RG_SYSPLL_BIAS_LPF_EN); + core_write(priv, CORE_PLL_GROUP2, + RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | + RG_SYSPLL_POSDIV(1)); + core_write(priv, CORE_PLL_GROUP7, + RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | + RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); + + /* Enable MT7530 core and TRGMII Tx clocks */ + core_set(priv, CORE_TRGMII_GSW_CLK_CG, + REG_GSWCK_EN | REG_TRGMIICK_EN); + } else { for (i = 0 ; i < NUM_TRGMII_CTRL; i++) mt7530_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_MASK, RD_TAP(16)); + } + return 0; }