From patchwork Thu Mar 9 06:28:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 13166816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 974A1C6FD1F for ; Thu, 9 Mar 2023 06:29:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 69EDA10E79B; Thu, 9 Mar 2023 06:29:54 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2DEDC10E79B; Thu, 9 Mar 2023 06:29:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678343393; x=1709879393; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w8mHYT0gPw9zY7lvjpEG57Gre5RQZ9K6RRjLojOHRHk=; b=C8SJ38FE4iviABJnq8E2bQVfrKdFbovQq9IaxttAFjSQT1R4S4ks/lGI WeYiCkQptSj/yeg3fq1onyWqDUNCWs1P6p2ylS9SoIdUiE2nONj8GMM/M 0ipFAWuRMUSjSK49Jq3JKa9TWP7eY53xkWLc4qml6amcaA1IIlilPr+Th ZmyGlDGVWWaEclvuyr5X9GJcMlLUODExybblMZfcNUi6zdLS2c8voSJNB H2ovjljpPg3FBDeIGNEDO++Ig1cGaiZ6wde07VMZY0/UfcrnxjMlXL598 YvZ4ERXpVmarrWcMxamlTeK9qbK5cRn77r75MsVCua2DXs4F/BbDBW6Ri g==; X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="335070004" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="335070004" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 22:29:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="1006614856" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="1006614856" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.32]) by fmsmga005.fm.intel.com with ESMTP; 08 Mar 2023 22:29:51 -0800 From: Suraj Kandpal To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v3 1/7] drm/dp_helper: Add helper to check DSC support with given o/p format Date: Thu, 9 Mar 2023 11:58:49 +0530 Message-Id: <20230309062855.393087-2-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230309062855.393087-1-suraj.kandpal@intel.com> References: <20230309062855.393087-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ankit Nautiyal Add helper to check if the DP sink supports DSC with the given o/p format. v2: Add documentation for the helper. (Uma Shankar) v3: /** instead of /* (Uma Shankar) Signed-off-by: Ankit Nautiyal Reviewed-by: Uma Shankar --- include/drm/display/drm_dp_helper.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index ab55453f2d2c..533d3ee7fe05 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -194,6 +194,19 @@ drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) DP_DSC_SLICE_WIDTH_MULTIPLIER; } +/** + * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format + * @dsc_dpcd : DSC-capability DPCDs of the sink + * @output_format: output_format which is to be checked + * + * Returns true if the sink supports DSC with the given output_format, false otherwise. + */ +static inline bool +drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) +{ + return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format; +} + /* Forward Error Correction Support on DP 1.4 */ static inline bool drm_dp_sink_supports_fec(const u8 fec_capable) From patchwork Thu Mar 9 06:28:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 13166817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C5DDC64EC4 for ; Thu, 9 Mar 2023 06:30:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 867FB10E79C; Thu, 9 Mar 2023 06:29:57 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id A224B10E79C; Thu, 9 Mar 2023 06:29:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678343394; x=1709879394; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HFkMkKq3vmVgzKCQJuQBbmBSq35D0tFY98BzqMvMW/8=; b=nUKWnYRQeXpgJAXSWVffX8ilZL+8bWanC0DdJdHtYYeb1RqYak4H5Z/u DqEAN9ZdoiJJGd5iFxYp82luApfPAfTF4TtrxXpiekUaBmZARaDdJBlNm 4qmlihFb/CCvPbvAEppVUhM7rJTC4TmhCKyrGoSuFLY3ZPgWBVZxn8NCM oPshqenzHutI1dx9Sktxk8rOCR/0SVDlHnhObttQY0yeEPCBjoSl2DBGp QN8uR1HbU/LAQwYvLKiu6l8wEfg62wDcdLOdmQNsEc+gmmGl/oZyT98JS /pUtoD1uIJmFtVqQoaLxcFgrXZfBVP14ZFFhBCx2E8FIG3S00heyx72kv g==; X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="335070007" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="335070007" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 22:29:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="1006614861" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="1006614861" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.32]) by fmsmga005.fm.intel.com with ESMTP; 08 Mar 2023 22:29:53 -0800 From: Suraj Kandpal To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v3 2/7] drm/i915/dp: Check if DSC supports the given output_format Date: Thu, 9 Mar 2023 11:58:50 +0530 Message-Id: <20230309062855.393087-3-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230309062855.393087-1-suraj.kandpal@intel.com> References: <20230309062855.393087-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Ankit Nautiyal Go with DSC only if the given output_format is supported. v2: Use drm helper to get DSC format support for sink. v3: remove drm_dp_dsc_compute_bpp. Cc: Uma Shankar Signed-off-by: Ankit Nautiyal Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index aee93b0d810e..c725b40e2718 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1492,6 +1492,31 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return drm_dsc_compute_rc_parameters(vdsc_cfg); } +static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, + enum intel_output_format output_format) +{ + u8 sink_dsc_format; + + switch (output_format) { + case INTEL_OUTPUT_FORMAT_RGB: + sink_dsc_format = DP_DSC_RGB; + break; + case INTEL_OUTPUT_FORMAT_YCBCR444: + sink_dsc_format = DP_DSC_YCbCr444; + break; + case INTEL_OUTPUT_FORMAT_YCBCR420: + if (min(intel_dp_source_dsc_version_minor(intel_dp), + intel_dp_sink_dsc_version_minor(intel_dp)) < 2) + return false; + sink_dsc_format = DP_DSC_YCbCr420_Native; + break; + default: + return false; + } + + return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1512,6 +1537,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_supports_dsc(intel_dp, pipe_config)) return -EINVAL; + if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) + return -EINVAL; + if (compute_pipe_bpp) pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); else From patchwork Thu Mar 9 06:28:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 13166818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC13CC61DA4 for ; Thu, 9 Mar 2023 06:30:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0AE5A10E7A0; Thu, 9 Mar 2023 06:30:00 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id AED1810E79C; Thu, 9 Mar 2023 06:29:56 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="1006614869" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.32]) by fmsmga005.fm.intel.com with ESMTP; 08 Mar 2023 22:29:54 -0800 From: Suraj Kandpal To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v3 3/7] drm/i915/dsc: Adding the new registers for DSC Date: Thu, 9 Mar 2023 11:58:51 +0530 Message-Id: <20230309062855.393087-4-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230309062855.393087-1-suraj.kandpal@intel.com> References: <20230309062855.393087-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vandita Kulkarni , ankit.k.nautiyal@intel.com, uma.shankar@intel.com, Suraj Kandpal Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Adding new DSC register which are introducted MTL onwards Signed-off-by: Suraj Kandpal Reviewed-by: Vandita Kulkarni Reviewed-by: Uma Shankar --- .../gpu/drm/i915/display/intel_vdsc_regs.h | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 4fd883463752..b71f00b5c761 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -46,6 +46,32 @@ _ICL_PIPE_DSS_CTL2_PB, \ _ICL_PIPE_DSS_CTL2_PC) +/* MTL Display Stream Compression registers */ +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4 +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4 +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4 +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4 +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \ + _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC) +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \ + _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC) +#define DSC_SL_BPG_OFFSET(offset) ((offset) << 27) + +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8 +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8 +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8 +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8 +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \ + _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC) +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ + _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \ + _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC) +#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16) +#define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0) + /* Icelake Display Stream Compression Registers */ #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) @@ -59,6 +85,8 @@ #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) +#define DSC_NATIVE_422_ENABLE BIT(23) +#define DSC_NATIVE_420_ENABLE BIT(22) #define DSC_ALT_ICH_SEL (1 << 20) #define DSC_VBR_ENABLE (1 << 19) #define DSC_422_ENABLE (1 << 18) From patchwork Thu Mar 9 06:28:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 13166820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 90167C6FD1F for ; Thu, 9 Mar 2023 06:30:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1541910E7A4; Thu, 9 Mar 2023 06:30:03 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1061310E7A0; Thu, 9 Mar 2023 06:29:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678343399; x=1709879399; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vhHJu/nEcsIkYEsEaWRCObo7BFTTKSudU9bM4ugsxhA=; b=k6dJPvN4U9gjRbApWPV6M80ZX1x3f7VUQhqp1q0ex1RJRIkwOHMxn/hQ IVURHw639OVGBfTBEdHY3GZQ1/4gb5jNrVX/j5tdcGzHmDFRilZS4ojhO I6gJg4OCmiPSJ2Wg704IQ0+he7yRG+eBMgwO0IbRYo1AurKFmxDcNGbY3 37lUeL8W3oqFUSoRdMo7eHNQVmxv+b58U9axbfqOoekg2ZK/vreC9Ln8J CVgAy92kCGbk25zK1mDeDIowte9fBy0i2WGjGpiy0uX9mO31REGZLxyUp 3ZE5iA2rjUde8xwb8uywiBA6Y3+EKEQjQeDOLQIdY1oAkIN/+tsza2QuN A==; X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="335070015" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="335070015" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 22:29:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="1006614873" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="1006614873" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.32]) by fmsmga005.fm.intel.com with ESMTP; 08 Mar 2023 22:29:56 -0800 From: Suraj Kandpal To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v3 4/7] drm/i915/dsc: Enable YCbCr420 for VDSC Date: Thu, 9 Mar 2023 11:58:52 +0530 Message-Id: <20230309062855.393087-5-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230309062855.393087-1-suraj.kandpal@intel.com> References: <20230309062855.393087-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vandita Kulkarni , ankit.k.nautiyal@intel.com, uma.shankar@intel.com, Suraj Kandpal Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implementation of VDSC for YCbCr420. Add QP tables for 8,10,12 BPC from rc_tables.h in intel_qp_tables.c (Derived from C-Model, which is given along with DSC1.2a Spec from Vesa) intel_lookup_range_min/max_qp functons need to take into account the output format. Based on that appropriate qp table need to be chosen. Other rc_parameters need to be set where currently values for 444 format is hardcoded in calculate_rc_parameters( ). vdsc_cfg struct needs to be filled with output format information, where these are hardcoded for 444 format. Bspec: 49259 Signed-off-by: Suraj Kandpal Reviewed-by: Vandita Kulkarni Reviewed-by: Uma Shankar --- .../gpu/drm/i915/display/intel_qp_tables.c | 187 ++++++++++++++++-- .../gpu/drm/i915/display/intel_qp_tables.h | 4 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +- 3 files changed, 180 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c index 6f8e4ec5c0fb..6e86c0971d24 100644 --- a/drivers/gpu/drm/i915/display/intel_qp_tables.c +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c @@ -17,6 +17,15 @@ /* from BPP 6 to 36 in steps of 0.5 */ #define RC_RANGE_QP444_12BPC_MAX_NUM_BPP 61 +/* from BPP 6 to 24 in steps of 0.5 */ +#define RC_RANGE_QP420_8BPC_MAX_NUM_BPP 17 + +/* from BPP 6 to 30 in steps of 0.5 */ +#define RC_RANGE_QP420_10BPC_MAX_NUM_BPP 23 + +/* from BPP 6 to 36 in steps of 0.5 */ +#define RC_RANGE_QP420_12BPC_MAX_NUM_BPP 29 + /* * These qp tables are as per the C model * and it has the rows pointing to bpps which increment @@ -283,26 +292,182 @@ static const u8 rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC 11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4 } }; -#define PARAM_TABLE(_minmax, _bpc, _row, _col) do { \ - if (bpc == (_bpc)) \ - return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \ +static const u8 rc_range_minqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = { + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 }, + { 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 }, + { 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0 }, + { 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 0 }, + { 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0 }, + { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1 }, + { 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 1, 1 }, + { 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 2, 2, 1 }, + { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 3, 3, 2, 1 }, + { 9, 8, 8, 7, 7, 7, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 2 }, + { 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3 } +}; + +static const u8 rc_range_maxqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = { + { 4, 4, 3, 3, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 4, 4, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, + { 5, 5, 5, 5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 }, + { 6, 6, 6, 6, 6, 5, 4, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0 }, + { 7, 7, 7, 7, 7, 5, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 0 }, + { 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 2, 2, 2, 1, 1, 0 }, + { 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1 }, + { 8, 8, 8, 8, 8, 7, 6, 5, 4, 4, 4, 3, 3, 2, 2, 2, 1 }, + { 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 }, + { 10, 10, 9, 9, 9, 8, 7, 6, 5, 5, 5, 4, 4, 3, 3, 2, 2 }, + { 10, 10, 10, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 2, 2 }, + { 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2 }, + { 11, 11, 11, 10, 9, 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3, 2 }, + { 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4, 4, 4, 3 }, + { 14, 13, 13, 12, 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4 } +}; + +static const u8 rc_range_minqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = { + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0 }, + { 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0 }, + { 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0 }, + { 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 0 }, + { 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 4, 4, 4, 3, 2, 2, 2, 1, 1, 1, 0 }, + { 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 2, 1, 1 }, + { 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1 }, + { 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 }, + { 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 5, 4, 4, 3, 3, 2, 1 }, + { 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 2, 1 }, + { 13, 12, 12, 11, 11, 11, 11, 11, 11, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4, 3, 3, + 2, 2 }, + { 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 10, 9, 8, 8, 7, 6, 6, 5, + 5, 4, 4 } +}; + +static const u8 rc_range_maxqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = { + { 8, 8, 7, 6, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { 8, 8, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, + { 9, 9, 9, 8, 8, 7, 6, 5, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0 }, + { 10, 10, 10, 9, 9, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 0, + 0 }, + { 11, 11, 11, 10, 10, 8, 7, 6, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1, 1, 1, + 0 }, + { 11, 11, 11, 10, 10, 9, 8, 7, 6, 6, 6, 5, 4, 4, 3, 3, 2, 2, 2, 2, 2, 1, + 1 }, + { 11, 11, 11, 11, 11, 10, 9, 8, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2, + 1 }, + { 12, 12, 12, 12, 12, 11, 10, 9, 8, 8, 8, 7, 6, 5, 5, 4, 3, 3, 3, 2, 2, + 2, 1 }, + { 13, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 3, + 2, 2 }, + { 14, 14, 13, 13, 13, 12, 11, 10, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, + 2, 2 }, + { 14, 14, 14, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4, 4, + 3, 3, 2 }, + { 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4, + 4, 3, 2 }, + { 15, 15, 15, 14, 13, 13, 13, 12, 11, 11, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4, + 4, 3, 2 }, + { 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4, + 4, 3, 3 }, + { 18, 17, 17, 16, 15, 15, 14, 13, 13, 12, 11, 11, 11, 10, 9, 9, 8, 7, 7, + 6, 6, 5, 5 } +}; + +static const u8 rc_range_minqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = { + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0 }, + { 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0 }, + { 9, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0 }, + { 10, 9, 9, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 3, 2, 2, 1, 1, 1, 0, 0, 0, + 0, 0, 0, 0, 0 }, + { 11, 10, 10, 10, 10, 9, 9, 8, 7, 6, 6, 6, 6, 5, 5, 4, 3, 3, 3, 2, 2, 1, + 0, 0, 0, 0, 0, 0, 0 }, + { 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 7, 6, 5, 5, 4, 4, 3, 3, 3, 2, + 1, 1, 0, 0, 0, 0, 0 }, + { 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 7, 6, 5, 5, 5, 5, 4, 3, 3, + 2, 1, 1, 1, 1, 1, 0 }, + { 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 8, 8, 7, 6, 6, 5, 4, 4, + 3, 2, 2, 1, 1, 1, 1, 1 }, + { 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5, + 5, 4, 4, 2, 2, 1, 1, 1, 1 }, + { 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, + 5, 4, 4, 3, 2, 2, 1, 1, 1 }, + { 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, + 6, 5, 4, 3, 3, 2, 2, 1, 1 }, + { 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 11, 10, 10, 9, 8, 8, + 7, 7, 6, 5, 4, 3, 3, 2, 2, 1 }, + { 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8, + 7, 7, 6, 5, 4, 4, 3, 2, 2, 1 }, + { 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 13, 13, 12, 11, 11, 10, 9, 9, 8, + 8, 7, 6, 6, 5, 4, 4, 3, 3, 2 }, + { 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 14, 13, 12, 12, 11, 10, + 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4 } +}; + +static const u8 rc_range_maxqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = { + { 11, 10, 9, 8, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, + 0, 0, 0, 0, 0, 0 }, + { 12, 11, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, + 1, 0, 0, 0, 0, 0, 0 }, + { 13, 12, 12, 11, 11, 10, 9, 8, 7, 6, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, + 1, 0, 0, 0, 0, 0, 0 }, + { 14, 13, 13, 12, 12, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1, + 1, 1, 0, 0, 0, 0, 0 }, + { 15, 14, 14, 13, 13, 11, 10, 9, 8, 7, 7, 7, 7, 6, 6, 5, 4, 4, 4, 3, 3, 2, + 1, 1, 1, 0, 0, 0, 0 }, + { 15, 15, 15, 14, 14, 13, 12, 11, 10, 10, 10, 9, 8, 7, 6, 6, 5, 5, 4, 4, + 4, 3, 2, 2, 1, 1, 0, 0, 0 }, + { 15, 15, 15, 15, 15, 14, 13, 12, 11, 11, 11, 10, 9, 8, 7, 6, 6, 6, 6, 5, + 4, 4, 3, 2, 2, 2, 1, 1, 0 }, + { 16, 16, 16, 16, 16, 15, 14, 13, 12, 12, 12, 11, 10, 9, 9, 8, 7, 7, 6, 5, + 5, 4, 3, 3, 2, 2, 2, 1, 1 }, + { 17, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8, 7, + 6, 6, 5, 5, 3, 3, 2, 2, 1, 1 }, + { 18, 18, 17, 17, 17, 16, 15, 14, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8, + 7, 6, 5, 5, 4, 3, 3, 2, 2, 1 }, + { 18, 18, 18, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 10, 9, 9, 8, + 8, 7, 6, 5, 4, 4, 3, 3, 2, 2 }, + { 19, 19, 18, 18, 17, 17, 16, 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 9, + 9, 8, 8, 7, 6, 5, 4, 4, 3, 3, 2 }, + { 19, 19, 19, 18, 17, 17, 17, 16, 15, 15, 14, 13, 13, 12, 12, 11, 10, 9, + 9, 8, 8, 7, 6, 5, 5, 4, 3, 3, 2 }, + { 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, + 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3 }, + { 22, 21, 21, 20, 19, 19, 18, 17, 17, 16, 15, 15, 15, 14, 13, 13, 12, 11, + 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5 } +}; + +#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420) do { \ + if (bpc == (_bpc)) { \ + if (_is_420) \ + return rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \ + else \ + return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \ + } \ } while (0) -u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i) +u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420) { - PARAM_TABLE(min, 8, buf_i, bpp_i); - PARAM_TABLE(min, 10, buf_i, bpp_i); - PARAM_TABLE(min, 12, buf_i, bpp_i); + PARAM_TABLE(min, 8, buf_i, bpp_i, is_420); + PARAM_TABLE(min, 10, buf_i, bpp_i, is_420); + PARAM_TABLE(min, 12, buf_i, bpp_i, is_420); MISSING_CASE(bpc); return 0; } -u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i) +u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420) { - PARAM_TABLE(max, 8, buf_i, bpp_i); - PARAM_TABLE(max, 10, buf_i, bpp_i); - PARAM_TABLE(max, 12, buf_i, bpp_i); + PARAM_TABLE(max, 8, buf_i, bpp_i, is_420); + PARAM_TABLE(max, 10, buf_i, bpp_i, is_420); + PARAM_TABLE(max, 12, buf_i, bpp_i, is_420); MISSING_CASE(bpc); return 0; diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h b/drivers/gpu/drm/i915/display/intel_qp_tables.h index 9fb3c36bd7c6..a9ff9ca29938 100644 --- a/drivers/gpu/drm/i915/display/intel_qp_tables.h +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h @@ -8,7 +8,7 @@ #include -u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i); -u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i); +u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420); +u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420); #endif diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 09b32ffdc552..6fa70f3c074b 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -423,9 +423,9 @@ calculate_rc_params(struct rc_parameters *rc, for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) { /* Read range_minqp and range_max_qp from qp tables */ rc->rc_range_params[buf_i].range_min_qp = - intel_lookup_range_min_qp(bpc, buf_i, bpp_i); + intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420); rc->rc_range_params[buf_i].range_max_qp = - intel_lookup_range_max_qp(bpc, buf_i, bpp_i); + intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420); /* Calculate range_bgp_offset */ if (bpp <= 6) { From patchwork Thu Mar 9 06:28:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 13166819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 783E3C64EC4 for ; Thu, 9 Mar 2023 06:30:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B790B10E7A3; Thu, 9 Mar 2023 06:30:02 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3310F10E7A1; Thu, 9 Mar 2023 06:30:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678343401; x=1709879401; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Oo2JwWyi+mXPMoir8dyQqKX5Htz3O+LrsNVUXPaw6aY=; b=LgkjDVI3myOm+GI05OF324hLeopNOMlQxbAR1xvj3y1Uo8NioBFnan47 qvUetjaimSsGDoaxod/VgbuzHI1Xu3HOjhguWGmvvOG45Eam7FCq2vwcW Ombr7Uxz0P5SJUR91mAOCUnAebdUQk85Jb2SzsZAqF4ZRYMJdNIeSWPSE cHd5LXKmI8aFTzi+kTtMJskF7ThzLrcv3x7aUZjywevf6hY6edl+vHDSn yiUQbtBDzYzMGx8+g9XYIVnPtqTruv1nI4Q3A+M1bAoRfNHShQL/IHmyL 86hMUvbQeCv34Q5TajnE26r1z5aCCtp+m8/HUETp5m/NqusQ2o3gKdn/8 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="335070019" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="335070019" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 22:30:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="1006614888" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="1006614888" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.32]) by fmsmga005.fm.intel.com with ESMTP; 08 Mar 2023 22:29:59 -0800 From: Suraj Kandpal To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v3 5/7] drm/i915/dsc: Fill in native_420 field Date: Thu, 9 Mar 2023 11:58:53 +0530 Message-Id: <20230309062855.393087-6-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230309062855.393087-1-suraj.kandpal@intel.com> References: <20230309062855.393087-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, Suraj Kandpal Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Now that we have laid the groundwork for YUV420 Enablement we fill up native_420 field in vdsc_cfg and add appropriate checks wherever required. ---v2 -adding native_422 field as 0 [Vandita] -filling in second_line_bpg_offset, second_line_offset_adj and nsl_bpg_offset in vds_cfg when native_420 is true ---v3 -adding display version check to solve igt issue --v7 -remove is_pipe_dsc check as its always true for D14 [Jani] --v10 -keep sink capability check [Jani] -move from !(x == y || w == z) to x !=y && w != z [Jani] --v11 -avoid native_420 computation if not gen14 [Uma] --v12 -fix state mismatch issue of compressed_bpp Cc: Uma Shankar Cc: Jani Nikula Signed-off-by: Suraj Kandpal Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/icl_dsi.c | 2 - drivers/gpu/drm/i915/display/intel_dp.c | 16 +++- drivers/gpu/drm/i915/display/intel_vdsc.c | 98 ++++++++++++++++++++--- 3 files changed, 100 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 50dcaa895854..dde0269a2778 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1552,8 +1552,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, if (crtc_state->dsc.slice_count > 1) crtc_state->dsc.dsc_split = true; - vdsc_cfg->convert_rgb = true; - /* FIXME: initialize from VBT */ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c725b40e2718..b40bb5fd9abb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1467,9 +1467,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, vdsc_cfg->dsc_version_minor = min(intel_dp_source_dsc_version_minor(intel_dp), intel_dp_sink_dsc_version_minor(intel_dp)); - - vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & - DP_DSC_RGB; + if (vdsc_cfg->convert_rgb) + vdsc_cfg->convert_rgb = + intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & + DP_DSC_RGB; line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); if (!line_buf_depth) { @@ -1587,6 +1588,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->bigjoiner_pipes, pipe_bpp, timeslots); + /* + * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum + * supported PPS value can be 63.9375 and with the further + * mention that bpp should be programmed double the target bpp + * restricting our target bpp to be 31.9375 at max + */ + if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4); + if (!dsc_max_output_bpp) { drm_dbg_kms(&dev_priv->drm, "Compressed BPP not supported\n"); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 6fa70f3c074b..0388efb49b92 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -461,14 +461,50 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, pipe_config->dsc.slice_count); - - /* Gen 11 does not support YCbCr */ + /* + * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0 + * else 1 + */ + vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 && + pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444; + + if (DISPLAY_VER(dev_priv) >= 14 && + pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + vdsc_cfg->native_420 = true; + /* We do not support YcBCr422 as of now */ + vdsc_cfg->native_422 = false; vdsc_cfg->simple_422 = false; /* Gen 11 does not support VBR */ vdsc_cfg->vbr_enable = false; /* Gen 11 only supports integral values of bpp */ vdsc_cfg->bits_per_pixel = compressed_bpp << 4; + + /* + * According to DSC 1.2 specs in Section 4.1 if native_420 is set: + * -We need to double the current bpp. + * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice + * height < 8. + * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma + * preservation in second line. + * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded + * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11 + * fractional bits. + */ + if (vdsc_cfg->native_420) { + vdsc_cfg->bits_per_pixel <<= 1; + + if (vdsc_cfg->slice_height >= 8) + vdsc_cfg->second_line_bpg_offset = 12; + else + vdsc_cfg->second_line_bpg_offset = + 2 * (vdsc_cfg->slice_height - 1); + + vdsc_cfg->second_line_offset_adj = 512; + vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11, + vdsc_cfg->slice_height - 1); + } + vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { @@ -595,8 +631,13 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) DSC_VER_MIN_SHIFT | vdsc_cfg->bits_per_component << DSC_BPC_SHIFT | vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT; - if (vdsc_cfg->dsc_version_minor == 2) + if (vdsc_cfg->dsc_version_minor == 2) { pps_val |= DSC_ALT_ICH_SEL; + if (vdsc_cfg->native_420) + pps_val |= DSC_NATIVE_420_ENABLE; + if (vdsc_cfg->native_422) + pps_val |= DSC_NATIVE_422_ENABLE; + } if (vdsc_cfg->block_pred_enable) pps_val |= DSC_BLOCK_PREDICTION; if (vdsc_cfg->convert_rgb) @@ -907,6 +948,33 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) pps_val); } + if (DISPLAY_VER(dev_priv) >= 14) { + /* Populate PICTURE_PARAMETER_SET_17 registers */ + pps_val = 0; + pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); + drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val); + intel_de_write(dev_priv, + MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe), + pps_val); + if (crtc_state->dsc.dsc_split) + intel_de_write(dev_priv, + MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe), + pps_val); + + /* Populate PICTURE_PARAMETER_SET_18 registers */ + pps_val = 0; + pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) | + DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj); + drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val); + intel_de_write(dev_priv, + MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe), + pps_val); + if (crtc_state->dsc.dsc_split) + intel_de_write(dev_priv, + MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe), + pps_val); + } + /* Populate the RC_BUF_THRESH registers */ memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword)); for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { @@ -1181,7 +1249,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; - u32 dss_ctl1, dss_ctl2, val; + u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0; if (!intel_dsc_source_support(crtc_state)) return; @@ -1204,13 +1272,21 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) /* FIXME: add more state readout as needed */ - /* PPS1 */ - if (!is_pipe_dsc(crtc, cpu_transcoder)) - val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); - else - val = intel_de_read(dev_priv, - ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); - vdsc_cfg->bits_per_pixel = val; + /* PPS0 & PPS1 */ + if (!is_pipe_dsc(crtc, cpu_transcoder)) { + pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); + } else { + pps0 = intel_de_read(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)); + pps1 = intel_de_read(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); + } + + vdsc_cfg->bits_per_pixel = pps1; + + if (pps0 & DSC_NATIVE_420_ENABLE) + vdsc_cfg->bits_per_pixel >>= 1; + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; out: intel_display_power_put(dev_priv, power_domain, wakeref); From patchwork Thu Mar 9 06:28:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 13166822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7649FC6FD1F for ; Thu, 9 Mar 2023 06:30:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 01E6110E7A9; Thu, 9 Mar 2023 06:30:09 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id E4AE710E7A1; Thu, 9 Mar 2023 06:30:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678343402; x=1709879402; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MCoQ5mO8mv/007JiaAnPAJTu/1Fe3GE2q5m/tq9zwpY=; b=XgwWmWvvozzxMgAIuSZDFQkEMl9ATesmwTtX/pm13vX8bu9awQ3jynU7 L3Qb47obxdW43XELw5xs5FZC6cwe2LbFvHpXN52o6A76C+rg1zJJsj8T3 Tva0bzaIXNiL1I7km8q3WAtKh0EG5TeGGZ6h4fcpXZCwisw9EtLopOM7v L+wlMxx7hn+8XLYGbyx7p7+fbME2NKB4AvxA9OvNud/WwMOEIZlOJ6Fb1 fUCF9KI3jmFh69fcugn0TdyHIzOUYtHEQSaQ63Y9CmCLmZCWPmSfvwSxw Gq7A+H0ZQmUwmw/lw2sFcpaFQ1ixPoRT1AMGjHxuAJ/gGmpbrYu+IObwY Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="335070031" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="335070031" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 22:30:02 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="1006614911" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="1006614911" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.32]) by fmsmga005.fm.intel.com with ESMTP; 08 Mar 2023 22:30:01 -0800 From: Suraj Kandpal To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v3 6/7] drm/i915/vdsc: Check slice design requirement Date: Thu, 9 Mar 2023 11:58:54 +0530 Message-Id: <20230309062855.393087-7-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230309062855.393087-1-suraj.kandpal@intel.com> References: <20230309062855.393087-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, Suraj Kandpal Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add function to check if slice design requirements are being met as defined in Bspec: 49259 in the section Slice Design Requirement --v7 -remove full bspec link [Jani] -rename intel_dsc_check_slice_design_req to intel_dsc_slice_dimensions_valid [Jani] --v8 -fix condition to check if slice width and height are of two -fix minimum pixel in slice condition --v10 -condition should be < rather then >= [Uma] Cc: Uma Shankar Signed-off-by: Suraj Kandpal Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 0388efb49b92..8e787c13d26d 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -448,6 +448,29 @@ calculate_rc_params(struct rc_parameters *rc, } } +static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config, + struct drm_dsc_config *vdsc_cfg) +{ + if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB || + pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { + if (vdsc_cfg->slice_height > 4095) + return -EINVAL; + if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000) + return -EINVAL; + } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { + if (vdsc_cfg->slice_width % 2) + return -EINVAL; + if (vdsc_cfg->slice_height % 2) + return -EINVAL; + if (vdsc_cfg->slice_height > 4094) + return -EINVAL; + if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000) + return -EINVAL; + } + + return 0; +} + int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) { struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); @@ -456,11 +479,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) u16 compressed_bpp = pipe_config->dsc.compressed_bpp; const struct rc_parameters *rc_params; struct rc_parameters *rc = NULL; + int err; u8 i = 0; vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, pipe_config->dsc.slice_count); + + err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg); + + if (err) { + drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n"); + return err; + } + /* * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0 * else 1 From patchwork Thu Mar 9 06:28:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 13166821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E694DC742A7 for ; Thu, 9 Mar 2023 06:30:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 41FD410E7A7; Thu, 9 Mar 2023 06:30:08 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0E0AE10E7A7; Thu, 9 Mar 2023 06:30:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678343405; x=1709879405; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wcUiNKCHLCVu4jOpkf5PLXYNbVFpWZxxXTB7L/9KxXs=; b=QB72cEXHB6kO8oE+Lx2V7SgMgxu4HXPNW6hNPpqKVgBOJT+NQYikwwnE zzxbqyBKRD4PpiLfSVYqA9OrawGLubahBitO+Aa/5XUkBMIsTCMezPTsk kSmn/j6j8HvhgiLL2+e8ZyXSL/ZLW4gSCUd8U/I+4O6t63uAdEw4kn2N6 YdTGrwtIGThXvAdsTt6JUfBxbTgmpSLOJnvY+n99FeOcnn+flLs1Pq68s KzvycTSo7zaQ5d3+xz/6gDz/8hLoCbRDURa36xz6nixlo33dl+/mABwGY dM67Qa31a6ILlpAWh8Nsp0svYyVokH8dx6mr68TA9qwj3HHqxU68FCGcE Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="335070039" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="335070039" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2023 22:30:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10643"; a="1006614924" X-IronPort-AV: E=Sophos;i="5.98,245,1673942400"; d="scan'208";a="1006614924" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.32]) by fmsmga005.fm.intel.com with ESMTP; 08 Mar 2023 22:30:02 -0800 From: Suraj Kandpal To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v3 7/7] drm/i915/dsc: Add debugfs entry to validate DSC output formats Date: Thu, 9 Mar 2023 11:58:55 +0530 Message-Id: <20230309062855.393087-8-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230309062855.393087-1-suraj.kandpal@intel.com> References: <20230309062855.393087-1-suraj.kandpal@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com, Swati Sharma Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Swati Sharma DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444). Also, new debugfs entry is created to enforce output format. This is required because of our driver policy. For ex. if a mode is supported in both RGB and YCbCr420 output formats by the sink, our policy is to try RGB first and fall back to YCbCr420, if mode cannot be shown using RGB. So, to test other output formats like YCbCr420 or YCbCr444, we need a debugfs entry (force_dsc_output_format) to force this output format. v2: -Func name changed to intel_output_format_name() (Jani N) -Return forced o/p format from intel_dp_output_format() (Jani N) v3: -output_format_str[] to remain static (Jani N) Signed-off-by: Swati Sharma Reviewed-by: Uma Shankar --- .../drm/i915/display/intel_crtc_state_dump.c | 4 +- .../drm/i915/display/intel_crtc_state_dump.h | 2 + .../drm/i915/display/intel_display_debugfs.c | 78 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 4 + 5 files changed, 87 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 766633566fd6..54c8adc0702e 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -123,7 +123,7 @@ static const char * const output_format_str[] = { [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", }; -static const char *output_formats(enum intel_output_format format) +const char *intel_output_format_name(enum intel_output_format format) { if (format >= ARRAY_SIZE(output_format_str)) return "invalid"; @@ -181,7 +181,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, "active: %s, output_types: %s (0x%x), output format: %s\n", str_yes_no(pipe_config->hw.active), buf, pipe_config->output_types, - output_formats(pipe_config->output_format)); + intel_output_format_name(pipe_config->output_format)); drm_dbg_kms(&i915->drm, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h index 9399c35b7e5e..780f3f1190d7 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h @@ -8,9 +8,11 @@ struct intel_crtc_state; struct intel_atomic_state; +enum intel_output_format; void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state, struct intel_atomic_state *state, const char *context); +const char *intel_output_format_name(enum intel_output_format format); #endif /* __INTEL_CRTC_STATE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 1e654ddd0815..fc2905574e5b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -12,6 +12,7 @@ #include "i915_irq.h" #include "i915_reg.h" #include "intel_de.h" +#include "intel_crtc_state_dump.h" #include "intel_display_debugfs.h" #include "intel_display_power.h" #include "intel_display_power_well.h" @@ -1535,6 +1536,13 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) str_yes_no(crtc_state->dsc.compression_enable)); seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))); + seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n", + str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, + DP_DSC_RGB)), + str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, + DP_DSC_YCbCr420_Native)), + str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, + DP_DSC_YCbCr444))); seq_printf(m, "Force_DSC_Enable: %s\n", str_yes_no(intel_dp->force_dsc_en)); if (!intel_dp_is_edp(intel_dp)) @@ -1660,6 +1668,73 @@ static const struct file_operations i915_dsc_bpc_fops = { .write = i915_dsc_bpc_write }; +static int i915_dsc_output_format_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + struct drm_device *dev = connector->dev; + struct drm_crtc *crtc; + struct intel_crtc_state *crtc_state; + struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); + int ret; + + if (!encoder) + return -ENODEV; + + ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex); + if (ret) + return ret; + + crtc = connector->state->crtc; + if (connector->status != connector_status_connected || !crtc) { + ret = -ENODEV; + goto out; + } + + crtc_state = to_intel_crtc_state(crtc->state); + seq_printf(m, "DSC_Output_Format: %s\n", + intel_output_format_name(crtc_state->output_format)); + +out: drm_modeset_unlock(&dev->mode_config.connection_mutex); + + return ret; +} + +static ssize_t i915_dsc_output_format_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct drm_connector *connector = + ((struct seq_file *)file->private_data)->private; + struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + int dsc_output_format = 0; + int ret; + + ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format); + if (ret < 0) + return ret; + + intel_dp->force_dsc_output_format = dsc_output_format; + *offp += len; + + return len; +} + +static int i915_dsc_output_format_open(struct inode *inode, + struct file *file) +{ + return single_open(file, i915_dsc_output_format_show, inode->i_private); +} + +static const struct file_operations i915_dsc_output_format_fops = { + .owner = THIS_MODULE, + .open = i915_dsc_output_format_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = i915_dsc_output_format_write +}; + /* * Returns the Current CRTC's bpc. * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc @@ -1731,6 +1806,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector) debugfs_create_file("i915_dsc_bpc", 0644, root, connector, &i915_dsc_bpc_fops); + + debugfs_create_file("i915_dsc_output_format", 0644, root, + connector, &i915_dsc_output_format_fops); } if (connector->connector_type == DRM_MODE_CONNECTOR_DSI || diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index c32bfba06ca1..59c0340d102b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1735,6 +1735,7 @@ struct intel_dp { /* Display stream compression testing */ bool force_dsc_en; + int force_dsc_output_format; int force_dsc_bpc; bool hobl_failed; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b40bb5fd9abb..cdfec559d423 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -76,6 +76,7 @@ #include "intel_tc.h" #include "intel_vdsc.h" #include "intel_vrr.h" +#include "intel_crtc_state_dump.h" /* DP DSC throughput values used for slice count calculations KPixels/s */ #define DP_DSC_PEAK_PIXEL_RATE 2720000 @@ -810,6 +811,9 @@ intel_dp_output_format(struct intel_connector *connector, { struct intel_dp *intel_dp = intel_attached_dp(connector); + if (intel_dp->force_dsc_output_format) + return intel_dp->force_dsc_output_format; + if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output) return INTEL_OUTPUT_FORMAT_RGB;