From patchwork Thu Mar 9 15:49:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13167753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D15DAC6FD19 for ; Thu, 9 Mar 2023 15:50:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229476AbjCIPuG (ORCPT ); Thu, 9 Mar 2023 10:50:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230365AbjCIPuE (ORCPT ); Thu, 9 Mar 2023 10:50:04 -0500 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9DB8F289F for ; Thu, 9 Mar 2023 07:50:01 -0800 (PST) Received: by mail-ed1-x532.google.com with SMTP id k10so8703993edk.13 for ; Thu, 09 Mar 2023 07:50:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678377000; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=5hDw377R+3WveEHHISt0O+B0HNboj//Q7JnZS8WCHQk=; b=xFOeIBq/oenmpZgse9ypMIySBxHojJR+priTRx4ns8SVP7D39nQ6GWvynrSpoOZ5R4 HsKcT908aKbyY+mWmwZRF55bt35KR1yKcW6++DQauTZLH6LO5XQhIsgcSLObp6gQi6hm a3C1Phim93FONjhxlLRQF8vnGyv5kEKRKyqqR4+hFR4Sgk3etvYPV7Q2wgf+quQeWcXe hxC2Ucy6M/FWI8NXM4FSsbi4SSEtTGBa+kYiuwRsDKUcCqugBKPlLx+sYmJ/K9BI1x47 dyALpaqG6NJ6cPLoOigP4lVhPtGskb7OAMXxdEwptXITcYfMfg+ad/t27LGV1Lpt5K5d pncA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678377000; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5hDw377R+3WveEHHISt0O+B0HNboj//Q7JnZS8WCHQk=; b=pvU6H33icl36fgBJYAtWp8Su8pfrGMoX9Rbs4plxWP1G07s5PykdFoLj/jQaxr8OZE 1elU+lcJ36cdKVR7MwCUKjR5yv3a8h10dhYSxjmngFms3QLroNdR5F6Z+eLGHIhxvnbt YE7jBOG1q0nJYrcmd+UMLnG7M5bjipvFf7ZnavARGzQCZ/azkNBTxSIrhVPweqFPtIp+ 2eAlFN/o+91zzsPtD7hs1sb4OalosKQBo2Ik3q062KhTiEuPfXCXVWbyUvGWQiwUX3wr wtKUez3VAPq99AKR9ELual+y7HZjuAehjaDn9UtEAp4d0sdTG182u1d8EWjSicmA6HTt qNXg== X-Gm-Message-State: AO0yUKVASs2NVduFTLb5Ebgt2VUTeR0pSi8l9+Tf/0QQPOLBuNE2KZ6b gZT1dTkM2KJu620LaRHMJGVAUQ== X-Google-Smtp-Source: AK7set+ShI583mjtu+t07MzMAYJ711BR0WtRErkuBFVx28IQ6paK6KKAKh5e4gkiWKvsgXlvtUbldw== X-Received: by 2002:a17:906:a1c5:b0:906:3373:cfe9 with SMTP id bx5-20020a170906a1c500b009063373cfe9mr21147766ejb.10.1678377000203; Thu, 09 Mar 2023 07:50:00 -0800 (PST) Received: from krzk-bin.. ([2a02:810d:15c0:828:7ee2:e73e:802e:45c1]) by smtp.gmail.com with ESMTPSA id h17-20020a17090634d100b008ee5356801dsm8981683ejb.187.2023.03.09.07.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 07:49:59 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Linus Walleij , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , stable@vger.kernel.org Subject: [PATCH 1/4] pinctrl: qcom: lpass-lpi: set output value before enabling output Date: Thu, 9 Mar 2023 16:49:46 +0100 Message-Id: <20230309154949.658380-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As per Hardware Programming Guide, when configuring pin as output, set the pin value before setting output-enable (OE). Similar approach is in main SoC TLMM pin controller. Cc: Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 87920257bb73..27fc8b671954 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -221,6 +221,15 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, } } + /* + * As per Hardware Programming Guide, when configuring pin as output, + * set the pin value before setting output-enable (OE). + */ + if (output_enabled) { + val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); + lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); + } + val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); @@ -230,11 +239,6 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); - if (output_enabled) { - val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); - lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); - } - return 0; } From patchwork Thu Mar 9 15:49:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13167754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 212B5C74A44 for ; Thu, 9 Mar 2023 15:50:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230365AbjCIPuI (ORCPT ); Thu, 9 Mar 2023 10:50:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229817AbjCIPuF (ORCPT ); Thu, 9 Mar 2023 10:50:05 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B157F24AA for ; Thu, 9 Mar 2023 07:50:02 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id da10so8873135edb.3 for ; Thu, 09 Mar 2023 07:50:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678377001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3doP5Qh80iui4dCoQV94mzeJJ78H6cWhfnuThkzdLnc=; b=bzSGWbK3XBNYMI/l6mAcjcVv8J0CJHGL6ZJ6DKroEYmhmhX1kbIoMNUDAD5+NIfBqB 7aLZkpAMosJgKma9DuE/ecGfNTU7AaiDqOBGCgTEAhnr9gHZRHQiLsiDM5G7AaJHvUPx tANvC8NhYBgv95Oy+azKdLYh+nKWlN8u+ujD23DQLDoIJaP6oJjLouv3elNzYUPn1Yf0 rWCqbnX+iXOr9SC/UYKFr1rDtiwz8+KdljOWu30t3wPTfSuig37kijy16EwyjeUGGRxR kHHh/KSVziq8kKc1kMDVnToa2Px4pxaM2Jqwa+HjLFHOnByN6/C9AZ7MeLvWD/t0Rb2Q NgsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678377001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3doP5Qh80iui4dCoQV94mzeJJ78H6cWhfnuThkzdLnc=; b=xkpmQjNbyf/BTraMoCZSlyY7qfJoX822Q4PF/sh8WRelcaVzbW2JgM0ihhv0oSVEPP 9qyYOb6L1HBtJCbvF8U17umA6qdt+2gMN1KBGZ8JfAHwzDYzSdvxR6Cfll2vuB6AfdP/ RjP4RM08TcSW6HPNM5IyQAtaYo/yRDL4PXS86rM+/NMI8dhYNmvqe5Te6vAUuQnpQYP5 yBXQlb9wGdaTI/ProJFys9UiEgAOvW4+aN5GyzwZVdwKuMA5lITadMPK6vLxe5jyLyPA r+wxjUxzATQgg3+nUYUGi0PeNjBKQu0Isg4XPaOr/QTQbWCZAG9WoMobSchHXZakG5It xjnw== X-Gm-Message-State: AO0yUKXDXigNrYlhrczejo8IeZYRibcGoiaGkARJvwscdM8/vM2uDMfn wyormCbQhRqSsTup4IzgbXqNuw== X-Google-Smtp-Source: AK7set96sRuCK2f6npm0e0rHwbfQ7f6lUjGN8ui1Ctxa0KmEiZ6XhRhwH1Ua80UeRdtXrmrvaB6Fcg== X-Received: by 2002:a17:906:dac9:b0:8aa:c090:a9ef with SMTP id xi9-20020a170906dac900b008aac090a9efmr28883479ejb.55.1678377001056; Thu, 09 Mar 2023 07:50:01 -0800 (PST) Received: from krzk-bin.. ([2a02:810d:15c0:828:7ee2:e73e:802e:45c1]) by smtp.gmail.com with ESMTPSA id h17-20020a17090634d100b008ee5356801dsm8981683ejb.187.2023.03.09.07.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 07:50:00 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Linus Walleij , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/4] pinctrl: qcom: lpass-lpi: use consistent name for "group" variable Date: Thu, 9 Mar 2023 16:49:47 +0100 Message-Id: <20230309154949.658380-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230309154949.658380-1-krzysztof.kozlowski@linaro.org> References: <20230309154949.658380-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The set_mux callback in SoC TLMM driver (pinctrl-msm.c) uses "group", not "group_num" for the number of the pin group. Other places of lpass-lpi also use "group", so let's be consistent for code readability. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 27fc8b671954..bd32556d75a5 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -84,10 +84,10 @@ static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev, } static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, - unsigned int group_num) + unsigned int group) { struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct lpi_pingroup *g = &pctrl->data->groups[group_num]; + const struct lpi_pingroup *g = &pctrl->data->groups[group]; u32 val; int i, pin = g->pin; From patchwork Thu Mar 9 15:49:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13167755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAA66C6FD19 for ; Thu, 9 Mar 2023 15:50:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231555AbjCIPuK (ORCPT ); Thu, 9 Mar 2023 10:50:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231490AbjCIPuG (ORCPT ); Thu, 9 Mar 2023 10:50:06 -0500 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76180F28B9 for ; Thu, 9 Mar 2023 07:50:03 -0800 (PST) Received: by mail-ed1-x52a.google.com with SMTP id a25so8989095edb.0 for ; Thu, 09 Mar 2023 07:50:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678377002; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BcQHpyuRa8telS2z61Wu0G0Mj91kmKtPrkTuDj0nJzc=; b=bKQLs3Cao3Qr+7xgoWm8wqxFjz9Pk8Dra+NzlXub+7IgfcIT46ZANSF/ssMPKeZmVF Y0SZ50fRLK37ycP/Pp8cACIt6eN7h9vwfK/5ktc1q3FFkz/dlTAdqcrRowJcqI1WcKm8 1ChtptJDOMl02FVZws7evuh0c9B3b7EZFLCYNnqQZW2JWMh7GfvA/IbH75xawmvOLTec TvllrrTVu2/2+7J9yLatuG/npcvN0AhQ+y9x/BcIALMBVyouugrHH7kHXBYNUlpG7aOY tTIauB6SOtwQEKsgX93/sQe3FLQ2BDiUUp7121+UuyRaecyRIBNZ4hkEFRyShevppIDk ZC8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678377002; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BcQHpyuRa8telS2z61Wu0G0Mj91kmKtPrkTuDj0nJzc=; b=pDZlT7udvlkaTa7dyovQ3y5RkxxckQ9haFRDcko3iY5/ws9LYQZRYN6gdGAIcqJ8SE 4UyhpsR2HeFBubzHb78uL3OMuRnRtOMC26MjGKNzk+GRTaH0VxixDwGxeLN8TVgjeRuZ ctS6wb2kowk+sueUR5FHeeHvMRrjWCEj2Kk+SScf36vivnYgKEE6hC9fMVkVGcTPWcZ+ dm9E6ys1Ds0ZFV1E7dAExQ8pdHn1Rxfcf5rT5uwzRT7qYphuamb69RCLtL2/DR3CjjJy VrEBAj7+huVFBWa+DlvEet6Dn1t6BPP3W2jbJOr3HYlcRkqgnCSHx1l+2trNXvz7B1fa G7vg== X-Gm-Message-State: AO0yUKW31uQOyK44Ne4FBglslZO3rp7Avq398q6btWcQsFlBIuaZ/MmU PKcjsoH6SJfCznEymKTcYoFOoA== X-Google-Smtp-Source: AK7set92zrvqbxYZohYM0hs5HGDmbaIHAgjbHr4KGcYksm+XO3vASQwOfpAgPYu1+j5QhqH6lLogUQ== X-Received: by 2002:a17:907:3e8f:b0:8b1:779c:a8b1 with SMTP id hs15-20020a1709073e8f00b008b1779ca8b1mr28652540ejc.5.1678377001945; Thu, 09 Mar 2023 07:50:01 -0800 (PST) Received: from krzk-bin.. ([2a02:810d:15c0:828:7ee2:e73e:802e:45c1]) by smtp.gmail.com with ESMTPSA id h17-20020a17090634d100b008ee5356801dsm8981683ejb.187.2023.03.09.07.50.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 07:50:01 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Linus Walleij , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 3/4] pinctrl: qcom: lpass-lpi: allow glitch-free output GPIO Date: Thu, 9 Mar 2023 16:49:48 +0100 Message-Id: <20230309154949.658380-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230309154949.658380-1-krzysztof.kozlowski@linaro.org> References: <20230309154949.658380-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When choosing GPIO function for pins, use the same glitch-free method as main TLMM pinctrl-msm.c driver in msm_pinmux_set_mux(). This replicates the commit d21f4b7ffc22 ("pinctrl: qcom: Avoid glitching lines when we first mux to output") to LPASS pin controller with same justification. Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 28 ++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index bd32556d75a5..fdb6585a9234 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -19,6 +19,8 @@ #include "pinctrl-lpass-lpi.h" +#define MAX_NR_GPIO 23 +#define GPIO_FUNC 0 #define MAX_LPI_NUM_CLKS 2 struct lpi_pinctrl { @@ -30,6 +32,7 @@ struct lpi_pinctrl { char __iomem *slew_base; struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; struct mutex slew_access_lock; + DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); const struct lpi_pinctrl_variant_data *data; }; @@ -100,6 +103,28 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, return -EINVAL; val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); + + /* + * If this is the first time muxing to GPIO and the direction is + * output, make sure that we're not going to be glitching the pin + * by reading the current state of the pin and setting it as the + * output. + */ + if (i == GPIO_FUNC && (val & LPI_GPIO_OE_MASK) && + !test_and_set_bit(group, pctrl->ever_gpio)) { + u32 io_val = lpi_gpio_read(pctrl, group, LPI_GPIO_VALUE_REG); + + if (io_val & LPI_GPIO_VALUE_IN_MASK) { + if (!(io_val & LPI_GPIO_VALUE_OUT_MASK)) + lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, + io_val | LPI_GPIO_VALUE_OUT_MASK); + } else { + if (io_val & LPI_GPIO_VALUE_OUT_MASK) + lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, + io_val & ~LPI_GPIO_VALUE_OUT_MASK); + } + } + u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); @@ -394,6 +419,9 @@ int lpi_pinctrl_probe(struct platform_device *pdev) if (!data) return -EINVAL; + if (WARN_ON(data->npins > MAX_NR_GPIO)) + return -EINVAL; + pctrl->data = data; pctrl->dev = &pdev->dev; From patchwork Thu Mar 9 15:49:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13167756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C929C74A44 for ; Thu, 9 Mar 2023 15:50:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229817AbjCIPuK (ORCPT ); Thu, 9 Mar 2023 10:50:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231532AbjCIPuH (ORCPT ); Thu, 9 Mar 2023 10:50:07 -0500 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD1DCF28BC for ; Thu, 9 Mar 2023 07:50:04 -0800 (PST) Received: by mail-ed1-x534.google.com with SMTP id a25so8989385edb.0 for ; Thu, 09 Mar 2023 07:50:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678377003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SgRFCt619WmiOOy/KiaJocmKNsNdPTYaRqkITCznBlQ=; b=VclA2Usv5TOQL2tjYEaywOVcbjTRbt5QTlUyua2Pq3vHwT0lIaQM/mNyIOV0TOQI52 IYZaDZIyxI6bfTtSPdkATbzV/vwSKO9WATOYBvvvdfBxINsdOu+9jhVMxgvRVNPKD0DU pBh7wCzQvILtnKTs0D5k9mFn19e2w1H/RLRe+LCuwUq6sN2BP3U82PEETdzvkuDRBatn VC+R8O5s2DjeFay6ztM3X3xLToPRkxTWqQ0+XJHTbOR7nzGi/HLb4CO5t5PSCVMdBptW FJkBfzgxbwDDqL9/oGrik3qqY2WROaHcBKDMY35wBfluGRt2mtPv+Dsin4sC8lt2iHvQ NOig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678377003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SgRFCt619WmiOOy/KiaJocmKNsNdPTYaRqkITCznBlQ=; b=2MdFCpfIA4aiNwhDixLy2slahbIbXo66KZvJbelIxQvea7pxVBteyCUAdCl0KcmPXt fb2XodvPksMxVBIQS9dOaEmRrGy1Og/diMdAmFWo/JOWfVsFnPXPHy5orHFhXzh929u5 Dp2iylv66ZU7SXthoxp6ouGNij7Ju+h8Wpt+fMF9Lon8CUh7i1QmD8MVfDykzgEG2Drz ZS/2CTWI3dEkSWSb+wcgMrL7/v/7LVTnFrGNZKoDmGgm3GQnwldqDY4Cpu0hFgZqC7iV vyVWClgQtbC5jHaek37X2LnufBi62Eikp4AyOB9xqOCfL2V84qe/ASFXCIGVt4H9dX47 qn5A== X-Gm-Message-State: AO0yUKWB/utsKGo36IIO/J7X6Sy8F8hH4oYDiCBAhNHD0aqQR7cD4hDn 3cR6+WmmuFeZDaXhWJ23JKznCQ== X-Google-Smtp-Source: AK7set9OUMyp7/zfcn1xB/Hxk4VIhd+uwK0b4bIxnhLcxo97/DDeed+1+0rKVoHM3A7Jm4MeebJXTg== X-Received: by 2002:a17:906:d28c:b0:8e5:88ca:ebac with SMTP id ay12-20020a170906d28c00b008e588caebacmr22319782ejb.40.1678377003285; Thu, 09 Mar 2023 07:50:03 -0800 (PST) Received: from krzk-bin.. ([2a02:810d:15c0:828:7ee2:e73e:802e:45c1]) by smtp.gmail.com with ESMTPSA id h17-20020a17090634d100b008ee5356801dsm8981683ejb.187.2023.03.09.07.50.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 07:50:03 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Linus Walleij , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 4/4] pinctrl: qcom: sm8550-lpass-lpi: allow GPIO function Date: Thu, 9 Mar 2023 16:49:49 +0100 Message-Id: <20230309154949.658380-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230309154949.658380-1-krzysztof.kozlowski@linaro.org> References: <20230309154949.658380-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org All LPASS pins have basic GPIO function and most of the code is ready for that. Add missing glue pieces to allow LPASS pins to work as GPIO, which is going to be used on MTP8550 and QRD8550 boards. Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c index c2bdd936d27f..db1a46fee9c6 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -102,6 +102,13 @@ static const struct pinctrl_pin_desc sm8550_lpi_pins[] = { PINCTRL_PIN(22, "gpio22"), }; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", +}; + static const char * const dmic1_clk_groups[] = { "gpio6" }; static const char * const dmic1_data_groups[] = { "gpio7" }; static const char * const dmic2_clk_groups[] = { "gpio8" }; @@ -168,6 +175,7 @@ static const struct lpi_pingroup sm8550_groups[] = { }; static const struct lpi_function sm8550_functions[] = { + LPI_FUNCTION(gpio), LPI_FUNCTION(dmic1_clk), LPI_FUNCTION(dmic1_data), LPI_FUNCTION(dmic2_clk),