From patchwork Thu Mar 9 21:04:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Green X-Patchwork-Id: 13168327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF5E2C61DA4 for ; Thu, 9 Mar 2023 21:05:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FvVBHvYo5PCvL4M3dFLxsMPnjamk2TTn3KNNyLW5LSk=; b=ZzDpwYZFSa5okA8D9oHa/TCijf tlviNbS7WdI3GjkrSeYiau2DGQxgb/axMzGnz49+WWn1ChNrt8yUOlpG2gWxSDLvSzE9MiceIcnX0 SdGNHwiSs+UirV2u3jAFs14RVLqROspvjwpOzrGkziI+xh6/BKpyya0ZEqusMHpEBXslwwlm51+5C iTv1NctWJiZ08SXsx3inw20ggLybIkF/aAj8n6boZbLjBxOCyD9zrByBIMzFnHcJhs07Uy4ETV7bB 9TSxYRAJoeRGfacioYUeJB3xI5lYYFm+pdgsPiZob/TvMRmLSRuxXVbKxyV4RpzLbtbX1BWk5easi Ub5dA7Yg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1paNSF-00BvOe-HT; Thu, 09 Mar 2023 21:05:39 +0000 Received: from mail-qt1-x82a.google.com ([2607:f8b0:4864:20::82a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1paNS9-00BvLf-Lk for linux-mediatek@lists.infradead.org; Thu, 09 Mar 2023 21:05:37 +0000 Received: by mail-qt1-x82a.google.com with SMTP id y10so3612672qtj.2 for ; Thu, 09 Mar 2023 13:05:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1678395932; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FvVBHvYo5PCvL4M3dFLxsMPnjamk2TTn3KNNyLW5LSk=; b=XWCPwUQGxJMWuwLvyWPN20b7x+5F9L8NgqXR1YlWFwn9BFTLvR+6z7FoEytMc4WcGb xC0qmknL7itNZpujB5p5fAme/f8rzPOkMg2djObe1nfb/m7PFJAirfIDSQbsc2QA26wr xofBWKsau0aTZyRSDLdUahS8oKI9GZnSd/C1w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678395932; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FvVBHvYo5PCvL4M3dFLxsMPnjamk2TTn3KNNyLW5LSk=; b=GSu8a8vcKQIAtcHZEtfxX3zY7zE0pbT/pXKfDNvGl8r6MahSETozZe9zLLqFg3oQrj TIfL7C7YpBHvI0M4+WR5FnjoH7MBheU9A3PEYdJ0H6WN/Yx954muR9TbTm0gkKviN0Fe 7ooEGX0sfUCL4F2GpJkrdyFBrIaXnlddfqrlK0g7DRbg698pxCO8ScRjsPHoH2Uw9IR7 OZTlHrvbs3k2ti6uk6qtuvdkSgtOHDywX+lk7mzEnJ+xOx1tG8eubteSAgu8QSWWGAHW fVx864ODpQVvt3n/NuAXPF3Ftq46upatVc9p125cBixfsC4P8N97Gnlhc8716gnPe8Gi bWaA== X-Gm-Message-State: AO0yUKV7YiLMTIyYt6sKp33WyfIF/MbkD6ZIStOiLRKWBf7voqC1NfB+ 9IioXciOb6U6LuWO96Laidi+1JliG95WhgW+LIPoiQ== X-Google-Smtp-Source: AK7set+yTjyyrP7pSXYGgS3TOnfnhe8YnQQ/L6dG5pAPlJmihwJcNEaLZqoMrWZzeMVh0n1eTgXjrQ== X-Received: by 2002:ac8:5c13:0:b0:3c0:3b79:9fb0 with SMTP id i19-20020ac85c13000000b003c03b799fb0mr18754512qti.47.1678395931928; Thu, 09 Mar 2023 13:05:31 -0800 (PST) Received: from greenjustin3.nyc.corp.google.com ([2620:0:1003:314:a575:2520:a8e1:989d]) by smtp.gmail.com with ESMTPSA id 69-20020a370548000000b007426f115a4esm14302375qkf.129.2023.03.09.13.05.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 13:05:31 -0800 (PST) From: Justin Green To: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org Cc: angelogioacchino.delregno@collabora.com, jason-jh.lin@mediatek.com, justin.yeh@mediatek.com, wenst@chromium.org, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, daniel@ffwll.ch, daniel@fooishbar.org, greenjustin@chromium.org Subject: [PATCH v8 1/3] drm/mediatek: Refactor pixel format logic Date: Thu, 9 Mar 2023 16:04:14 -0500 Message-Id: <20230309210416.1167020-2-greenjustin@chromium.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230309210416.1167020-1-greenjustin@chromium.org> References: <20230309210416.1167020-1-greenjustin@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230309_130533_768789_C29BBDBF X-CRM114-Status: GOOD ( 16.95 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add an DDP component interface for querying pixel format support and move list of supported pixel formats into DDP components instead of mtk_drm_plane.c Tested by running Chrome on an MT8195. Signed-off-by: Justin Green Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 ++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 44 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 38 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 20 ++++++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.c | 24 ++++------- drivers/gpu/drm/mediatek/mtk_drm_plane.h | 3 +- 8 files changed, 123 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 33e61a136bbc..0df6a06defb8 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -96,6 +96,8 @@ void mtk_ovl_register_vblank_cb(struct device *dev, void mtk_ovl_unregister_vblank_cb(struct device *dev); void mtk_ovl_enable_vblank(struct device *dev); void mtk_ovl_disable_vblank(struct device *dev); +const u32 *mtk_ovl_get_formats(struct device *dev); +size_t mtk_ovl_get_num_formats(struct device *dev); void mtk_rdma_bypass_shadow(struct device *dev); int mtk_rdma_clk_enable(struct device *dev); @@ -115,6 +117,8 @@ void mtk_rdma_register_vblank_cb(struct device *dev, void mtk_rdma_unregister_vblank_cb(struct device *dev); void mtk_rdma_enable_vblank(struct device *dev); void mtk_rdma_disable_vblank(struct device *dev); +const u32 *mtk_rdma_get_formats(struct device *dev); +size_t mtk_rdma_get_num_formats(struct device *dev); int mtk_mdp_rdma_clk_enable(struct device *dev); void mtk_mdp_rdma_clk_disable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 84daeaffab6a..8743c8047dc9 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -66,6 +66,20 @@ #define OVL_CON_VIRT_FLIP BIT(9) #define OVL_CON_HORZ_FLIP BIT(10) +static const u32 mt8173_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -73,6 +87,8 @@ struct mtk_disp_ovl_data { bool fmt_rgb565_is_0; bool smi_id_en; bool supports_afbc; + const u32 *formats; + size_t num_formats; }; /* @@ -138,6 +154,20 @@ void mtk_ovl_disable_vblank(struct device *dev) writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); } +const u32 *mtk_ovl_get_formats(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + return ovl->data->formats; +} + +size_t mtk_ovl_get_num_formats(struct device *dev) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + + return ovl->data->num_formats; +} + int mtk_ovl_clk_enable(struct device *dev) { struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); @@ -495,6 +525,8 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { .gmc_bits = 8, .layer_nr = 4, .fmt_rgb565_is_0 = false, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { @@ -502,6 +534,8 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { .gmc_bits = 8, .layer_nr = 4, .fmt_rgb565_is_0 = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { @@ -509,6 +543,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { .gmc_bits = 10, .layer_nr = 4, .fmt_rgb565_is_0 = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { @@ -516,6 +552,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { .gmc_bits = 10, .layer_nr = 2, .fmt_rgb565_is_0 = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { @@ -524,6 +562,8 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { .layer_nr = 4, .fmt_rgb565_is_0 = true, .smi_id_en = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { @@ -532,6 +572,8 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { .layer_nr = 2, .fmt_rgb565_is_0 = true, .smi_id_en = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { @@ -541,6 +583,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { .fmt_rgb565_is_0 = true, .smi_id_en = true, .supports_afbc = true, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 0ec2e4049e07..cf92df845160 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -54,8 +54,24 @@ #define RDMA_MEM_GMC 0x40402020 +static const u32 mt8173_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + struct mtk_disp_rdma_data { unsigned int fifo_size; + const u32 *formats; + size_t num_formats; }; /* @@ -126,6 +142,20 @@ void mtk_rdma_disable_vblank(struct device *dev) rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0); } +const u32 *mtk_rdma_get_formats(struct device *dev) +{ + struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); + + return rdma->data->formats; +} + +size_t mtk_rdma_get_num_formats(struct device *dev) +{ + struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); + + return rdma->data->num_formats; +} + int mtk_rdma_clk_enable(struct device *dev) { struct mtk_disp_rdma *rdma = dev_get_drvdata(dev); @@ -360,18 +390,26 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = { .fifo_size = SZ_4K, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { .fifo_size = SZ_8K, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .fifo_size = 5 * SZ_1K, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = { .fifo_size = 1920, + .formats = mt8173_formats, + .num_formats = ARRAY_SIZE(mt8173_formats), }; static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 112615817dcb..2ba01c484228 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -856,7 +856,9 @@ static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, BIT(pipe), mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, num_planes), - mtk_ddp_comp_supported_rotations(comp)); + mtk_ddp_comp_supported_rotations(comp), + mtk_ddp_comp_get_formats(comp), + mtk_ddp_comp_get_num_formats(comp)); if (ret) return ret; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 6b6d5335c834..4a4c1928f83d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -359,6 +359,8 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .layer_config = mtk_ovl_layer_config, .bgclr_in_on = mtk_ovl_bgclr_in_on, .bgclr_in_off = mtk_ovl_bgclr_in_off, + .get_formats = mtk_ovl_get_formats, + .get_num_formats = mtk_ovl_get_num_formats, }; static const struct mtk_ddp_comp_funcs ddp_postmask = { @@ -381,6 +383,8 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = { .disable_vblank = mtk_rdma_disable_vblank, .layer_nr = mtk_rdma_layer_nr, .layer_config = mtk_rdma_layer_config, + .get_formats = mtk_rdma_get_formats, + .get_num_formats = mtk_rdma_get_num_formats, }; static const struct mtk_ddp_comp_funcs ddp_ufoe = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 2d0052c23dcb..7f2e638cfdc2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -71,6 +71,8 @@ struct mtk_ddp_comp_funcs { void (*bgclr_in_off)(struct device *dev); void (*ctm_set)(struct device *dev, struct drm_crtc_state *state); + const u32 *(*get_formats)(struct device *dev); + size_t (*get_num_formats)(struct device *dev); }; struct mtk_ddp_comp { @@ -203,6 +205,24 @@ static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, comp->funcs->ctm_set(comp->dev, state); } +static inline +const u32 *mtk_ddp_comp_get_formats(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->get_formats) + return comp->funcs->get_formats(comp->dev); + + return NULL; +} + +static inline +size_t mtk_ddp_comp_get_num_formats(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->get_num_formats) + return comp->funcs->get_num_formats(comp->dev); + + return 0; +} + int mtk_ddp_comp_get_id(struct device_node *node, enum mtk_ddp_comp_type comp_type); unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index d54fbf34b000..31f9420aff6f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -19,20 +19,6 @@ #include "mtk_drm_gem.h" #include "mtk_drm_plane.h" -static const u32 formats[] = { - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, - DRM_FORMAT_BGRX8888, - DRM_FORMAT_BGRA8888, - DRM_FORMAT_ABGR8888, - DRM_FORMAT_XBGR8888, - DRM_FORMAT_RGB888, - DRM_FORMAT_BGR888, - DRM_FORMAT_RGB565, - DRM_FORMAT_UYVY, - DRM_FORMAT_YUYV, -}; - static const u64 modifiers[] = { DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | @@ -315,13 +301,19 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = { int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations) + unsigned int supported_rotations, const u32 *formats, + size_t num_formats) { int err; + if (!formats || !num_formats) { + DRM_ERROR("no formats for plane\n"); + return -EINVAL; + } + err = drm_universal_plane_init(dev, plane, possible_crtcs, &mtk_plane_funcs, formats, - ARRAY_SIZE(formats), modifiers, type, NULL); + num_formats, modifiers, type, NULL); if (err) { DRM_ERROR("failed to initialize plane\n"); return err; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h b/drivers/gpu/drm/mediatek/mtk_drm_plane.h index 8f39011cdbfc..99aff7da0831 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h @@ -48,6 +48,7 @@ to_mtk_plane_state(struct drm_plane_state *state) int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, unsigned long possible_crtcs, enum drm_plane_type type, - unsigned int supported_rotations); + unsigned int supported_rotations, const u32 *formats, + size_t num_formats); #endif From patchwork Thu Mar 9 21:06:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Green X-Patchwork-Id: 13168351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4645EC61DA4 for ; Thu, 9 Mar 2023 21:45:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=SIaFfAz3P9BLs/IYvg/JH0rGRkNx7pnu6ZolwnmHv7w=; b=gqv8EyqGKtn8IWv6R7HUHHhGkY YIGeWPmpkSTlg4WxoQApEOq4N85IHKiXsjEJFjV0hP1p+vvWdW5JQs4AwvFPxfzPRZikVzO/qj30V +lz+6n4esngyGOJ9UvXY1lcGNB8YpuyqMWo1RF1SlyQXfdXvPZXBthEyiNJioCgimA7kO7jZSJ8Lr mwEWQfnqKRXmC+BJcYJ9TwYl8mLy6cU1anYwHuiN14bNwOAAtEseBn6XrCANlfnY9JV6MaP1//zye KozSP00LGN0oB8ADDgVkld2SLRL+WELaha1WP5f1Rvk5Gmwe5BKBzpfdSSSZqedj9qAzunMlZDFXA kpGgijjg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1paO4n-00C3qn-LI; Thu, 09 Mar 2023 21:45:29 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1paO4m-00C3q8-M4 for linux-mediatek@bombadil.infradead.org; Thu, 09 Mar 2023 21:45:28 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:MIME-Version :Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:In-Reply-To:References; bh=SIaFfAz3P9BLs/IYvg/JH0rGRkNx7pnu6ZolwnmHv7w=; b=J7kKecwgJGOgUd9zkjZqjZjmGw 7Cn9mJ3q3lzZTVgugH2JwIl1JMQwqOvJSrH5pogIgZmm9Fu+f76J0/myJZD7f0Q5oVqlbwMA8CGdK uY/CWj5JC5+YbJ0CmUE49jJwQXn41qQDd+wGvJnvKXGA0BEptgdsWIlS5Xa7dvDLYB50Qh48hMkuL loT99jlPciRexgC3poA/PmCiJzocKUSx4SIe7EGH/C36aDPrd0sVdp+j9VZQ/nhWnzmkG7cQk4//7 6q8v22iksOBRRfESC56arsCLRFCygt9BpROLx4Mzuf1GKMdJGSwjq2E4biLDtNYardBXH/2zELU/A CAvFUmpw==; Received: from mail-qt1-x829.google.com ([2607:f8b0:4864:20::829]) by desiato.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1paNT5-000F9F-1n for linux-mediatek@lists.infradead.org; Thu, 09 Mar 2023 21:06:33 +0000 Received: by mail-qt1-x829.google.com with SMTP id l18so3621095qtp.1 for ; Thu, 09 Mar 2023 13:06:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1678395989; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=SIaFfAz3P9BLs/IYvg/JH0rGRkNx7pnu6ZolwnmHv7w=; b=ekWyusYFBpL12RMJ+xvCmW/23PN0mVoUwpkWDXSBy7uTYlczExZGwqhsw10ZVnQ8un PYn6kas62DojHAnFoBGAOkxcdlbOPOB5n0THClLiUdWo7X73bttjjc2jfk3s2H636rX+ 8iwrsmG/RynX1J0PDPXWwDBGQAERmZ5+0UwjU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678395989; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=SIaFfAz3P9BLs/IYvg/JH0rGRkNx7pnu6ZolwnmHv7w=; b=tdiOdhEy0CD7PWCe0y2Diuo2USnyR6eoOeKHe6KCh7jNHyCZvIhjl0Pdo0mmlfI4xS ejp15lAWnNI0Ijejf3xHho1FV39hzSMxXPTAIphdy+YBZnCT2CZkebE624UwMY95EH+e cL+8Hb/VaVfYckAfyRtv8I4nWC2Bnhp5Auk+MDlbcR0/Rxz4Hr+oJ0eFQvORv0tK273C cXQRghvp3N4UtCCCRg2yiBK9CNhjeGAGY3s2OgvLvCZ8n7HdColYJrsbgr2Yp1pocroQ Qz13iepD2mj5Qqwuvtts73Q8r3jJFL74pWaeOcje3pRdpNWKJPKyhu8KVuMZrHSIIbYD wMVA== X-Gm-Message-State: AO0yUKV7ZeCVTd+Xk/Bw7ushnozU6SFL+5qUAQFFQFERPFc/RSlc7rkm oK+PH8F+oslGSqVXTMlvGpqbqtfHC8SHz22DpyyEOw== X-Google-Smtp-Source: AK7set9+cW2dY4lRlZ2wjs/dFqUlUz4X6cE4Ahn/kwSWdAA3QSe5aG9VDxtlu7wjRKI3PG1mzqCYSg== X-Received: by 2002:a05:622a:1991:b0:3b9:bc8c:c20f with SMTP id u17-20020a05622a199100b003b9bc8cc20fmr49172335qtc.26.1678395988941; Thu, 09 Mar 2023 13:06:28 -0800 (PST) Received: from greenjustin3.nyc.corp.google.com ([2620:0:1003:314:a575:2520:a8e1:989d]) by smtp.gmail.com with ESMTPSA id r7-20020ac85c87000000b003b9bc00c2f1sm14289316qta.94.2023.03.09.13.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 13:06:28 -0800 (PST) From: Justin Green To: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org Cc: angelogioacchino.delregno@collabora.com, jason-jh.lin@mediatek.com, justin.yeh@mediatek.com, wenst@chromium.org, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, daniel@ffwll.ch, daniel@fooishbar.org, greenjustin@chromium.org Subject: [PATCH v8 2/3] drm/mediatek: Add support for AR30 and BA30 overlays Date: Thu, 9 Mar 2023 16:06:23 -0500 Message-Id: <20230309210623.1167567-1-greenjustin@chromium.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230309_210631_860119_6459918D X-CRM114-Status: GOOD ( 15.95 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Add the ability for the Mediatek DRM driver to control the bit depth register. If the DTS indicates the device supports 10-bit overlays and the current format has a fourcc of AR30, BA30, or RA30, we set the bit depth register to 10 bit. The next patch in the series actually enables 10-bit overlays for MT8195 devices, but this current patch should be a no-op. This patch was tested by simply running Chrome on an MT8195 and looking for regressions. Signed-off-by: Justin Green Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 8743c8047dc9..a6255e847104 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -41,6 +41,7 @@ #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 +#define DISP_REG_OVL_CLRFMT_EXT 0x02D0 #define DISP_REG_OVL_ADDR_MT8173 0x0f40 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) @@ -61,6 +62,10 @@ 0 : OVL_CON_CLRFMT_RGB) #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ OVL_CON_CLRFMT_RGB : 0) +#define OVL_CON_CLRFMT_BIT_DEPTH_MASK(ovl) (0xFF << 4 * (ovl)) +#define OVL_CON_CLRFMT_BIT_DEPTH(depth, ovl) (depth << 4 * (ovl)) +#define OVL_CON_CLRFMT_8_BIT 0x00 +#define OVL_CON_CLRFMT_10_BIT 0x01 #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff #define OVL_CON_VIRT_FLIP BIT(9) @@ -89,6 +94,7 @@ struct mtk_disp_ovl_data { bool supports_afbc; const u32 *formats; size_t num_formats; + bool supports_clrfmt_ext; }; /* @@ -218,6 +224,30 @@ static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx)); } +static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format, + struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ovl *ovl = dev_get_drvdata(dev); + unsigned int reg; + unsigned int bit_depth = OVL_CON_CLRFMT_8_BIT; + + if (!ovl->data->supports_clrfmt_ext) + return; + + reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); + reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); + + if (format == DRM_FORMAT_RGBA1010102 || + format == DRM_FORMAT_BGRA1010102 || + format == DRM_FORMAT_ARGB2101010) + bit_depth = OVL_CON_CLRFMT_10_BIT; + + reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); + + mtk_ddp_write(cmdq_pkt, reg, &ovl->cmdq_reg, + ovl->regs, DISP_REG_OVL_CLRFMT_EXT); +} + void mtk_ovl_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -332,9 +362,11 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) return OVL_CON_CLRFMT_ARGB8888; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRA1010102: return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ARGB2101010: return OVL_CON_CLRFMT_RGBA8888; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: @@ -418,6 +450,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx)); } + mtk_ovl_set_bit_depth(dev, idx, fmt, cmdq_pkt); mtk_ovl_layer_on(dev, idx, cmdq_pkt); } From patchwork Thu Mar 9 21:04:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Green X-Patchwork-Id: 13168326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32507C74A4B for ; Thu, 9 Mar 2023 21:05:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=zQruPEvUWXea5iv6fg4nOA01GAuR/ZB8cLPDfAhHg6M=; b=G4qK6N2YrmXJuAYHELTUlbvLOk 6DsKT3Vcg7XlW4XJk03L+e2grCzY0OyDXZXaO8tXkpKGqBvvS7P+Av3/keicc8LkFLSXL7RBK8dgI FUm4i/HLoamuB1Ta9Wtmvjg36Q5XhtwCP/enrHE1CnBnG192bo95IWOrZk4LULk5pTDqRNBykV6MO ClR95ALUmA0ABAtH7QPW5Q9pwiS/mHja0/U8ZUvaQKD29kfHi3xYf0abO/+zhqKFoQBneFp2RtSO5 9XZM7qJ+q4oUAht09goS1PFq6IhVGmS2Xq1GhD5Y0ClDfbwt23jdmyAgZtmjihzO3iQbxXjaAd4xd dTWTk01w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1paNSG-00BvOy-9D; Thu, 09 Mar 2023 21:05:40 +0000 Received: from mail-qt1-x832.google.com ([2607:f8b0:4864:20::832]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1paNSC-00BvMy-0F for linux-mediatek@lists.infradead.org; Thu, 09 Mar 2023 21:05:37 +0000 Received: by mail-qt1-x832.google.com with SMTP id l13so3605983qtv.3 for ; Thu, 09 Mar 2023 13:05:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1678395934; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zQruPEvUWXea5iv6fg4nOA01GAuR/ZB8cLPDfAhHg6M=; b=Ps6exi3xpI87CzQUY4hXNPGVsjZaFoqg4HGL8a1MxAqCqKlL1H8+jHtFD2GpTj36e+ rpmphds1pfv7T/WkSa8vwmH48RssfA7nSoRFejaypkRswaUN/+PtXflJ//zhRv3Zgp9t cqOaLThEboUnygyl80BCIcIaFtgsn3DGskeYA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678395934; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zQruPEvUWXea5iv6fg4nOA01GAuR/ZB8cLPDfAhHg6M=; b=GiMMk7xuMTjG8NnPXtnsJc5PJHpGg8j4gABIyd43JKb1ugScd2JdRzKYGg3l4pT3zn WliTUl+zdAtjOAJ05dnRXRAeOWkQJNidpMFYZZAQzgX4K6bvPeRxO8q9zWsksPaLvEQ/ cM/YE0baDs6zr9eX40IsikmOlNpxrELxHcJ54Px5KDsNxPKSHfmEdqjr0ucPy8pyo2Xq bWPcShT5pR2bODLSCbzmYHJh2rXEbNWFa0vOO9nWt3APRgoQywMmc8XHVznzZBcblgyJ FyCfMHm8GxCQ5Q+6Aw9grR+kanMcVcwrR6lEX4krIhpsE4Ifp760Jqd2XpCkCzNiBr9J ddNA== X-Gm-Message-State: AO0yUKXbH0BsPqMMu7pB6glPGYi+lje4z+vbLSv+fK4WUMJTRk0IAhm1 rXwNUJySjdv48gkiOdOPKaLQFv4VB1nJVySB53FCBw== X-Google-Smtp-Source: AK7set+TqWj6nJuKc1WVAKlRbKRPSQEHg026dY/owgOMx8qMZrSMaVkii4FshfhymFINPelDj02TzQ== X-Received: by 2002:ac8:7f4a:0:b0:3bf:dae3:bde2 with SMTP id g10-20020ac87f4a000000b003bfdae3bde2mr41004683qtk.36.1678395933876; Thu, 09 Mar 2023 13:05:33 -0800 (PST) Received: from greenjustin3.nyc.corp.google.com ([2620:0:1003:314:a575:2520:a8e1:989d]) by smtp.gmail.com with ESMTPSA id 69-20020a370548000000b007426f115a4esm14302375qkf.129.2023.03.09.13.05.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 13:05:33 -0800 (PST) From: Justin Green To: linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org Cc: angelogioacchino.delregno@collabora.com, jason-jh.lin@mediatek.com, justin.yeh@mediatek.com, wenst@chromium.org, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, daniel@ffwll.ch, daniel@fooishbar.org, greenjustin@chromium.org Subject: [PATCH v8 3/3] drm/mediatek: Enable AR30 and BA30 overlays on MT8195 Date: Thu, 9 Mar 2023 16:04:16 -0500 Message-Id: <20230309210416.1167020-4-greenjustin@chromium.org> X-Mailer: git-send-email 2.40.0.rc1.284.g88254d51c5-goog In-Reply-To: <20230309210416.1167020-1-greenjustin@chromium.org> References: <20230309210416.1167020-1-greenjustin@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230309_130536_111034_F0696868 X-CRM114-Status: GOOD ( 12.01 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Modify the overlay driver data for MT8195 to enable bit depth control and enable support for AR30 and BA30 framebuffer formats. This patch in combination with the previous two patches in the series will allow MT8195 devices to scanout AR30 and BA30 framebuffers. Tested using "modetest -P" on an MT8195 device. The test pattern displays correctly for both AR30 and BA30 formats. Signed-off-by: Justin Green Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index a6255e847104..7d26f7055751 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -85,6 +85,22 @@ static const u32 mt8173_formats[] = { DRM_FORMAT_YUYV, }; +static const u32 mt8195_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_BGRX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRA1010102, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, +}; + struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -616,8 +632,9 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { .fmt_rgb565_is_0 = true, .smi_id_en = true, .supports_afbc = true, - .formats = mt8173_formats, - .num_formats = ARRAY_SIZE(mt8173_formats), + .formats = mt8195_formats, + .num_formats = ARRAY_SIZE(mt8195_formats), + .supports_clrfmt_ext = true, }; static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {