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Fri, 10 Mar 2023 17:37:14 +0000 From: Joey Gouly To: , Mark Rutland CC: , Joey Gouly Subject: [PATCH v1 1/2] aarch64: enable access to TCR2_ELx Date: Fri, 10 Mar 2023 17:36:56 +0000 Message-ID: <20230310173657.57228-1-joey.gouly@arm.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT042:EE_|DU0PR08MB8496:EE_|DBAEUR03FT050:EE_|PAXPR08MB7468:EE_ X-MS-Office365-Filtering-Correlation-Id: 026f2863-1991-4ee1-f0ae-08db218e1ba0 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: +byVmP1iKC8g07b+f1Ijun78sxcoI+cSpR8PwqcDwQB4NdFtAx8VfIBsZQtA4hkFEDEQJEN7LULJhav/Z1FPgvg8GJRaDIDfCmddq/Z9t2t/kLdUILBcZeEpqaGTRVvLSp+cqzW2N5DV/lt8LM2FOUWoUu7X/GNruBV1IsaHzAv7CD0r21RubbghSep02iztsvp6POgNI70E3CR7FB8lqv4zPeIY8tvVCCD8+ZIJEFcJ8w1GFIjFgqzrusUBPEqmjDDhhHF73Vk2WmrT/+odU0tgo7dtzm06lDTSkEJT8zmxxelrTH3PvJcJShae00FmjNXMMxCz79tlCMEQNcl+dH54XrCH8QoUsKgZk5UnI1QLRzXOeGmd2COM/TfJphmYhq58yBFnItEDJixk5xJQk3LSb/W2tyxgMZZbw5Y7k34Kozyz+DlK3aoKDt8Jyov0sZPJ6reUn8fbQXfrcvK19ZlhuVJUCEIRKnGxNYcLut12EkwcWgaZJbQJcrjxuo7gJAsm9eVA6TXjMjK+QdiI13PHtjSlxCjIGBFMjXIHmUJZgrq5T9hM9zUtYXzIL5fayaF1B0CLA2RCcWLwooQMK1mC0sgBCwhwOvG9GoeMzF+fzEZxWGrGGNHqcyhnMxZnUCvFNzBJfrU7GF+nCoAcEKhVJ3LNn+K749hO43Pj4qZEziIi3vaSQtFdKzpqAc03oVmKxJ0iw4DUGLD+OGtNcEDt5/C3wdtHIUc7DhghLYs= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(396003)(376002)(136003)(346002)(39860400002)(451199018)(36840700001)(46966006)(40470700004)(82310400005)(82740400003)(36860700001)(83380400001)(426003)(47076005)(36756003)(6636002)(40480700001)(110136005)(478600001)(54906003)(81166007)(316002)(356005)(336012)(8936002)(40460700003)(41300700001)(7696005)(2616005)(6666004)(26005)(186003)(1076003)(5660300002)(44832011)(70586007)(8676002)(2906002)(86362001)(4326008)(70206006)(36900700001);DIR:OUT;SFP:1101; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow access the TCR2_ELx register which provides extended translation controls similar to TCR_ELx. Signed-off-by: Joey Gouly --- arch/aarch64/include/asm/cpu.h | 5 +++++ arch/aarch64/init.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 89a8f78..3686e08 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -51,6 +51,7 @@ #define SCR_EL3_TME BIT(34) #define SCR_EL3_HXEn BIT(38) #define SCR_EL3_EnTP2 BIT(41) +#define SCR_EL3_TCR2EN BIT(43) #define HCR_EL2_RES1 BIT(1) @@ -73,6 +74,8 @@ #define ID_AA64MMFR1_EL1_HCX BITS(43, 40) +#define ID_AA64MMFR3_EL1_TCRX BITS(4, 0) + #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) #define ID_AA64PFR0_EL1_SVE BITS(35, 32) @@ -122,6 +125,8 @@ #define ID_AA64ISAR2_EL1 s3_0_c0_c6_2 +#define ID_AA64MMFR3_EL1 s3_0_c0_c7_3 + #define SCTLR_EL1_CP15BEN (1 << 5) #ifdef KERNEL_32 diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index 471e234..f004e41 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -64,6 +64,9 @@ void cpu_init_el3(void) if (mrs_field(ID_AA64MMFR1_EL1, HCX)) scr |= SCR_EL3_HXEn; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow lower ELs to access the registers associated with the Permission Indirection Extension. Signed-off-by: Joey Gouly --- arch/aarch64/include/asm/cpu.h | 2 ++ arch/aarch64/init.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 3686e08..fe732dc 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -52,6 +52,7 @@ #define SCR_EL3_HXEn BIT(38) #define SCR_EL3_EnTP2 BIT(41) #define SCR_EL3_TCR2EN BIT(43) +#define SCR_EL3_PIEN BIT(45) #define HCR_EL2_RES1 BIT(1) @@ -75,6 +76,7 @@ #define ID_AA64MMFR1_EL1_HCX BITS(43, 40) #define ID_AA64MMFR3_EL1_TCRX BITS(4, 0) +#define ID_AA64MMFR3_EL1_S1PIE BITS(11, 8) #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index f004e41..0fd7535 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -67,6 +67,9 @@ void cpu_init_el3(void) if (mrs_field(ID_AA64MMFR3_EL1, TCRX)) scr |= SCR_EL3_TCR2EN; + if (mrs_field(ID_AA64MMFR3_EL1, S1PIE)) + scr |= SCR_EL3_PIEN; + if (mrs_field(ID_AA64PFR1_EL1, MTE) >= 2) scr |= SCR_EL3_ATA;