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[46.138.144.249]) by smtp.gmail.com with ESMTPSA id u14-20020ac2518e000000b004db250355b3sm712408lfi.138.2023.03.12.11.04.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 11:04:42 -0700 (PDT) Message-ID: <640e143a.c20a0220.39070.1ae1@mx.google.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 20:58:50 +0300 Subject: [PATCH v5 1/3] dt-bindings: exynos-dw-mshc-common: add exynos7885 variants To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. Add two new compatible strings, "samsung,exynos7885-dw-mshc" and "samsung,exynos7885-dw-mshc-smu" respectively, to denote exynos7885 boards that need this quirk. But it's very possible that all "samsung,exynos7-dw-mshc" boards are actually affected. --- .../devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml index fdaa18481..3eebaed2c 100644 --- a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -22,6 +22,8 @@ properties: - samsung,exynos5420-dw-mshc-smu - samsung,exynos7-dw-mshc - samsung,exynos7-dw-mshc-smu + - samsung,exynos7885-dw-mshc + - samsung,exynos7885-dw-mshc-smu - axis,artpec8-dw-mshc reg: From patchwork Sun Mar 12 17:58:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Lisov X-Patchwork-Id: 13171738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 654B2C6FD1C for ; Sun, 12 Mar 2023 18:27:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232200AbjCLS1g (ORCPT ); Sun, 12 Mar 2023 14:27:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231494AbjCLS1T (ORCPT ); Sun, 12 Mar 2023 14:27:19 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CCAD580F3 for ; Sun, 12 Mar 2023 11:22:07 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id g10so11292077eda.1 for ; Sun, 12 Mar 2023 11:22:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678645235; h=cc:to:subject:date:from:message-id:from:to:cc:subject:date :message-id:reply-to; bh=R/ZxX3DwmCtqhIm3cqoC0hxQvGcxZ6dvB//gAmJzTdM=; b=lOYslAiYEfZGRFQGrUbKr8JOXtUQuFV+hLzrlo8oWxM+0tkPZFsCVUUxJsq2TiYbmO iMhkf4ZD2sh7ptbMLfBCpCeP7i1ze+hMOOuor9IoOV8rk9xXYdrNFlcWHUsgD2AO5yXM PSFQQyXChuyx9DmyoDngZwZ0mGMe4hKGE54F9ScT8gPgmQZLSLVQUyC5SlsY7TVwRABh zIwkY9e6Pq18+2aDs4I508Wbt9+cYxjVIpSLVHkgWwHNVTo3T5L50vdbIzojSsUkh3hv NRpVZj+A09TfYNjiM5tymAol+k9Dpw+fk//mStN8ECbhAipxc9h2LbZyb8GQsnI4siWV xL1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678645235; h=cc:to:subject:date:from:message-id:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R/ZxX3DwmCtqhIm3cqoC0hxQvGcxZ6dvB//gAmJzTdM=; b=t81R20B7qsVRHJA7MGskcYetCS3cVQ5id/zVvccq+K94dofsfZzrKaAZ+JogUz2K/N y0dYedt0GfOinaAPtn3zffIioH0yqFPuxYR+4urlOvl09A2Cqsy/N+DU9bjPxvTppa0D NAxPVVeq13vmxJzyKQJyhA7HRqVSP8uRZxYG8onQ1twpqIegOo5HcN3fmNe2UdCaJDHI bbXlUF8VoOTBWvoOF8rliL5pKjn0ypp0QHsqAfV464DrNfwgm0PQ5d6g9lP2dCFwhtCK WnKK6xlhuMwrdiseO+c+DkvR2tbjeXqHuAl1Mj0S+yu3GFet0WPO/uJ0V4MsiANd+hmE b/zg== X-Gm-Message-State: AO0yUKXoMoWSaNIf0lPXwlW4ubAHJpMSJuq+vx0M0f3kLFn9t+eSNkCo jriL3jOYaWzW/QN7F3PQxowLbb8fi9NE/ylZ X-Google-Smtp-Source: AK7set+GzDFBwf0flHAI2MxNqIcTq2n7/pMvxblYjgOfi6ZFCmlx0IgY9JN3/YDSjqi155MzrEsAmQ== X-Received: by 2002:a2e:8641:0:b0:293:5317:5780 with SMTP id i1-20020a2e8641000000b0029353175780mr9668111ljj.49.1678644296818; Sun, 12 Mar 2023 11:04:56 -0700 (PDT) Received: from 0002-mmc-dw_mmc-add-an-option-to-force-32-bit-access-to-6.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id f23-20020a2e3817000000b002987088bda4sm697267lja.69.2023.03.12.11.04.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 11:04:56 -0700 (PDT) Message-ID: <640e1448.2e0a0220.365cb.1924@mx.google.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 20:58:50 +0300 Subject: [PATCH v5 2/3] mmc: dw_mmc: add an option to force 32-bit access to 64-bit FIFO To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. --- drivers/mmc/host/dw_mmc-exynos.c | 43 ++++++++++- drivers/mmc/host/dw_mmc.c | 122 ++++++++++++++++++++++++++++++- drivers/mmc/host/dw_mmc.h | 2 + 3 files changed, 164 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 9f20ac524..b4c0ba2eb 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -28,6 +28,8 @@ enum dw_mci_exynos_type { DW_MCI_TYPE_EXYNOS5420_SMU, DW_MCI_TYPE_EXYNOS7, DW_MCI_TYPE_EXYNOS7_SMU, + DW_MCI_TYPE_EXYNOS78XX, + DW_MCI_TYPE_EXYNOS78XX_SMU, DW_MCI_TYPE_ARTPEC8, }; @@ -70,6 +72,12 @@ static struct dw_mci_exynos_compatible { }, { .compatible = "samsung,exynos7-dw-mshc-smu", .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU, + }, { + .compatible = "samsung,exynos7885-dw-mshc", + .ctrl_type = DW_MCI_TYPE_EXYNOS78XX, + }, { + .compatible = "samsung,exynos7885-dw-mshc-smu", + .ctrl_type = DW_MCI_TYPE_EXYNOS78XX_SMU, }, { .compatible = "axis,artpec8-dw-mshc", .ctrl_type = DW_MCI_TYPE_ARTPEC8, @@ -86,6 +94,8 @@ static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) return EXYNOS4210_FIXED_CIU_CLK_DIV; else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; else @@ -101,7 +111,8 @@ static void dw_mci_exynos_config_smu(struct dw_mci *host) * set for non-ecryption mode at this time. */ if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU) { mci_writel(host, MPSBEGIN0, 0); mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | @@ -127,6 +138,12 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); } + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU) { + /* Quirk needed for certain Exynos SoCs */ + host->quirks |= DW_MMC_QUIRK_FIFO64_32; + } + if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { /* Quirk needed for the ARTPEC-8 SoC */ host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; @@ -144,6 +161,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -153,6 +172,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -223,6 +244,8 @@ static int dw_mci_exynos_resume_noirq(struct device *dev) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -231,6 +254,8 @@ static int dw_mci_exynos_resume_noirq(struct device *dev) if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -410,6 +435,8 @@ static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); else @@ -423,6 +450,8 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -430,6 +459,8 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -444,6 +475,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -454,6 +487,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -633,6 +668,12 @@ static const struct of_device_id dw_mci_exynos_match[] = { .data = &exynos_drv_data, }, { .compatible = "samsung,exynos7-dw-mshc-smu", .data = &exynos_drv_data, }, + /* XXX: more SoCs probably have the same quirk, + the compatible should be something more generic */ + { .compatible = "samsung,exynos7885-dw-mshc", + .data = &exynos_drv_data, }, + { .compatible = "samsung,exynos7885-dw-mshc-smu", + .data = &exynos_drv_data, }, { .compatible = "axis,artpec8-dw-mshc", .data = &artpec_drv_data, }, {}, diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 581614196..9fe816c61 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2575,6 +2575,119 @@ static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) } } +/* + Some dw_mmc devices have 64-bit FIFOs, but expect them to be + accessed using two 32-bit accesses. If such controller is used + with a 64-bit kernel, this has to be done explicitly. + + XXX: Is this issue specific to Exynos7? +*/ + +static inline uint64_t mci_fifo_readq_32(void __iomem *addr) +{ + uint64_t ans; + uint32_t proxy[2]; + + proxy[0] = mci_fifo_readl(addr); + proxy[1] = mci_fifo_readl(addr+4); + memcpy(&ans, proxy, 8); + return ans; +} + +static inline void mci_fifo_writeq_32(void __iomem *addr, uint64_t value) +{ + uint32_t proxy[2]; + + memcpy(proxy, &value, 8); + mci_fifo_writel(addr, proxy[0]); + mci_fifo_writel(addr+4, proxy[1]); +} + +static void dw_mci_push_data64_32(struct dw_mci *host, void *buf, int cnt) +{ + struct mmc_data *data = host->data; + int init_cnt = cnt; + + /* try and push anything in the part_buf */ + if (unlikely(host->part_buf_count)) { + int len = dw_mci_push_part_bytes(host, buf, cnt); + + buf += len; + cnt -= len; + + if (host->part_buf_count == 8) { + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + host->part_buf_count = 0; + } + } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >= 8) { + u64 aligned_buf[16]; + int len = min(cnt & -8, (int)sizeof(aligned_buf)); + int items = len >> 3; + int i; + /* memcpy from input buffer into aligned buffer */ + memcpy(aligned_buf, buf, len); + buf += len; + cnt -= len; + /* push data from aligned buffer into fifo */ + for (i = 0; i < items; ++i) + mci_fifo_writeq_32(host->fifo_reg, aligned_buf[i]); + } + } else +#endif + { + u64 *pdata = buf; + + for (; cnt >= 8; cnt -= 8) + mci_fifo_writeq_32(host->fifo_reg, *pdata++); + buf = pdata; + } + /* put anything remaining in the part_buf */ + if (cnt) { + dw_mci_set_part_bytes(host, buf, cnt); + /* Push data if we have reached the expected data length */ + if ((data->bytes_xfered + init_cnt) == + (data->blksz * data->blocks)) + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + } +} + +static void dw_mci_pull_data64_32(struct dw_mci *host, void *buf, int cnt) +{ +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >= 8) { + /* pull data from fifo into aligned buffer */ + u64 aligned_buf[16]; + int len = min(cnt & -8, (int)sizeof(aligned_buf)); + int items = len >> 3; + int i; + + for (i = 0; i < items; ++i) + aligned_buf[i] = mci_fifo_readq_32(host->fifo_reg); + + /* memcpy from aligned buffer into output buffer */ + memcpy(buf, aligned_buf, len); + buf += len; + cnt -= len; + } + } else +#endif + { + u64 *pdata = buf; + + for (; cnt >= 8; cnt -= 8) + *pdata++ = mci_fifo_readq_32(host->fifo_reg); + buf = pdata; + } + if (cnt) { + host->part_buf = mci_fifo_readq_32(host->fifo_reg); + dw_mci_pull_final_bytes(host, buf, cnt); + } +} + static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) { int len; @@ -3367,8 +3480,13 @@ int dw_mci_probe(struct dw_mci *host) width = 16; host->data_shift = 1; } else if (i == 2) { - host->push_data = dw_mci_push_data64; - host->pull_data = dw_mci_pull_data64; + if ((host->quirks & DW_MMC_QUIRK_FIFO64_32)) { + host->push_data = dw_mci_push_data64_32; + host->pull_data = dw_mci_pull_data64_32; + } else { + host->push_data = dw_mci_push_data64; + host->pull_data = dw_mci_pull_data64; + } width = 64; host->data_shift = 3; } else { diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 4ed81f94f..edd642b92 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -280,6 +280,8 @@ struct dw_mci_board { /* Support for longer data read timeout */ #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) +/* Force 32-bit access to the FIFO */ +#define DW_MMC_QUIRK_FIFO64_32 BIT(1) #define DW_MMC_240A 0x240a #define DW_MMC_280A 0x280a From patchwork Sun Mar 12 17:58:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Lisov X-Patchwork-Id: 13171734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE43BC6FA99 for ; Sun, 12 Mar 2023 18:14:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232190AbjCLSOe (ORCPT ); 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[46.138.144.249]) by smtp.gmail.com with ESMTPSA id v23-20020a197417000000b004dc807b904bsm712172lfe.120.2023.03.12.11.05.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 11:05:11 -0700 (PDT) Message-ID: <640e1457.190a0220.75a58.1af0@mx.google.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 20:58:50 +0300 Subject: [PATCH v5 3/3] arm64: dts: exynos: fix wrong mmc compatible in exynos7885.dtsi To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This DW-MMC variant is not actually compatible with "samsung,exynos7-dw-mshc-smu", and requires an additional quirk to handle very short data transfers, typically used by SDIO cards. Update the compatible string to "samsung,exynos7885-dw-mshc-smu" to reflect this fact. --- arch/arm64/boot/dts/exynos/exynos7885.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 23c2e0bb0..b0addb0b3 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -294,7 +294,7 @@ pmu_system_controller: system-controller@11c80000 { }; mmc_0: mmc@13500000 { - compatible = "samsung,exynos7-dw-mshc-smu"; + compatible = "samsung,exynos7885-dw-mshc-smu"; reg = <0x13500000 0x2000>; interrupts = ; #address-cells = <1>;