From patchwork Sun Mar 12 17:58:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Lisov X-Patchwork-Id: 13171742 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54891C6FA99 for ; Sun, 12 Mar 2023 18:26:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230303AbjCLS00 (ORCPT ); Sun, 12 Mar 2023 14:26:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230289AbjCLS0I (ORCPT ); Sun, 12 Mar 2023 14:26:08 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCE9212053 for ; Sun, 12 Mar 2023 11:19:54 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id da10so40255878edb.3 for ; Sun, 12 Mar 2023 11:19:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678645110; h=cc:to:subject:date:from:in-reply-to:message-id:from:to:cc:subject :date:message-id:reply-to; bh=THHnNubc2+UuqNjcDLN8j6le5gzsAvvJJbRATCHsptA=; b=KdLNWvheQNnDkdC6K6DcEkMXgyWm3H6ZMt4UmeMZGwVCuiBxLAQ2AXsLS7hjnxHd3a NAaz8XjQG0wGPhE2Df5gWsHZCKMdrTSYNh0rtxVGyxquWDTdUNIwLEmfUcZ5srDlWJL5 LtujHh75zoeJV509Zm4/usxgT4p8J4O/8TX+M9uSO2Z7MdHGPePiyaD3dBCShOzsQ2Es QV9IZ9Io0Fe8ouIsoCOp63pV968IC/UjfFeGpeYWZj4MynyYz0avGie7aqWs9eTb16Gi Q1ywPbnc83UkZJvVGPlXjrSyrL/cwA/f0Vn5Rwuek//BNYqMwqfrN+hQTX30hMW8Nk9L aKOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678645110; h=cc:to:subject:date:from:in-reply-to:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=THHnNubc2+UuqNjcDLN8j6le5gzsAvvJJbRATCHsptA=; b=RcSxWNIw0IBi2xomWl8GNM1am9vbhFXeKHMT8Hi1rvV+kThcMaMlPvbZaFCRn4NIDp dfkIyu/zKXH5kHlHnRG4Yf6U3u9So7kbj1/D5Eb025XvbOwmr8dGNMNWGue1XWL5v9Jx JPLRycberT+VjakGdt9mLs5XIS/eaUtOfoxubkZ6WlHQ4hfrjPImtW21iKXIOTds31Db wOHdKruqOvUf1puHYkXSAdeG0SKKai7FF5PtRdNJ5iNPNQvqbM0Dpa7LYlOVpIxp27dK 60bWpZjCa730nFE5sUujmMC3N9QA9XRGJRPCCoFqbRTmppc8j8UfHjpkbz8FiC8Wc4GD zW+Q== X-Gm-Message-State: AO0yUKU3h6l2wstYoeoOdez+ZvusNXnIPjqo6HjH1bgLpoD1Y42jPQj0 K0l2wqIumHBQebdJ11jc/Wp3Mo4VwuWacpa6 X-Google-Smtp-Source: AK7set9Moi9Os6nCqNL55kt6YnIJSreULqN4bxUrc5pY0nx+g0T81URh3NySuPbcHUvZFzE4qkpFyQ== X-Received: by 2002:a2e:990e:0:b0:292:f882:95ee with SMTP id v14-20020a2e990e000000b00292f88295eemr2286603lji.9.1678644649172; Sun, 12 Mar 2023 11:10:49 -0700 (PDT) Received: from 0001-dt-bindings-exynos-dw-mshc-common-add-exynos7885-var.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id a9-20020a2eb549000000b002934d555783sm727843ljn.6.2023.03.12.11.10.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 11:10:48 -0700 (PDT) Message-Id: <1678644516.665314-1-sleirsgoevy@gmail.com> In-Reply-To: <1678644516.665314-0-sleirsgoevy@gmail.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 20:58:50 +0300 Subject: [PATCH v5 1/3] dt-bindings: exynos-dw-mshc-common: add exynos7885 variants To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. Add two new compatible strings, "samsung,exynos7885-dw-mshc" and "samsung,exynos7885-dw-mshc-smu" respectively, to denote exynos7885 boards that need this quirk. But it's very possible that all "samsung,exynos7-dw-mshc" boards are actually affected. --- .../devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml index fdaa18481..3eebaed2c 100644 --- a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -22,6 +22,8 @@ properties: - samsung,exynos5420-dw-mshc-smu - samsung,exynos7-dw-mshc - samsung,exynos7-dw-mshc-smu + - samsung,exynos7885-dw-mshc + - samsung,exynos7885-dw-mshc-smu - axis,artpec8-dw-mshc reg: From patchwork Sun Mar 12 17:58:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Lisov X-Patchwork-Id: 13171743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAE5CC6FA99 for ; Sun, 12 Mar 2023 18:26:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232142AbjCLS0l (ORCPT ); Sun, 12 Mar 2023 14:26:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230339AbjCLS01 (ORCPT ); Sun, 12 Mar 2023 14:26:27 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0E727AAC for ; Sun, 12 Mar 2023 11:20:29 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id h9so10425713ljq.2 for ; Sun, 12 Mar 2023 11:20:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678645145; h=cc:to:subject:date:from:message-id:from:to:cc:subject:date :message-id:reply-to; bh=R/ZxX3DwmCtqhIm3cqoC0hxQvGcxZ6dvB//gAmJzTdM=; b=Fin1lDzAwEvhp3Wf0d/EQRl42r4IRtF7wZuNV0iOr2Sc3Q+8OtJWAUgyql1jICvw/G MS8STVKPLy75mz7CB5cQ0VadtxyRc4VFEWLK4lEsbSkVltjbmAL578WKkwQT0OeQ67UD ADQPJ65haRa02/mYdzl8LTyMJoFxUgPwhZeNGPTXOqVZ3msOaNLv91+ofYtA3lIS7OoP 4a9kMevyxuYZslzjnPSZ4+xZGYxz22TYrFrAgBNldi6g5zviKM7jmt3YuoW9+r6ZDvZQ AQdmmhDIPZvMsWG8HDaFBcrd29xfK988XIavGCATkEYxSGEwpyt8bas229rsJNFGIq2G /JLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678645145; h=cc:to:subject:date:from:message-id:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R/ZxX3DwmCtqhIm3cqoC0hxQvGcxZ6dvB//gAmJzTdM=; b=EVqLTXaP5/Fooph7GKO0MI20BP9aa8Uuwcd0NPmR9mJ0wtiYK1HvA/HN3lbaSJszt6 oApQojJANpm/EVyMeHdzxWA/7BeA24IEJAFDVdzthJwBxCfhKmBCADmU5hKe6999nVLP xRzz6HSlcUi4Br0CtewM+3bCASIMUKxrNW8qgwb4uhDsF69Hrqb5z/Wr3lQFsqdVpMrQ Ghmyy9tLcsXfTKrAieevxeHryYXTMyODLbPeE0GQwAeoOljrnlk6d3BzY38PPbEBcO2G 76kPsXrcWCfnHW25WYyCKNMtMfltUJE69/r4Gf1mroIEwraWuiGAIPKIvDlz3HdfeFi7 cwEA== X-Gm-Message-State: AO0yUKVKFmJs3joYauD9KHEOO/nXVOTK22eNpAzXdE7OXb/odJn1mlnA 89Jzu5AFKtK/dQ5jt0LYGljA+X0QcfcZAPX5 X-Google-Smtp-Source: AK7set8EVTQ0M8wwToogXlCovzofIGhh+13s+1OMZcMakKnSaAaeCx6Sb9QhFkr38g8h58J9u+3smQ== X-Received: by 2002:ac2:44cb:0:b0:4b5:a207:8d70 with SMTP id d11-20020ac244cb000000b004b5a2078d70mr8889093lfm.5.1678644300941; Sun, 12 Mar 2023 11:05:00 -0700 (PDT) Received: from 0002-mmc-dw_mmc-add-an-option-to-force-32-bit-access-to-6.patch (46-138-144-249.dynamic.spd-mgts.ru. [46.138.144.249]) by smtp.gmail.com with ESMTPSA id y4-20020ac255a4000000b004b5774726dcsm707104lfg.236.2023.03.12.11.05.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 11:05:00 -0700 (PDT) Message-ID: <640e144c.c20a0220.7c216.196c@mx.google.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 20:58:50 +0300 Subject: [PATCH v5 2/3] mmc: dw_mmc: add an option to force 32-bit access to 64-bit FIFO To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Some Samsung Exynos boards using the arm64 architecture have DW MMC controllers configured for a 32-bit data bus but a 64-bit FIFO. On these systems the 64-bit FIFO registers must be accessed in two 32-bit halves. --- drivers/mmc/host/dw_mmc-exynos.c | 43 ++++++++++- drivers/mmc/host/dw_mmc.c | 122 ++++++++++++++++++++++++++++++- drivers/mmc/host/dw_mmc.h | 2 + 3 files changed, 164 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 9f20ac524..b4c0ba2eb 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -28,6 +28,8 @@ enum dw_mci_exynos_type { DW_MCI_TYPE_EXYNOS5420_SMU, DW_MCI_TYPE_EXYNOS7, DW_MCI_TYPE_EXYNOS7_SMU, + DW_MCI_TYPE_EXYNOS78XX, + DW_MCI_TYPE_EXYNOS78XX_SMU, DW_MCI_TYPE_ARTPEC8, }; @@ -70,6 +72,12 @@ static struct dw_mci_exynos_compatible { }, { .compatible = "samsung,exynos7-dw-mshc-smu", .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU, + }, { + .compatible = "samsung,exynos7885-dw-mshc", + .ctrl_type = DW_MCI_TYPE_EXYNOS78XX, + }, { + .compatible = "samsung,exynos7885-dw-mshc-smu", + .ctrl_type = DW_MCI_TYPE_EXYNOS78XX_SMU, }, { .compatible = "axis,artpec8-dw-mshc", .ctrl_type = DW_MCI_TYPE_ARTPEC8, @@ -86,6 +94,8 @@ static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) return EXYNOS4210_FIXED_CIU_CLK_DIV; else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; else @@ -101,7 +111,8 @@ static void dw_mci_exynos_config_smu(struct dw_mci *host) * set for non-ecryption mode at this time. */ if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU) { mci_writel(host, MPSBEGIN0, 0); mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | @@ -127,6 +138,12 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); } + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU) { + /* Quirk needed for certain Exynos SoCs */ + host->quirks |= DW_MMC_QUIRK_FIFO64_32; + } + if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { /* Quirk needed for the ARTPEC-8 SoC */ host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; @@ -144,6 +161,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -153,6 +172,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -223,6 +244,8 @@ static int dw_mci_exynos_resume_noirq(struct device *dev) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -231,6 +254,8 @@ static int dw_mci_exynos_resume_noirq(struct device *dev) if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -410,6 +435,8 @@ static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); else @@ -423,6 +450,8 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -430,6 +459,8 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -444,6 +475,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else @@ -454,6 +487,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU || priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else @@ -633,6 +668,12 @@ static const struct of_device_id dw_mci_exynos_match[] = { .data = &exynos_drv_data, }, { .compatible = "samsung,exynos7-dw-mshc-smu", .data = &exynos_drv_data, }, + /* XXX: more SoCs probably have the same quirk, + the compatible should be something more generic */ + { .compatible = "samsung,exynos7885-dw-mshc", + .data = &exynos_drv_data, }, + { .compatible = "samsung,exynos7885-dw-mshc-smu", + .data = &exynos_drv_data, }, { .compatible = "axis,artpec8-dw-mshc", .data = &artpec_drv_data, }, {}, diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 581614196..9fe816c61 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2575,6 +2575,119 @@ static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) } } +/* + Some dw_mmc devices have 64-bit FIFOs, but expect them to be + accessed using two 32-bit accesses. If such controller is used + with a 64-bit kernel, this has to be done explicitly. + + XXX: Is this issue specific to Exynos7? +*/ + +static inline uint64_t mci_fifo_readq_32(void __iomem *addr) +{ + uint64_t ans; + uint32_t proxy[2]; + + proxy[0] = mci_fifo_readl(addr); + proxy[1] = mci_fifo_readl(addr+4); + memcpy(&ans, proxy, 8); + return ans; +} + +static inline void mci_fifo_writeq_32(void __iomem *addr, uint64_t value) +{ + uint32_t proxy[2]; + + memcpy(proxy, &value, 8); + mci_fifo_writel(addr, proxy[0]); + mci_fifo_writel(addr+4, proxy[1]); +} + +static void dw_mci_push_data64_32(struct dw_mci *host, void *buf, int cnt) +{ + struct mmc_data *data = host->data; + int init_cnt = cnt; + + /* try and push anything in the part_buf */ + if (unlikely(host->part_buf_count)) { + int len = dw_mci_push_part_bytes(host, buf, cnt); + + buf += len; + cnt -= len; + + if (host->part_buf_count == 8) { + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + host->part_buf_count = 0; + } + } +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >= 8) { + u64 aligned_buf[16]; + int len = min(cnt & -8, (int)sizeof(aligned_buf)); + int items = len >> 3; + int i; + /* memcpy from input buffer into aligned buffer */ + memcpy(aligned_buf, buf, len); + buf += len; + cnt -= len; + /* push data from aligned buffer into fifo */ + for (i = 0; i < items; ++i) + mci_fifo_writeq_32(host->fifo_reg, aligned_buf[i]); + } + } else +#endif + { + u64 *pdata = buf; + + for (; cnt >= 8; cnt -= 8) + mci_fifo_writeq_32(host->fifo_reg, *pdata++); + buf = pdata; + } + /* put anything remaining in the part_buf */ + if (cnt) { + dw_mci_set_part_bytes(host, buf, cnt); + /* Push data if we have reached the expected data length */ + if ((data->bytes_xfered + init_cnt) == + (data->blksz * data->blocks)) + mci_fifo_writeq_32(host->fifo_reg, host->part_buf); + } +} + +static void dw_mci_pull_data64_32(struct dw_mci *host, void *buf, int cnt) +{ +#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS + if (unlikely((unsigned long)buf & 0x7)) { + while (cnt >= 8) { + /* pull data from fifo into aligned buffer */ + u64 aligned_buf[16]; + int len = min(cnt & -8, (int)sizeof(aligned_buf)); + int items = len >> 3; + int i; + + for (i = 0; i < items; ++i) + aligned_buf[i] = mci_fifo_readq_32(host->fifo_reg); + + /* memcpy from aligned buffer into output buffer */ + memcpy(buf, aligned_buf, len); + buf += len; + cnt -= len; + } + } else +#endif + { + u64 *pdata = buf; + + for (; cnt >= 8; cnt -= 8) + *pdata++ = mci_fifo_readq_32(host->fifo_reg); + buf = pdata; + } + if (cnt) { + host->part_buf = mci_fifo_readq_32(host->fifo_reg); + dw_mci_pull_final_bytes(host, buf, cnt); + } +} + static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) { int len; @@ -3367,8 +3480,13 @@ int dw_mci_probe(struct dw_mci *host) width = 16; host->data_shift = 1; } else if (i == 2) { - host->push_data = dw_mci_push_data64; - host->pull_data = dw_mci_pull_data64; + if ((host->quirks & DW_MMC_QUIRK_FIFO64_32)) { + host->push_data = dw_mci_push_data64_32; + host->pull_data = dw_mci_pull_data64_32; + } else { + host->push_data = dw_mci_push_data64; + host->pull_data = dw_mci_pull_data64; + } width = 64; host->data_shift = 3; } else { diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 4ed81f94f..edd642b92 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -280,6 +280,8 @@ struct dw_mci_board { /* Support for longer data read timeout */ #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) +/* Force 32-bit access to the FIFO */ +#define DW_MMC_QUIRK_FIFO64_32 BIT(1) #define DW_MMC_240A 0x240a #define DW_MMC_280A 0x280a From patchwork Sun Mar 12 17:58:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergey Lisov X-Patchwork-Id: 13171754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD33BC6FD19 for ; Sun, 12 Mar 2023 18:36:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230282AbjCLSg6 (ORCPT ); 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[46.138.144.249]) by smtp.gmail.com with ESMTPSA id y14-20020a2e9d4e000000b00295a32db4e1sm716776ljj.91.2023.03.12.11.05.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Mar 2023 11:05:16 -0700 (PDT) Message-ID: <640e145c.2e0a0220.422d2.19f2@mx.google.com> From: Sergey Lisov Date: Sun, 12 Mar 2023 20:58:50 +0300 Subject: [PATCH v5 3/3] arm64: dts: exynos: fix wrong mmc compatible in exynos7885.dtsi To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Jaehoon Chung Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This DW-MMC variant is not actually compatible with "samsung,exynos7-dw-mshc-smu", and requires an additional quirk to handle very short data transfers, typically used by SDIO cards. Update the compatible string to "samsung,exynos7885-dw-mshc-smu" to reflect this fact. --- arch/arm64/boot/dts/exynos/exynos7885.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 23c2e0bb0..b0addb0b3 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -294,7 +294,7 @@ pmu_system_controller: system-controller@11c80000 { }; mmc_0: mmc@13500000 { - compatible = "samsung,exynos7-dw-mshc-smu"; + compatible = "samsung,exynos7885-dw-mshc-smu"; reg = <0x13500000 0x2000>; interrupts = ; #address-cells = <1>;